RD38F2240WWZDQ0 [NUMONYX]
Memory Circuit, Flash+PSRAM, Hybrid, PBGA88,;
| 型号： | RD38F2240WWZDQ0 |
| 厂家： | 
NUMONYX B.V |
| 描述： | Memory Circuit, Flash+PSRAM, Hybrid, PBGA88, 静态存储器 内存集成电路 |
| 文件： | 总46页 (文件大小：652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Numonyx™ Wireless Flash Memory
(W18/W30 SCSP)
32WQ and 64WQ Family with Asynchronous RAM
Datasheet
Product Features
Device Architecture
Flash Performance
— Flash Density: 32-Mbit, 64-Mbit
— Async PSRAM Density: 16-Mbit, 32-Mbit
— 65 ns initial access at 1.8 V I/O
— 70 ns initial access at 3.0 V I/O
— Top, Bottom or Dual flash parameter
configuration
Device Voltage
— 25 ns async page at 1.8 V or 3.0 V I/O
— 14 ns sync reads (tCHQV) at 1.8 V I/O
— 20 ns sync reads (tCHQV) at 3.0 V I/O
— Flash VCC = 1.8 V; Flash VCCQ = 1.8 V or 3.0 V
— RAM VCC = 1.8 V or 3.0 V
Device Packaging
— Enhanced Factory Programming:
3.10 µs/Word (Typ)
Flash Architecture
— 88 balls (8 x 10 active ball matrix)
— Area: 8x10 mm
— Read-While-Write/Erase
— Asymmetrical blocking structure
— Height: 1.2 mm to 1.4 mm
PSRAM Performance
— 4-KWord parameter blocks (Top or
Bottom)
— 32-KWord main blocks
— 4-Mbit partition size
— 70 ns initial access, 25 ns async page reads at
1.8 V I/O
— 70 ns initial access async PSRAM at 1.8 V
I/O
— 128-bit One-Time Programmable
(OTP) Protection Register
— 70 ns initial access, 25 ns async page
reads at 3.0 V I/O
SRAM Performance
— Zero-latency block locking
— Absolute write protection with block
lock using F-VPP and F-WP#
— 70 ns initial access at 1.8 V or 3.0 V I/O
Quality and Reliability
Flash Software
— Numonyx™ Flash Data Integrator
(FDI) and Common Flash Interface
(CFI)
— Extended Temperature: –25 °C to +85 °C
— Minimum 100K flash block erase cycle
— 90 nm ETOX™ IX flash technology
— 130 nm ETOX™ VIII flash technology
Order Number: 251407-13
November 2007
LLegal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Numonyx B.V., All Rights Reserved.
Datasheet
2
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Contents
1.0 Introduction..............................................................................................................6
1.1
1.2
Nomenclature.....................................................................................................6
Conventions .......................................................................................................7
2.0 Functional Overview..................................................................................................8
2.1
2.2
Block Diagram ....................................................................................................8
Flash Memory Map and Partitioning........................................................................9
3.0 Package Information...............................................................................................10
4.0 Ballout and Signal Description.................................................................................13
4.1
4.2
Signal Ballout ................................................................................................... 13
Signal Descriptions............................................................................................ 14
5.0 Maximum Ratings and Operating Conditions............................................................ 16
5.1
5.2
5.3
Absolute Maximum Ratings.................................................................................16
Operating Conditions .........................................................................................16
Capacitance......................................................................................................17
6.0 Electrical Specifications........................................................................................... 18
6.1 DC Characteristics............................................................................................. 18
7.0 AC Characteristics ................................................................................................... 20
7.1
7.2
7.3
7.4
Flash AC Characteristics..................................................................................... 20
SRAM AC Characteristics .................................................................................... 20
PSRAM AC Characteristics................................................................................... 22
Device AC Test Conditions.................................................................................. 27
8.0 Flash Power Consumption .......................................................................................28
9.0 Device Operation..................................................................................................... 29
9.1
Bus Operations .................................................................................................29
10.0 Flash Command Definitions ..................................................................................... 33
11.0 Flash Read Operations............................................................................................. 33
12.0 Flash Program Operations .......................................................................................33
13.0 Flash Erase Operations............................................................................................ 33
14.0 Flash Security Modes...............................................................................................33
15.0 Flash Read Configuration Register........................................................................... 33
16.0 SRAM Operations..................................................................................................... 34
16.1 Power-up Sequence and Initialization................................................................... 34
16.2 Data Retention Mode .........................................................................................34
17.0 PSRAM Operations................................................................................................... 36
17.1 Power-Up Sequence and Initialization................................................................... 36
17.1.1 16Mbit PSRAM Power-Up Sequence (Non-Page Mode)..................................36
17.2 Standby Mode/ Deep Power-Down Mode............................................................... 37
17.3 PSRAM Special Read and Write Constraints...........................................................37
A
B
C
D
Write State Machine ................................................................................................38
Common Flash Interface.......................................................................................... 38
Flash Flowcharts ..................................................................................................... 38
Additional Information ............................................................................................ 38
November 2007
Order Number: 251407-13
Datasheet
3
32WQ and 64WQ Family with Asynchronous RAM
E
F
Ordering Information (Active Line Items)................................................................39
Ordering Information (Retired Line Items) ..............................................................40
Datasheet
4
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Revision History
Date
Revision
Description
June 2003
-001
Initial release
Changed PSRAM Read values.
Added new Transient Equivalent Testing Load Circuit figure.
General text edits.
September
2003
-002
-006
-007
May 2004
Reformatted the datasheet and moved sections around according to the new layout.
Added 90 nm product information.
Added line items.
Added DC and AC specs for the new line items and edits to related sections.
August 2004
Added line items.
Added 32WQ product information.
January 2005
June 2005
-008
-009
-010
Added line items.
Removed Power-up sequence from Section 16; Added 70ns PSRAM (non-page mode) specification
Updated Ordering Information
October 2005
Updated Ordering information with active and retired line items.
Updated AC spec & power-up specs for 38F2030W0YxQE & 38F2040W0YxQE
June 2007
-011
Rempved 38F2030W0YxQE & 38F2040W0YxQE Line Items
Updated ordering information
August 2007
-012
13
November 2007
Applied Numonyx branding.
November 2007
Order Number: 251407-13
Datasheet
5
32WQ and 64WQ Family with Asynchronous RAM
1.0
Introduction
This document contains information pertaining to the products in the Numonyx™
Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM. The W18/
W30 SCSP 32WQ and 64WQ families offer a wide variety of stacked combinations that
include single flash die, two flash die, flash + PSRAM, and flash + SRAM options. This
document provides information where this SCSP family differs from the Numonyx
Wireless Flash Memory (W18/W30) discrete device.
Refer to the discrete datasheets Numonyx™ Wireless Flash Memory (W18) Datasheet
(order number 290701) and Numonyx™ Wireless Flash Memory (W30) Datasheet
(order number 290702) for flash product details not included in this SCSP datasheet.
The Numonyx Wireless Flash Memory (W18/W30 SCSP) family offers various flash plus
static RAM combinations in a common package footprint. The flash memory features
1.8 V low-power operations with flexible, multi-partition, dual-operation Read-While-
Write / Read-While-Erase, asynchronous, and synchronous reads. This SCSP device
integrates up to two flash die, and one PSRAM or SRAM die in a low-profile package
compatible with other SCSP families with QUAD+ ballout.
1.1
Nomenclature
0x
Hexadecimal prefix
Binary prefix
0b
Byte
CFI
8 bits
Common Flash Interface
Command User Interface
Don’t Use
CUI
DU
ETOX
FDI
EPROM Tunnel Oxide
Numonyx™ Flash Data Integrator (software solution)
1 thousand
K(noun)
Kb
1024 bits
KB
1024 bytes
Kword
M (noun)
Mb
1024 words
1 million
1,048,576 bits
MB
1,048,576 bytes
OTP
PLR
One-Time Programmable
Protection Lock Register
Protection Register
Protection Register Data
Read Configuration Register
PR
PRD
RCR
Datasheet
6
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
RFU
Reserved for Future Use
SCSP
SR
Stacked Chip Scale Package
Status Register
SRD
Word
WSM
Status Register Data
16 bits
Write State Machine
1.2
Conventions
Group Membership Brackets: Square brackets are used to designate group membership
or to define a group of signals with a similar function, such as A[21:1] and SR[4,1].
VCC vs. VCC: When referring to a signal or package-connection name, the notation
used is VCC, etc. When referring to a timing or electrical level, the notation used is
subscripted such as VCC, etc.
Device: This term is used interchangeably throughout this document to denote either a
particular die, or the combination of multiple die within a single package.
F[3:1]-CE#, F[2:1]-OE#: This is the method used to refer to more than one chip-
enable or output enable at the same time. When each is referred to individually, the
reference will be F1-CE# and F1-OE# (for die #1), and F2-CE# and F2-OE# (for die
#2).
F-VCC, P-VCC or S-VCC: When referencing flash memory signals or timings, the
notation used is F-VCC or F-VCC, respectively. When the reference is to PSRAM signals
or timings, the notation is prefixed with “P-” (e.g., P-VCC, P-VCC). When referencing
SRAM signals or timings, the notation is prefixed with “S-” (e.g., S-VCC or S-VCC). P-
VCC and S-VCC are RFU for stacked combinations that do not include PSRAM or SRAM.
R-OE#, R-LB#, R-UB#, R-WE#: These are used to identify RAM OE#, LB#, UB#,
WE# signals, and are usually shared between 2 or more RAM die. R-OE#, R-LB#, R-
UB# and R-WE are RFU for stacked combinations that do not include PSRAM or SRAM.
November 2007
Order Number: 251407-13
Datasheet
7
32WQ and 64WQ Family with Asynchronous RAM
2.0
Functional Overview
This section provides an overview of the features and capabilities of the Numonyx
Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM device.
The W18/W30 SCSP device provides flash + RAM die combinations. Products range
from single flash die, two flash die, flash + PSRAM, or flash + SRAM. You can choose a
W18 SCSP device or a W30 SCSP device with SRAM or PSRAM offered with the same
package footprint and signal ballout.
2.1
Block Diagram
Show here are all internal package connections for the SCSP family with multiple die.
See Table 21, “Ordering Information on Active Line Items” on page 40 for valid
combinations of flash and RAM die. Unused connections on combinations with less than
three die are reserved and should not be used.
Please contact your local Numonyx representative for details regarding any reserved or
RFU pins.
Figure 1: Block Diagram
F2-VCC
F2-CE#
F2-OE#
Flash Die #2
32- or 64-Mbit W18/W30
CLK
ADV#
F-WE#
F-VPP
VCCQ
WAIT
F-WP#
F-RST#
Flash Die #1
F1-OE#
F1-CE#
32- or 64-Mbit W18/W30
VSS
F1-VCC
A[MAX:0]
D[15:0]
RAM Die
4-, 8-, 16-Mbit SRAM
or
S-VCC/P-VCC
P-CS#/S-CS1#
S-CS2
R-WE#
P-MODE
R-UB#
R-LB#
16- or 32-Mbit PSRAM
R-OE#
Datasheet
8
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
2.2
Flash Memory Map and Partitioning
Consult the latest Numonyx™ Wireless Flash Memory (W18) Datasheet (order number
290701) and the Numonyx™ Wireless Flash Memory (W30) Datasheet (order number
290702), for individual flash die memory map and partitioning information.
Table 1 and Table 2 show memory map and partitioning information for dual-flash
memory die configurations. Flash Die #1 (with F1-CE# as its Chip Select) is configured
as a bottom parameter while Flash Die #2 (with F2-CE# as its Chip Select) is
configured as top parameter.
November 2007
Order Number: 251407-13
Datasheet
9
32WQ and 64WQ Family with Asynchronous RAM
3.0
Package Information
The following two packages are offered with the 32WQ and 64WQ Family.
Figure 2: Mechanical Specifications for 1- or 2-Die SCSP Device (8x10x1.2 mm)
A1 Index
Mark
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
A
B
C
D
B
C
D
E
F
E
F
D
e
G
H
G
H
J
J
K
K
L
L
M
M
b
E
Top View - Ball
Down
Bottom View - Ball Up
A
A2
A1
Y
Drawing not to scale.
Millimeters
Nom
Inches
Nom
Dimens ions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
S ymbol
Min
Max Notes
1.200
Min
Max
0.0472
A
A1
A2
b
D
E
0.200
0.0079
0.860
0.375
10.000
8.000
0.800
88
0.0339
0.0148
0.3937
0.3150
0.0315
88
0.325
9.900
7.900
0.425
10.100
8.100
0.0128
0.3898
0.3110
0.0167
0.3976
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Y
S1
S2
0.100
1.300
0.700
0.0039
0.0512
0.0276
1.100
0.500
1.200
0.600
0.0433
0.0197
0.0472
0.0236
Datasheet
10
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 3: Mechanical Specifications for Triple-Die SCSP Device (8x10x1.4 mm)
A1
S1
Index
Mark
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
A
B
C
D
B
C
D
E
F
E
F
D
e
G
H
G
H
J
J
K
K
L
L
M
M
b
E
Top View - Ball Down
Bottom View - Ball Up
A
A2
A1
Y
Drawing not to scale.
Millimeters
Nom
Inches
Nom
Dimensions
Symbol
Min
Max Notes
Min
Max
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
A
A1
A2
b
D
E
1.400
0.0551
0.200
0.0079
1.070
0.375
10.000
8.000
0.800
88
0.0421
0.0148
0.3937
0.3150
0.0315
88
0.325
9.900
7.900
0.425
10.100
8.100
0.0128
0.3898
0.3110
0.0167
0.3976
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Y
S1
S2
0.100
1.300
0.700
0.0039
0.0512
0.0276
1.100
0.500
1.200
0.600
0.0433
0.0197
0.0472
0.0236
November 2007
Order Number: 251407-13
Datasheet
11
32WQ and 64WQ Family with Asynchronous RAM
Table 1:
64-Mbit Flash + 32-Mbit Flash Die W18/W30 SCSP Memory Map and Partitioning
Block Size
(KW)
Partitioning
Block #
Address Range
4
63-70
56-62
48-55
40-47
32-39
0-31
1F8000-1FFFFF
1C0000-1F7FFF
180000-1BFFFF
140000-17FFFF
100000-13FFFF
000000-0FFFFF
Parameter
Partition
Partition 0
32
32
32
32
32
Flash Die #2
(32-Mbit) Top
Parameter
Partition 1
Partition 2
Partition 3
Partitions 4-7
Main Partitions
Partitions 8-15
Partitions 4-7
Partition 3
32
32
32
32
32
32
4
71-134
39-70
31-38
23-30
15-22
8-14
200000-3FFFFF
100000-1FFFFF
0C0000-0FFFFF
080000-0BFFFF
040000-07FFFF
008000-03FFFF
000000-007FFF
Main Partitions
Flash Die #1
(64-Mbit)
Bottom
Partition 2
Parameter
Partition 1
Parameter
Partition
Partition 0
0-7
Table 2:
64-Mbit Dual-Flash Die W18/W30 SCSP Memory Map and Partitioning
Block Size
(KW)
Partitioning
Block #
Address Range
4
127-134
120-126
112-119
104-111
96-103
64-95
3F8000-3FFFFF
3C0000-3F7FFF
380000-3BFFFF
340000-37FFFF
300000-33FFFF
200000-2FFFFF
000000-1FFFFF
Parameter
Partition
Partition 0
32
32
32
32
32
32
Partition 1
Flash Die #2
(64-Mbit) Top
Parameter
Partition 2
Main Partitions
Partition 3
Partitions 4-7
Partitions 8-15
0-63
Partitions 8-15
Partitions 4-7
Partition 3
32
32
32
32
32
32
4
71-134
39-70
31-38
23-30
15-22
8-14
200000-3FFFFF
100000-1FFFFF
0C0000-0FFFFF
080000-0BFFFF
040000-07FFFF
008000-03FFFF
000000-007FFF
Main Partitions
Flash Die #1
(64-Mbit)
Bottom
Partition 2
Parameter
Partition 1
Parameter
Partition
Partition 0
0-7
Datasheet
12
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
4.0
Ballout and Signal Description
4.1
Signal Ballout
Figure 4 shows the 32WQ and 64WQ W18/W30 SCSP family 88-ball (8x10 active ball
matrix) device.
Figure 4: 88-Ball (8x10 Active Ball Matrix) QUAD+ Ballout
Pin 1
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
DU
DU
DU
A
B
C
D
E
F
A4
A5
A18
R-LB#
A17
A19
A23
VSS
VSS
F1-VCC F2-VCC
A21
A22
A11
A12
S-CS2
R-WE#
ADV#
F-WE#
DQ5
CLK
P1-CS#
A20
A3
A24
F-VPP
F-WP#
F-RST#
DQ10
DQ3
A9
A13
A2
A7
A25
A10
A15
A1
A6
R-UB#
DQ2
A8
A14
A16
G
H
J
A0
DQ8
DQ13
DQ14
DQ6
WAIT
DQ7
DQ15
VCCQ
VSS
F2-CE#
F2-OE#
VCCQ
G
H
J
R-OE#
S-CS1#
F1-CE#
VSS
DQ0
DQ1
DQ12
DQ4
F1-OE#
P2-CS#
VSS
DQ9
DQ11
S-VCC
F1-VCC
P-Mode/
P-CRE
F3-CE#
VCCQ
P-VCC
VSS
F2-VCC
VSS
K
L
K
L
VSS
DU
DU
DU
DU
M
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Global Signals
De-Populated Balls
Flash Specific
Legend:
SRAM/PSRAM Specific
Do Not Use
November 2007
Order Number: 251407-13
Datasheet
13
32WQ and 64WQ Family with Asynchronous RAM
4.2
Signal Descriptions
Table 3:
Signal Descriptions (Sheet 1 of 2)
Symbol
Type
Name and Function
ADDRESS INPUTS: Inputs for all die addresses during read and write operations. Addresses are
internally latched during write operations.
•
•
•
•
•
4-Mbit: A[17:0]
8-Mbit: A[18:0]
16-Mbit: A[19:0]
32-Mbit: A[20:0]
64-Mbit: A[21:0]
A[21:0]
Input
A0 is the lowest-order word address.
A[25:22] denote high-order addresses reserved for future device densities
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during read
cycles. Data signals float when the device or its outputs are deselected. Data are internally latched
during writes.
Input/
D[15:0]
CLK
Output
FLASH CLOCK: CLK synchronizes the selected flash die to the memory bus frequency in
synchronous-read mode. During synchronous read operations, the initial address is latched on the
rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first.
Input
CLK is only used in synchronous-read mode. Refer to the flash discrete product datasheet for
information on how to use this signal in asynchronous-read mode.
FLASH ADDRESS VALID: Low-true; During synchronous read operations, the initial address is
latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever
occurs first.
ADV#
WAIT
Input
Refer to the flash discrete product datasheet for information on how to use this signal in
asynchronous-read mode.
FLASH WAIT: When asserted, WAIT indicates invalid data from the selected flash die on D[15:0].
WAIT is High-Z whenever the flash die is deselected (CE# = VIL). WAIT is not gated by OE#.
WAIT is only used in synchronous array-read mode. Refer to the flash discrete product datasheet for
information on how to use this signal in asynchronous-read mode.
Output
FLASH CHIP ENABLE: Low-true; CE#-low selects the associated flash memory die. When asserted,
flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted,
the associated flash die is deselected; power is reduced to standby levels, data and WAIT outputs are
placed in High-Z.
F1-CE# selects flash die #1; F2-CE# selects flash die #2 and is RFU on combinations with only one
flash die. F3-CE# selects flash die #3 and is RFU on SCSP combinations with only one or two flash
die.
F[3:1]-CE#
Input
Input
Input
SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input
buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are
deasserted (S-CS1# = VIH and/or S-CS2 = VIL), the SRAM is deselected and its power is reduced to
standby levels.
S-CS1#
S-CS2
S-CS1# and S-CS2 are only available on SCSP combinations with SRAM die.
PSRAM CHIP SELECTS: Low-true; When asserted, PSRAM internal control logic, input buffers,
decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power
is reduced to standby levels.
P1-CS# selects PSRAM die #1 and is available only on SCSP combinations with PSRAM die. This ball is
RFU on SCSP combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available only on
SCSP combinations with two PSRAM die. This ball is RFU on SCSP combinations without PSRAM or
with a single PSRAM.
P[2:1]-CS#
FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables
the flash output buffers, and places the flash outputs in High-Z.
F[2:1]-OE#
R-OE#
Input
Input
F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and #3, and
is available only on SCSP combinations with two or three flash die and is RFU on SCSP combinations
with only one flash die.
RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the RAM output buffers. R-OE#-high disables
the RAM output buffers, and places the RAM outputs in High-Z.
R-OE# is only available on SCSP combinations with RAM die.
Datasheet
14
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 3:
Signal Descriptions (Sheet 2 of 2)
Symbol
Type
Name and Function
RAM UPPER/ LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM
R-UB#
R-LB#
high-order bytes on D[15:8], and R-LB#-low enables the RAM low-order bytes on D[7:0].
Input
R-UB# and R-LB# are only available on SCSP combinations with either SRAM die or PSRAM die.
FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data
are latched on the rising edge of WE#.
F-WE#
R-WE#
Input
Input
RAM WRITE ENABLE: Low-true; R-WE# controls writes to the RAM die.
R-WE# is only available on SCSP combinations with RAM die.
FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of
the flash die. WP#-low enables the lock-down mechanism- locked down blocks cannot be unlocked
with software commands. WP#-high disables the lock-down mechanism, allowing locked down blocks
to be unlocked with software commands.
F-WP#
Input
Input
FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations.
RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode.
F-RST#
FLASH PROGRAM/ ERASE POWER: A valid F-VPP voltage on this ball enables flash program/erase
operations. Flash memory array contents cannot be altered when F-VPP(VPEN) < VPPLK(VPENLK). Erase/
program operations at invalid F-VPP(VPEN) voltages should not be attempted. Refer to the flash
discrete product datasheet for additional details.
F-VPP
Power
Input
Power
F-VPEN
F-VPEN (Erase/Program/Block Lock Enables) is not available for W18/W30 products.
PSRAM MODE: Low-true; P-MODE is used to enter/exit low power mode.
Low power mode is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1,
38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0.
P-MODE
P-Mode is only available on SCSP combinations with PSRAM die.
FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies
power to the core logic of flash die #2 and #3. Write operations are inhibited when F-VCC < VLKO
.
Device operations at invalid F-VCC voltages should not be attempted.
F[2:1]-VCC
F2-VCC is only available on SCSP combinations with two or three flash die, and is RFU on SCSP
combinations with only one flash die.
SRAM Power Supply: Supplies power to the SRAM die.
S-VCC is only available on SCSP combinations with SRAM die.
S-VCC
P-VCC
Power
Power
PSRAM Power Supply: Supplies power to the PSRAM die.
P-VCC is only available on SCSP combinations with PSRAM die.
VCCQ
VSS
RFU
DU
Power
Power
—
FLASH OUTPUT-BUFFER POWER: Supplies power for the I/O output buffers.
Ground: Connect to ground. Do not float any VSS connection.
Reserved for Future Use: Reserve for future device functionality/ enhancements.
Don’t Use: Do not connect to any other signal, or power supply; must be left floating.
—
November 2007
Order Number: 251407-13
Datasheet
15
32WQ and 64WQ Family with Asynchronous RAM
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only.
NOTICE: This document contains information available at the time of its release. The specifications
are subject to change without notice. Verify with your local Numonyx sales office that you have the
latest datasheet before finalizing a design.
Table 4:
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Notes
Temperature under Bias Extended
Storage Temperature
–25
–55
–0.2
–0.2
–0.5
–0.2
–0.2
–0.2
–
+85
+125
+2.45
+3.6
°C
°C
V
7
1.8 V I/O
3.0 V I/O
1,2,3
Voltage On Any Signal (except F[2:1]-VCC, VCCQ, F-VPP, S-VCC
and P-VCC)
V
2,3
2,3
F[2:1]-VCC Voltage
+2.45
+2.45
+3.6
V
1.8 V I/O
3.0 V I/O
V
1,2,3
2,3
VCCQ, S-VCC and P-VCC Voltage
V
F-VPP Voltage
+14.0
100
V
2,3,4,5
6
ISH Output Short Circuit Current
mA
Notes:
1.
2.
90 nm is only avail with the 1.8 V I/O.
All Specified voltages are relative to VSS. Minimum DC voltage is –0.2 V on input/output signals, –0.2 V on F[2:1]-VCC
and F-VPP signals. For 90 nm devices, during transitions, this level may overshoot to –1.5 V for periods < 20 ns, during
transitions, may overshoot to F-VCC + 1.5 V for periods < 20 ns.
3.
All Specified voltages are relative to VSS. Minimum DC voltage is –0.2 V on input/output signals, –0.2 V on F[2:1]-VCC
and F-VPP signals. For 130 nm devices, during transitions, this level may overshoot to –2 V for periods < 20 ns, during
transitions, may overshoot to F-VCC + 2 V for periods < 20 ns.
4.
5.
Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns.
F-VPP program voltage is normally VPPL. The maximum DC voltage on F-VPP may overshoot to +14 V for periods < 20
ns. F-VPP can be VPPH for 1000 erase cycles on main blocks, 2500 cycles on parameter blocks.
Output shorted for no more than one second. No more than one output shorted at a time.
Devices available with -30o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1,
38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F2030W0YTQF,
38F2030W0YBQF, 38F2040W0YTQF, 38F2040W0YBQF
6.
7.
5.2
Operating Conditions
Warning:
Operation beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions” may affect device reliability.
Table 5:
Operating Conditions (Sheet 1 of 2)
Flash +
Flash
Flash +
SRAM
Flash +
PSRAM
Symbol
Parameter
Unit
Notes
Min Max Min Max Min Max
TC
Operating Temperature
Flash Supply Voltage
–25
1.7
+85
1.95
–25
1.7
+85
1.95
–25
1.7
+85
1.95
°C
V
2
F-VCC
Datasheet
16
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 5:
Operating Conditions (Sheet 2 of 2)
3.0 V I/O
2.2
1.7
3.3
2.2
1.7
3.3
2.7
1.8
3.1
V
V
VCCQ
S-VCC
P-VCC
Flash I/O Voltage
PSRAM and SRAM Supply Voltage
1.8 V I/O
1.95
1.95
1.95
VPPL
Flash Program Logic Level
0.9
1.95
0.9
1.95
0.9
1.95
V
V
VPPH
Flash Factory Program Voltage
11.4 12.6 11.4 12.6 11.4 12.6
1
Note:
1.
F-VPP is normally VPPL. F-VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks for extended
temperatures and 2500 cycles on parameter blocks at extended temperature.
2.
Devices available with -30o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1,
38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F2030W0YTQF,
38F2030W0YBQF, 38F2040W0YTQF, 38F2040W0YBQF
5.3
Capacitance
NOTICE: Refer to the Numonyx™ Wireless Flash Memory (W18) Datasheet
(order number 290701) and Numonyx™ Wireless Flash Memory (W30)
Datasheet (order number 290702) for flash capacitance details. For SCSP
products with two flash die, flash capacitances for each of the flash die need
to be considered accordingly.
Table 6:
Symbol
CIN
SRAM, PSRAM Capacitance
Parameter
Typ
10
Unit
pF
Condition
VIN = 0.0 V, Tc = 25 °C, f = 1 MHz
VOUT = 0.0 V, Tc = 25 °C, f = 1 MHz
Input Capacitance
Output Capacitance
COUT
10
pF
November 2007
Order Number: 251407-13
Datasheet
17
32WQ and 64WQ Family with Asynchronous RAM
6.0
Electrical Specifications
6.1
DC Characteristics
SRAM and PSRAM DC characteristics are shown in Table 7 and Table 8. Refer to the
Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and the
Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for flash DC
characteristics.
Table 7:
SRAM DC Characteristics
1.8 V SRAM
3.0 V SRAM
Parameter
Description
Test Conditions
Unit
Min
Max
Min
Max
S-VCC
VDR
Voltage Range
1.7
1.0
–
1.95
–
2.2
1.5
–
3.3
–
V
V
VCC for Data Retention
4M
8M
25
35
40
4
45
50
55
10
10
15
15
25
45
5
Operating Current at
min cycle time
ICC
ICC2
ISB
IIO = 0 mA
IIO = 0 mA
–
–
mA
mA
μA
16M
4M
–
–
–
–
Operating Current at
max cycle time (1 μs)
8M
–
6
–
16M
4M
–
10
12
20
30
6
–
S-CS1# ≥ S-VCC-0.2V
or S-CS2 ≤ VSS+0.2V
Address/Data toggling at
minimum cycle time
–
–
Standby Current
8M
–
–
16M
4M
–
–
1.8 V SRAM:
S-VCC = 1.0 V
3.0 V SRAM:
S-VCC = 1.5 V
–
–
Current in Data
Retention mode
8M
–
10
18
–
12
15
IDR
μA
16M
–
–
S-VCC
0.15
-
-
S-VCC
0.1
-
-
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = -100 μA
–
–
V
V
V
IOL = 100 μA,
-0.1
0.2
-0.1
0.1
VCCMIN
S-VCC
0.4
S-VCC
0.2
+
S-VCC
0.4
S-VCC
0.2
+
VIL
IOH
IOL
Input LOW Voltage
-0.2
–
0.4
–
-0.2
–
0.6
–
V
Output HIGH Current
Output LOW Current
Input Leakage Current
mA
mA
μA
–
–
–
–
*IIL
-0.2 < VIN < S-VCC + 0.2 V
-1
+1
-1
+1
-0.2 < VIN < S-VCC + 0.2 V
S-VCC = VDR
Input Leakage Current
in Data Retention Mode
*ILDR
-1
+1
-1
+1
μA
* Input leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state
outputs.
Datasheet
18
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 8:
Parameter
VCC
PSRAM DC Characteristics
1.8 V PSRAM
3.0 V PSRAM
Description
Test Conditions
Unit
Notes
Min
Max
Min
Max
Voltage Range
1.8
1.95
2.7
3.1
V
8M
16M
16M
32M
8M
–
–
–
–
–
–
–
–
–
30
20
35
–
–
–
–
–
–
–
–
–
30
35
–
mA
2
OperatingCurrent
at min cycle time
ICC
IIO = 0 mA
mA
mA
3
2
45
5
OperatingCurrent
at max cycle time
(1 μs)
ICC2
IIO = 0 mA
16M
32M
8M
5
7
mA
2
–
7
P-CS# ≥ P-VCC
-
–
80
0.2V.
μA
2, 4
All inputs stable
(either high or
low)
16M
16M
–
–
100
–
–
–
100
85
P-CS# ≥ P-VCC
-
ISB
Standby Current
0.2V or
P-Mode ≥ P-VCC
-
0.2V
μA
μA
2, 5
2, 4
Address/Data
toggling at
minimum cycle
time
32M
–
100
–
100
16M
32M
–
–
–
–
–
10
10
Deep Power-
Down
Isbd
VOH
VOL
VIH
P-Mode ≤ 0.2 V
30
0.8P -
VCC
IOH = -0.5 mA
–
–
2.4
–
–
V
V
4
5
Output HIGH
Voltage
P-VCC
0.3
-
-
IOH = -0.1 mA
IOL = 1 mA,
1.4
–
0.2P - VCC
0.2
–
0.4
0.3
V
V
4
5
Output LOW
Voltage
IOL = 0.1 mA, VCCMin
-0.1
-0.1
P-VCC
0.3
+
P-VCC
0.3
P-VCC
0.2
+
+
0.8P -VCC
V
V
4
5
Input HIGH
Voltage
P-VCC
0.3
-
P-VCC
0.2
+
P-VCC
0.4
-
P-VCC
0.2
–0.3
–0.2
0.2P - VCC
0.4
-0.2
-0.2
0.5
0.6
V
V
4
5
Input LOW
Voltage
VIL
Input Leakage
Current
-0.2 < VIN < P-VCC + 0.2
V
IIL
-1
-1
+1
+1
-1
-1
+1
+1
μA
μA
1, 2
1, 2
-0.2 < VIN < P-VCC + 0.2
V
Output Leakage
Current
IOL
P-VCC = VDR
Notes:
1.
2.
3.
4.
5.
Input Leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs.
All currents are in RMS unless noted otherwise.
Applicable only to parts 38F1030W0YxQF & 38F2030W0YxQF.
Applicable to parts with P-Mode pin (38F2030W0ZxQ1, 38F2040W0YxQ0, 28F2240WWYxQ0).
Applicable to No-P-Mode (38F1030W0YxQF, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1,
38F2030W0YxQF, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0).
November 2007
Order Number: 251407-13
Datasheet
19
32WQ and 64WQ Family with Asynchronous RAM
7.0
AC Characteristics
7.1
Flash AC Characteristics
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701)
and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702)
7.2
SRAM AC Characteristics
Table 9:
SRAM AC Characteristics
#
Symbol1
Parameter
Min
Max
Unit
Notes
R1
R2
R3
R3
R4
R5
R6
R7
R8
R9
tRC
tAA
Read Cycle Time
70
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Address to Output Delay
S-CS1# to Output Delay
S-CS2 to Output Delay
R-OE# to Output Delay
70
70
70
35
70
–
1
1
tCO1
tCO2
tOE
–
–
1
–
1
tBA
R-UB#, R-LB# to Output Delay
S-CS1# or S-CS2 to Output in Low-Z
R-OE# to Output in Low-Z
–
1
tLZ
5
1,3,4
1,4
1,2,3,4
1,2,4
tOLZ
tHZ
0
–
S-CS1# or S-CS2 to Output in High-Z
R-OE# to Output in High-Z
0
25
25
tOHZ
0
Output Hold (from Address, S-CS1#, S-CS2 or R-OE# Change,
whichever occurs first)
R10
tOH
0
–
ns
1
R11
R12
tBLZ
tBHZ
R-UB#, R-LB# to Output in Low-Z
R-UB#, R-LB# to Output in High-Z
0
0
–
ns
ns
1,4
1,4
25
Note:
1.
2.
See Figure 5, “AC Waveform SRAM Read Operations” .
Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
3.
4.
At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device
to device interconnection.
Sampled, but not 100% tested.
Datasheet
20
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 5: AC Waveform SRAM Read Operations
R1
Address Stable
Standby
ADDRESSES
S-CS1#
R3
R8
R9
R6
S-CS2
R7
R-OE#
R-WE#
R4
R2
R10
DATA
Valid Data
R11
R5
R12
R-UB#, R-LB#
November 2007
Order Number: 251407-13
Datasheet
21
32WQ and 64WQ Family with Asynchronous RAM
Table 10: SRAM AC Characteristics (Write)
#
Symbol1
Parameter
Min
Max
Unit
Notes
W1
W2
W3
W4
W5
W6
W7
W8
W9
tWC
tAS
Write Cycle Time
70
0
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1,4
1,2,3
1
Address Setup to R-WE# (S-CS1#) and R-UB#/R-LB# Low
R-WE# (S-CS1#) Pulse Width
tWP
tDW
tAW
tCW
tDH
tWR
tBW
55
30
60
60
0
Data to Write Time Overlap
Address Setup to R-WE# (S-CS1#) High
S-CS1# (R-WE#) Setup to R-WE# (S-CS1#) High
Data Hold from R-WE# (S-CS1#) High
Write Recovery
1
1
1
0
1,5
1
R-UB#, R-LB# Setup to R-WE# (S-CS1#) High
60
Notes:
1.
2.
See Figure 6, “AC Waveform SRAM Write Operations” .
A write occurs during the overlap (tWP) of low S-CS1# and low R-WE#. A write begins when S-CS1# goes low and R-
WE# goes low with asserting R-UB# and R-LB# for single byte operation or simultaneously asserting R-UB#R-LB# and
R-LB# for double byte operation. A write ends at the earliest high transition of S-CS1# and R-WE#.
tWP is measured from S-CS1# low to the end of a write.
3.
4.
5.
tAS is measured from the address valid to the beginning of a write.
tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CS1# or R-WE#
goes high.
Figure 6: AC Waveform SRAM Write Operations
W1
Standby
ADDRESSES
Address Stable
W6
W8
S-CS1#
S-CS2
R-OE#
W3
W5
R-WE#
DATA
W4
W7
Data In
W2
W9
R-UB#, R-LB#
7.3
PSRAM AC Characteristics
Table 11: PSRAM AC Characteristics (85ns or 88ns Initial Access) — Read Operations
1.8 V
Max
3.0 V
Max
#
Symbol
Parameter5
Unit
Notes
Min
Min
R1
R2
R3
tRC
tAA
tCO
Read Cycle Time
88
–
4,000
88
85
–
4,000
85
ns
ns
ns
Address to Output Delay
P-CS# to Output Delay
–
88
–
85
Datasheet
22
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 11: PSRAM AC Characteristics (85ns or 88ns Initial Access) — Read Operations
1.8 V
Max
3.0 V
Max
#
Symbol
Parameter5
Unit
Notes
Min
Min
R4
R5
R6
R7
R8
R9
tOE
tBA
R-OE# to Output Delay
–
–
65
88
–
–
–
40
85
–
ns
ns
ns
ns
ns
ns
R-UB#, R-LB# to Output Delay
P-CS# to Output in Low-Z
R-OE# to Output in Low-Z
P-CS# to Output in High-Z
R-OE# to Output in High-Z
tLZ
10
5
10
0
1,2
2
tOLZ
tHZ
–
–
–
25
25
0
25
25
1,2,3
2,3
tOHZ
–
0
Output Hold (from Address, P-CS# or R-
OE# change, whichever occurs first)
R10
tOH
5
–
0
–
ns
R11
R12
PR1
PR2
tBLZ
tBHZ
tPC
R-UB#, R-LB# to Output in Low-Z
R-UB#, R-LB# to Output in High-Z
Page Cycle Time
5
–
–
25
–
0
0
–
25
–
ns
ns
ns
ns
2
2
4
4
30
–
40
–
tPA
Page Access Time
30
35
Note:
1.
At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device
to device interconnection.
2.
3.
Sampled but not 100% tested.
Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
4.
5.
4-Word Page read only available for 32-Mbit PSRAM. No page mode feature for 16-Mbit PSRAM.
Applicable to parts with 85ns or 88ns initial access time: 38F2030W0ZxQ1, 38F2040W0YxQ0, 38F2040W0ZxQ0,
28F2240WWYxQ0.
November 2007
Order Number: 251407-13
Datasheet
23
32WQ and 64WQ Family with Asynchronous RAM
Table 12: PSRAM AC Characteristics (70ns Initial Access) — Read Operations
1.8 V
Max
3.0 V
Max
#
Symbol1
Parameter7
Unit
Notes
Min
Min
70
70
–
15000
8000
70
70
–
–
–
–
–
5
0
0
0
15000
–
R1
tRC
Read Cycle Time
ns
2
R2
R3
R4
R5
R6
R7
R8
R9
tAA
tCO
tOE
tBA
Address to Output Delay
P-CS# to Output Delay
70
70
45
70
–
ns
ns
ns
ns
ns
ns
ns
ns
–
70
R-OE# to Output Delay
–
45
R-UB#, R-LB# to Output Delay
P-CS# to Output in Low-Z
R-OE# to Output in Low-Z
P-CS# to Output in High-Z
R-OE# to Output in High-Z
–
70
tLZ
5
–
3
tOLZ
tHZ
tOHZ
0
–
–
0
25
25
25
3, 4
4
0
25
Output Hold (from Address, P-CS# or R-OE#
change, whichever occurs first)
R10
tOH
0
–
0
–
ns
R11
R12
PR1
PR2
tBLZ
tBHZ
tPC
R-UB#, R-LB# to Output in Low-Z
R-UB#, R-LB# to Output in High-Z
Page Cycle Time
0
0
–
25
0
0
–
25
–
ns
ns
ns
ns
ns
25
–
–
25
–
5
5
6
tPA
Page Access Time
25
25
4
tCEL
CE# low-time restriction
–
8,000
ns
Note:
1.
See Figure 7, “AC Waveform of PSRAM Read Operations” on page 25 and Figure 8, “AC
Waveform of PSRAM 4-Word Page Read Operation” on page 25
Spec’s only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF
At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device
to device interconnection.
2.
3.
4.
5.
Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
4-Word Page read only available for 16-Mbit PSRAM. No page mode feature for 8-Mbit PSRAM. Parts 38F1030W0YxQF &
38F2030W0YxQF do not support page mode, so this spec will not apply to them
CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns
Applicable to 70ns initial access P-SRAM’s ( 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQ2,
38F2030W0YxQF, 38F2030W0ZxQ2)
6.
7.
Datasheet
24
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 7: AC Waveform of PSRAM Read Operations
R1
R2
ADDRESSES
R3
R8
R12
R9
P-CS#
R5
R-UB#, R-LB#
R4
R-OE#
R7
R11
R6
R10
DATA
Valid Data
Figure 8: AC Waveform of PSRAM 4-Word Page Read Operation
R1
R2
A[Max:2]
A[1:0]
Valid Address
PR1
Valid Address
R3
Valid Address
Valid Address
Valid Address
R8
R9
P-CS#
R-OE#
R4
R7
R6
PR2
DATA
Valid Data
Valid Data
Valid Data
Valid Data
Note: Available only for 32-Mbit PSRAM and line items with 16-Mbit PSRAM (70 ns) 38F2030W0YTQ1,
38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0. Not
applicable to 8-Mbit PSRAM.
v
Table 13: PSRAM AC Characteristics—Write (Sheet 1 of 2)
1.8 V
Max
3.0 V
#
Symbol1
Parameter7
Unit Notes
Min
Min
Max
W1
W2
tWC
tAS
tWP
tDW
Write Cycle Time
70
8000
–
70
–
ns
Address Setup to R-WE#
0
0
–
ns
4
(P-CS#) and R-UB#, R-LB# going low
W3
W4
R-WE#(P-CS#) Pulse Width
Data to Write Time Overlap
55
35
–
–
55
35
–
–
ns
ns
2,3
November 2007
Order Number: 251407-13
Datasheet
25
32WQ and 64WQ Family with Asynchronous RAM
Table 13: PSRAM AC Characteristics—Write (Sheet 2 of 2)
1.8 V
Max
3.0 V
#
Symbol1
Parameter7
Unit Notes
Min
Min
Max
Address Setup to R-WE#
W5
W6
tAW
60
–
–
60
–
ns
ns
ns
(P-CS#) Going High
P-CS# (R-WE#) Setup to R-WE# (P-CS#)
Going High
tCW
60
60
–
Data Hold from R-WE#
(P-CS#) High
W7
W8
W9
tDH
tWR
tBW
0
0
–
–
–
0
0
–
–
–
Write Recovery
ns
ns
5
R-UB#, R-LB# Setup to R-WE# (P-CS#) Going
High
60
60
tCEL
P-CE# low-time restriction
Write High Pulse Width
–
8,000
–
–
–
–
–
ns
ns
7,8
8
W10
tWPH
10
Notes:
1.
2.
See Figure 9, “AC Waveform PSRAM Write Operation” .
A write occurs during the overlap (tWP) of low P-CS# and low R-WE#. A write begins when P-CS# goes low and R-WE#
goes low with asserting R-UB# or R-LB# for single byte operation or simultaneously asserting R-UB# and R-LB# for
double byte operation. A write ends at the earliest transition when P-CS# goes high and R-WE# goes high.
tWP is measured from P-CS# going low to end of a write.
3.
4.
5.
tAS is measured from the address valid to the beginning of a write.
tWR is measured from the end of a write to the address change. tWR applied in case a write ends as P-CS# or R-WE#
going high.
W3 is 70 ns for continuous write operations over 50 times.
P-CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns
Spec’s only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF
Applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2,
38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0.
6.
7.
8.
9.
Figure 9: AC Waveform PSRAM Write Operation
W1
W6
W2
ADDRESSES
P-CS#
W9
R-UB#, R-LB#
W8
W3
W5
R-WE#
DATA
W4
W7
Data In
Datasheet
26
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
7.4
Device AC Test Conditions
Figure 10: Transient Input/Output Reference Waveform
VCCQ, P-VCC
VCCQ/2,
P-VCC/2
VCCQ/2,
P-VCC/2
Test Points
Input
Output
0 V
Note: AC test inputs are driven to VCCQ, P-VCC for logic “1” and 0.0 V for logic “0”. input/output timing begins/ends at VCCQ/2,
P-VCC/2. Input rise and fall time (10% to 90%) < 5 ns. Worse case speed occurs at VCC = VCCMin
.
Figure 11: Transient Equivalent Testing Load Circuit
ZO = 50 Ohms
I/O
Output
CL= 30 pf
50
Ohms
P-VCC /2 = VCCQ/2
Notes:
1.
2.
Test configuration component value for worst case specification conditions.
CL includes jig capacitance.
November 2007
Order Number: 251407-13
Datasheet
27
32WQ and 64WQ Family with Asynchronous RAM
8.0
Flash Power Consumption
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701)
and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for
detailed information.
Datasheet
28
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
9.0
Device Operation
9.1
Bus Operations
Bus operations for the W18/W30 SCSP family involve the following chip enable and
output enable signals, respectively:
• F1-CE# for Flash Die#1 and F2-CE# for Flash Die#2
• F1-OE# for Flash Die#1 and F2-OE# for Flash Die#2
All other control signals are shared between the two flash die. Table to Table 16
explain the bus operations of products across this SCSP family. Refer to the W18/W30
discrete datasheets (order numbers 290701 and 290702) for single flash die SCSP bus
operations.
Table 14: Flash-Only Bus Operations
Mode
Flash
DOUT
Sync Array Read
All Async /
H
H
L
L
L
L
H
H
L
X
X
Active
H
H
X
X
2, 3, 4
Flash
DOUT
1, 3, 4,
5
X
Asserted
Sync Non-Array
Read
VPPL
or
VPPH
Flash
DIN
Write
H
L
H
L
X
Asserted
H
X
3, 4, 6
Flash
Output Disable
Standby
H
H
L
L
H
X
H
X
X
H
X
X
X
X
X
X
X
X
Active
High-Z
High-Z
X
X
X
X
X
X
4
4
4
High-Z
Flash
High-Z
Flash
High-Z
Reset
November 2007
Order Number: 251407-13
Datasheet
29
32WQ and 64WQ Family with Asynchronous RAM
Table 14: Flash-Only Bus Operations
Mode
Flash
DOUT
Sync Array Read
All Async /
Sync Non-Array
Read
H
H
H
H
X
X
H
H
L
X
X
Active
L
L
L
L
2, 3, 4
Flash
DOUT
1, 3, 4,
5
X
Asserted
VPPL
or
VPPH
Flash
DIN
Write
H
H
X
L
X
Asserted
L
H
3, 4, 6
Flash
High-Z
Output Disable
Standby
H
H
L
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
Active
High-Z
High-Z
L
H
X
H
X
X
4
4
4
Flash
High-Z
Flash
High-Z
Reset
Notes:
1.
For asynchronous read operation, both die may be simultaneously selected, but may not simultaneously drive the
memory bus. See Section 10.0, “Flash Command Definitions” on page 33 for details regarding flash
selection overlap.
2.
3.
WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. Refer to the W18 or W30
datasheet (order number 290701 and 29702) for further information regarding WAIT Signal.
For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular
flash die, F[2:1]-OE# will override F-WE#.
4.
5.
6.
L means VIL while H means VIH. X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP.
Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].
Refer to W18/W30 datasheet for valid DIN during flash writes.
Table 15: Flash + SRAM Bus Operations
Mode
Sync
Array
Read
Flash
DOUT
1, 2,
3, 5
H
H
H
L
L
L
L
L
H
H
L
L
X
L
X
X
Active
All Async/
Sync Non-
array
1, 2,
3, 5,
6
SRAM must be in High-Z
Flash
DOUT
Asserted
Asserted
Read
VPPL
or
VPPH
Flash
DIN
Write
H
3, 7
Output
Disable
Flash
High-Z
H
H
L
L
H
X
H
X
X
H
X
X
X
X
X
X
X
X
Active
High-Z
High-Z
5
5
5
Flash
High-Z
Standby
Reset
Any SRAM mode allowed
Flash
High-Z
Datasheet
30
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 15: Flash + SRAM Bus Operations
Mode
SRAM
DOUT
1, 4,
8, 2
Read
L
L
L
H
H
H
L
X
H
H
L
L
L
Flash must be in High-Z
Write
SRAM
DIN
4, 5,
8, 2
Output
Disable
SRAM
High-Z
H
X
5, 2
H
X
X
L
SRAM
High-Z
5, 8,
2
Standby
Any flash mode allowed
X
X
X
Data
Retention
SRAM
High-Z
Same as SRAM standby
9, 2
Notes:
1.
For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the
memory bus.
2.
3.
WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted.
For flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so, F[2:1]-OE# will
override F-WE#.
4.
5.
6.
7.
8.
9.
For SRAM, R-OE# and R-WE# should never be asserted simultaneously.
X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP.
Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].
Refer to W18 and W30 datasheet for valid DIN during flash writes.
The SRAM is enabled and/or disabled with the logical function: S-CS1# OR S-CS2.
The SRAM can be placed into data retention mode by lowering S-VCC to the VDR limit when in standby mode.
Table 16: Flash + PSRAM Bus Operations
Mode
Sync
Array
Read
Flash
DOUT
1, 2,
H
H
H
L
L
L
L
L
H
H
L
L
X
X
X
X
Active
3, 4, 6
All Async/
Sync Non-
array
1, 2,
3, 4,
6, 7
Flash
DOUT
Asserted
Asserted
PSRAM must be in High-Z
Read
VPPL
or
VPPH
Flash
DIN
3, 4,
6, 8
Write
H
Output
Disable
Flash
High-Z
H
H
L
L
H
X
H
X
X
H
X
X
X
X
X
X
X
X
Active
High-Z
High-Z
6
6
6
Flash
High-Z
Standby
Reset
Any PSRAM mode allowed
Flash
High-Z
November 2007
Order Number: 251407-13
Datasheet
31
32WQ and 64WQ Family with Asynchronous RAM
Table 16: Flash + PSRAM Bus Operations
Mode
PSRAM
DOUT
Read
L
L
H
H
H
H
L
H
H
X
H
L
L
L
1, 5, 2
5, 2
Flash#1 and #2 must be in High-Z
Write
PSRAM
DIN
Output
Disable
PSRAM
High-Z
L
H
X
X
X
6, 2
PSRAM
High-Z
Standby
H
6, 2
Any flash mode allowed
PSRAM
High-Z
Deep
Power-
Down
H
L
X
X
X
6, 9, 2
Notes:
1.
For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory
bus. For synchronous burst-mode reads, only two die (one flash and the PSRAM) may be simultaneously selected.
WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted.
F1-CE# for Flash Die#1, F2-CE# for Flash Die#2. F1-OE# is for Flash Die#1, F2-OE# for Flash Die#2.
For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash
die, F[2:1]-OE# will override F-WE#.
For PSRAM, R-OE# and R-WE# should never be asserted simultaneously.
X can be VIL or VIH for inputs, VPPL,VPPH or VPPLK for F-VPP.
Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].
Refer to W30/W18 datasheet for Valid DIN during flash writes.
Deep power-down is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1,
38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0.
2.
3.
4.
5.
6.
7.
8.
9.
Datasheet
32
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
10.0
Flash Command Definitions
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701)
and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for
detailed information regarding the following:
11.0
12.0
13.0
14.0
15.0
Flash Read Operations
Flash Program Operations
Flash Erase Operations
Flash Security Modes
Flash Read Configuration Register
November 2007
Order Number: 251407-13
Datasheet
33
32WQ and 64WQ Family with Asynchronous RAM
16.0
SRAM Operations
16.1
Power-up Sequence and Initialization
The SRAM functionality and reliability are independent of the power-up sequence and
power-up slew rate of the core S-VCC. Any power-up sequence and power-up slew rate
is possible under use conditions. SRAM reliability is also independent of the power-
down sequence and power-down slew rate of the core S-VCC.
16.2
Data Retention Mode
Table 17: SRAM Data Retention Operation
Symbol
Parameter
Min
Max
Unit
Notes
tSDR
tRDR
Data Retention Set-up Time
Data Retention Recovery Time
0
–
–
ns
ns
tRC
1
Note:
1.
tRC is defined in Table 9, “SRAM AC Characteristics” on page 20.
Figure 12: SRAM Data Retention Operation Waveform—S-CS1# Controlled
tRDR
tSDR
Data Retention Mode
S-VCC
S-VCCmin
S-VIHmin
VDR
S-CS1#
VSS
Datasheet
34
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 13: SRAM Data Retention Operation Waveform—S-CS2 Controlled
tSDR
tRDR
Data Retention Mode
S-VCC
S-CS2
S-VCCMIN
VDR
VILMAX
VSS
November 2007
Order Number: 251407-13
Datasheet
35
32WQ and 64WQ Family with Asynchronous RAM
17.0
PSRAM Operations
17.1
Power-Up Sequence and Initialization
The PSRAM functionality and reliability are independent of the power-up sequence and
slew rate of the core P-VCC. Any power-up sequence and slew rate is possible under use
conditions. PSRAM reliability are also independent of the power-down sequence and
slew rate of the core P-VCC
.
The following power-up sequence and register setting should be used before starting
normal operation. The PSRAM power-up sequence is represented in Figure 14.
Following power application, make P-Mode high after fixing P-Mode to a low level for a
period of tI1. Make P-CS# high before making P-Mode high. P-CS# and P-Mode are
fixed to a high level for period of tI3.
Figure 14: Timing Waveform for Power-Up Sequence
Register Setting
Power Up
P-VCC
tI2
P-CS#
tI1
tI3
P-MODE
Table 18: Power-Up Sequence Specifications
Parameter
Description
Min
50
Max
—
Unit
Notes
tI1
tI2
Power application with P-Mode held low
P-CS# high to P-Mode high
P-Mode high to P-CS# low
μs
ns
μs
1,2,3
10
—
tI3
500
—
Notes:
1.
2.
3.
Toggle P-Mode to low when starting the power-up sequence.
tI1 is specified from when the power supply voltage reaches VCCMIN
.
Does not apply to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1,
38F2030W0ZTQ2, and 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0 line items. Valid
PSRAM operations for these line items can begin 200 μs after P-Vcc has reached P-Vcc min.
17.1.1
16Mbit PSRAM Power-Up Sequence (Non-Page Mode)
For the non-page mode PSRAM (part’s RD38F1030W0YQF, PF38F1030W0YQF,
RD38F2030W0YQF, PF38F2030W0YQF) the PSRAM functionality and reliability must be
independent of the power-up sequence and power-up slew rate of the core Vcc and the
I/O Vcc (Vccq.) Any power-up sequence and power-up slew rate is possible under use
conditions. PSRAM reliability must also be independent of the power-down sequence
and power-down slew rate of the core Vcc and the I/O Vcc (Vccq.)
Once power supply voltages have reached the minimum spec value of 1.7V (or higher),
CE# must be maintained high for minimum 200us prior to commencing valid PSRAM
operation.
Datasheet
36
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
17.2
Standby Mode/ Deep Power-Down Mode
Caution:
All line items that do not have the P-Mode pine will not have the deep power-
down feature (38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1,
38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0).
Data is lost during deep power-down mode as shown in the Table below. Wake-up from
deep power-down mode involves the same initialization sequence as discussed in
Section 17.1, “Power-Up Sequence and Initialization” on page 36.
Mode
Memory Cell Data
Delay time to go Active
Standby
Valid
0 ns
Deep Power-Down
Invalid
Start-Up Sequence
Figure 15: Timing Waveform for Entering Deep Power-Down Mode
1 us
P-MODE
P-CS#
Suspend Mode
Deep Power Down Mode
Device Mode
17.3
PSRAM Special Read and Write Constraints
Caution:
This section will not apply to line items that do not have the P-Mode pine will
not have the deep power-down feature (38F1030W0YxQ2, 38F1030W0ZxQ0,
38F2030W0YxQ1, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2,
38F2040W0ZxQ0).
Table 19: PSRAM Special Read Constraints
Description
Min
Max
Unit
Notes
Cannot have sub tRC address toggle for more than 4 μs in active mode. Need
either a read operation or P-CS# high for tRC in that time frame
N/A
N/A
–
P-CS# high level pulse width
10
10
10
–
–
–
ns
ns
ns
ns
ns
1
1
R-UB#/R-LB# high level pulse width
R-OE# high level pulse width in active mode (P-CS# low)
P-CS# low to R-OE# low
10,000
10,000
10
Address Skew time (unstable address with P-CS# low)
Notes:
–
2
1.
2.
Toggling of these control signals is not necessary during address controlled read operations.
Address skew time (tSKEW) indicates the following three types of time depending on the condition.
a. When switching P-CS# from high to low, tSKEW is the time from the P-CS# low input point until the next address is
determined.
b. When switching P-CS# from low to high, tSKEW is the time from the address change start point to the P-CS# high input
point.
c. When P-CS# is fixed to low, tSKEW is the time from the address start point until the next address is determined.
Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to
limitations when P-CS# is switched from high to low following address determination, or
when the address is changed after P-CS# is switched from low to high.
November 2007
Order Number: 251407-13
Datasheet
37
32WQ and 64WQ Family with Asynchronous RAM
Table 20: PSRAM Special Write Constraints
Description
Min
Max
Unit
Notes
Need either R-WE# high or P-CS# high for at least tWC time, for every 4us
window during write operations.
N/A
N/A
–
R-OE# high to R-WE# low in active mode (P-CS# low)
R-WE# high to R-OE# low in active mode (P-CS# low)
Address Skew time (unstable address with P-CS# low)
Note:
0
10
–
10,000
10,000
10
ns
ns
ns
1
1.
Address skew time (tSKEW) indicates the following three types of time depending on the condition.
a. When switching P-CS# from high to low, tSKEW is the time from the P-CS# low input point until the next address is
determined.
b. When switching P-CS# from low to high, tSKEW is the time from the address change start point to the P-CS# high input
point.
c. When P-CS# is fixed to low, tSKEW is the time from the address start point until the next address is determined.
Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to limitations when P-CS# is switched from
high to low following address determination, or when the address is changed after P-CS# is switched from low to high.
Appendix A Write State Machine
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx
Wireless Flash Memory (W30) Datasheet (order number 290702) for the WSM details.
Appendix B Common Flash Interface
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx™
Wireless Flash Memory (W30) Datasheet (order number 290702) for the CFI details.
Appendix C Flash Flowcharts
Refer to the Numonyx™ Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx™
Wireless Flash Memory (W30) Datasheet (order number 290702) for the flash flowchart details.
Appendix D Additional Information
:
Order Number
Document
290701
290702
251216
Numonyx™ Wireless Flash Memory (W18) Datasheet
Numonyx™ Wireless Flash Memory (W30) Datasheet
64-Mbit 1.8 Volt Numonyx™ Wireless Flash Memory SCSP Family Application Note
Note: Contact your local Numonyx or distribution sales office or visit the Numonyx website at http://www.numonyx.com for
the most current information on Numonyx Flash memory products, software, and tools.
Datasheet
38
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Appendix E Ordering Information (Active Line Items)
Figure 16: Decoder for Flash + RAM SCSP Family Devices
R D 3 8 F 2 0 3 0 W 0 Z B Q 0
Device Details
Package
RD = SCSP
PF = Pb-free SCSP
0-9, A-D = 1st Generation, 130 nm
E-R = 2nd Generation, 90 nm
(note: 90 nm is only 1.8 V I/O)
S-Z = 3rd Generation, TBD
Product Line
Designator
Pinout Indicator
38F = Flash & RAM Stack Device
Q= QUAD+ ballout
Flash Density
2 = 64-Mbit
1 = 32-Mbit
0 = No die
Parameter Location
B = Bottom Parameter
T = Top Parameter
D = Dual Parameter
RAM Density
Voltage
4 = 32-Mbit
3 = 16-Mbit
2 = 8-Mbit
1 = 4-Mbit
0 = No Die
Y = 1.8 Volt I/O
Z = 3 Volt I/O
Product Family
W = Intel® Wireless Flash Memory
0 = No Die
November 2007
Order Number: 251407-13
Datasheet
39
32WQ and 64WQ Family with Asynchronous RAM
Table 21: Ordering Information on Active Line Items
Flash Component
RAM
Package
Product Number
PSRAM
Size in Mbit and
Family
Size in Mbit
and Type
Size (mm)
Ballout
Type
32M Flash + 16M PSRAM
PF38F1030W0YTQ2
PF38F1030W0YBQ2
70 ns,
16 PSRAM
16 PSRAM
16 PSRAM
No PMODE pin &
Non-Page Mode
Support
32 W18
8 x 10 x 1.2
8 x 10 x 1.2
Quad+
Quad+
Lead-free
Lead-free
PF38F1030W0YTQF
PF38F1030W0YBQF
PF38F1030W0ZTQ0
PF38F1030W0ZBQ0
70 ns,
32 W30
No PMODE pin
64M Flash + 16M PSRAM
PF38F2030W0YTQ1
PF38F2030W0YBQ1
70 ns,
16 PSRAM
16 PSRAM
16 PSRAM
No PMODE pin
PF38F2030W0YTQ2
PF38F2030W0YBQ2
70 ns,
64 W18
8 x 10 x 1.2
8 x 10 x 1.2
Quad+
Quad+
Lead-free
Lead-free
No PMODE pin &
Non-Page Mode
Support
PF38F2030W0YTQF
PF38F2030W0YBQF
PF38F2030W0ZTQ2
PF38F2030W0ZBQ2
70 ns,
64 W30
64M Flash + 32M PSRAM
64 W18
No PMODE pin
PF38F2040W0YTQ0
PF38F2040W0YBQ0
88 ns,
with PMODE pin
32 PSRAM
32 PSRAM
8 x 10 x 1.2
8 x 10 x 1.2
QUAD+
QUAD+
Lead-free
Lead-free
PF38F2040W0ZTQ1
PF38F2040W0ZBQ1
85 ns,
No PMODE pin
64 W30
Appendix F Ordering Information (Retired Line Items)
Shown here are the decoder for products in the SCSP family with both flash and RAM
and the decoder for products in the SCSP family with flash die only (no RAM). The
decoders are following by available product combinations.
Datasheet
40
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 17: Decoder for Flash + RAM SCSP Family Devices
R D 3 8 F 2 0 3 0 W 0 Z B Q 0
Device Details
Package
0-9, A-D = 1st Generation, 130 nm
E-R = 2nd Generation, 90 nm
(note: 90 nm is only 1.8 V I/O)
S-Z = 3rd Generation, TBD
RD = SCSP
PF = Pb-free SCSP
Product Line
Designator
38F = Flash & RAM Stack Device
Pinout Indicator
Q= QUAD+ ballout
Flash Density
2 = 64-Mbit
1 = 32-Mbit
0 = No die
Parameter Location
B = Bottom Parameter
T = Top Parameter
D = Dual Parameter
RAM Density
Voltage
4 = 32-Mbit
3 = 16-Mbit
2 = 8-Mbit
1 = 4-Mbit
0 = No Die
Y = 1.8 Volt I/O
Z = 3 Volt I/O
Product Family
W = Intel® Wireless Flash Memory
0 = No Die
November 2007
Order Number: 251407-13
Datasheet
41
32WQ and 64WQ Family with Asynchronous RAM
Figure 18: Decoder for Flash-Only SCSP Family Devices
R D 4 8 F 2 2 0 0 W 0 Z D Q 0
Device Details
0-9, A-D = 1sGt eneration, 130 nm
E-R = 2nd Generation, 90 nm
(note: 90 nm is only 1.8 V I/O)
S-Z = 3rd Generation, TBD
Package
RD = SCSP
PF = Pb-free SCSP
Product Line
Designator
Pinout Indicator
Q = QUAD+ Ballout
48F = Flash-only Stack Device
Parameter Location
Flash Density
D = Dual Parameter
T = Top Parameter
B = Bottom Parameter
2 = 64-Mbit
1 = 32-Mbit
0 = No Die
Voltage
Y = 1.8 Volt I/O
Z = 3 Volt I/O
Product Family
W = Intel® Wireless Flash Memory
0 = No Die
Datasheet
42
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 22: 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)
Package
Flash Component
Product Number (1,2,3,4,5)
Size (mm)
Type
Ballout
PF48F1000W0ZTQ0
PF48F1000W0ZBQ0
32 W30
8 x 10 x 1.2
Lead-free
Quad +
PF48F2000W0ZTQ0
PF48F2000W0ZBQ0
64 W30
8 x 10 x 1.2
8 x 10 x 1.2
Lead-free
Leaded
Quad +
Quad +
64 W18 + 64W18
RD48F2200W0YDQ0
November 2007
Order Number: 251407-13
Datasheet
43
32WQ and 64WQ Family with Asynchronous RAM
Notes:
1.
2.
3.
4.
W18 = Numonyx™ Wireless Flash Memory (W18); W30 = Numonyx™ Wireless Flash Memory (W30).
B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter.
T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter.
D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter.
Table 23: 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + SRAM)
Flash
Component
RAM
Package
Product Number(1,2,3,4)
Size in Mbit and
Family
Size in Mbit
and Type
Size (mm)
8 x 10 x 1.2
8 x 10 x 1.2
8 x 10 x 1.2
8 x 10 x 1.2
8 x 10 x 1.2
Type
Ballout
Quad+
Quad+
Quad+
Quad+
Quad+
RD38F2010W0YTQ0
RD38F2010W0YBQ0
4 SRAM
8 SRAM
16 SRAM
8 SRAM
16 SRAM
Leaded
Leaded
Leaded
Leaded
Leaded
RD38F2020W0YTQ0
RD38F2020W0YBQ0
64 W18
RD38F2030W0YTQ0
RD38F2030W0YBQ0
RD38F2020W0ZTQ0
RD38F2020W0ZBQ0
64 W30
RD38F2030W0ZTQ0
RD38F2030W0ZBQ0
64 W18 + 64 W18
64 W30 + 64 W30
16 SRAM
16 SRAM
8 x 10 x 1.4
8 x 10 x 1.4
Leaded
Leaded
Quad+
Quad+
RD38F2230WWYDQ0
RD38F2230WWZDQ0
Notes:
1.
2.
3.
4.
W18 = Numonyx™ Wireless Flash Memory (W18); W30 = Numonyx™ Wireless Flash Memory (W30).
B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter.
T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter.
D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter.
Table 24: 32WQ & 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 1
of 2)
Flash Component
RAM
Package
Product Number
(1,2,3,4,5)
PSRAM used
Size in Mbit and
Family
Size in Mbit
and Type
Size (mm)
Ballout
Type
70 ns,
RD38F1030W0YTQ2
RD38F1030W0YBQ2
No PMODE pin &
Non-Page Mode
Support
32 W18
16 PSRAM
8 x 10 x 1.2
Quad+
Leaded
RD38F1030W0ZTQ0
RD38F1030W0ZBQ0
70 ns,
32 W30
64 W18
16 PSRAM
16 PSRAM
8 x 10 x 1.2
8 x 10 x 1.2
Quad+
Quad+
Leaded
Leaded
No PMODE pin
RD38F2030W0YTQ1
RD38F2030W0YBQ1
70 ns,
No PMODE pin
70 ns,
RD38F2030W0YTQ2
RD38F2030W0YBQ2
No PMODE pin &
Non-Page Mode
Support
64 W18
16 PSRAM
8 x 10 x 1.2
Quad+
Leaded
RD38F2030W0ZTQ1
RD38F2030W0ZBQ1
85 ns,
64 W30
64 W30
16 PSRAM
16 PSRAM
8 x 10 x 1.2
8 x 10 x 1.2
Quad+
Quad+
Leaded
Leaded
with PMODE pin
RD38F2030W0ZTQ2
RD38F2030W0ZBQ2
70 ns,
No PMODE pin
Datasheet
44
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 24: 32WQ & 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 2
of 2)
Flash Component
RAM
Package
Product Number
(1,2,3,4,5)
PSRAM used
Size in Mbit and
Family
Size in Mbit
and Type
Size (mm)
8 x 10 x 1.2
8 x 10 x 1.2
8 x 10 x 1.2
8 x 10 x 1.4
8 x 10 x 1.4
Ballout
Type
RD38F2040W0YTQ0
RD38F2040W0YBQ0
88 ns,
64 W18
64 W30
32 PSRAM
32 PSRAM
32 PSRAM
32 PSRAM
32 PSRAM
QUAD+
QUAD+
QUAD+
QUAD+
QUAD+
Leaded
Leaded
Leaded
Leaded
Leaded
with PMODE pin
RD38F2040W0ZTQ0
RD38F2040W0ZBQ0
85 ns,
No PMODE pin
RD38F2040W0ZTQ1
RD38F2040W0ZBQ1
85 ns,
No PMODE pin
64 W30
RD38F2240WWYDQ0(6)
RD38F2240WWYDQ1
88 ns,
64 W18 + 64 W18
64 W30 + 64 W30
with PMODE pin
RD38F2240WWZDQ0
RD38F2240WWZDQ1
85 ns,
No PMODE pin
Notes:
1.
2.
3.
4.
5.
W18 = Numonyx™ Wireless Flash Memory (W18); W30 = Numonyx™ Wireless Flash Memory (W30).
B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter.
T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter.
D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter.
RD38F2240WWYDQ0 = Engineering Samples; RD38F2240WWYDQ1 = Production
November 2007
Order Number: 251407-13
Datasheet
45
32WQ and 64WQ Family with Asynchronous RAM
Datasheet
46
November 2007
Order Number: 251407-13
相关型号：
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