RD48F3000L0YCQ0 [NUMONYX]
Flash, 8MX16, 85ns, PBGA88,;
| 型号： | RD48F3000L0YCQ0 |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 8MX16, 85ns, PBGA88, |
| 文件： | 总98页 (文件大小：1152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Numonyx™ StrataFlash Wireless Memory
(L18) with AD-Multiplexed I/O
Datasheet
Product Features
High performance Read-While-Write/Erase
Power
— 1.7 V to 2.0 V VCC operation
— 85 ns initial access
— 54MHz with zero wait state, 14 ns clock-to-
data output synchronous-burst mode
— I/O voltage: 1.35 V – 2.0 V, 1.7 V– 2.0 V
— Standby current: 25 µA (Typ) for 256-Mbit
— 4-, 8-, 16-, and continuous-word burst
mode
— Burst suspend
— 4-Word synchronous read current: 15 mA
(Typ) @ 54 MHz
— Automatic Power Savings (APS) mode
— Programmable WAIT configuration
Security
— Buffered Enhanced Factory Programming
(Buffered EFP): 5 µs/byte (Typ)
— 1.8 V low-power buffered and non-buffered
programming @ 7 µs/byte (Typ)
— OTP space:
• 64 unique device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OTP
bits
Architecture
— Absolute write protection: VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64Mb and 128Mb
devices
— Multiple 16-Mbit partitions: 256Mb devices
— Four 16-KWord parameter blocks: top
configuration
— 64-KWord main blocks
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Dual-operation: Read-While-Write (RWW)
or Read-While-Erase (RWE)
— Intel® Flash Data Integrator (FDI)
optimized
— Status register for partition and device
status
Density and Packaging
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
Quality and Reliability
— 64-, 128-, and 256 Mbit density in VF BGA
package
— 16-bit wide data bus
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— Intel ETOX* VIII process technology (0.13
µm)
313295-04
November 2007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Numonyx B.V., All Rights Reserved.
Datasheet
2
November 2007
313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Contents
1.0 Introduction..............................................................................................................7
1.1
1.2
1.3
Nomenclature.....................................................................................................7
Acronyms...........................................................................................................7
Conventions .......................................................................................................8
2.0 Functional Overview..................................................................................................9
3.0 Package Information...............................................................................................10
4.0 Ballout and Signal Descriptions ...............................................................................12
4.1
4.2
Signal Descriptions............................................................................................ 13
Memory Map..................................................................................................... 15
5.0 Maximum Ratings and Operating Conditions............................................................ 17
5.1
5.2
Absolute Maximum Ratings.................................................................................17
Operating Conditions .........................................................................................17
6.0 Electrical Specifications........................................................................................... 18
6.1
6.2
DC Current Characteristics.................................................................................. 18
DC Voltage Characteristics.................................................................................. 19
7.0 AC Characteristics ................................................................................................... 20
7.1
7.2
7.3
7.4
7.5
7.6
7.7
AC Test Conditions ............................................................................................ 20
Capacitance......................................................................................................21
AC Read Specifications (VCCQ = 1.35 V – 2.0 V) ...................................................21
AC Read Specifications: 64- and 128-Mb Densities.................................................22
AC Read Specifications for 256-Mb Density ...........................................................23
AC Write Specifications ...................................................................................... 30
Program and Erase Characteristics....................................................................... 32
8.0 Power and Reset Specifications...............................................................................33
8.1
8.2
8.3
8.4
Power Up and Down .......................................................................................... 33
Reset...............................................................................................................33
Power Supply Decoupling ................................................................................... 34
Automatic Power Saving (APS)............................................................................ 35
9.0 Device Operations ................................................................................................... 36
9.1
Bus Operations .................................................................................................36
9.1.1 Reads................................................................................................... 36
9.1.2 Writes................................................................................................... 36
9.1.3 Output Disable.......................................................................................36
9.1.4 Standby................................................................................................37
9.1.5 Reset.................................................................................................... 37
Device Commands............................................................................................. 37
Command Definitions.........................................................................................38
9.2
9.3
10.0 Read Operations......................................................................................................41
10.1 Asynchronous Read Mode................................................................................... 41
10.2 Synchronous Burst-Mode Read............................................................................ 41
10.2.1 Burst Suspend .......................................................................................42
10.3 Read Configuration Register (RCR) ...................................................................... 42
10.3.1 Read Mode ............................................................................................ 43
10.3.2 Latency Count........................................................................................43
10.3.3 WAIT Polarity.........................................................................................45
10.3.3.1 WAIT Signal Function ................................................................45
10.3.4 Data Hold.............................................................................................. 46
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Datasheet
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
10.3.5 WAIT Delay............................................................................................46
10.3.6 Burst Sequence......................................................................................47
10.3.7 Clock Edge.............................................................................................47
10.3.8 Burst Wrap ............................................................................................48
10.3.9 Burst Length..........................................................................................48
11.0 Programming Operations.........................................................................................49
11.1 Word Programming............................................................................................49
11.1.1 Factory Word Programming......................................................................50
11.2 Buffered Programming .......................................................................................50
11.3 Buffered Enhanced Factory Programming..............................................................51
11.3.1 Buffered EFP Requirements and Considerations...........................................51
11.3.2 Buffered EFP Setup Phase........................................................................52
11.3.3 Buffered EFP Program/Verify Phase...........................................................52
11.3.4 Buffered EFP Exit Phase...........................................................................53
11.4 Program Suspend ..............................................................................................53
11.5 Program Resume ...............................................................................................53
11.6 Program Protection ............................................................................................53
12.0 Erase Operations......................................................................................................55
12.1 Block Erase.......................................................................................................55
12.2 Erase Suspend ..................................................................................................55
12.3 Erase Resume ...................................................................................................56
12.4 Erase Protection ................................................................................................56
13.0 Security Modes ........................................................................................................57
13.1 Block Locking....................................................................................................57
13.1.1 Lock Block .............................................................................................57
13.1.2 Unlock Block ..........................................................................................57
13.1.3 Lock-Down Block ....................................................................................57
13.1.4 Block Lock Status ...................................................................................58
13.1.5 Block Locking During Suspend..................................................................58
13.2 Protection Registers ...........................................................................................59
13.2.1 Reading the Protection Registers...............................................................60
13.2.2 Programming the Protection Registers .......................................................61
13.2.3 Locking the Protection Registers ...............................................................61
14.0 Dual-Operation Considerations ................................................................................62
14.1 Memory Partitioning...........................................................................................62
14.2 Read-While-Write Command Sequences................................................................62
14.2.1 Simultaneous Operation Details................................................................63
14.2.2 Synchronous and Asynchronous Read-While-Write Characteristics and
Waveforms ............................................................................................63
14.2.2.1 Write operation to asynchronous read transition............................63
14.2.2.2 Write to synchronous read operation transition..............................63
14.2.2.3 Write Operation with Clock Active................................................64
14.2.3 Read Operation During Buffered Programming Flowchart..............................64
14.2.4 Simultaneous Operation Restrictions .........................................................64
15.0 Special Read States..................................................................................................66
15.1 Read Status Register..........................................................................................66
15.1.1 Clear Status Register ..............................................................................67
15.2 Read Device Identifier ........................................................................................67
15.3 CFI Query.........................................................................................................68
A
B
Write State Machine.................................................................................................69
Flowcharts...............................................................................................................76
Datasheet
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November 2007
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
B.1
B.2
B.3
B.4
B.5
B.6
Common Flash Interface (CFI) ............................................................................ 83
Query Structure Output...................................................................................... 84
Query Structure Overview .................................................................................. 84
CFI Query Identification String............................................................................ 85
Device Geometry Definition ................................................................................87
Intel-Specific Extended Query Table..................................................................... 88
C
Ordering Information .............................................................................................. 96
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Datasheet
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Revision History
Date
Revision Description
May 2006
July 2006
001
002
003
04
Initial Release
Removed Intel Confidential status.
Updated ordering information
Applied Numonyx branding.
August 2007
November 2007
Datasheet
6
November 2007
313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
1.0
Introduction
This document provides information about the Numonyx™ StrataFlash® Wireless
Memory (L18) with AD-Multiplexed I/O device. This document describes device
features, operation, and specifications.
The Numonyx™ StrataFlash® Wireless Memory (L18) with AD-Multiplexed I/O product
is the latest generation of Intel StrataFlash® memory featuring flexible, multiple-
partition, dual operation. It provides high performance asynchronous read mode and
synchronous-burst read mode using 1.8 V low-voltage, multi-level cell (MLC)
technology.
The multiple-partition architecture enables background programming or erasing to
occur in one partition while code execution or data reads take place in another
partition. This dual-operation architecture also allows two processors to interleave code
operations while program and erase operations take place in the background. 8-Mbit
partitions allow system designers to choose the size of the code and data segments.
The Numonyx™ StrataFlash® Wireless Memory (L18) with AD-Multiplexed I/O device is
manufactured using Intel 0.13 µm ETOX™ VIII process technology, available in
industry-standard chip scale packaging.
1.1
Nomenclature
1.8 V
Vcc voltage range of 1.7 V – 2.0 V (except where noted)
1.8 V Extended Range
VPP = 9.0 V
Vccq voltage range of 1.35 V – 2.0 V
VPP voltage range of 8.5 V – 9.5 V
A group of bits, bytes or words within the flash memory array that erase simultaneously when the
Erase command is issued to the device. The device has two block sizes: 16K-Word and 64K-Word.
Block
An array block that is usually used to store code and/or data. Main blocks are larger than parameter
blocks.
Main block
Parameter block
An array block that is usually used to store frequently changing data or small system parameters
that traditionally would be stored in EEPROM.
Previously referred to as a top-boot device, a device with its parameter partition located at the
highest physical address of its memory map. Parameter blocks within a parameter partition are
located at the highest physical address of the parameter partition.
Top parameter device
Partition
A group of blocks that share common program/erase circuitry. Blocks within a partition also share a
common status register. If any block within a partition is being programmed or erased, only status
register data (rather than array data) is available when any address within that partition is read.
Main partition
A partition containing only main blocks.
Parameter partition
A partition containing parameter blocks and main blocks.
1.2
Acronyms
CUI
MLC
OTP
PLR
PR
Command User Interface
Multi-Level Cell
One-Time Programmable
Protection Lock Register
Protection Register
November 2007
Order Number: 313295-04
Datasheet
7
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
RCR
SR
Read Configuration Register
Status Register
WSM
Write State Machine
1.3
Conventions
VCC
VCC
Signal or voltage connection
Signal or voltage level
0x
0b
Hexadecimal number prefix
Binary number prefix
SR[4]
A[15:0]
A5
Denotes an individual register bit
Denotes a group of similarly named signals, such as address or data bus
bit
Binary unit
byte
word
Eight bits
Two bytes, or sixteen bits
Kbit
1024 bits
KByte
KWord
Mbit
1024 bytes
1024 words
1,048,576 bits
1,048,576 bytes
1,048,576 words
MByte
MWord
Datasheet
8
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
2.0
Functional Overview
The Numonyx™ StrataFlash® Wireless Memory (L18) with AD-Multiplexed I/O device
provides read-while-write and read-while-erase capability with density upgrades
through 256-Mbit. This device provides high performance at low voltage on a 16-bit
data bus. Individually erasable memory blocks are sized for optimum code and data
storage.
Each device density contains one parameter partition and several main partitions. The
flash memory array is grouped into multiple 8-Mbit partitions for the 64-Mbit and
128-Mbit devices, and into multiple 16-Mbit partitions for the 256-Mbit device. By
dividing the flash memory into partitions, program or erase operations can take place
at the same time as read operations.
Although each partition has write, erase and burst read capabilities, simultaneous
operation is limited to write or erase in one partition while other partitions are in read
mode. The device allows burst reads that cross partition boundaries. User application
code is responsible for ensuring that burst reads don’t cross into a partition that is
programming or erasing.
Upon initial power up or return from reset, the device defaults to asynchronous read
mode. Configuring the Read Configuration Register enables synchronous burst-mode
reads. In synchronous burst mode, output data is synchronized with a user-supplied
clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast factory program and erase operations. Designed for low-
voltage systems, it supports read operations with VCC at 1.8 V, and erase and program
operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming
(Buffered EFP) provides the fastest flash array programming performance with VPP at
9.0 V, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be tied
together for a simple, ultra low power design. In addition to voltage flexibility, a
dedicated VPP connection provides complete data protection when VPP is less than
VPPLK
.
A Command User Interface (CUI) is the interface between the system processor and all
internal operations of the device. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each
erase operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations. Data is
programmed in word increments (x16).
The Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) device offers power
savings through Automatic Power Savings (APS) mode and standby mode. The device
automatically enters APS following read-cycle completion. Standby is initiated when the
system deselects the device by deasserting CE# or by asserting RST#. Combined,
these features can significantly reduce power consumption.
The device’s protection register allows unique flash device identification that can be
used to increase system security. Also, the individual Block Lock feature provides zero-
latency block locking and unlocking.
November 2007
Order Number: 313295-04
Datasheet
9
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
3.0
Package Information
Figure 1: 64- and 128-Mbit, 88-ball (80-active ball) (8x10x1.2 mm)
A 1 I n d e x
M a rk
S 1
8
7
6
5
4
3
2
1
2
3
4
5
6
7
8
1
S
2
A
A
B
C
B
C
D
D
E
E
F
F
D
e
G
G
H
H
J
J
K
K
L
L
M
M
b
E
B o t t o m V ie w
Up
-
B a ll
T o p V ie w
-
B a ll
D
o w n
A
2
A
1
A
Y
D r a w in g n o t to s c a le .
M il li m e te r s
N o m
I nc h e s
D i m e n s io n s
S y m bo l
M i n
M a x
N o t e s
M in
N o m
M a x
Pa c k a g e H e ig h t
A
1 .2 0 0
0 . 0 4 7 2
B a ll H e ig h t
A 1
A 2
0 .2 0 0
0 .0 0 7 9
Pa c k a g e B o d y T h ic k n e s s
B a ll (L e a d ) id th
Pa c k a g e B o d y L e n g th
0 . 8 6 0
0 .0 3 3 9
W
b
0 .3 2 5
9 .9 0 0
7 .9 0 0
0 . 3 7 5
1 0 .0 0 0
8 . 0 0 0
0 .4 2 5
0 .0 1 2 8
0 .3 8 9 8
0 .3 1 1 0
0 .0 1 4 8
0 .3 9 3 7
0 .3 1 5 0
0 . 0 1 6 7
0 . 3 9 7 6
0 . 3 1 8 9
D
E
1 0 .1 0 0
8 .1 0 0
Pa c k a g e B o d y
Pitc h
W id th
e
0 . 8 0 0
8 8
0 .0 3 1 5
8 8
B a ll (L e a d ) C o u n t
Se a tin g P la n e C o p la n a rity
N
Y
0 .1 0 0
1 .3 0 0
0 .7 0 0
0 . 0 0 3 9
0 . 0 5 1 2
0 . 0 2 7 6
C o r n e r t o B a ll A 1 D is ta n c e A lo n g
C o r n e r t o B a ll A 1 D is ta n c e A lo n g
E
S 1
S 2
1 .1 0 0
0 .5 0 0
1 . 2 0 0
0 . 6 0 0
0 .0 4 3 3
0 .0 1 9 7
0 .0 4 7 2
0 .0 2 3 6
D
Datasheet
10
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 2: 256-Mbit, 88-ball (80-active ball) (8x11x1.0 mm)
A
1
M
I n d e x
a r k
S
1
8
7
6
5
4
3
2
1
2
3
4
5
6
7
8
1
S
2
A
A
B
C
B
C
D
D
E
F
E
F
D
e
G
G
H
H
J
J
K
K
L
L
M
M
b
E
T
o p
V
ie
w
-
B
a ll
D
o w
n
B
o t t o
m
V
i e w
-
B
A
a
ll
U
p
A
2
A
1
Y
D
r a w i n g n o t t o s c a l e .
N o t e : D im e n s io n s A 1 , A 2 , a n d
b
a r e p r e lim in a r y
M
i l l i m e t e r s
N o m
In c h e s
D
i m e n s i o n s
S
y m b o l
M
i n
M
a x
N
o te s
M
i n
N
o m
M
a x
P a c k a g e
H
e ig h t
A
1 . 0 0
0 . 0 3 9 4
B a ll
H
e ig h t
A
A
1
2
0 . 1 1 7
0 . 0 0 4 6
P a c k a g e B o d y T h ic k n e s s
0 .7 4 0
0 .3 5 0
1 1 . 0 0
8 . 0 0
0 . 8 0
8 8
0 . 0 2 9 1
0 . 0 1 3 8
0 . 4 3 3 1
0 . 3 1 5 0
0 . 0 3 1 5
8 8
B a ll ( L e a d )
W
id t h
b
0 . 3 0 0
1 0 . 9 0 0
7 . 9 0 0
0 . 4 0 0
1 1 . 1 0 0
8 . 1 0 0
0 . 0 1 1 8
0 . 4 2 9 1
0 . 3 1 1 0
0 . 0 1 5 7
0 . 4 3 7 0
0 . 3 1 8 9
P a c k a g e B o d y L e n g t h
D
E
e
P a c k a g e B o d y
P it c h
W
id t h
B a ll ( L e a d ) C o u n t
N
Y
S e a t in g P la n e C o p la n a r it y
0 . 1 0 0
1 . 3 0 0
1 . 2 0 0
0 . 0 0 3 9
0 . 0 5 1 2
0 . 0 4 7 2
C o r n e r t o B a ll
C o r n e r t o B a ll
A
A
1
1
D is t a n c e
D is t a n c e
A
A
lo n g
lo n g
E
S 1
S 2
1 . 1 0 0
1 . 0 0 0
1 .2 0 0
1 .1 0 0
0 . 0 4 3 3
0 . 0 3 9 4
0 . 0 4 7 2
0 . 0 4 3 3
D
November 2007
Order Number: 313295-04
Datasheet
11
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
4.0
Ballout and Signal Descriptions
Table 1:
QUAD+ Ballout
Pin 1
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
A4
DU
DU
DU
A
B
C
D
E
F
A18
R-LB#
A17
A19
A23
VSS
VSS
F1-VCC
S-CS2
R-WE#
ADV#
F-WE#
DQ5
F2-VCC
CLK
A21
A22
A11
A12
A5
A3
A24
F-VPP
F-WP#
F-RST#
DQ10
DQ3
P1-CS#
A20
A9
A13
A2
A7
A25
A10
A15
A1
A6
R-UB#
DQ2
A8
A14
A16
G
H
J
A0
DQ8
DQ13
DQ14
DQ6
WAIT
DQ7
DQ15
VCCQ
VSS
F2-CE#
F2-OE#
VCCQ
G
H
J
R-OE#
S-CS1#
F1-CE#
VSS
DQ0
DQ1
DQ12
DQ4
F1-OE#
P2-CS#
VSS
DQ9
DQ11
S-VCC
F1-VCC
P-Mode# /
P-CRE
F3-CE#
VCCQ
P-VCC
VSS
F2-VCC
VSS
K
L
K
L
VSS
DU
DU
DU
DU
M
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Legend:
Active Signals
De-Populated Balls
Do Not Use
Datasheet
12
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
4.1
Signal Descriptions
Table 2:
Signal Descriptions (Sheet 1 of 3)
Note
s
Symbol
Type
Signal Descriptions
Address and Data Signals, AD-Mux
ADDRESS: Global device signals.
Shared address inputs for all memory die during Read and Write operations.
•
•
•
•
•
256-Mbit: AMAX = A23
128-Mbit: AMAX = A22
64-Mbit: AMAX = A21
A[MAX:16
]
Input
A0 is the lowest-order word address.
Unused address inputs should be treated as RFU.
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux I/O flash signals.
During AD-Mux Read cycles, DQ[15:0] are used to input the lower address followed by read-data
output. During AD-Mux Write cycles, DQ[15:0] are used to input the lower address followed by
commands or data.
Input /
Output
DQ[15:0]
1
•
•
DQ[15:0] are High-Z when the device is deselected or its output is disabled.
DQ[15:0] is only used with AD-Mux I/O flash device.
Control Signals
ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input.
•
During a synchronous flash Read operation, the address is latched on the rising edge of ADV#
or the first active CLK edge whichever occurs first. In an asynchronous flash Read operation,
the address is latched on the rising edge of ADV# or continuously flows through while ADV#
is low.
ADV#
Input
•
During synchronous PSRAM read and synchronous write modes, the address is either latched
on the first rising clock edge after ADV# assertion or on the rising edge of ADV# whichever
edge comes first. In asynchronous read and asynchronous write modes, ADV# can be used to
latch the address, but can be held low for the entire operation as well.
Note: During A/D-Mux I/O operation, ADV# must remain deasserted during the data phase.
FLASH CHIP ENABLE: Flash-specific signal; low-true input.
When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the
associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs
are placed in a High-Z state.
F[3:1]-
CE#
Input
•
•
F1-CE# is dedicated to flash die #1.
F[3:2]-CE# are dedicated to flash die #3 through #2, respectively, if present. Otherwise, any
unused flash chip enable should be treated as RFU.
CLOCK: Flash- and Synchronous PSRAM-specific input signal.
CLK
Input
Input
CLK synchronizes the flash and/or synchronous PSRAM with the system clock during synchronous
operations.
FLASH OUTPUT ENABLE: Flash-specific signal; low-true input.
When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE# disables
the output drivers of the selected flash die and places the output drivers in High-Z.
F[2:1]-
OE#
•
F2-OE# common to all other flash dies, if present. Otherwise it is an RFU, however, it is highly
recommended to always common F1-OE# and F2-OE# on the PCB.
RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input.
When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE#
disables the output drivers of the selected memory die and places the output drivers in High-Z. If
device not present, treat as RFU.
R-OE#
Input
Input
2
FLASH RESET: Flash-specific signal; low-true input.
F-RST#
When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables
normal operation.
November 2007
Order Number: 313295-04
Datasheet
13
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 2:
Signal Descriptions (Sheet 2 of 3)
Note
Symbol
Type
Signal Descriptions
s
WAIT: Flash -and Synchronous PSRAM-specific signal; configurable true-level output.
When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid output
data.
WAIT
Output
•
WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output
enable is low.
•
WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output enable
is high.
FLASH WRITE ENABLE: Flash-specific signal; low-true input.
F-WE#
R-WE#
Input
Input
When low, F-WE# enables Write operations for the enabled flash die. Address and data are latched
on the rising edge of F-WE#.
RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input.
2
When low, R-WE# enables Write operations for the selected memory die. Data is latched on the
rising edge of R-WE#. If device not present, treat as RFU.
FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.
When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-
Down function, enabling locked-down blocks to be unlocked with the Unlock command.
F-WP#
Input
•
•
F-WP1# is dedicated to flash die #1.
F-WP2# is common to all other flash dies, if present. Otherwise it is an RFU.
PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input.
When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control
Register (P-BCR). When low, P-CRE enables normal Read or Write operations. If PSRAM not
present, treat as RFU.
P-CRE
Input
Input
3
3
PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input.
When low, P-MODE# enables access to the configuration register, and to enter or exit Low-Power
mode. When high, P-MODE# enables normal Read or Write operations. If PSRAM not present,
treat as RFU.
P-MODE#
PSRAM CHIP SELECT: PSRAM-specific signal; low-true input.
When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the
associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT
outputs are placed in a High-Z state.
P[2:1]-
CS#
Input
•
•
P1-CS# is dedicated to PSRAM die #1. If PSRAM not present, treat as RFU.
P2-CS# is dedicated to PSRAM die #2. If PSRAM not present, treat as RFU.
SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input.
S-CS1#
S-CS2
When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or
S-CS2 is deasserted, the SRAM die is deselected.
Input
Input
2
2
•
S-CS1# and S-CS2 are dedicated to SRAM when present. If SRAM not present, treat as RFU.
RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs.
R-UB#
R-LB#
When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read
and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0]. If device not
present, treat as RFU./
Power Signals
FLASH PROGRAM/ERASE VOLTAGE: Flash specific.
F-VPP supplies program or erase power to the flash die.
F-VPP
Power
FLASH CORE POWER SUPPLY: Flash specific.
Power F[2:1]-VCC supplies the core power to the flash die.
F2-VCC is recommended to be tied to F1-VCC, else it is an RFU.
F[2:1]-
VCC
I/O POWER SUPPLY: Global device I/O power.
Power
VCCQ
P-VCC
S-VCC
VCCQ supplies the device input/output driver voltage.
PSRAM CORE POWER SUPPLY: PSRAM specific.
P-VCC supplies the core power to the PSRAM die. If PSRAM not present, treat as RFU.
Power
2
2
SRAM POWER SUPPLY: SRAM specific.
Power
S-VCC supplies the core power to the SRAM die. If SRAM not present, treat as RFU.
Datasheet
14
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 2:
Signal Descriptions (Sheet 3 of 3)
Note
s
Symbol
Type
Signal Descriptions
DEVICE GROUND: Global ground reference for all signals and power supplies.
Connect all VSS balls to system ground. Do not float any VSS connections.
Groun
d
VSS
DU
DO NOT USE:
—
—
This ball should not be connected to any power supplies, signals, or other balls. This ball can be
left floating.
RESERVED for FUTURE USE:
RFU
Reserved by Intel for future device functionality and enhancement. This ball must be left floating.
Notes:
1.
2.
3.
Only used when AD-Mux I/O flash is present.
Only available on stacked device combinations with PSRAM, and/or SRAM die. Otherwise treated as RFU.
P-CRE and P-MODE# share the same package ball at location K8. Only one signal function is available, depending on the
stacked device combination.
4.2
Memory Map
The 64Mb and 128Mb memory array is divided into multiple 8-Mbit partitions. Each
device density contains one parameter partition and several main partitions. The 8-Mbit
top parameter partition contains four 16K-Word blocks and seven 64K-Word blocks.
There are multiple 8-Mbit main partitions. The 8-Mbit main partitions each contains
eight 64K-Word blocks.
The device multi-partition architecture is divided as follow:
• The 64-Mbit device contains eight partitions: one 8-Mbit parameter partition,
seven 8-Mbit main partitions.
• The 128-Mbit device contains sixteen partitions: one 8-Mbit parameter partition,
fifteen 8-Mbit main partitions.
The 256Mb memory array is divided into multiple 16-Mbit partitions. Each device
contains one parameter partition and fifteen main partitions. The 16-Mbit top
parameter partition contains four 16K-Word blocks and fifteen 64K-Word blocks. There
are fifteen 16-Mbit main partitions. The 16-Mbit main partitions each contains sixteen
64K-Word blocks.
Table 3:
Top Parameter Memory Map, 128-Mbit (Sheet 1 of 2)
Size (KW)
Blk
43
64-Mbit
Size (KW)
Blk
128-Mbit
16
66
65
64
63
62
3FC000-3FFFFF
3F8000-3FBFFF
3F4000-3F7FFF
3F0000-3F3FFF
3E0000-3EFFFF
16
16
16
16
64
130
129
128
127
126
7FC000-7FFFFF
7F8000-7FBFFF
7F4000-7F7FFF
7F0000-7F3FFF
7E0000-7EFFFF
16
16
16
64
64
56
380000-38FFFF
64
120
780000-78FFFF
November 2007
Order Number: 313295-04
Datasheet
15
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 3:
Top Parameter Memory Map, 128-Mbit (Sheet 2 of 2)
Size (KW)
Blk
64-Mbit
Size (KW)
Blk
128-Mbit
43
64
64
55
370000-37FFFF
000000-00FFFF
64
119
0
770000-77FFFF
000000-00FFFF
0
64
64
64
Table 4:
Top Parameter Memory Map, 256-Mbit
Size (KW)
Blk
256-Mbit
16
16
16
16
64
258
257
256
253
254
FFC000-FFFFFF
FF8000-FFBFFF
FF4000-FF7FFF
FF0000-FF3FFF
FE0000-FEFFFF
64
64
240
239
F00000-FFFFFF
EF0000-EFFFFF
64
64
128
127
800000-80FFFF
7F0000-7FFFFF
64
0
000000-00FFFF
Datasheet
16
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only.
Table 5:
Absolute Maximum Ratings Table
Parameter
Maximum Rating
Notes
Temperature under bias
Storage temperature
–25 °C to +85 °C
–65 °C to +125 °C
–0.5 V to +2.5 V
–0.2 V to +10 V
–0.2 V to +2.5 V
–0.2 V to +2.5 V
100 mA
Voltage on any signal (except VCC, VPP)
VPP voltage
1
1,2,3
VCC voltage
1
1
4
VCCQ voltage
Output short circuit current
Notes:
1.
Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on
VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on
VCC is VCC +0.5 V, which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. Maximum DC voltage on
input/output signals and VCCQ is VCCQ +0.5 V, which, during transitions, may overshoot to VCCQ +2.0 V for periods <20
ns.
2.
3.
Maximum DC voltage on VPP may overshoot to +10.0 V for periods <20 ns.
Program/erase voltage is typically 1.7 V to 2.0 V. 9 V can be applied for 80 hours maximum total, to any blocks for 1000
cycles maximum. 9 V program/erase voltage may reduce block cycling capability.
4.
Output shorted for no more than one second. No more than one output shorted at a time.
5.2
Operating Conditions
Warning:
Operation beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions” may affect device reliability.
Table 6:
Operating Conditions Table
Symbol
Parameter
Min
Max
Units
Notes
TC
Operating Temperature
VCC Supply Voltage
–25
1.7
+85
2.0
2.0
2.0
2.0
9.5
80
°C
V
VCC
1.8 V Range
1.7
V
VCCQ
I/O Supply Voltage
1.8 V Extended Range
1.35
0.9
V
VPPL
VPPH
tPPH
VPP Voltage Supply (Logic Level)
Factory programming VPP
Maximum VPP Hours
V
8.5
VPP = VPPH
VPP = VCC
Hours
Main and Parameter Blocks
Main Blocks
100,000
Block
Erase
Cycles
1
VPP = VPPH
VPP = VPPH
1000
2500
Cycles
Parameter Blocks
Notes:
1.
2.
TC = Case Temperature
In typical operation, the VPP program voltage is VPPL. VPP can be connected to 8.5 V – 9.5 V for 1000 cycles on main
blocks, and 2500 cycles on parameter blocks.
November 2007
Order Number: 313295-04
Datasheet
17
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
6.0
Electrical Specifications
6.1
DC Current Characteristics
Table 7:
DC Current Characteristics (Sheet 1 of 2)
VCC
1.7 V – 2.0 V
1.7 V – 2.0 V
1.35 V – 2.0 V
Sym
Parameter
VCCQ
Unit
Test Conditions
Notes
Typ
Max
VCC = VCC MAX
VCCQ = VCCQ Max
VIN = VCCQ or GND
ILI
Input Load Current
Output
±1
µA
µA
1
VCC = VCC MAX
VCCQ = VCCQ Max
VIN = VCCQ or GND
ILO
Leakage
Current
AD[15:0], WAIT
±1
64 Mbit
15
20
30
70
VCC = VCCMax
VCCQ = VCCQMax
CE# = VCCQ
RST# = VCCQ (for ICCS
RST# = GND (for ICCD
WP# = VIH
128
Mbit
ICCS
ICCD
VCC Standby,
Power Down
µA
1,2
)
)
256
Mbit
25
15
20
110
30
64 Mbit
VCC = VCC MAX
VCCQ = VCCQ Max
CE# = VSSQ
128
Mbit
70
ICCAPS APS
µA
RST# = VCCQ
All inputs are at rail to rail (VCCQ or
VSSQ).
256
25
13
110
15
Mbit
Asynchronous Single-Word
f = 5MHz (1 CLK)
mA
12
14
16
16
18
20
mA Burst length=4
mA Burst length=8
mA Burst length=16
1
Synchronous Burst Read
f = 40MHz, LC = 3
VCC = VCCMAX
CE# = VIL
OE# = VIH
Average
VCC Read
Current
Burst length =
mA
ICCR
20
25
Continuous
Inputs: VIL or VIH
15
18
21
18
22
25
mA Burst length=4
mA Burst length=8
mA Burst length=16
Synchronous Burst Read
f = 54MHz, LC = 4
Burst Length =
mA
22
27
Continuous
35
25
15
50
32
30
mA VPP = VPPL, program/erase in progress
mA VPP = VPPH, program/erase in progress
1,3,4,7
1,3,5,7
VCC Program Current,
VCC Erase Current
ICCW,
ICCE
64 Mbit
VCC Program Suspend
Current,
128
ICCWS,
ICCES
20
25
70
Mbit
µA
µA
CE# = VCCQ; suspend in progress
VPP = VPPL, suspend in progress
1,6,3
1,3
VCC Erase Suspend Current
256
Mbit
110
IPPS,
VPP Standby Current,
IPPWS, VPP Program Suspend Current,
0.2
5
VPP Erase Suspend Current
IPPES
Datasheet
18
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 7:
DC Current Characteristics (Sheet 2 of 2)
VCC
1.7 V – 2.0 V
1.7 V – 2.0 V
1.35 V – 2.0 V
Sym
Parameter
VCCQ
Unit
Test Conditions
Notes
Typ
Max
IPPR
VPP Read
2
0.05
8
15
0.10
22
µA
VPP ≤ VCC
VPP = VPPL, program in progress
VPP = VPPH, program in progress
IPPW
VPP Program Current
VPP Erase Current
mA
1,3
0.05
8
0.10
22
V
PP = VPPL, erase in progress
IPPE
mA
VPP = VPPH, erase in progress
Notes:
1.
2.
3.
4.
5.
6.
7.
All currents are RMS unless noted. Typical values at typical VCC, TC = +25°C.
ICCS is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.
Sampled, not 100% tested.
V
CC read + program current is the sum of VCC read and VCC program currents.
VCC read + erase current is the sum of VCC read and VCC erase currents.
ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR
ICCW, ICCE measured over typical or max times specified in Section 7.7, “Program and Erase
Characteristics” on page 32.
6.2
DC Voltage Characteristics
Table 8:
DC Voltage Characteristics
VCC
Q
1.35 V – 2.0 V
1.7 V – 2.0 V
Sym
Parameter
Unit
Test Condition
Notes
Min
Max
Min
Max
VIL
Input Low Voltage
Input High Voltage
0
0.2
0
0.4
V
V
1
VCCQ
–0.2
VCCQ
–0.4
VIH
VCCQ
0.1
VCCQ
0.1
V
CC = VCCMIN
VOL
Output Low Voltage
Output High Voltage
V
V
VCCQ = VCCQMIN
IOL = 100 µA
V
CC = VCCMIN
VCCQ
–0.1
VCCQ
–0.1
VOH
VCCQ = VCCQMIN
IOH = –100 µA
VPPLK VPP Lock-Out Voltage
VLKO VCC Lock Voltage
0.4
0.4
V
V
V
2
1.0
0.9
1.0
0.9
VLKOQ VCCQ Lock Voltage
Notes:
1.
2.
VIL can undershoot to –0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less.
VPP < VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
November 2007
Order Number: 313295-04
Datasheet
19
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
7.0
AC Characteristics
7.1
AC Test Conditions
Figure 3: AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
Note: AC test inputs are driven at VCCQ for Logic “1” and 0.0 V for Logic “0.” Input/output timing begins/ends at VCCQ/2. Input
rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin.
Figure 4: Transient Equivalent Testing Load Circuit
Device
Out
Under Test
CL
Notes:
1.
2.
3.
See the following table for component values.
Test configuration component value for worst case speed conditions.
CL includes jig capacitance.
Table 9:
Test Configuration
Test Configuration
CL (pF)
VCCQ Min Standard Test
30
Figure 5: Clock Input AC Waveform
R201
VIH
CLK [C]
VIL
R202
R203
Datasheet
20
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
7.2
Capacitance
Table 10: Capacitance
Symbol
Parameter
Signals
Min
Typ
Max
Unit
Condition
Note
Address, CE#, WE#,
OE#, RST#, CLK,
ADV#, WP#
Typ temp= 25 °C, Max
temp = 85 °C,
VCC=VCCQ=(0-1.95)
V, Silicon die
CIN
Input Capacitance
Output Capacitance
2
2
6
4
7
5
pF
pF
1,2
COUT
Data, WAIT
Notes:
1.
2.
Sampled, not 100% tested.
Silicon die capacitance only, add 1 pF for discrete packages.
7.3
AC Read Specifications (VCCQ = 1.35 V – 2.0 V)
Table 11: AC Read Specifications (VCCQ = 1.35 V – 2.0 V) (Sheet 1 of 2)
-90
All Densities
Num
Symbol
Parameter
Units
Notes
Speed
Min
Max
Asynchronous Specifications
R1
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read cycle time
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R2
Address to output valid
90
90
1,6
R3
CE# low to output valid
R4
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
25
1,2
1
R5
150
R6
0
0
1,3
1,2,3
R7
R8
20
20
R9
1,3
R10
R11
R12
R13
R14
R15
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
0
tEHEL
tELTV
tEHTZ
tGHTV
tGLTV
17
1
1
CE# low to WAIT valid
17
17
17
17
CE# high to WAIT high Z
OE# high to WAIT Valid
1,3
OE# low to WAIT Valid
Latching Specifications
R101
R102
R103
R104
R105
R106
R107
R111
tAVVH
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
tVHGL
tPHVH
Address setup to ADV# high
CE# low to ADV# high
7
ns
ns
ns
ns
ns
ns
ns
ns
10
ADV# low to output valid
ADV# pulse width low
90
1
7
7
ADV# pulse width high
Address hold from ADV# high
ADV# high to OE# low
RST# high to ADV# high
7
1,4
1
7
30
1
Clock Specifications
November 2007
Order Number: 313295-04
Datasheet
21
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 11: AC Read Specifications (VCCQ = 1.35 V – 2.0 V) (Sheet 2 of 2)
-90
All Densities
Speed
Num
Symbol
Parameter
Units
Notes
Min
Max
R200
R201
R202
R203
fCLK
CLK frequency
CLK period
47
MHz
ns
tCLK
21.3
4.5
1,3
tCH/CL
CLK high/low time
CLK fall/rise time
ns
tFCLK/RCLK
3
ns
Synchronous Specifications
R301
R302
R303
R304
R305
R306
R307
R311
R312
tAVCH/L
tVLCH/L
tELCH/L
tCHQV / tCLQV
tCHQX
Address setup to CLK
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
1
17
17
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
3
7
1,5
1,4,5
1,5
1
tCHAX
tCHTV
tCHVL
CLK Valid to ADV# Setup
WAIT Hold from CLK
0
3
tCHTX
1,5
7.4
AC Read Specifications: 64- and 128-Mb Densities
Table 12: AC Read Specifications (VCCQ = 1.7 V – 2.0 V) (Sheet 1 of 2)
-85
All Densities
Num
Symbol
Parameter
Units
Notes
Speed
Min
Max
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
Read cycle time
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to output valid
85
85
1,6
CE# low to output valid
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
20
1,2
1
150
0
0
1,3
1,2,3
17
17
1,3
Output hold from first occurring address, CE#, or
OE# change
R10
tOH
0
ns
R11
R12
R13
R14
R15
tEHEL
tELTV
tEHTZ
tGHTV
tGLTV
CE# pulse width high
CE# low to WAIT valid
CE# high to WAIT high Z
OE# high to WAIT Valid
OE# low to WAIT Valid
14
ns
ns
ns
ns
ns
1
1,3
1
14
14
14
14
Latching Specifications
Datasheet
22
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 12: AC Read Specifications (VCCQ = 1.7 V – 2.0 V) (Sheet 2 of 2)
-85
All Densities
Num
Symbol
Parameter
Units
Notes
Speed
Min
Max
R101
tAVVH
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
7
ns
ns
ns
ns
ns
ns
ns
ns
R102
R103
R104
R105
R106
R107
R111
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
tVHGL
tphvh
10
85
1
7
7
ADV# pulse width high
Address hold from ADV# high
ADV# high to OE# low
RST# high to ADV# high
7
1,4
1
7
30
1
Clock Specifications
R200
R201
R202
R203
fCLK
CLK frequency
CLK period
54
3
MHz
ns
tCLK
18.5
3.5
1,3
tCH/CL
tFCLK/RCLK
CLK high/low time
CLK fall/rise time
ns
ns
Synchronous Specifications
R301
R302
R303
R304
R305
R306
R307
R311
R312
tAVCH/L
tVLCH/L
tELCH/L
tCHQV / tCLQV
tCHQX
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
14
14
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
3
7
1,5
1,4,5
1,5
1
tCHAX
tCHTV
tCHVL
CLK Valid to ADV# Setup
WAIT Hold from CLK
0
3
tCHTX
1,5
Notes:
1.
See Figure 3, “AC Input/Output Reference Waveform” on page 20 for timing measurements and max
allowable input slew rate.
2.
3.
4.
5.
6.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
Sampled, not 100% tested.
Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
Applies only to subsequent synchronous reads.
The specifications in Table 11 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR
(2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
7.5
AC Read Specifications for 256-Mb Density
Table 13: AC Read Specifications (Sheet 1 of 3)
-90
Num
Symbol
Parameter
All Densities Speed
Units
Notes
Min
Max
Asynchronous Specifications
November 2007
Order Number: 313295-04
Datasheet
23
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 13: AC Read Specifications (Sheet 2 of 3)
-90
Num
Symbol
Parameter
All Densities Speed
Units
Notes
Min
Max
VCC = VCCQ = 1.8 V – 2.0
85
88
R1
tAVAV
Read cycle time
ns
ns
ns
VCC = VCCQ = 1.7 V – 2.0
VCC = VCCQ = 1.8 V – 2.0
VCC = VCCQ = 1.7 V – 2.0
85
88
1,6
R2
R3
tAVQV
Address to output valid
CE# low to output valid
VCC = VCCQ = 1.8 V – 2.0
CC = VCCQ = 1.7 V – 2.0
85
tELQV
V
88
R4
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
OE# low to output valid
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1
R5
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
150
R6
0
0
1,3
1,2,3
R7
R8
17
17
R9
1,3
R10
R11
R12
R13
R14
R15
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
0
tEHEL
tELTV
tEHTZ
tGHTV
tGLTV
14
1
1,3
1
CE# low to WAIT valid
14
14
14
14
CE# high to WAIT high Z
OE# high to WAIT Valid
OE# low to WAIT Valid
Latching Specifications
R101
R102
tAVVH
tELVH
Address setup to ADV# high
CE# low to ADV# high
7
ns
ns
10
V
CC = VCCQ = 1.8 V – 2.0
CC = VCCQ = 1.7 V – 2.0
85
88
R103
tVLQV
ADV# low to output valid
ns
1
V
R104
R105
R106
R107
R111
tVLVH
tVHVL
tVHAX
tVHGL
tphvh
ADV# pulse width low
7
7
ns
ns
ns
ns
ns
ADV# pulse width high
Address hold from ADV# high
ADV# high to OE# low
RST# high to ADV# high
7
1,4
1
7
30
1
Clock Specifications
R200
R201
R202
R203
fCLK
CLK frequency
CLK period
54
3
MHz
ns
tCLK
18.5
3.5
1,3
tCH/CL
tFCLK/RCLK
CLK high/low time
CLK fall/rise time
ns
ns
Synchronous Specifications
R301
R302
R303
R304
tAVCH/L
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
7
7
7
ns
ns
ns
ns
tVLCH/L
1
tELCH/L
tCHQV / tCLQV
14
Datasheet
24
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 13: AC Read Specifications (Sheet 3 of 3)
-90
Num
Symbol
Parameter
All Densities Speed
Units
Notes
Min
Max
R305
R306
R307
R311
R312
tCHQX
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
3
7
ns
ns
ns
ns
ns
1,5
1,4,5
1,5
1
tCHAX
tCHTV
tCHVL
tCHTX
14
CLK Valid to ADV# Setup
WAIT Hold from CLK
0
3
1,5
Figure 6: Asynchronous Single-Word Read Timing
R2
A[Max:16] [A]
R3
R4
A/DQ[15:0]
A
Q
R106
R101
ADV# [V]
CE#[E]
R8
R7
R107
R9
OE# [G]
R12
R13
WAIT [T]
Note: WAIT is deasserted (CR [10] = 0) during asynchronous read mode.
November 2007
Order Number: 313295-04
Datasheet
25
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 7: Synchronous Array Read with Flow-through Feature Timing
First Access Latency
CLK [C]
A[max:16] [A}
A
A
R304
R304
R3
R8
A/DQ[15:0]
ADV# [V]
Q0
Q1
Q2
Q3
R106
R102
R303
CE# [E]
OE# [G]
R4
R107
R9
R13
R14
R12
R15
R307
R307
WAIT [T]
Notes:
1.
2.
3.
WAIT active low (asserted) during initial access and deasserted during valid read array data
WAIT deasserted during OE# = Vih.
Flow through feature as shown during the first data word.
Figure 8: Synchronous Non-Array Read with Flow-through Feature Timing
Latency Count
CLK [C]
A[Max:16] [A]
A/DQ[15:0]
ADV# [V]
A
A
R304
R304
R3
R8
Q0
Q0
Q0
Q0
R106
R102
R303
CE# [E]
OE# [G]
R4
R107
R9
R13
R14
R12
R15
R307
R307
WAIT [T]
Notes:
1.
2.
3.
WAIT active low (asserted) during initial access and deasserted during valid read non-array data
WAIT deasserted during OE# = Vih
Flow through feature as shown during the first data word.
Datasheet
26
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 9: Burst Suspend Timing
Latenc
Count
CLK [C]
Note 1
R7
ADQ [ADQ]
A
Q0
Q1
Q1
R101
R105
R106
ADV# [V]
CE# [E]
R107
R9
R4
OE# [G]
R12
R15
R307
WAIT [T]
WE# [W]
Notes:
1.
2.
During burst suspend Clock signal can be held high or low
WAIT asserted low (CR[10] = 0).
Figure 10: Asynchronous Read to Write Timing
R2
A[Max:16][A]
A/DQ [15:0]
A
R3
W5
R7
W4
A
Q
A
D
A
D
R106
R101
R104
R106
R101
R104
R101
R104
W20
R106
ADV#[V]
CE# [E]
OE# [G]
R11
R4
R12
R12
R13
WAIT [T]
WE# [W]
W7
W15
W2
W3
W9
Note: WAIT deasserted (CR[10] = 0) during asynchronous operations.
November 2007
Order Number: 313295-04
Datasheet
27
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 11: Write to Asynchronous Read Timing
A[Max:16][A]
W5
W7
W4
D
W8
A/DQ [15:0]
A
A
D
A
Q
R106
W15
R106
R2
R106
R101
R104
R104
R101
R104
R101
ADV#[V]
CE# [E]
WE# [W]
R11
W2
W2
W6
R3
R8
W18
W3
W9
W3
R7
R4
R107
W14
R12
R9
OE# [G]
WAIT [T]
RST#[P]
R12
R13
W1
Note: WAIT deasserted (CR[10] = 0) during asynchronous operations.
Datasheet
28
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 12: Synchronous Read to Write Timing
R306
CLK
R301
R2
A[Max:16] [A]
A/DQ[15:0]
A
A
R3
W5
R7
W4
Q
Q
A
D
A
D
R106
R104
R101
R106
R104
R106
R104
R101
R101
ADV# [V]
CE# [E]
R11
R4
OE# [G]
WAIT [T]
R12
R12
R15
R13
W15
W7
W2
W3
W9
WE#
Note: WAIT shown deasserted (CR[10] = 0) during write operation.
November 2007
Order Number: 313295-04
Datasheet
29
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 13: Write to Synchronous Read
CLK [C]
A[Max:16] [A]
W5
W7
W4
W8
R304
A/DQ[15:0]
A
D
A
D
A
Q
Q
R106
R101
R104
W15
R106
R104
R101
R106
R104
R101
ADV# [V]
CE# [E]
WE#
R11
W20
W2
W6
W18
W9
W19
W3
W3
R107
W14
OE# [G]
WAIT [T]
R12
R12
R15
R307
Note: WAIT shown deasserted (CR[10] = 0) during write operation.
7.6
AC Write Specifications
Table 14: AC Write Specifications (Sheet 1 of 2)
Num
W1
Symbol
Parameter
Min
Max
Units
Notes
tPHWL
tELWL
RST# high recovery to WE# low
CE# setup to WE# low
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,3
1,2,4
W2
W3
tWLWH
tDVWH
tAVWH
tWHEH
tWHDX
tWHAX
tWHWL
tVPWH
tQVVL
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
50
50
50
0
W4
W5
W6
1,2
W7
0
W8
0
W9
20
200
0
1,2,5
W10
W11
W12
W13
W14
VPP setup to WE# high
1,2,3,7
VPP hold from Status read
WP# hold from Status read
WP# setup to WE# high
WE# high to OE# low
tQVBL
tBHWH
tWHGL
0
1,2,3,7
1,2,9
200
0
Datasheet
30
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 14: AC Write Specifications (Sheet 2 of 2)
Num
W15
W16
Symbol
Parameter
ADV# low to WE# high
WE# high to read valid
Min
Max
Units
Notes
tVLWH
69
ns
1,2
1,2,3,6,
10
tWHQV
tAVQV+35
ns
ns
Write to Asynchronous Read Specification
W18 tWHAV WE# high to Address valid
Write to Synchronous Read Specification
1,2,3,6,
10
0
W19
W20
tWHCH/L
tWHVH
WE# high to Clock valid
WE# high to ADV# high
19
19
ns
ns
1,2,3,6, 10
1,2,3,11
Write Specifications with Clock Active
W21
W22
tVHWL
tCHWL
ADV# high to WE# low
Clock high to WE# low
20
20
ns
ns
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH
.
5.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHW).
6.
7.
8.
tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read.
VPP should be at a valid level until erase or program success is determined.
This specification is only applicable when transitioning from a write cycle to an asynchronous read. See specs W19 and
W20 for synchronous read.
9.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
Add 10ns if the write operation results in a RCR or block lock status change, for the subsequent read operation to reflect
this change.
10.
11.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
Figure 14: Write Timing
A[Max-16] [A]
W5
W7
W4
W8
A/DQ[15-0]
A
D
A
D
R104
R101
R104
R101
W20
R106
W15
R106
ADV# [v]
CE# [E]
W2
W6
W2
W6
W18
W21
W3
W9
W3
WE# [W]
OE# [G]
W1
RST# [P]
November 2007
Order Number: 313295-04
Datasheet
31
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
7.7
Program and Erase Characteristics
Table 15: Program and Erase Characteristics
VPPL
Typ
VPPH
Typ
Unit
s
Num
Symbol
Parameter
Notes
Min
Max
Min
Max
Word Programming
Single word
Single cell
90
30
180
60
85
30
170
60
Program
Time
W200
tPROG/W
µs
µs
1
Buffered Programming
W200
W201
tPROG/W
tPROG/PB
Single word
90
180
880
85
170
680
Program
Time
1,2
One Buffer (32 words)
Buffered EFP
440
340
W400
W452
tBEFP/W
Single word
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5
10
N/A
N/A
µs
µs
1,2
1,2
Program
tBEFP/
SETUP
Buffered EFP Setup
N/A
Erasing and Suspending
16-KWord Parameter
W500
W501
W600
W601
tERS/PB
tERS/MB
tSUSP/P
tSUSP/E
0.4
1.2
20
2.5
4
0.4
1.0
20
2.5
4
Erase Time
s
64-KWord Main
Program suspend
Erase suspend
1
25
25
25
25
Suspend
Latency
µs
20
20
Notes:
1.
Typical values measured at TC = +25 °C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system
overhead. Sampled, but not 100% tested.
2.
Averaged over entire device.
Datasheet
32
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
8.0
Power and Reset Specifications
8.1
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected
together. If VCCQ and/or VPP are not connected to the VCC supply, then VCC should
attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before
supply voltage equals VCCMIN.
Power supply transitions should only occur when RST# is low. This protects the device from
accidental programming or erasure during power transitions.
8.2
Reset
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active-low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
System designers should guard against spurious writes when VCC voltages are above
VLKO. Because both WE# and CE# must be asserted for a write operation, deasserting
either signal inhibits writes to the device.
The Command User Interface (CUI) architecture provides additional protection because
alteration of memory contents can only occur after successful completion of a two-step
command sequence (see Section 9.2, “Device Commands” on page 37).
November 2007
Order Number: 313295-04
Datasheet
33
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 15: Reset Operation Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
read mode
RST# [P]
RST# [P]
RST# [P]
VCC
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
Table 16: Reset Specifications
Num
Symbol
Parameter
Min
Max
Unit
Notes
P1
tPLPH
RST# pulse width low
RST# low to device reset during erase
100
ns
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
25
25
P2
tPLRH
RST# low to device reset during program
VCC Power valid to RST# deassertion (high)
µs
P3
tVCCPH
60
Notes:
1.
2.
3.
4.
5.
6.
These specifications are valid for all device versions (packages and speeds).
The device may reset if tPLPH is <tPLPH MIN, but this is not guaranteed.
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC >= VCC min.
If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC >=
VCC(min).
7.
Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
8.3
Power Supply Decoupling
Flash memory devices require careful power supply decoupling. Three basic power
supply current considerations are as follows:
1. Standby current levels
2. Active current levels
3. Transient peaks produced when CE# and OE# are asserted and deasserted.
Datasheet
34
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of
these internal activities produce transient signals. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct
decoupling capacitor selection suppress transient voltage peaks.
Because Intel® Multi-Level Cell (MLC) flash memory devices draw their power from
VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor
connected to a corresponding ground connection (e.g.VCCQ to VSSQ). High-frequency,
inherently low-inductance capacitors should be placed as close as possible to package
leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
8.4
Automatic Power Saving (APS)
Automatic Power Saving (APS) provides low power operation during a read’s active
state. ICCAPS is the average current measured over any 5 ms time interval, 5 μs after
CE# is deasserted. During APS, average current is measured over the same time
interval 5 μs after the following events happen: (1) there is no internal read, program
or erase operations cease; (2) CE# is asserted; (3) the address lines are quiescent and
at VSSQ or VCCQ. OE# may also be driven during APS.
November 2007
Order Number: 313295-04
Datasheet
35
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
9.0
Device Operations
This section provides an overview of device operations. The system CPU provides
control of all in-system read, write, and erase operations of the device via the system
bus. The on-chip Write State Machine (WSM) manages all block-erase and word-
program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the flash device is controlled.
9.1
Bus Operations
CE#-low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed partition. ADV#-low opens the internal
address latches. OE#-low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high. In synchronous
mode, the address is latched by the first of either the rising ADV# edge or the next
valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must be VIL).
9.1.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus. See Section 10.0, “Read Operations” on
page 41 for details on the available read modes, and see Section 15.0, “Special Read
States” on page 66 for details regarding the available read states.
The Automatic Power Savings (APS) feature provides low power operation following
reads during active mode. After data is read from the memory array and the address
lines are quiescent, APS automatically places the device into standby. In APS, device
current is reduced to ICCAPS (see Section 6.1, “DC Current Characteristics” on page 18).
9.1.2
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. All device write operations are asynchronous, with CLK being ignored.
During a write operation, address and data are latched on the rising edge of WE# or
CE#, whichever occurs first. Table 17, “Command Bus Cycles” on page 38 shows the
bus cycle sequence for each of the supported device commands, while Table 18,
“Command Codes and Definitions” on page 39 describes each command. See Section
7.0, “AC Characteristics” on page 20 for signal-timing details.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
9.1.3
Output Disable
When OE# is deasserted, device outputs AD[15:0] are disabled and placed in a high-
impedance (High-Z) state.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
9.1.4
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5 μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
9.1.5
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Intel® flash memories allow
proper CPU initialization following a system reset through the use of the RST# input.
RST# should be controlled by the same low-true reset signal that resets the system
CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array, and the
Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and
places the output drivers in High-Z. When RST# is asserted, the device shuts down the
operation in progress, a process which takes a minimum amount of time to complete.
When RST# has been deasserted, the device is reset to asynchronous Read Array
state.
Note:
If RST# is asserted during a program or erase operation, the operation is terminated
and the memory contents at the aborted location (for a program) or block (for an
erase) are no longer valid, because the data may have been only partially written or
erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a write cycle can be initiated. After this wake-up interval passes, normal
operation is restored. See Section 7.0, “AC Characteristics” on page 20 for details
about signal-timing.
9.2
Device Commands
Device operations are initiated by writing specific device commands to the Command
User Interface (CUI). See Table 17, “Command Bus Cycles” on page 38.
Several commands are used to modify array data including Word Program and Block
Erase commands. Writing either command to the CUI initiates a sequence of internally-
timed functions that culminate in the completion of the requested task. However, the
operation can be aborted by either asserting RST# or by issuing an appropriate
suspend command.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 17: Command Bus Cycles
First Bus Cycle
Second Bus Cycle
Bus
Cycles
Note
s
Mode
Command
Oper
Addr
Data
Oper
Addr
Data
Read Array
1
≥ 2
≥ 2
2
Write
Write
Write
Write
Write
PnA
PnA
PnA
PnA
X
0xFF
0x90
0x98
0x70
0x50
Read Device Identifier
CFI Query
Read
Read
Read
PBA+IA
PnA+QA
PnA
ID
QD
Read
1,2
Read Status Register
Clear Status Register
SRD
1
0x40/
0x10
Word Program
2
Write
Write
Write
WA
WA
WA
Write
Write
Write
WA
WA
WA
WD
Program
Buffered Program
> 2
> 2
0xE8
0x80
N - 1
0xD0
1,2,3
1,2,4
Buffered Enhanced Factory Program
(Buffered EFP)
Erase
Block Erase
2
Write
BA
0x20
Write
BA
0xD0
Program/Erase Suspend
Program/Erase Resume
Lock Block
1
1
2
2
2
2
2
Write
Write
Write
Write
Write
Write
Write
X
X
0xB0
0xD0
0x60
0x60
0x60
0xC0
0xC0
Suspend
BA
Write
Write
Write
BA
BA
BA
0x01
0xD0
0x2F
Block
Locking/
Unlocking
Unlock Block
BA
1,2
Lock-down Block
BA
Program Protection Register
Program Lock Register
PRA
LRA
Write PRA
Write LRA
PD
LRD
Protection
Configuration Program Read Configuration Register
2
Write
RCD
0x60
Write
RCD
0x03
Notes:
1.
First command cycle address should be the same as the operation’s target address.
PnA = Address within the partition.
PBA = Partition base address.
IA = Identification code address offset.
QA = CFI Query address offset.
BA = Address within the block.
WA = Word address of memory location to be written.
PRA = Protection Register address.
LRA = Lock Register address.
X = Any valid address within the device.
ID = Identifier data.
2.
QD = Query data on AD[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
PD = Protection Register data.
PD = Protection Register data.
LRD = Lock Register data.
RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition.
3.
4.
The second cycle of the Write-to-Buffer command is the word count of the data to be loaded into the write buffer. This is
followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming
operation.
The confirm command (0xD0) is followed by the buffer data.
9.3
Command Definitions
Table 18 shows valid device command codes and descriptions.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 18: Command Codes and Definitions (Sheet 1 of 2)
Mode
Code
Device Mode
Description
Places the addressed partition in Read Array mode. Array data is output on
AD[15:0].
0xFF
Read Array
Places the addressed partition in Read Status Register mode. The partition enters
this mode after a program or erase command is issued. Status Register data is
output on AD[7:0].
Read Status
Register
0x70
0x90
Places the addressed partition in Read Device Identifier mode. Subsequent reads
from addresses within the partition outputs manufacturer/device codes,
Configuration Register data, Block Lock status, or Protection Register data on
AD[15:0].
Read Device ID
or Configuration
Register
Read
Places the addressed partition in Read Query mode. Subsequent reads from the
partition addresses output Common Flash Interface information on AD[7:0].
0x98
0x50
Read Query
Clear Status
Register
The WSM can only set Status Register error bits. The Clear Status Register
command is used to clear the SR error bits.
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the WSM
executes the programming algorithm at the addressed location. During program
operations, the partition responds only to Read Status Register and Program
Suspend commands. In asynchronous mode the falling edge of OE#, or CE#
(whichever occurs first) updates and latches the Status Register contents.
However, reading the Status Register in synchronous burst mode, CE# or ADV#
must be toggled to update status data. The Read Array command must be issued
to read array data after programming has finished.
Word Program
Setup
0x40
Alternate Word
Program Setup
0x10
0xE8
Equivalent to the Word Program Setup command, 0x40.
First cycle of a 2-cycle command; prepares the device to receive a variable
number of bytes up to the write buffer size of 32 words. The second cycle
contains the number of bytes to be transferred.
Buffered
Program Setup
Write
Issued after writing all data to the write buffer; instructs the WSM to perform its
Buffered Programming algorithm, writing the data from the write buffer to the
flash memory array.
Buffered
Program Confirm
0xD0
Buffered
Enhanced
Factory
Programming
Setup
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program
mode (Buffered EFP). The CUI then waits for the Buffered EFP Confirm command,
0xD0, that initiates the Buffered EFP algorithm. All other commands are ignored
when Buffered EFP mode begins.
0x80
0xD0
0x20
Buffered EFP
Confirm
If the previous command was Buffered EFP Setup (0x80), the CUI latches the
address and data, and prepares the device for Buffered EFP mode.
First cycle of a 2-cycle command; prepares the CUI for a block-erase operation.
The WSM performs the erase algorithm on the block addressed by the Erase
Confirm command. If the next command is not the Erase Confirm (0xD0)
command, the CUI sets Status Register bits SR[4] and SR[5], and places the
addressed partition in read status register mode.
Block Erase
Setup
Erase
If the first command was Block Erase Setup (0x20), the CUI latches the address
and data, and the WSM erases the addressed block. During block-erase
operations, the partition responds only to Read Status Register and Erase
Suspend commands.
Block Erase
Confirm
0xD0
This command issued to any device address initiates a suspend of the currently-
executing program or block erase operation. The Status Register indicates
successful suspend operation by setting either SR[2] (program suspended) or
SR[6] (erase suspended), along with SR[7] (ready). The Write State Machine
remains in the suspend mode regardless of control signal states (except for RST#
asserted).
Program or
0xB0
0xD0
Erase Suspend
Suspend
Suspend
Resume
This command issued to any device address resumes the suspended program or
block-erase operation.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 18: Command Codes and Definitions (Sheet 2 of 2)
Mode
Code
Device Mode
Description
First cycle of a 2-cycle command; prepares the CUI for block lock configuration
changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0), or
Block Lock-Down (0x2F), the CUI sets Status Register bits SR[4] and SR[5],
indicating a command sequence error.
0x60
Lock Block Setup
If the previous command was Block Lock Setup (0x60), the addressed block is
locked.
0x01
0xD0
0x2F
Lock Block
Block Locking/
Unlocking
If the previous command was Block Lock Setup (0x60), the addressed block is
unlocked. If the addressed block is in a lock-down state, the operation has no
effect.
Unlock Block
Lock-Down Block
If the previous command was Block Lock Setup (0x60), the addressed block is
locked down.
First cycle of a 2-cycle command; prepares the device for a Protection Register or
Lock Register program operation. The second cycle latches the register address
and data, and starts the programming algorithm. The Read Array command must
be issued to read array data after programming has finished.
Program
Protection
Register Setup
Protection
0xC0
0x60
0x03
First cycle of a 2-cycle command; prepares the CUI for a Read Configuration
Register program operation. If the Configure Read Configuration Register
command (0x03) is not the next command, the CUI sets Status Register bits
SR[4] and SR[5], indicating a command sequence error.
Configure Read
Configuration
Register Setup
Configuration
If the previous command was Configure Read Configuration Register Setup
(0x60), the CUI latches the address and writes A[15:0] to the Read Configuration
Register. Following a Configure Read Configuration Register command,
subsequent read operations access array data.
Configure Read
Configuration
Register
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
10.0
Read Operations
The device supports two read modes: asynchronous read mode and synchronous burst
mode. Asynchronous array read mode is the default read mode after device power-up
or a reset. The Read Configuration Register (RCR) must be set before synchronous
burst operation can be performed (see Section 10.3, “Read Configuration Register
(RCR)” on page 42).
Each partition of the device can be in any of four read states: Read Array, Read
Identifier, Read Status or Read Query. To change a partition’s read state, the
appropriate read command must be written to the device (see Section 9.2, “Device
Commands” on page 37). See Section 15.0, “Special Read States” on page 66 for
details regarding Read Status, Read ID, and CFI Query modes.
If the Read Array command is written to a partition that is performing a program or
erase operation, invalid data is read until the program or erase operation completes.
Subsequent reads produce array data. If a Program Suspend or Erase Suspend
command is issued during a program or erase operation, a subsequent Read Array
command puts the addressed partition into Read Array. The Read Array command
functions independent of VPP.
The following sections describe read-mode operations in detail.
10.1
Asynchronous Read Mode
Following a device power-up or reset, asynchronous array read is the default read
mode and all partitions are set to Read Array. However, to perform array reads after
any other device operation (e.g. write operations, reads Status, Query, ID, etc.), the
Read Array command must be issued in order to read from the flash memory array.
Each asynchronous read retrieves one data word. Asynchronous reads are permitted in
all blocks.
Note:
Asynchronous reads can only be performed when Read Configuration Register bit
RCR[15] is set (see Section 10.3, “Read Configuration Register (RCR)” on page 42).
To perform an asynchronous array or non-array read, an address is driven onto
A[MAX:16] and AD[15:0], and ADV# and CE# are asserted. WE# and RST# must
already have been deasserted. WAIT is deasserted during asynchronous read mode.
ADV# is driven high to latch the address information. CLK is not used during
asynchronous reads, and is ignored. A valid data is driven onto AD[15:0] after an initial
access delay (see Section 7.0, “AC Characteristics” on page 20).
10.2
Synchronous Burst-Mode Read
Synchronous burst mode outputs 4-, 8-, 16-, or a continuous number of contiguous
words after the device latches one address. Read Configuration register bits CR[15:0]
must be set before synchronous burst operation can be performed. (See Section 10.3,
“Read Configuration Register (RCR)” on page 42 for details). To perform a synchronous
burst read, an initial address is driven onto A[MAX:16] and AD[15:0], and ADV# and
CE# are asserted. WE# and RST# must already have been deasserted.
During synchronous array and non-array read modes, the first valid data is driven onto
AD[15:0], with respect to a valid clock edge after the asynchronous access time
(tAVQV) has been met, regardless of the latency setting. As shown in Figure 17,
“Example Latency Count Setting with Flow- through feature” on page 45, with a latency
setting of 4 clocks, data is driven after the third clock since the tAVQV requirement has
been met. That data continues to be available on the data bus until the first access
latency period is over, as described in Section 10.3.2, “Latency Count” on page 43. This
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
“flow through” behavior only applies to the first access of any synchronous read bus
cycle. All subsequent data is driven on valid clock edges following the first access
latency; however, for a synchronous non-array read, the same word of data will be
output on successive clock edges until the burst length requirements are satisfied.
During synchronous read operations, after OE# is driven low WAIT indicates invalid
data on subsequent clock edges when asserted, and valid data when de-asserted with
respect to a valid clock edge. See Figure 7, “Synchronous Array Read with Flow-
through Feature Timing” on page 26 and Figure 9, “Burst Suspend Timing” on page 27
for additional details. Synchronous burst reads are permitted in all blocks.
10.2.1
Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access
latency incurred when system software needs to suspend a burst sequence that is in
progress in order to retrieve data from another device on the same system bus. The
system processor can resume the burst sequence later. Burst suspend provides
maximum benefit in non-cache systems.
Burst accesses can be suspended during the initial access latency (before data is
received) or after the device has output data. When a burst access is suspended,
internal array sensing continues and any previously latched internal data is retained. A
burst sequence can be suspended and resumed without limit as long as device
operation conditions are met.
Burst Suspend occurs when CE# is asserted, the current address has been latched
(either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK
can be halted when it is at VIH or VIL.
To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent CLK
edges resume the burst sequence. See Figure 9, “Burst Suspend Timing” on page 27.
10.3
Read Configuration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see Section 9.2, “Device Commands”
on page 37).
RCR contents can be examined using the Read Device Identifier command, and then
reading from <partition base address> + 0x05 (see Section 15.2, “Read Device
Identifier” on page 67).
The RCR is shown in Table 19. The following sections describe each RCR bit
.
Table 19: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Read
Mode
WAIT
Polarity
Data
Hold
WAIT
Delay
Burst
Seq
CLK
Edge
Burst
Wrap
RES
Latency Count
LC[2:0]
RES
RES
Burst Length
RM
15
Bit
R
WP
10
DH
9
WD
8
BS
7
CE
6
R
5
R
4
BW
3
BL[2:0]
1
14
13
12
11
2
0
Name
Description
0 = Synchronous burst-mode read
1 = Asynchronous read (default)
15
Read Mode (RM)
Reserved (R)
14
Reserved bits should be cleared (0)
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 19: Read Configuration Register Description (Sheet 2 of 2)
010 =Code 2
011 =Code 3
100 =Code 4
13:11
Latency Count (LC[2:0])
Wait Polarity (WP)
101 =Code 5
110 =Code 6
111 =Code 7(default)
(Other bit settings are reserved)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
10
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
9
8
7
Data Hold (DH)
0 =WAIT de-asserted with valid data
1 =WAIT de-asserted one data cycle before valid data (default)
Wait Delay (WD)
Burst Sequence (BS)
0 =Reserved
1 =Linear (default)
0 = Falling edge
6
Clock Edge (CE)
Reserved (R)
1 = Rising edge (default)
5:4
3
Reserved bits should be cleared (0)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
Burst Wrap (BW)
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
2:0
Burst Length (BL[2:0])
(Other bit settings are reserved)
10.3.1
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous read-mode
operation for the device. When the RM bit is set, asynchronous read mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
10.3.2
Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse
from the rising edge of ADV# or from the first valid clock edge after ADV# is asserted
before the WAIT signal indicates valid data is present on the device data signals
AD[15:0]. The input clock frequency determines this value. Figure 16 shows the data
output latency from ADV#-asserted for different settings of LC[2:0]. The Latency Count
does not affect when data becomes available on the data signals. Valid data is driven
onto the data bus, with respect to a valid clock edge, as soon as possible after the
asynchronous access time is satisfied (or another word after it is sensed). In this way,
the data “flows-through” on the first access, with respect to an active clock edge. The
data continues to be available on the data bus until the latency period is over. The flow-
through behavior only applies to the first access of any bus cycle. All subsequent data
is driven on valid clock edges following the first access latency period.
During synchronous burst a Latency Count setting of Code 5 will cause 1 WAIT state
(Code 6 will cause 2 WAIT states, and Code 7 will cause 3 WAIT states) after every four
words, regardless of whether a 16-word boundary is crossed. If CR.[9] (Data Hold) bit
is set (data hold of two clocks) this WAIT condition will not occur because enough
clocks elapse during each burst cycle to eliminate subsequent WAIT states.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 16: First-Access Latency Count
CLK
Valid
Address
Address
ADV#
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
AD[15:0]
Code 3
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
AD[15:0]
Code 4
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
AD[15:0]
Code 5
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
AD[15:0]
Code 6
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
AD[15:0]
Code 7
Valid
Output
Valid
Output
Valid
Output
Valid
Output
AD[15:0]
Table 20: LC and Frequency Support (tAVQV/tCHQV = 85 ns / 14 ns)
VCCQ = 1.7 V to 2.0 V
Latency Count Settings
Frequency Support (MHz)
2
£ 28
£ 40
£ 54
3
4, 5, 6 or 7
Table 21: LC and Frequency Support (tAVQV/tCHQV = 90 ns / 17 ns)
VCCQ = 1.35 V to 2.0 V
Latency Count Settings
Frequency Support (MHz)
2
£ 27
£ 40
3, 4, 5, 6 or 7
See Figure 17, “Example Latency Count Setting with Flow- through feature” on
page 45.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 17: Example Latency Count Setting with Flow- through feature
tADD
tDATA
3rd
2nd
4th
1st
6th
5th
CLK
CE#
ADV#
tCHQV
AMAX-16
Code 4
Valid
Output
Valid
Output
High Z
A/DQ15-0
Valid Address
R2
Note: The waveform above illustrates the Latency Count of 4 with Flow-through feature. The Flow-through feature will be shown
only when the initial access time is one clock less than the LC setting.
10.3.3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of
WAIT. When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is
asserted-low. WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted and RST# deasserted).
10.3.3.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(CR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous single word read mode, WAIT is set to an
“de-asserted” state as determined by CR[10]. See Table 22, “WAIT Summary Table” on
page 45, and Figure 6, “Asynchronous Single-Word Read Timing” on page 25.
Table 22: WAIT Summary Table
CONDITION
WAIT
CE# = VIH
CE# = VIL
High-Z
Driven
OE# = VIH
OE# = VIL
De-asserted
Active
Synchronous Array and Non-array Reads
All Asynchronous Read and all Write
Active
De-asserted
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Note: Active: WAIT is asserted until data becomes valid, then de-asserts. WAIT is asserted during the initial access (latency) and
at the end of the burst cycle with OE# low.
10.3.4
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output
remains valid on AD[15:0] for one or two clock cycles. This period of time is called the
“data cycle”. When DH is set, output data is held for two clocks (default). When DH is
cleared, output data is held for one clock (see Figure 18). The processor’s data setup
time and the flash memory’s clock-to-data output delay should be considered when
determining whether to hold output data for one or two clocks.
A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
t
CHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
t
DATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 54 MHz, the clock period is 18.5 ns. Assuming
tCHQV = 14ns and tDATA = 4ns. Applying these values to the formula above:
14 ns + 4 ns ≤ 18.5 ns
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock.
If tCHQV (ns) + DATA
t
(ns) > One CLK Period (ns), data hold setting of 2 clock periods
must be used.
Figure 18: Data Hold Timing
CLK [C]
1 CLK
Valid
Output
Valid
Output
Valid
Output
AD[15:0] [Q]
Data Hold
2 CLK
Valid
Output
Valid
Output
AD[15:0] [Q]
Data Hold
10.3.5
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on AD[15:0]. When WD is set, WAIT is de-asserted one data cycle
before valid data (default). When WD is cleared, WAIT is de-asserted during valid data.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
10.3.6
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Table 23 shows the synchronous burst sequence for all burst
lengths, as well as the effect of the Burst Wrap (BW) setting.
Table 23: Burst Sequence Word Ordering
Burst Addressing Sequence (DEC)
Start
Addr.
(DEC)
Burst
Wrap
(RCR[3])
4-Word Burst
(BL[2:0] =
0b001)
8-Word Burst
(BL[2:0] = 0b010)
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
0
1
2
3
4
5
0
0
0
0
0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
0-1-2-3-4…14-15
1-2-3-4-5…15-0
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
2-3-4-5-6…15-0-1
3-4-5-6-7…15-0-1-2
4-5-6-7-8…15-0-1-2-3
5-6-7-8-9…15-0-1-2-3-4
6-7-8-9-10…15-0-1-2-3-
4-5
6
7
0
0
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
7-8-9-10…15-0-1-2-3-4-
5-6
14
15
0
0
14-15-0-1-2…12-13
15-0-1-2-3…13-14
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
0
1
2
3
4
5
6
1
1
1
1
1
1
1
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
0-1-2-3-4…14-15
1-2-3-4-5…15-16
2-3-4-5-6…16-17
3-4-5-6-7…17-18
4-5-6-7-8…18-19
5-6-7-8-9…19-20
6-7-8-9-10…20-21
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-
14
7
1
7-8-9-10-11…21-22
7-8-9-10-11-12-13…
14
15
1
1
14-15-16-17-18…28-29
15-16-17-18-19…29-30
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
10.3.7
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
10.3.8
Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length
accesses wrap within the selected word-length boundaries or cross over to the next
burst-length segment. When BW is set, burst wrapping does not occur (default). When
BW is cleared, burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may
occur when the burst sequence crosses its first device-row (16-word) boundary. If the
burst sequence’s start address is 4-word aligned, then no delay occurs. If the start
address is at the end of a 4-word boundary, the worst case output delay is one clock
cycle less than the first access Latency Count. This delay can take place only once, and
doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT
informs the system of this delay when it occurs.
10.3.9
Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and
continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 23, “Burst Sequence Word Ordering” on page 47). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
11.0
Programming Operations
The device supports three programming methods: word programming, buffered
programming, and Buffered Enhanced Factory Programming (Buffered EFP). See
Section 9.0, “Device Operations” on page 36 for details on the various programming
commands issued to the device.
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be deasserted and the block unlocked before attempting to
program the block. Attempting to program a locked block causes a program error
(SR[4] and SR[1] set) and termination of the operation. See Section 13.0, “Security
Modes” on page 57 for details on locking and unlocking blocks.
The following sections describe device programming in detail.
11.1
Word Programming
Word programming operations are initiated by writing the Word Program Setup
command to the device (see Section 9.0, “Device Operations” on page 36). This is
followed by a second write to the device with the address and data to be programmed.
The partition accessed during both write cycles outputs Status Register data when
read. The partition accessed during the second cycle (the data cycle) of the program
command sequence is the location where the data is written. See Figure 31, “Word
Program Flowchart” on page 76.
Programming can occur in only one partition at a time; all other partitions must be in a
read state or in erase suspend. VPP must be above VPPLK, and within the specified VPPL
min/max values (nominally 1.8 V).
During programming, the Write State Machine (WSM) executes a sequence of
internally-timed events that program the desired data bits at the addressed location,
and verifies that the bits are sufficiently programmed. Programming the flash memory
array changes “ones” to “zeros.” Memory array bits that are zeros can be changed to
ones only by erasing the block (see Section 12.0, “Erase Operations” on page 55).
The Status Register can be examined for programming progress and errors by reading
any address within the partition that is being programmed. The partition remains in the
Read Status Register state until another command is written to that partition. Issuing
the Read Status Register command to another partition address sets that partition to
the Read Status Register state, allowing programming progress to be monitored at that
partition’s address.
Status Register bit SR[7] indicates the programming status while the sequence
executes. Commands that can be issued to the programming partition during
programming are Program Suspend, Read Status Register, Read Device Identifier, CFI
Query, and Read Array (this returns unknown data). In asynchronous mode the falling
edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register
contents. However, reading the Status Register in synchronous burst mode, CE# or
ADV# must be toggled to update status data.
When programming has finished, Status Register bit SR[4] (when set) indicates a
programming failure. If SR[3] is set, the WSM could not perform the word
programming operation because VPP was outside of its acceptable limits. If SR[1] is set,
the word programming operation attempted to program a locked block, causing the
operation to abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow,
when word programming has completed.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
11.1.1
Factory Word Programming
Factory word programming is similar to word programming in that it uses the same
commands and programming algorithms. However, factory word programming
enhances the programming performance with VPP = VPPH. This can enable faster
programming times during OEM manufacturing processes. Factory word programming
is not intended for extended use. See Section 5.2, “Operating Conditions” on page 17
for limitations when VPP = VPPH
.
Note:
When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is
driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When
VPP = VPPH, the device draws programming current from the VPP supply. Figure 19,
“Example VPP Supply Connections” on page 54 shows examples of device power supply
configurations.
11.2
Buffered Programming
The device features a 32-word buffer to enable optimum programming performance.
For buffered programming, data is first written to an on-chip write buffer. Then the
buffer data is programmed into the flash memory array in buffer-size increments. This
can improve system programming performance significantly over non-buffered
programming.
When the Buffered Programming Setup command is issued (see Section 9.2, “Device
Commands” on page 37), Status Register information is updated and reflects the
availability of the write buffer. SR[7] indicates buffer availability: if set, the buffer is
available; if cleared, the write buffer is not available. To retry, issue the Buffered
Programming Setup command again, and re-check SR[7]. When SR[7] is set, the
buffer is ready for loading. (see Figure 33, “Buffer Program Flowchart” on page 78).
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. Subsequent writes provide additional device addresses and
data. All data addresses must lie within the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing
a 32-word boundary during programming will double the total programming time.
After the last data is written to the buffer, the Buffered Programming Confirm command
is issued to the original block address. The WSM begins to program buffer contents to
the flash memory array. If a command other than the Buffered Programming Confirm
command is written to the device, a command sequence error occurs and Status
Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device
stops programming, and Status Register bits SR[7,4] are set, indicating a programming
failure.
Reading from another partition is allowed while data is being programmed into the
array from the write buffer (see Section 14.0, “Dual-Operation Considerations” on
page 62).
Additional buffer writes can be initiated by issuing another Buffered Programming
Setup command and repeating the buffered program sequence. Buffered programming
may be performed with VPP = VPPL or VPPH (see Section 5.2, “Operating Conditions” on
page 17 for limitations when operating the device with VPP = VPPH).
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If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and Status Register bits SR[5,4] are set.
If Buffered programming is attempted while VPP is below VPPLK, Status Register bits
SR[4,3] are set. If any errors are detected that have set Status Register bits, the
Status Register should be cleared using the Clear Status Register command.
11.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC)
flash programming for today's beat-rate-sensitive manufacturing environments. The
enhanced programming algorithm used in Buffered EFP eliminates traditional
programming elements that drive up overhead in device programmer systems.
Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 34,
“Buffered EFP Flowchart” on page 79). It uses a write buffer to spread MLC program
performance across 32 data words. Verification occurs in the same phase as
programming to accurately program the flash memory cell to the correct bit state.
A single command sequence is used to program a block of data. This enhancement
eliminates three write cycles per buffer: two commands and the word count for each
set of 32 data words. Host programmer bus cycles fill the device’s write buffer followed
by a status check. SR[0] indicates when data from the buffer has been programmed
into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 32-word array
boundary. This aspect of Buffered EFP saves host programming equipment the address-
bus setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
11.3.1
Buffered EFP Requirements and Considerations
Buffered EFP requirements:
• Ambient temperature: TC = 25°C, ±5°C
• VCC within specified operating range.
• VPP driven to VPPH
.
• Target block unlocked before issuing the Buffered EFP Setup and Confirm
commands.
• The first-word address (WA0) for the block to be programmed must be held
constant from the setup phase through all data streaming into the target block,
until transition to the exit phase is desired.
• WA0 must align with the start of an array buffer boundary1.
Buffered EFP considerations:
• For optimum performance, cycling must be limited below 100 erase cycles per
block2.
• Buffered EFP programs one block at a time; all buffer data must fall within a single
block3.
• Buffered EFP cannot be suspended.
• Programming to the flash memory array can occur only when the buffer is full4.
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• Read operation while performing Buffered EFP is not supported.
Notes:
1.
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] =
0x00.
2.
3.
4.
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work
properly.
If the internal address counter increments beyond the block's maximum address, addressing wraps around to the
beginning of the block.
If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2
Buffered EFP Setup Phase
After receiving the Buffered EFP Setup and Confirm command sequence, Status
Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with Buffered EFP
algorithm startup. A delay before checking SR[7] is required to allow the WSM enough
time to perform all of its setups and checks (Block-Lock status, VPP level, etc.). If an
error is detected, SR[4] is set and Buffered EFP operation terminates. If the block was
found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an
incorrect VPP level.
Note:
Reading from the device after the Buffered EFP Setup and Confirm command sequence
outputs Status Register data. Do not issue the Read Status Register command; it will
be interpreted as data to be loaded into the buffer.
11.3.3
Buffered EFP Program/Verify Phase
After the Buffered EFP Setup Phase has completed, the host programming system must
check SR[7,0] to determine the availability of the write buffer for data streaming.
SR[7] cleared indicates the device is busy and the Buffered EFP program/verify phase
is activated. SR[0] indicates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For Buffered EFP, the count value for buffer loading is
always the maximum buffer size of 32 words. During the buffer-loading sequence, data
is stored to sequential buffer locations starting at address 0x00. Programming of the
buffer contents to the flash memory array starts as soon as the buffer is full. If the
number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an
address outside of the current block's range during a buffer-fill sequence
causes the algorithm to exit immediately. Any data previously loaded into the
buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the Buffered EFP
algorithm will be aborted and the program fail (SR[4]) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the
flash memory array; programming continues from where the previous buffer sequence
ended. The host programming system must poll SR[0] to determine when the buffer
program sequence completes. SR[0] cleared indicates that all buffer data has been
transferred to the flash array; SR[0] set indicates that the buffer is not available yet for
the next fill cycle. The host system may check full status for errors at any time, but it is
only necessary on a block basis after Buffered EFP exit.
The host programming system continues the Buffered EFP algorithm by providing the
next group of data words to be written to the buffer. Alternatively, it can terminate this
phase by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the Buffered EFP Exit phase.
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11.3.4
11.4
Buffered EFP Exit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed
successfully. After Buffered EFP exit, any valid command can be issued to the device.
Program Suspend
Issuing the Program Suspend command while programming suspends the
programming operation. This allows data to be accessed from memory locations other
than the one being programmed. The Program Suspend command can be issued to any
device address; the corresponding partition is not affected. A program operation can be
suspended to perform reads only. Additionally, a program operation that is running
during an erase suspend can be suspended to perform a read operation (see Figure 32,
“Program Suspend/Resume Flowchart” on page 77).
When a programming operation is executing, issuing the Program Suspend command
requests the WSM to suspend the programming algorithm at predetermined points. The
partition that is suspended continues to output Status Register data after the Program
Suspend command is issued. Programming is suspended when Status Register bits
SR[7,2] are set. Suspend latency is specified in Section 7.7, “Program and Erase
Characteristics” on page 32.
To read data from blocks within the suspended partition, the Read Array command
must be issued to that partition. Read Array, Read Status Register, Read Device
Identifier, CFI Query, program RCR and Program Resume are valid commands during a
program suspend.
A program operation does not need to be suspended in order to read data from a block
in another partition that is not programming. If the other partition is already in a Read
Array, Read Device Identifier, or CFI Query state, issuing a valid address returns
corresponding read data. If the other partition is not in a read mode, one of the read
commands must be issued to the partition before data can be read.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at its programming level, and WP# must remain
unchanged while in program suspend. If RST# is asserted, the device is reset.
11.5
11.6
Program Resume
The Resume command instructs the device to continue programming, and
automatically clears Status Register bits SR[7,2]. This command can be written to any
partition. When read at the partition that’s programming, the device outputs data
corresponding to the partition’s last state. If error bits are set, the Status Register
should be cleared before issuing the next instruction. RST# must remain deasserted
(see Figure 32, “Program Suspend/Resume Flowchart” on page 77).
Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If
VPP is below VPPLK, programming operations halt and SR[3] is set indicating a VPP-level
error. Block lock registers are not affected by the voltage level on VPP; they may still be
programmed and read, even if VPP is less than VPPLK
.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 19: Example VPP Supply Connections
VCC
VCC
VPP
VCC
VPP
VCC
PROT #
VPP
≤ 10K Ω
• Low-voltage Programming only
• Logic Control of Device Protection
• Factory Programming with VPP = VPPH
• Complete write/Erase Protection when VPP ≤ VPPLK
VCC
VCC
VCC
VCC
VPP=VPPH
VPP
VPP
• Low Voltage Programming Only
• Full Device Protection Unavailable
• Low Voltage and Factory Programming
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12.0
Erase Operations
Flash erasing is performed on a block basis. An entire block is erased each time an
erase command sequence is issued, and only one block is erased at a time. When a
block is erased, all bits within that block read as logical ones. The following sections
describe block erase operations in detail.
12.1
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to
be erased (see Section 9.2, “Device Commands” on page 37). Next, the Block Erase Confirm
command is written to the address of the block to be erased. Erasing can occur in only one partition at a time;
all other partitions must be in a read state. If the device is placed in standby (CE# deasserted)
during an erase operation, the device completes the erase operation before entering
standby.VPP must be above VPPLK and the block must be unlocked (see Figure 35, “Block Erase
Flowchart” on page 80).
During a block erase, the Write State Machine (WSM) executes a sequence of
internally-timed events that conditions, erases, and verifies all bits within the block.
Erasing the flash memory array changes “zeros” to “ones.” Memory array bits that are
ones can be changed to zeros only by programming the block (see Section 11.0,
“Programming Operations” on page 49).
The Status Register can be examined for block erase progress and errors by reading
any address within the partition that is being erased. The partition remains in the Read
Status Register state until another command is written to that partition. Issuing the
Read Status Register command to another partition address sets that partition to the
Read Status Register state, allowing erase progress to be monitored at that partition’s
address. SR[0] indicates whether the addressed partition or another partition is
erasing. The partition’s Status Register bit SR[7] is set upon erase completion.
Status Register bit SR[7] indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR[5] indicates an erase
failure if set. SR[3] set would indicate that the WSM could not perform the erase
operation because VPP was outside of its acceptable limits. SR[1] set indicates that the
erase operation attempted to erase a locked block, causing the operation to abort. CE#
or OE# must be toggled to update Status Register contents.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase operation has completed.
12.2
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend command can be issued to any device address; the
corresponding partition is not affected. A block erase operation can be suspended to
perform a word or write-buffer program operation, or a read operation within any block
except the block that is erase suspended (see Figure 32, “Program Suspend/Resume
Flowchart” on page 77).
When a block erase operation is executing, issuing the Erase Suspend command
requests the WSM to suspend the erase algorithm at predetermined points. The
partition that is suspended continues to output Status Register data after the Erase
Suspend command is issued. Block erase is suspended when Status Register bits
SR[7,6] are set. Suspend latency is specified in Section 7.7, “Program and Erase
Characteristics” on page 32.
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To read data from blocks within the suspended partition (other than an erase-
suspended block), the Read Array command must be issued to that partition first.
During Erase Suspend, a Program command can be issued to any block other than the
erase-suspended block. Block erase cannot resume until program operations initiated
during erase suspend complete. Read Array, Read Status Register, Read Device
Identifier, CFI Query, and Erase Resume are valid commands during Erase Suspend.
Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block
Unlock, and Block Lock-Down are valid commands during Erase Suspend.
To read data from a block in a partition that is not erasing, the erase operation does not
need to be suspended. If the other partition is already in Read Array, Read Device
Identifier, or CFI Query, issuing a valid address returns corresponding data. If the other
partition is not in a read state, one of the read commands must be issued to the
partition before data can be read.
During an erase suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at a valid level, and WP# must remain unchanged
while in erase suspend. If RST# is asserted, the device is reset.
12.3
12.4
Erase Resume
The Erase Resume command instructs the device to continue erasing, and
automatically clears status register bits SR[7,6]. This command can be written to any
partition. When read at the partition that’s erasing, the device outputs data
corresponding to the partition’s last state. If status register error bits are set, the
Status Register should be cleared before issuing the next instruction. RST# must
remain deasserted (see Figure 32, “Program Suspend/Resume Flowchart” on page 77).
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If
VPP is below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error.
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13.0
Security Modes
The device features security modes used to protect the information stored in the flash
memory array. The following sections describe each security mode in detail.
13.1
Block Locking
Individual instant block locking is used to protect user code and/or data within the flash
memory array. All blocks power up in a locked state to protect array data from being
altered during power transitions. Any block can be locked or unlocked with no latency.
Locked blocks cannot be programmed or erased; they can only be read.
Software-controlled security is implemented using the Block Lock and Block Unlock
commands. Hardware-controlled security can be implemented using the Block Lock-
Down command along with asserting WP#. Also, VPP data security can be used to
inhibit program and erase operations (see Section 11.6, “Program Protection” on
page 53 and Section 12.4, “Erase Protection” on page 56).
13.1.1
Lock Block
To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command
issued to the desired block’s address (see Section 9.2, “Device Commands” on page 37 and
Figure 37, “Block Lock Operations Flowchart” on page 82). If the Set Read Configuration
Register command is issued after the Block Lock Setup command, the device
configures the RCR instead.
Block lock and unlock operations are not affected by the voltage level on VPP. The block
lock bits may be modified and/or read even if VPP is below VPPLK
.
Table 24: Block Locking
VPP
WP#
RST#
Block Write Protection
Block Lock Bits
X
X
VIL
All blocks write/erase protected
Block lock bits may not be changed
Lock-Down block states may not be
changed
≤ VPPLK
≤ VPPLK
> VPPLK
> VPPLK
VIL
VIH
VIL
VIH
VIH
VIH
VIH
VIH
All blocks write/erase protected
All blocks write/erase protected
All Lock-Down block states may be
changed
All Lock-Down and Locked blocks write/
erase protected
Lock-Down block states may not be
changed
All Lock-Down and Locked blocks write/
erase protected
All Lock-Down block states may be
changed
13.1.2
Unlock Block
The Unlock Block command is used to unlock blocks (see Section 9.2, “Device
Commands” on page 37). Unlocked blocks can be read, programmed, and erased.
Unlocked blocks return to a locked state when the device is reset or powered down. If a
block is in a lock-down state, WP# must be deasserted before it can be unlocked (see
Figure 20, “Block Locking State Diagram” on page 58).
13.1.3
Lock-Down Block
A locked or unlocked block can be locked-down by writing the Lock-Down Block
command sequence (see Section 9.2, “Device Commands” on page 37). Blocks in a
lock-down state cannot be programmed or erased; they can only be read. However,
unlike locked blocks, their locked state cannot be changed by software commands
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
alone. A locked-down block can only be unlocked by issuing the Unlock Block command
with WP# deasserted. To return an unlocked block to locked-down state, a Lock
command (60h/01h) must be issued prior to changing WP# to VIL. A locked or
unlocked block can be locked-down by writing the Lock-Down Block command
sequence. Locked-down blocks revert to the locked state upon reset or power up the
device (see Figure 20, “Block Locking State Diagram” on page 58).
13.1.4
Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see
Section 15.2, “Read Device Identifier” on page 67). Data bits AD[1:0] display the
addressed block’s lock status; AD0 is the addressed block’s lock bit, while AD1 is the
addressed block’s lock-down bit.
Figure 20: Block Locking State Diagram
Unlocked
Locked
Unlock
Cmd
Lock
Cmd
Unlocked
[000]
Locked
[001]
Power-Up/
Reset
Default
Lock-Down Cmd
Lock-Down Cmd
WP# Asserted
Locked
-Down
[011]
Lock-Down
Cmd
Unlock
Cmd
Unlocked
[110]
Locked
[111]
WP# De-Asserted
WP# A/DQ1 A/DQ0 Block Status
Lock-Down Cmd
x
x
0
1
1
0
0
1
1
1
0
1
1
0
1
Unlocked
Locked
Locked-Down
Unlocked
Locked
Power-Up/
Reset
Lock-Down Cmd
Default
Unlock
Cmd
Lock
Cmd
Unlocked
[100]
Locked
[101]
13.1.5
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change
block locking during an erase operation, first issue the Erase Suspend command.
Monitor the Status Register until SR[7] and SR[6] are set, indicating the device is
suspended and ready to accept another command.
Next, write the desired lock command sequence to a block, which changes the lock
state of that block. After completing block lock or unlock operations, resume the erase
operation using the Erase Resume command.
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Note:
A Lock Block Setup command followed by any command other than Lock Block, Unlock
Block, or Lock-Down Block produces a command sequence error and set Status
Register bits SR[4] and SR[5]. If a command sequence error occurs during an erase
suspend, SR[4] and SR[5] remains set, even after the erase operation is resumed.
Unless the Status Register is cleared using the Clear Status Register command before
resuming the erase operation, possible erase errors may be masked by the command
sequence error.
If a block is locked or locked-down during an erase suspend of the same block, the lock
status bits change immediately. However, the erase operation completes when it is
resumed. Block lock operations cannot occur during a program suspend. See Appendix
A, “Write State Machine” on page 69, which shows valid commands during an erase
suspend.
13.2
Protection Registers
The device contains 17 Protection Registers (PRs) that can be used to implement
system security measures and/or device identification. Each Protection Register can be
individually locked.
The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The
lower 64-bit segment is pre-programmed at the factory with a unique 64-bit number.
The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are
blank. Users can program these registers as needed. When programmed, users can
then lock the Protection Register(s) to prevent additional bit programming (see
Figure 21, “Protection Register Map” on page 60).
The user-programmable Protection Registers contain one-time programmable (OTP)
bits; when programmed, register bits cannot be erased. Each Protection Register can
be accessed multiple times to program individual bits, as long as the register remains
unlocked.
Each Protection Register has an associated Lock Register bit. When a Lock Register bit
is programmed, the associated Protection Register can only be read; it can no longer be
programmed. Additionally, because the Lock Register bits themselves are OTP, when
programmed, Lock Register bits cannot be erased. Therefore, when a Protection
Register is locked, it cannot be unlocked.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 21: Protection Register Map
0x109
128-bit Protection Register 16
(User-Programmable)
0x102
0x91
128-bit Protection Register 1
(User-Programmable)
0x8A
0x89
Lock Register 1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit Protection Register 0
64-bit Segment
(Factory-Programmed)
0x81
0x80
Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
.
13.2.1
Reading the Protection Registers
The Protection Registers can be read from within any partition’s address space. To read
the Protection Register, first issue the Read Device Identifier command at any
partitions’ address to place that partition in the Read Device Identifier state (see
Section 9.2, “Device Commands” on page 37). Next, perform a read operation at that
partition’s base address plus the address offset corresponding to the register to be
read. Table 27, “Device Identifier Information” on page 67 shows the address offsets of
the Protection Registers and Lock Registers. Register data is read 16 bits at a time.
Note:
If a program or erase operation occurs within the device while it is reading a Protection
Register, certain restrictions may apply. See Table 25, “Simultaneous Operation
Restrictions” on page 65 for details.
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13.2.2
Programming the Protection Registers
To program any of the Protection Registers, first issue the Program Protection Register
command at the parameter partition’s base address plus the offset to the desired
Protection Register (see Section 9.2, “Device Commands” on page 37). Next, write the
desired Protection Register data to the same Protection Register address (see
Figure 21, “Protection Register Map” on page 60).
The device programs the 64-bit and 128-bit user-programmable Protection Register
data 16 bits at a time (see Figure 38, “Protection Register Programming Flowchart” on
page 83). Issuing the Program Protection Register command outside of the Protection
Register’s address space causes a program error (SR[4] set). Attempting to program a
locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1]
set).
Note:
If a program or erase operation occurs when programming a Protection Register,
certain restrictions may apply. See Table 25, “Simultaneous Operation Restrictions” on
page 65 for details.
13.2.3
Locking the Protection Registers
Each Protection Register can be locked by programming its respective lock bit in the
Lock Register. To lock a Protection Register, program the corresponding bit in the Lock
Register by issuing the Program Lock Register command, followed by the desired Lock
Register data (see Section 9.2, “Device Commands” on page 37). The physical
addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These
addresses are used when programming the lock registers (see Table 27, “Device
Identifier Information” on page 67).
Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-
programmed 64-bit region of the first 128-bit Protection Register containing the unique
identification number of the device. Bit 1 of Lock Register 0 can be programmed by the
user to lock the user-programmable, 64-bit region of the first 128-bit Protection
Register. The other bits in Lock Register 0 are not used.
Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers.
Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit
Protection Registers. Programming a bit in Lock Register 1 locks the corresponding
128-bit Protection Register.
Caution:
After being locked, the Protection Registers cannot be unlocked.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
14.0
Dual-Operation Considerations
The multi-partition architecture of the device allows background programming (or
erasing) to occur in one partition while data reads (or code execution) take place in
another partition.
14.1
Memory Partitioning
The flash memory array is divided into multiple 8-Mbit partitions, which allows
simultaneous read-while-write operations. Simultaneous program and erase is not
allowed. Only one partition at a time can be in program or erase mode.
The flash device supports read-while-write operations with bus cycle granularity and
not command granularity. In other words, it is not assumed that both bus cycles of a
two cycle command (an erase command for example) will always occur as back to back
bus cycles to the flash device. In practice, code fetches (reads) may be interspersed
between write cycles to the flash device, and they will likely be directed to a different
partition than the one being written. This is especially true when a processor is
executing code from one partition that instructs the processor to program or erase in
another partition.
14.2
Read-While-Write Command Sequences
When issuing commands to the device, a read operation can occur between 2-cycle
Write command’s (Figure 22, and Figure 23). However, a write operation issued
between a 2-cycle commands write sequence causes a command sequence error. (See
Figure 24)
When reading from the same partition after issuing a Setup command, Status Register
data is returned, regardless of the read mode of the partition prior to issuing the Setup
command.
Figure 22: Operating Mode with Correct Command Sequence Example
Address/Data [A/D]
ADV#
Partition A
Data: 0x20
Partition A
Data: 0xD0
Partition B
Data: 0xFF
CE#
WE# [W]
OE# [G]
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Figure 23: Operating Mode with Correct Command Sequence Example
Addr/Data [A/D]
ADV#
Partition A
Data: 0x20
Partition B
Array Data
Partition A
Data: 0xD0
CE#
WE# [W]
OE# [G]
Figure 24: Operating Mode with Illegal Command Sequence Example
Addr/Data [A/D]
ADV#
Part.
A
Data: 0x20
Part.
B
Data: 0xFF
Part.
A
Data: 0xD0
Part.
A
Data: SR
CE#
WE# [W]
OE# [G]
14.2.1
Simultaneous Operation Details
The L18 device supports simultaneous read from one partition while programming or
erasing in any other partition. Certain features like the Protection Registers and CFI
Query data have special requirements with respect to simultaneous operation
capability. (Table 25 provides details on restrictions during simultaneous operations.)
14.2.2
Synchronous and Asynchronous Read-While-Write
Characteristics and Waveforms
This section describes the transitions of write operation to asynchronous read, write to
synchronous read, and write operation with clock active.
14.2.2.1
Write operation to asynchronous read transition
W18 - tWHAV
The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when
transitioning from a write cycle (WE# going high) to perform an asynchronous read
(only address valid is required).
14.2.2.2
Write to synchronous read operation transition
W19 and W20 - tWHCV and tWHVH
The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE#
High to ADV# High) is required when transitioning from a write cycle (WE# going high)
to perform a synchronous burst read. A delay from WE# going high to a valid clock
edge or ADV# going high to latch a new address must be met.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
14.2.2.3
Write Operation with Clock Active
W21 - tVHWL
W22 - tCHWL
The AC parameters W21 (tVHWL- ADV# High to WE# Low) and W22 (tCHWL -Clock high
to WE# low) are required when the device is in a synchronous mode and clock is active.
A write bus cycle consists of two parts:
• the host provides an address to the flash device; and
• the host then provides data to the flash device.
The flash device in turn binds the received data with the received address. When
operating synchronously (RCR.15 = 0), the address of a write cycle may be provided to
the flash by the first active clock edge with ADV# low, or rising edge of ADV# as long
as the applicable cycle separation conditions are met between each cycle.
If neither a clock edge nor a rising ADV# edge is used to provide a new address at the
beginning of a write cycle (the clock is stopped and ADV# is low), the address may also
be provided to the flash device by holding the address bus stable for the required
amount of time (W5, tAVWH) before the rising WE# edge.
Alternatively, the host may choose not to provide an address to the flash device during
subsequent write cycles (if ADV# is high and only CE# or WE# is toggled to separate
the prior cycle from the current write cycle). In this case, the flash device will use the
most recently provided address from the host.
Refer to Figure 11, “Write to Asynchronous Read Timing” on page 28, Figure 12,
“Synchronous Read to Write Timing” on page 29, and Figure 13, “Write to Synchronous
Read” on page 30, for representation of these timings.
14.2.3
Read Operation During Buffered Programming Flowchart
The multi-partition architecture of the device allows background programming (or
erasing) to occur in one partition while data reads (or code execution) take place in
another partition.
To perform a read while buffered programming operation, first issue a Buffered
Program set up command in a partition. When a read operation occurs in the same
partition after issuing a setup command, Status Register data will be returned,
regardless of the read mode of the partition prior to issuing the setup command.
To read data from a block in other partition and the other partition already in read array
mode, a new block address must be issued. However, if the other partition is not
already in read array mode, issuing a read array command will cause the buffered
program operation to abort and a command sequence error would be posted in the
Status Register. See Figure 33, “Buffer Program Flowchart” on page 78 for more
details.
Note:
Simultaneous read-while-Buffered EFP is not supported.
14.2.4
Simultaneous Operation Restrictions
The Protection Registers share some of the same internal flash resources as the
parameter partition. Therefore, simultaneous read-while-write is only allowed between
the protection register and main partitions. Table 25 describes the operation allowed
using read-while-write/erase with the protection register.
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 25: Simultaneous Operation Restrictions
Protection
Register or
CFI data
Parameter
Partition
Array Data
Other
Partitions
Notes
While programming or erasing in a main partition, the Protection Register or
CFI data may be read from any other partition.
Read
(See Notes)
Read
Write/Erase
Write/Erase
Write/Erase
Reading the parameter partition array data is not allowed if the Protection
Register or Query data is being read from addresses within the parameter
partition.
While programming or erasing in a main partition, read operations are allowed
in the parameter partition.
(See Notes)
Accessing the Protection Registers or CFI data from parameter partition
addresses is not allowed when reading array data from the parameter
partition.
While programming or erasing in a main partition, read operations are allowed
in the parameter partition.
Accessing the Protection Registers or CFI data in a partition that is different
from the one being programed/erased, and also different from the parameter
partition is allowed.
Read
Read
While programming the Protection Register, reads are only allowed in the other
main partitions.
No Access
Allowed
Write
Read
Read
Access to array data in the parameter partition is not allowed. Programming of
the Protection Register can only occur in the parameter partition, which means
this partition is in Read Status.
While programming or erasing the parameter partition, reads of the Protection
No Access
Allowed
Registers or CFI data are not allowed in any partition.
Write/Erase
Reads in partitions other than the parameter partition are supported.
November 2007
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
15.0
Special Read States
The following sections describe non-array read states. Non-array reads can be
performed in asynchronous read or synchronous burst mode. A non-array read
operation is exactly the same as an array read. However, when using synchronous
burst mode for non-array reads, the same word of data requested will be output on
successive clock edges until the burst length requirements are satisfied. The “flow-
through” feature also applies to synchronous non-array reads. Refer to Section 10.3.1,
“Read Mode” on page 43 for details.
15.1
Read Status Register
The status of any partition is determined by reading the Status Register from the
address of that particular partition. To read the Status Register, issue the Read Status
Register command within the desired partition’s address range. Status Register
information is available at the partition address to which the Read Status Register,
Word Program, or Block Erase command was issued. Status Register data is
automatically made available following a Word Program, Block Erase, or Block Lock
command sequence. Reads from a partition after any of these command sequences
outputs that partition’s status until another valid command is written to that partition
(e.g. Read Array command).
Status Register data is output on AD[7:0], while 0x00 is output on AD[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update status data. Status
Register read operations do not affect the read state of the other partitions.
The Device Write Status bit (SR[7]) provides overall status of the device. The Partition
Status bit (SR[0]) indicates whether the addressed partition or some other partition is
actively programming or erasing. Status register bits SR[6:1] present status and error
information about the program, erase, suspend, VPP, and block-locked operations.
Table 26: Status Register Description (Sheet 1 of 2)
Status Register (SR)
Default Value = 0x80
Erase
Suspend
Status
Program
Suspend
Status
Device Write
Status
Program
Status
Block-Locked
Partition
Status
Erase Status
VPP Status
Status
DWS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
PWS
0
Bit
Name
Description
0 = Device is busy; program or erase cycle in progress; SR[0] valid.
1 = Device is ready; SR[6:1] are valid.
7
6
5
4
3
Device Write Status (DWS)
Erase Suspend Status (ESS)
Erase Status (ES)
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
0 = Erase successful.
1 = Erase fail or program sequence error when set with SR[4,7].
0 = Program successful.
1 = Program fail or program sequence error when set with SR[5,7].
Program Status (PS)
VPP Status (VPPS)
0 = VPP within acceptable limits during program or erase operation.
1 = VPP < VPPLK during program or erase operation.
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Table 26: Status Register Description (Sheet 2 of 2)
Status Register (SR)
Default Value = 0x80
0 = Program suspend not in effect.
1 = Program suspend in effect.
Program Suspend Status
(PSS)
2
1
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
Block-Locked Status (BLS)
Partition Write Status (PWS)
DWS PWS
0 0 = Program or erase operation in addressed partition.
0 1 = Program or erase operation in other partition.
1 0 = No active program or erase operations.
1 1 = Reserved.
0
(Non-buffered EFP operation. For Buffered EFP operation, see Section 11.3,
“Buffered Enhanced Factory Programming” on page 51).
Always clear the Status Register prior to resuming erase operations. Avoid Status
Register ambiguity when issuing commands during Erase Suspend. If a command
sequence error occurs during an erase-suspend state, the Status Register contains the
command sequence error status (SR[7,5,4] set). When the erase operation resumes
and finishes, possible errors during the erase operation cannot be detected via the
Status Register because it contains the previous error status.
15.1.1
15.2
Clear Status Register
The Clear Status Register command clears the status register, leaving all partition read
states unchanged. It functions independent of VPP. The Write State Machine (WSM) sets
and clears SR[7,6,2,0], but it sets bits SR[5:3,1] without clearing them. The Status
Register should be cleared before starting a command sequence to avoid any
ambiguity. A device reset also clears the Status Register.
Read Device Identifier
The Read Device Identifier command instructs the addressed partition to output
manufacturer code, device identifier code, block-lock status, protection register data,
or configuration register data when that partition’s addresses are read (see Section 9.2,
“Device Commands” on page 37 for details on issuing the Read Device Identifier
command). Table 27, “Device Identifier Information” on page 67 and Table 28, “Device
ID codes” on page 68 show the address offsets and data values for this device.
Issuing a Read Device Identifier command to a partition that is programming or erasing
places that partition in the Read Identifier state while the partition continues to
program or erase in the background.
Table 27: Device Identifier Information (Sheet 1 of 2)
Item
Address(1,2)
Data
Manufacturer Code
Device ID Code
PBA + 0x00
PBA + 0x01
0089h
ID (see Table 28)
Lock Bit:
Block Lock Configuration:
• Block Is Unlocked
• Block Is Locked
AD0 = 0b0
BBA + 0x02
PBA + 0x05
AD0 = 0b1
• Block Is not Locked-Down
• Block Is Locked-Down
Configuration Register
AD1 = 0b0
AD1 = 0b1
Configuration Register Data
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 27: Device Identifier Information (Sheet 2 of 2)
Item
Address(1,2)
Data
Lock Register 0
PBA + 0x80
PBA + 0x81–0x84
PBA + 0x85–0x88
PBA + 0x89
Protection Register Lock Bits
Factory Protection Register Data
User Protection Register Data
Protection Register Lock Bits
User Protection Register Data
64-bit Factory-Programmed Protection Register
64-bit User-Programmable Protection Register
Lock Register 1
128-bit User-Programmable Protection Registers
Notes:
PBA + 0x8A–0x109
1.
2.
PBA = Partition Base Address.
BBA = Block Base Address.
Table 28: Device ID codes
Device Identifier Codes
ID Code Type
Device Density
–T
–B
(Top Parameter)
(Bottom Parameter)
64 Mbit
128 Mbit
256 Mbit
8808
8809
880A
8834
8835
8836
Device Code
15.3
CFI Query
The CFI Query command instructs the device to output Common Flash Interface (CFI)
data when partition addresses are read. See Section 9.2, “Device Commands” on
page 37 for details on issuing the CFI Query command. Appendix B, “Common Flash
Interface (CFI)” on page 83 shows CFI information and address offsets within the CFI
database.
Issuing the CFI Query command to a partition that is programming or erasing places
that partition’s outputs in the CFI Query state, while the partition continues to program
or erase in the background.
The CFI Query command is subject to read restrictions dependent on parameter
partition availability, as described in Table 25.
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Appendix A Write State Machine
Figure 25 through Figure 30 show the command state transitions (Next State Table)
based on incoming commands. Only one partition can be actively programming or
erasing at a time. Each partition stays in its last read state (Read Array, Read Device
ID, CFI Query or Read Status Register) until a new command changes it. The next WSM
state does not depend on the partition’s output state.
Figure 25: Write State Machine—Next State Table (Sheet 1 of 6)
Command Input to Chip and resulting Chip Next State
BE Confirm,
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
P/E
Resume,
ULB,
Confirm (8)
Clear
Status
Register (5)
Lock, Unlock,
Lock-down,
CR setup (4)
Buffered
Program
(BP)
BP / Prg /
Erase
Suspend
Read
Word
Program (3,4)
Erase
Setup (3,4)
Read
Status
Read
ID/Query
(2)
Current Chip
State (7)
Array
(FFH)
(10H/40H)
(E8H)
(20H)
(80H)
(D0H)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
Program
Setup
Erase
Setup
Lock/CR
Setup
Ready
Ready
Ready
BP Setup
BEFP Setup
Ready
(Unlock
Block)
Lock/CR Setup
Ready (Lock Error)
Ready (Lock Error)
Setup
OTP
Busy
OTP Busy
Word Program Busy
Word
Setup
Program Busy
Word Program Busy
Busy
Program
Suspend
Word
Program
Word
Program
Busy
Word Program Suspend
Word Program Suspend
Suspend
BP Load 1
BP Load 2
Setup
BP Load 1
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
BP Load 2
BP
BP
Confirm
Ready (Error)
Ready (Error)
BP Busy
BP Busy
BP Busy
BP Suspend
Ready (Error)
Erase Busy
BP Busy
BP Suspend
BP
Suspend
BP Suspend
Ready (Error)
BP Busy
Setup
Erase Busy
Erase
Suspend
Erase Busy
Busy
Erase
Word
Program
Setup in
Erase
Lock/CR
Setup in
Erase
BP Setup in
Erase
Suspend
Erase
Suspend
Erase Suspend
Erase Suspend
Suspend
Erase Busy
Suspend
Suspend
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Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 26: Write State Machine—Next State Table (Sheet 2 of 6)
Chip
Command Input to Chip and resulting
Next State
BE Confirm,
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
P/E
Resume,
ULB,
Confirm (8)
Clear
Status
Register (5)
Lock, Unlock,
Lock-down,
CR setup (4)
Buffered
Program
(BP)
BP / Prg /
Erase
Suspend
Read
Word
Program (3,4)
Erase
Setup (3,4)
Read
Status
Read
ID/Query
(2)
Current Chip
State (7)
Array
(FFH)
(10H/40H)
(E8H)
(20H)
(80H)
(D0H)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
Word Program Busy in Erase Suspend
Setup
Word
Program
Word Program Busy in Erase Suspend
Word Program Busy in Erase Suspend Busy
Word Program Suspend in Erase Suspend
Busy
Suspend in
Erase
Suspend
Word
Program in
Erase
Word
Program
Busy in
Erase
Suspend
Word Program Suspend in Erase Suspend
Suspend
Suspend
BP Load 1
BP Load 2
Setup
BP Load 1
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
BP Load 2
BP Busy in
Erase
Suspend
BP in Erase
Suspend
BP
Confirm
Erase Suspend (Error)
Ready (Error in Erase Suspend)
BP Suspend
in Erase
BP Busy in Erase Suspend
BP Busy in Erase Suspend
BP Busy
Suspend
BP Busy in
Erase
Suspend
BP
Suspend
BP Suspend in Erase Suspend
BP Suspend in Erase Suspend
Erase
Suspend
(Unlock
Block)
Lock/CR Setup in Erase
Suspend
Erase Suspend (Lock Error)
Ready (Error)
Erase Suspend (Lock Error [Botch])
Ready (Error)
BEFP
Loading
Buffered
Setup
Enhanced
Data (X=32)
Factory
Program
BEFP
Mode
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)
Busy
Datasheet
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November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 27: Write State Machine—Next State Table (Sheet 3 of 6)
Chip
Command Input to Chip and resulting
Next State
Lock
Block
Confirm (8) Confirm
Lock-Down
OTP
Setup (4)
Write RCR
Block Address
Illegal Cmds or
BEFP Data (1)
Block
WSM
Operation
Completes
(8)
9
Current Chip
State (7)
Confirm
(?WA0)
(8)
(C0H)
(01H)
(2FH)
(03H)
(XXXXH)
(all other codes)
OTP
Setup
Ready
Ready
Ready
(Lock
Error)
Ready
(Lock
Block)
Ready
(Lock Down
Blk)
Ready
(Set CR)
N/A
Ready (Lock Error)
Lock/CR Setup
Setup
OTP Busy
OTP
Busy
Ready
N/A
Word Program Busy
Word Program Busy
Setup
Ready
Busy
Word
Program
Word Program Suspend
BP Load 1
Suspend
Setup
BP Load 2
Ready (BP Load 2 BP Load 2
BP Load 1
BP Confirm if
Data load into
Program Buffer is
complete; ELSE
BP Load 2
N/A
BP Confirm if Data load into Program Buffer is
complete; ELSE BP load 2
Ready
BP Load 2
BP
Ready (Error)
(Proceed if
unlocked or lock
error)
BP
Confirm
Ready (Error)
Ready (Error)
BP Busy
BP Busy
BP Suspend
Ready (Error)
Erase Busy
Ready
N/A
BP
Suspend
Setup
Busy
Ready
Erase
Suspend
Erase Suspend
N/A
November 2007
Order Number: 313295-04
Datasheet
71
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 28: Write State Machine—Next State Table (Sheet 4 of 6)
Chip
Command Input to Chip and resulting
Next State
Lock
Block
Confirm (8) Confirm
Lock-Down
OTP
Setup (4)
Write RCR
Block Address
Illegal Cmds or
BEFP Data (1)
Block
WSM
Operation
Completes
(8)
9
Current Chip
State (7)
Confirm
(?WA0)
(8)
(C0H)
(01H)
(2FH)
(03H)
(XXXXH)
(all other codes)
Word Program Busy in Erase Suspend
Setup
NA
Word Program Busy in Erase Suspend Busy
Busy
Erase Suspend
Word
Program in
Erase
Suspend
Word Program Suspend in Erase Suspend
BP Load 1
Suspend
N/A
Setup
BP Load 2
Ready (BP Load 2 BP Load 2
BP Load 1
BP Confirm if
Data load into
Program Buffer is
complete; Else
BP Load 2
BP Confirm if Data load into Program Buffer is
complete; Else BP Load 2
N/A
Ready
BP Load 2
BP in Erase
Suspend
BP
Ready (Error)
(Proceed if
unlocked or lock
error)
Ready (Error in Erase Suspend)
Ready (Error)
Confirm
BP Busy in Erase Suspend
Erase Suspend
BP Busy
BP
Suspend
BP Suspend in Erase Suspend
Erase
Suspend Suspend
(Lock
Error)
Erase
Erase
Erase
Suspend
Lock/CR Setup in Erase
Suspend
Erase Suspend (Lock Error)
Suspend
(Set CR)
N/A
(Lock
Block)
(Lock Down
Block)
Ready (BEFP
Ready (Error)
Loading Data)
Ready (Error)
Buffered
Enhanced
Factory
Program
Mode
Setup
BEFP Program and Verify Busy (if Block Address
given matches address given on BEFP Setup
command). Commands treated as data. (7)
BEFP
Busy
Ready
Ready
BEFP Busy
Datasheet
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November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 29: Write State Machine—Next State Table (Sheet 5 of 6)
Output Next State Table
Output
Command Input to Chip and resulting
Mux Next State
BE Confirm,
Buffered
P/E
Clear
Status
Register (5)
Lock, Unlock,
Lock-down,
Word
Program
Setup (3,4)
Program/
Erase
Suspend
Read
Erase
Enhanced
Factory Pgm
Setup (3, 4)
Read
Status
Read
ID/Query
Resume,
BP Setup
(E8H)
(2)
Array
Setup (3,4)
Current chip state
CR setup (4)
ULB Confirm
(8)
(FFH)
(10H/40H)
(20H)
(30H)
(D0H)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
BEFP Setup,
BEFP Pgm & Verify
Busy,
Erase Setup,
OTP Setup,
BP: Setup, Load 1,
Load 2, Confirm,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
Status Read
BP Setup, Load1,
Load 2, Confirm in
Erase Suspend
Lock/CR Setup,
Lock/CR Setup in
Erase Susp
Status Read
Status
Read
OTP Busy
Ready,
Erase Suspend,
BP Suspend
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
Output mux
does not
change.
Read Array
Status Read
Output does not change.
Status Read
Status Read
ID Read
BP Busy in Erase
Suspend
Word Pgm
Suspend,
Word Pgm Busy in
Erase Suspend,
Pgm Suspend In
Erase Suspend
November 2007
Order Number: 313295-04
Datasheet
73
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 30: Write State Machine—Next State Table (Sheet 6 of 6)
Output Next State Table
Output
Command Input to Chip and resulting
Mux Next State
Lock
Block
Confirm (8) Confirm
Lock-Down
OTP
Setup (4)
Write CR
Illegal Cmds or
BEFP Data (1)
Block Address
(?WA0)
Block
WSM
(8)
Confirm
(8)
Operation
Completes
Current chip state
(C0H)
(01H)
(2FH)
(03H)
(FFFFH)
(all other codes)
BEFP Setup,
BEFP Pgm & Verify
Busy,
Erase Setup,
OTP Setup,
BP: Setup, Load 1,
Load 2, Confirm,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
Status Read
BP Setup, Load1,
Load 2, Confirm in
Erase Suspend
Lock/CR Setup,
Lock/CR Setup in
Erase Susp
Array
Read
Status Read
Status Read
Output does
not change.
OTP Busy
Ready,
Erase Suspend,
BP Suspend
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
Status
Read
Output does not
change.
Output does not change.
Array Read
BP Busy in Erase
Suspend
Word Pgm
Suspend,
Word Pgm Busy in
Erase Suspend,
Pgm Suspend In
Erase Suspend
Notes:
1.
2.
3.
4.
"Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase],
etc.)
If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at
different locations in the address map.
1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will
occur.
To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle
command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an
erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be
ignored because it is unclear whether the user intends to erase the block or resume the program operation.
The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM
running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes).
5.
Datasheet
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November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
6.
7.
BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored.
The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI
or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on
where the partition's output mux is presently pointing to.
8.
9.
Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then
move to the Ready State.
WA0 refers to the block address latched during the first write cycle of the current operation.
November 2007
Order Number: 313295-04
Datasheet
75
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Appendix B Flowcharts
Figure 31: Word Program Flowchart
WORD PROGRAM PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0x40
Setup Addr = Location to program
Write
Write
Read
Write 0x40,
(Setup)
Word Address
Data = Data to program
Data
Addr = Location to program
Write Data,
(Confirm)
Word Address
None
None
Status register data
Program
Suspend
Loop
Read Status
Register
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Idle
No
Yes
0
SR[7] =
1
Suspend?
Repeat for subsequent Word Program operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Full Status
Check
(if desired)
Write 0xFF after the last operation to set to the Read Array
state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = VPP Error
Idle
Idle
None
None
1
1
1
VPP Range
Error
SR[3] =
0
Check SR[4]:
1 = Data Program Error
Program
Error
Check SR[1]:
1 = Block locked; operation aborted
SR[4] =
0
Idle
None
If an error is detected, clear the Status Register before
continuing operations - only the Clear Staus Register
command clears the Status Register error bits.
Device
Protect Error
SR[1] =
0
Program
Successful
Datasheet
76
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 32: Program Suspend/Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Start
Bus
Operation
Program Suspend
Write B0h
Command
Comments
Any Address
Program Data = B0h
Suspend Addr = Block to suspend (BA)
Write
Write
Read
Read Status
Write 70h
Same Partition
Read
Status
Data = 70h
Addr = Same partition
Read Status
Register
Status register data
Addr = Suspended block (BA)
Check SR.7
Standby
Standby
1 = WSM ready
0 = WSM busy
0
0
SR.7 =
1
Check SR.2
1 = Program suspended
0 = Program completed
Program
Completed
SR.2 =
Data = FFh
Addr = Any address within the
suspended partition
1
Read
Array
Write
Read
Write
Read Array
Write FFh
Susp Partition
Read array data from block other than
the one being programmed
Read Array
Data
Program Data = D0h
Resume Addr = Suspended block (BA)
If the suspended partition was placed in Read Array mode:
Done
No
Reading
Return partition to Status mode:
Read
Write
Data = 70h
Yes
Status
Addr = Same partition
Program Resume
Read Array
Write FFh
Write D0h
Any Address
Pgm'd Partition
Program
Resumed
Read Array
Data
Read Status
Write 70h
Same Partition
PGM_SUS.WMF
November 2007
Order Number: 313295-04
Datasheet
77
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 33: Buffer Program Flowchart
Buffer Programming Procedure
Start
Bus
Operation
Command
Comments
Device
Supports Buffer
Writes?
Use Single Word
Programming
Buffer Prog. Data = 0xE8
Write
Read
No
Setup
None
Addr = Word Address
SR[7] = Valid
Addr = Word Address
Yes
Set Timeout or
Loop Counter
Check SR[7]:
1 = Write Buffer available
0 = No Write Buffer available
Idle
None
None
Get Next
Target Address
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Word Address
Write
(Notes 1, 2)
Issue Buffer Prog. Cmd.
0xE8,
Write
(Notes 3, 4)
Data = Write Buffer Data
Addr = Start Word Address
None
None
Word Address
Write
(Note 3)
Data = Write Buffer Data
Addr = Word Address
Read Status Register
at Word Address
Write
Buffer Prog. Data = 0xD0
(Notes 5, 6)
Conf.
Addr = Original Word Address
No
Status register Data
Addr = Note 7
Read
Idle
None
Timeout
or Count
Expired?
Write Buffer
Available?
SR[7] =
0 = No
Yes
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
None
1 = Yes
Write Word Count,
Word Address
1. Word count value on D[7:0] is loaded into the word count
register. Count ranges for this device are N = 0x00 to 0x1F.
2. The device outputs the Status Register when read.
3. Write Buffer contents will be programmed at the issued word
address.
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A[4:0] of the Start
Word Address = 0x00).
5. The Buffered Programming Confirm command must be
issued to an address in the same block, for example, the
original Start Word Address, or the last address used during the
loop that loaded the buffer data.
Buffer Program Data,
Start Word Address
X = X + 1
Write Buffer Data,
Word Address
X = 0
No
No
6. The Status Register indicates an improper command
sequence if the Buffer Program command is aborted; use the
Clear Status Register command to clear error bits.
7. The Status Register can be read from any addresses within
the programming partition.
Abort Buffer
Program?
X = N?
Yes
Yes
Write to another
Block Address
Write Confirm 0xD0
and Word Address
(Note 5)
Full status check can be done after all erase and write
sequences complete. Write 0xFF after the last operation to
place the partition in the Read Array state.
Issue Read
Status Register
Command
Buffer Program Aborted
Read Status Register
(Note 7)
Suspend
Program
Loop
No
0=No
Yes
Suspend
Program?
Is BP finished?
SR[7] =
1=Yes
Full Status
Check if Desired
Program Complete
Datasheet
78
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 34: Buffered EFP Flowchart
BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE
Setup Phase
Program & Verify Phase
Exit Phase
Start
Read Status Reg.
Read Status Reg.
VPP applied,
Block unlocked
No (SR[0]=1)
No (SR[7]=0)
BEFP
Exited?
Data Stream
Ready?
Yes (SR[7]=1)
Yes (SR[0]=0)
Write 0x80 @
1ST Word Address
Initialize Count:
X = 0
Full Status Check
Procedure
Write 0xD0 @
1STWord Address
Write Data @ 1ST
Word Address
Program
Complete
BEFP setup delay
Read Status Reg.
Increment Count:
X = X+1
N
X = 32?
Yes (SR[7]=0)
BEFP Setup
Done?
Y
Read Status Reg.
No (SR[7]=1)
No (SR[0]=1)
Check VPP, Lock
Errors (SR[3,1])
Program
Done?
Exit
Yes (SR[0]=0)
N
Last
Data?
Y
Write 0xFFFF,
Address Not within
Current Block
BEFP Setup
BEFP Program & Verify
BEFP Exit
Bus
State
Bus
State
Operation
Comments
Bus State Operation
Comments
Operation
Status
Comments
Data = Status Reg. Data
Unlock
Block
Status
Read
Data = Status Register Data
Address = 1ST Word Addr.
Write
VPPHapplied to VPP
Read
Register
Register Address = 1ST Word Addr
Write
(Note 1)
BEFP
Setup
Data = 0x80 @ 1ST Word
Address
Check SR[0]:
0 = Ready for Data
1 = Not Ready for Data
Check SR[7]:
Check Exit
Data Stream
Standby
Standby
0 = Exit Not Completed
Status
Ready?
1 = Exit Completed
ST Word
Data = 0xD0 @
BEFP
Confirm Address
Write
Read
1
Initialize
Standby
Repeat for subsequent blocks;
X = 0
Count
Status
Data = Status Reg. Data
After BEFP exit, a full Status Register check can
determine if any program error occurred;
Register Address = 1STWord Addr
Write
Load
Data = Data to Program
Address = 1ST Word Addr.
(Note 2)
Buffer
BEFP
Setup
Done?
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
See full Status Register check procedure in the
Word Program flowchart.
Standby
Increment
Count
Standby
Standby
Read
X = X+1
Write 0xFF to enter Read Array state.
X = 32?
Yes = Read SR[0]
No = Load Next Data Word
Error
If SR[7] is set, check:
Buffer
Full?
Standby Condition SR[3] set = VPP Error
Check SR[1] set = Locked Block
Status
Register
Data = Status Reg. data
Address = 1ST Word Addr.
Check SR[0]:
0 = Program Done
1 = Program in Progress
Program
Done?
Standby
Last
Data?
No = Fill buffer again
Yes = Exit
Standby
Write
Exit Prog & Data = 0xFFFF @ address not in
Verify Phase current block
NOTES:
1. First-word address to be programmed within the target blockmust be aligned on a write-buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word addresWs;SM internally increments addressing.
November 2007
Order Number: 313295-04
Datasheet
79
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 35: Block Erase Flowchart
BLOCK ERASE PROCEDURE
Bus
Operation
Start
Command
Comments
Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write
Write
Read
Write 0x20,
(Block Erase)
Block Address
Erase Data = 0xD0
Confirm Addr = Block to be erased (BA)
Write 0xD0,
(Erase Confirm)
Block Address
None
None
Status Register data.
Suspend
Erase
Loop
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle
No
Suspend
Erase
0
Yes
SR[7] =
1
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Write 0xFF after the last operation to enter read array mode.
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = VPP Range Error
Idle
Idle
Idle
None
None
None
1
VPP Range
Error
SR[3] =
0
Check SR[4,5]:
Both 1 = Command Sequence Error
1,1
1
Command
Sequence Error
Check SR[5]:
1 = Block Erase Error
SR[4,5] =
0
Check SR[1]:
1 = Attempted erase of locked block;
erase aborted.
Block Erase
Error
Idle
None
SR[5] =
0
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
1
Block Locked
Error
SR[1] =
0
Block Erase
Successful
Datasheet
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November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 36: Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Start
Bus
Command
Comments
Operation
Write 0x70,
Same Partition
Read
Status
Data = 0x70
Addr = Any partition address
(Read Status)
Write
Write
Read
Data = 0xB0
Addr = Same partition address as
above
Erase
Suspend
Write 0xB0,
Any Address
(Erase Suspend)
Status Register data.
Addr = Same partition
None
None
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle
0
SR[7] =
1
Check SR[6]:
1 = Erase suspended
Idle
None
0 = Erase completed
0
Erase
Completed
SR[6] =
1
Data = 0xFF or 0x40
Addr = Any address within the
suspended partition
Read Array
or Program
Write
Read or
Write
Read array or program data from/to
block other than the one being erased
Read
Program
Read or
Program?
None
Read Array
Data
Program
Loop
Program Data = 0xD0
Resume Addr = Any address
No
Write
Done
If the suspended partition was placed in
Read Array mode or a Program Loop:
Read
Status
Return partition to Status mode:
Data = 0x70
Write 0xD0,
Any Address
Write
(Erase Resume)
Register Addr = Same partition
Erase
Resumed
Write 0xFF,
Erased Partition
(Read Array)
Write 0x70,
Same Partition
Read Array
Data
(Read Status)
November 2007
Order Number: 313295-04
Datasheet
81
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 37: Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Bus
Command
Comments
Operation
Write 0x60,
Block Address
Lock
Setup
Data = 0x60
Addr = Block to lock/unlock/lock-down
(Lock Setup)
Write
Lock,
Unlock, or
Lock-Down
Data = 0x01 (Block Lock)
0xD0 (Block Unlock)
Write either
0x01/0xD0/0x2F,
Block Address
(Lock Confirm)
(Read Device ID)
Write
Write
0x2F (Lock-Down Block)
Confirm Addr = Block to lock/unlock/lock-down
Read Data = 0x90
(Optional) Device ID Addr = Block address + offset 2
Write 0x90
Read
(Optional)
Block Lock Block Lock status data
Status Addr = Block address + offset 2
Read Block
Lock Status
Idle
None
Confirm locking change on D[1,0].
Locking
No
Change?
Yes
Read
Array
Data = 0xFF
Addr = Block address
Write
Write 0xFF
Partition Address
(Read Array)
Lock Change
Complete
Datasheet
82
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Figure 38: Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0xC0
PR Setup Addr = First Location to Program
Write
Write
Read
Write 0xC0,
PR Address
(Program Setup)
(Confirm Data)
Protection Data = Data to Program
Program Addr = Location to Program
Write PR
Address & Data
None
None
Status Register Data.
Read Status
Register
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Idle
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
0
SR[7] =
1
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
Bus
Operation
Command
Comments
Check SR[3]:
1 =VPP Range Error
Idle
Idle
Idle
None
1
1
SR[3] =
0
VPP Range Error
Check SR[4]:
1 =Programming Error
None
None
Check SR[1]:
1 =Block locked; operation aborted
SR[4] =
0
Program Error
Only the Clear Staus Register command clears SR[1, 3, 4].
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
1
Register Locked;
Program Aborted
SR[1] =
0
Program
Successful
B.1
Common Flash Interface (CFI)
Common Flash Interface (CFI) is part of an overall specification for multiple command-
set and control-interface descriptions. This appendix describes the database structure
containing the data returned by a read operation after issuing the CFI Query command
(see Section 9.2, “Device Commands” on page 37). System software can parse this
November 2007
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Datasheet
83
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
database structure to obtain information about the flash device, such as block size,
density, bus width, and electrical specifications. The system software will then know
which command set(s) to use to properly perform flash writes, block erases, reads and
otherwise control the flash device.
B.2
Query Structure Output
The Query database allows system software to obtain information for controlling the
flash device. This section describes the device’s CFI-compliant interface that allows
access to Query data.
Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical
offset value is the address relative to the maximum bus width supported by the device.
On this family of devices, the Query table device starting address is a 10h, which is a
word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0
and 00h in the high byte (DQ15-8).
)
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
Table 29: Summary of Query Structure Output as a Function of Device and Mode
Device
Hex Offset
00010
Hex Code
ASCII Value
51
52
59
“Q”
“R”
“Y”
Device Addresses
00011
00012
Table 30: Example of Query Structure Output of x16- Devices
Word Addressing:
Byte Addressing:
Offset
AX–A0
Hex Code
Value
Offset
AX–A0
Hex Code
Value
D15–D0
D7–D0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
0051
0052
0059
P_IDLO
P_IDHI
PLO
"Q"
"R"
"Y"
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
51
52
59
P_IDLO
P_IDLO
P_IDHI
...
"Q"
"R"
"Y"
PrVendor
ID #
PrVendor
TblAdr
AltVendor
ID #
PrVendor
ID #
ID #
PHI
...
A_IDLO
A_IDHI
...
...
B.3
Query Structure Overview
The Query command causes the flash component to display the Common Flash
Interface (CFI) Query structure or “database.” The structure sub-sections and address
locations are summarized below.
Datasheet
84
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 31: Query Structure
Description(1)
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
Offset
00001-Fh Reserved
00010h
0001Bh
00027h
P(3)
Sub-Section Name
CFI query identification string
System interface information
Device geometry definition
Primary Intel-specific Extended Query Table
Vendor-defined additional information specific
Notes:
1.
Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of
device bus width and mode.
2.
3.
BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 16K-word).
Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
B.4
CFI Query Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
Table 32: CFI Identification
Hex
Code
--51
--52
--59
--01
--00
--0A
--01
--00
--00
--00
--00
Offset
Length
Description
Query-unique ASCII string “QRY“
Add.
10:
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
Value
"Q"
"R"
3
10h
"Y"
2
2
2
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
13h
15h
17h
19h
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
November 2007
Order Number: 313295-04
Datasheet
85
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 33: System Interface Information
Hex
Code
Offset
Length
Description
Add.
Value
1Bh
1
V
CC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
1B:
--17
1.7V
bits 4–7 BCD volts
1Ch
1Dh
1Eh
1
1
1
VCC logic supply maximum program/erase voltage
1C:
1D:
1E:
--20
--85
--95
2.0V
8.5V
9.5V
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical single word program time-out = 2n μ-sec
“n” such that typical max. buffer write time-out = 2n μ-sec
“n” such that typical block erase time-out = 2n m-sec
“n” such that typical full chip erase time-out = 2n m-sec
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
1F:
20:
21:
22:
23:
24:
25:
26:
--08 256μs
--09 512μs
--0A
--00
1s
NA
--01 512μs
--01 1024μs
--02
--00
4s
NA
Datasheet
86
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
B.5
Device Geometry Definition
Table 34: Device Geometry Definition
Offset
27h
Length
Description
Code
See table below
“n” such that device size = 2n in number of bytes
Flash device interface code assignment:
1
27:
28:
"n" such that n+1 specifies the bit field that represents the flash
device width capabilities as described in the table:
7
6
5
4
3
2
1
x16
9
0
x8
8
28h
2
—
15
—
—
14
—
—
13
—
—
12
—
x64
11
x32
10
--01
x16
64
—
—
—
—
29:
2A:
2B:
2C:
--00
--06
--00
“n” such that maximum number of bytes in write buffer = 2n
2
1
2Ah
2Ch
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
See table below
3. Symmetrically blocked partitions have one blocking region
Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
4
4
4
2Dh
31h
35h
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
See table below
See table below
See table below
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Reserved for future erase block region information
64 Mbit
128 Mbit
–B
256 Mbit
–B
Address
–B
–T
–T
–T
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
--17
--01
--00
--06
--00
--02
--03
--00
--80
--00
--3E
--00
--00
--02
--00
--00
--00
--00
--17
--01
--00
--06
--00
--02
--3E
--00
--00
--02
--03
--00
--80
--00
--00
--00
--00
--00
--18
--01
--00
--06
--00
--02
--03
--00
--80
--00
--7E
--00
--00
--02
--00
--00
--00
--00
--18
--01
--00
--06
--00
--02
--7E
--00
--00
--02
--03
--00
--80
--00
--00
--00
--00
--00
--19
--01
--00
--06
--00
--02
--03
--00
--80
--00
--FE
--00
--00
--02
--00
--00
--00
--00
--19
--01
--00
--06
--00
--02
--FE
--00
--00
--02
--03
--00
--80
--00
--00
--00
--00
--00
November 2007
Order Number: 313295-04
Datasheet
87
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
B.6
Intel-Specific Extended Query Table
Table 35: Primary Vendor-Specific Extended Query
Offset(1)
P= 10Ah
Hex
Length
Description
(Optional flash features and commands)
Primary extended query table
Add. Code Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
10A
--50
"P"
"R"
"I"
"1"
"3"
Unique ASCII string “PRI“
10B: --52
10C: --49
10D: --31
10E: --33
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 10–31 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of Optional features follows at
the end of the bit–30 field.
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
bit 8 Synchronous read supported
bit 9 Simultaneous operations supported
bit 10 Reserved
--E6
10F:
110: --03
111: --00
112: --00
bit 0 = 0
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 1
bit 9 = 1
bit 10 = 0
bit 30 = 0
bit 31 = 0
113: --01
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
No
bit 30 CFI Link(s) to follow
No
No
bit 31 Another "Optional Features" field to follow
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
(P+9)h
1
2
bit 0 = 1
114: --03
115: --00
bit 0 = 1
Yes
(P+A)h
(P+B)h
Yes
Yes
bit 1 = 1
(P+C)h
(P+D)h
1
1
V
CC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
116: --18
1.8V
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
117: --90
9.0V
Datasheet
88
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 36: Protection Register Information
Offset(1)
Length
Hex
Description
P= 10Ah
(P+E)h
(Optional flash features and commands)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
Add. Code Value
1
4
118: --02
2
(P+F)h
(P+10)h
(P+11)h
(P+12)h
119: --80
11A: --00
80h
00h
11B: --03 8 byte
11C: --03 8 byte
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
(P+18)h
(P+19)h
(P+1A)h
(P+1B)h
(P+1C)h
10
Protection Field 2: Protection Description
Bits 0–31 point to the Protection register physical Lock-word
address in the Jedec-plane.
Following bytes are factory or user-programmable.
bits 32–39 = “n” ∴ n = factory pgm'd groups (low byte)
bits 40–47 = “n” ∴ n = factory pgm'd groups (high byte)
bits 48–55 = “n” \ 2n = user programmable bytes/group
bits 56–63 = “n” ∴ n = user pgm'd groups (low byte)
11D: --89
11E: --00
11F: --00
120: --00
89h
00h
00h
00h
0
0
0
16
0
16
--00
--00
--00
121:
122:
123:
124: --10
--00
125:
126:
∴
bits 64–71 = “n” n = user pgm'd groups (high byte)
n
∴
bits 72–79 = “n” 2 = user programmable bytes/group
--04
November 2007
Order Number: 313295-04
Datasheet
89
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 37: Burst Read Information
Offset(1)
Length
Hex
Description
P= 10Ah
(P+1D)h
(Optional flash features and commands)
Page Mode Read capability
Add. Code Value
127: --00 0 byte
1
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
(P+1E)h
(P+1F)h
1
1
128: --04
129: --01
4
4
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
(P+20)h
(P+21)h
(P+22)h
1
1
1
12A: --02
12B: --03
12C: --07
8
16
Cont
Table 38: Partition and Erase-block Region Information
Offset(1)
P= 10Ah
See table below
Address
Description
Bot
Top
Bottom
Top
(Optional flash features and commands)
Len
(P+23)h (P+23)h Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
1
12D:
12D:
Datasheet
90
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 39: Partition Region 1 Information
Offset(1)
P= 10Ah
See table below
Address
Description
Bot
Top
12E:
12F:
130:
Bottom
(P+24)h (P+24)h
(P+25)h (P+25)h
Top
(Optional flash features and commands)
Number of identical partitions within the partition region
Len
2
12E:
12F:
130:
(P+26)h (P+26)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
1
1
bits 4–7 = number of simultaneous Erase operations
(P+27)h (P+27)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+28)h (P+28)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+29)h (P+29)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
131:
132:
133:
131:
132:
133:
1
1
(P+2A)h (P+2A)h Partition Region 1 Erase Block Type 1 Information
(P+2B)h (P+2B)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition
(P+2C)h (P+2C)h bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+2D)h (P+2D)h
4
134:
135:
136:
137:
138:
139:
13A:
134:
135:
136:
137:
138:
139:
13A:
Partition 1 (Erase Block Type 1)
Minimum block erase cycles x 1000
(P+2E)h (P+2E)h
(P+2F)h (P+2F)h
2
1
(P+30)h (P+30)h Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+31)h (P+31)h Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined in Table 10.
1
4
13B:
13B:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+32)h
(P+33)h
(P+34)h
(P+35)h
(P+36)h
(P+37)h
Partition Region 1 Erase Block Type 2 Information
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(bottom parameter device only)
13C:
13D:
13E:
13F:
140:
141:
Partition 1 (Erase block Type 2)
2
1
Minimum block erase cycles x 1000
(P+38)h
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
142:
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+39)h
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined in Table 10
1
143:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
November 2007
Order Number: 313295-04
Datasheet
91
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 40: Partition Region 2 Information
Offset(1)
See table below
P= 10Ah
Description
(Optional flash features and commands)
Address
Bot
Top
13C:
13D:
13E:
Bottom
Top
Len
2
(P+3A)h (P+32)h Number of identical partitions within the partition region
(P+3B)h (P+33)h
(P+3C)h (P+34)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
144:
145:
146:
1
1
1
1
(P+3D)h (P+35)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+3E)h (P+36)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+3F)h (P+37)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
147:
148:
149:
13F:
140:
141:
(P+40)h (P+38)h Partition Region 2 Erase Block Type 1 Information
4
14A:
14B:
14C:
14D:
14E:
14F:
150:
142:
143:
144:
145:
146:
147:
148:
(P+41)h (P+39)h
(P+42)h (P+3A)h
(P+43)h (P+3B)h
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+44)h (P+3C)h Partition 2 (Erase block Type 1)
(P+45)h (P+3D)h Minimum block erase cycles x 1000
(P+46)h (P+3E)h Partition 2 (Erase block Type 1) bits per cell
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+47)h (P+3F)h Partition 2 (erase block Type 1) pagemode and synchronous
mode capabilities as defined in Table 10.
1
4
151:
149:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+40)h Partition Region 2 Erase Block Type 2 Information
14A:
14B:
14C:
14D:
14E:
14F:
150:
(P+41)h
(P+42)h
(P+43)h
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+44)h Partition 2 (Erase block Type 2)
(P+45)h Minimum block erase cycles x 1000
(P+46)h Partition 2 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+47)h Partition 2 (erase block Type 2) pagemode and synchronous
mode capabilities as defined in Table 10.
1
151:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Datasheet
92
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 41: Partition and Erase Block Information
Address
64 Mbit
128 Mbit
256 Mbit
–B
–T
–B
–T
–B
–T
12D:
12E:
12F:
130:
131:
132:
133:
134:
135:
136:
137:
138:
139:
13A:
13B:
--02
--01
--00
--11
--00
--00
--02
--03
--00
--80
--00
--64
--00
--02
--02
--02
--07
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--02
--02
--02
--01
--00
--11
--00
--00
--02
--03
--00
--80
--00
--64
--00
--02
--02
--02
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--02
--02
--02
--01
--00
--11
--00
--00
--02
--03
--00
--80
--00
--64
--00
--02
--02
--02
--0F
--00
--11
--00
--00
--01
--0F
--00
--00
--02
--64
--00
--02
--02
13C:
13D:
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
14B:
14C:
14D:
14E:
14F:
150:
151:
--06
--00
--00
--02
--64
--00
--02
--02
--07
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--02
--02
--01
--00
--11
--00
--00
--02
--06
--00
--00
--02
--64
--00
--02
--02
--03
--00
--80
--00
--64
--00
--02
--02
--06
--00
--00
--02
--64
--00
--02
--02
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--02
--02
--01
--00
--11
--00
--00
--02
--06
--00
--00
--02
--64
--00
--02
--02
--03
--00
--80
--00
--64
--00
--02
--02
--0E
--00
--00
--02
--64
--00
--02
--02
--0F
--00
--11
--00
--00
--01
--0F
--00
--00
--02
--64
--00
--02
--02
--01
--00
--11
--00
--00
--02
--0E
--00
--00
--02
--64
--00
--02
--02
--03
--00
--80
--00
--64
--00
--02
--02
November 2007
Order Number: 313295-04
Datasheet
93
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 42: Electrical Traceability
76h 76h
Bits 0 – 2: Stepping (See Table 3 and 4)
Bit 3: Production Bit (See Table 3 and 4)
Bits 4 – 7: Memory clock rate 0000 = 40MHz 0001 = 54MHz
0010 = 66MHz 1XXX = DDR
1
76h
76h
Bits 8 – 9: Process
Bit 10: Mass memory 0 = No 1 = Yes
Bits 11 - 12: Ram Type 00 = No 01 = SRAM 10 = PSRAM 11
= DRAM
Bits 13 – 15: RAM density 000 = no SRAM 001 = 4 Mb 010 =
8 Mb 011 = 16 Mb 100 = 32 Mb…
Reserved for future use
(P+48)h (P+48)h
Resv'd 152:
152:
Table 43: CFI Revision History for Engineering Sample at Address 76h
Density
CFI Field Data
xxxxh
Revision
Comments
000 00 0 00 0001 1100
001Ch
Revision 2
A2 Silicon (128Mb A2 Silicon)
OMPU 64 Mbit - Bin
1
OMPU 64 Mbit - Bin
1
000 00 0 00 0001 1011
001Bh
Revision 3
A3 Silicon (128Mb A3 Silicon)
64 Mbit - Bin 1
64 Mbit - Bin 1
128 Mbit - Bin 1
128 Mbit - Bin 1
128 Mbit - Bin 1
128 Mbit - Bin 1
128 Mbit - Bin 2
128 Mbit - Bin 2
128 Mbit - Bin 2
128 Mbit - Bin 2
256 Mbit - Bin 1
256 Mbit - Bin 1
256 Mbit - Bin 2
256 Mbit - Bin 2
000 00 0 00 0001 1110
000 00 0 00 0001 1101
000 00 0 00 0001 1110
000 00 0 00 0001 1101
000 00 0 00 0001 1100
000 00 0 00 0001 1011
000 00 0 00 0000 1110
000 00 0 00 0000 1101
000 00 0 00 0000 1100
000 00 0 00 0000 1011
000 00 0 00 0001 1110
000 00 0 00 0001 1101
000 00 0 00 0000 1110
000 00 0 00 0000 1101
001Eh
001Dh
001Eh
001Dh
001Ch
001Bh
000Eh
000Dh
000Ch
000Bh
001Eh
001Dh
000Eh
000Dh
Revision 0
Revision 1
Revision 0
Revision 1
Revision 2
Revision 3
Revision 0
Revision 1
Revision 2
Revision 3
Revision 0
Revision 1
Revision 0
Revision 1
A0 Silicon
A1 Silicon
A0 Silicon
A1 Silicon
A2 Silicon
A3 Silicon
A0 Silicon
A1 Silicon
A2 Silicon
A3 Silicon
A0 Silicon
A1 Silicon
A0 Silicon
A1 Silicon
Datasheet
94
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 44: CFI Revision History for Production Materials at Address 76h
Density
CFI Field Data
xxxxh
Revision
Comments
Production Silicon (128Mb Prod Silicon
Rev)
000 00 0 00 0001 0001
0011h
Revision 1
OMPU 64 Mbit - Bin 1
OMPU 64 Mbit - Bin 1
64 Mbit - Bin 1
000 00 0 00 0001 0010
000 00 0 00 0001 0001
000 00 0 00 0001 0010
000 00 0 00 0001 0011
000 00 0 00 0001 0001
000 00 0 00 0001 0010
000 00 0 00 0001 0011
000 00 0 00 0000 0001
000 00 0 00 0000 0010
000 00 0 00 0000 0011
000 00 0 00 0001 0001
000 00 0 00 0001 0010
000 00 0 00 0001 0011
000 00 0 00 0000 0001
000 00 0 00 0000 0010
000 00 0 00 0000 0011
0012h
0011h
0012h
0013h
0011h
0012h
0013h
0001h
0002h
0003h
0011h
0012h
0013h
0001h
0002h
0003h
Revision 2
Revision 1
Revision 2
Revision 3
Revision 1
Revision 2
Revision 3
Revision 1
Revision 2
Revision 3
Revision 1
Revision 2
Revision 3
Revision 1
Revision 2
Revision 3
Rev 2 If Errata
Production Silicon
Rev 2 If Errata
Rev 3 If Errata
Production Silicon
Rev 2 If Errata
Rev 3 If Errata
Production Silicon
Rev 2 If Errata
Rev 3 If Errata
Production Silicon
Rev 2 If Errata
Rev 3 If Errata
Production Silicon
Rev 2 If Errata
Rev 3 If Errata
64 Mbit - Bin 1
64 Mbit - Bin 1
128 Mbit - Bin 1
128 Mbit - Bin 1
128 Mbit - Bin 1
128 Mbit - Bin 2
128 Mbit - Bin 2
128 Mbit - Bin 2
256 Mbit - Bin 1
256 Mbit - Bin 1
256 Mbit - Bin 1
256 Mbit - Bin 2
256 Mbit - Bin 2
256 Mbit - Bin 2
November 2007
Order Number: 313295-04
Datasheet
95
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Appendix C Ordering Information
To order samples, obtain datasheets or inquire about any stack combination, please
contact your local Intel representative.
Table 45: 38F Type Stacked Components
PF
38F
5070
M0
Y
0
B
0
Product Die/
Density
Configuration
Voltage/NOR
Flash CE#
Configuration
Parameter /
Mux
Configuration
Package
Designator
Product Line
Designator
NOR Flash Product
Family
Ballout
Identifier
Device
Details
Char 1 = Flash
die #1
V =
0 =
First character
applies to Flash
die #1
1.8 V Core
and I/O;
Separate Chip
Enable per die
Char 2 = Flash
die #2
No parameter
blocks; Non-
Mux I/O
B =
x16D
Ballout
interface
Char 3 =
RAM die #1
0 =
PF =
Second character
applies to Flash
die #2
Original
released
version of
this
SCSP, RoHS
(See
(See
(See
Table 49,
“Voltage /
NOR Flash
CE#
Table 51
StackedNOR
Table 50,
“Parameter
/ Mux
,
Flash + RAM Char 4 =
RD =
“Ballout
Decoder
” on
(See Table 48,
“NOR Flash
Family
RAM die #2
SCSP, Leaded
product
Configurati
on
Configurati
on
(See
page 98
for details)
Decoder” on
page 97 for
details)
Decoder”
on page 98
for details)
Table 47,
“38F / 48F
Density
Decoder”
onpage 97
for details)
Decoder”
on page 97
for details)
Table 46: 48F Type Stacked Components
PC
48F
4400
P0
V
B
0
0
Product Die/
Density
Configuration
Voltage/NOR
Flash CE#
Configuration
Parameter /
Mux
Configuration
Package
Designator
Product Line
Designator
NOR Flash Product
Family
Ballout
Identifier
Device
Details
PC =
Easy BGA,
RoHS
Char 1 = Flash
die #1
V =
B =
First character
applies to Flash
dies #1 and #2
1.8 V Core
and 3 V I/O;
Virtual Chip
Enable
Char 2 = Flash
die #2
Bottom
0 =
RC =
parameter;
Non-Mux I/O
interface
Discrete
Ballout
Easy BGA,
Leaded
0 =
Char 3 = Flash
die #3
Second character
applies to Flash
dies #3 and #4
Original
released
version of
this
(See
(See
JS =
TSOP, RoHS
(See
Stacked
NOR Flash
only
Table 49,
“Voltage /
NOR Flash
CE#
Table 51
Table 50,
“Parameter
/ Mux
Char 4 = Flash
die #4
,
“Ballout
Decoder
” on
(See Table 48,
“NOR Flash
Family
product
TE =
TSOP, Leaded
Configurati
on
Configurati
on
(See
page 98
for details)
Table 47,
“38F / 48F
Density
Decoder” on
page 97 for
details)
Decoder”
on page 98
for details)
Decoder”
on page 97
for details)
PF =
SCSP, RoHS
Decoder”on
page 97 for
details)
RD =
SCSP, Leaded
Datasheet
96
November 2007
Order Number: 313295-04
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 47: 38F / 48F Density Decoder
Code
Flash Density
RAM Density
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
No Die
No Die
32-Mbit
64-Mbit
128-Mbit
256-Mbit
512-Mbit
1-Gbit
4-Mbit
8-Mbit
16-Mbit
32-Mbit
64-Mbit
128-Mbit
256-Mbit
512-Mbit
1-Gbit
2-Gbit
4-Gbit
8-Gbit
16-Gbit
32-Gbit
64-Gbit
128-Gbit
256-Gbit
512-Gbit
2-Gbit
4-Gbit
8-Gbit
16-Gbit
32-Gbit
64-Gbit
Table 48: NOR Flash Family Decoder
Code
Family
Marketing Name
C
C3
Intel Advanced+ Boot Block Flash Memory
Intel Embedded Flash Memory
Intel StrataFlash® Wireless Memory
Intel StrataFlash® Cellular Memory
Intel StrataFalsh® Embedded Memory
Intel Wireless Flash Memory
J3v.D
J
L
L18 / L30
M18
M
P
P30 / P33
W18 / W30
-
W
0(zero)
No Die
Table 49: Voltage / NOR Flash CE# Configuration Decoder (Sheet 1 of 2)
I/O Voltage
Code
Core Voltage (Volt)
CE# Configuration
Seperate Chip Enable per die
(Volt)
Z
3.0
1.8
3.0
3.0
1.8
3.0
1.8
1.8
3.0
1.8
1.8
3.0
Seperate Chip Enable per die
Seperate Chip Enable per die
Virtual Chip Enable
Y
X
V
U
T
Virtual Chip Enable
Virtual Chip Enable
November 2007
Order Number: 313295-04
Datasheet
97
Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux)
Table 49: Voltage / NOR Flash CE# Configuration Decoder (Sheet 2 of 2)
I/O Voltage
(Volt)
Code
Core Voltage (Volt)
CE# Configuration
R
Q
P
3.0
1.8
1.8
3.0
Virtual Address
Virtual Address
Virtual Address
1.8
3.0
Table 50: Parameter / Mux Configuration Decoder
Code, Mux
Identification
Number of Flash Die
Bus Width
Flash Die 1
Flash Die 2
Flash Die 3
Flash Die 4
0 = Non Mux
1 = AD Mux1
2= AAD Mux
Any
NA
Notation used for stacks that contain no parameter blocks
3 =Full" AD
Mux2
1
2
3
4
2
4
1
2
3
4
2
4
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Top
-
-
-
Top
-
-
B = Non Mux
C = AD Mux
F = "Full" Ad
Mux
X16
X32
X16
X32
Bottom
Top
Top
-
Bottom
Top
Bottom
Bottom
-
-
-
Top
Top
-
-
Top
Bottom
Top
-
-
T = Non Mux
U = AD Mux
W = "Full" Ad
Mux
Top
Bottom
Top
-
Top
Bottom
Top
Bottom
-
Top
-
Top
Top
Bottom
Bottom
1. Only Flash is Muxed and RAM is non-Muxed
2. Both Flash and RAM are AD-Muxed
Table 51: Ballout Decoder
Code
Ballout Definition
0 (Zero)
SDiscrete ballout (Easay BGA and TSOP)
B
x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus)
x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus)
QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus)
x32SH ballout, 106 ball (x32 NOR only Share Bus)
C
Q
U
V
x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus
x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus
W
Datasheet
98
November 2007
Order Number: 313295-04
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