SMC512AFY6 [NUMONYX]
32 Mbyte, 64 Mbyte, 128 Mbyte, 256 Mbyte and 512 Mbyte 3.3 V / 5 V supply CompactFlash⑩ card; 32兆字节， 64M字节，兆字节128 ， 256兆字节到512兆字节3.3 V / 5 V电源CompactFlash⑩卡
| 型号： | SMC512AFY6 |
| 厂家： | 
NUMONYX B.V |
| 描述： | 32 Mbyte, 64 Mbyte, 128 Mbyte, 256 Mbyte and 512 Mbyte 3.3 V / 5 V supply CompactFlash⑩ card |
| 文件： | 总82页 (文件大小：1651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMCxxxAF
32 Mbyte, 64 Mbyte, 128 Mbyte, 256 Mbyte and
512 Mbyte 3.3 V / 5 V supply CompactFlash™ card
Features
■ Custom-designed, highly-integrated memory
controller
TM
– Fully compliant with CompactFlash
specification 2.0
– Fully compatible with PCMCIA specification
– PC card ATA interface supported
– True IDE mode compatible
■ Small form factor
– 36.4 mm x 42.8 mm x 3.3 mm
CompactFlashTM
■ Low-power CMOS technology
■ 3.3 V / 5.0 V power supply
■ Power saving mode (with automatic wake-up)
■ High performance
■ High reliability
– Up to 16.6 Mbit/s transfer rate
– MTBF > 3,000,000 hours
– Sustained write performance
(host to card: 7.2 Mbit/s)
– Data reliability: < 1 non-recoverable error
14
per 10 bits read
■ Operating system support
– Endurance: > 2,000,000 Erase/Program
cycles
– Standard software drivers operation
■ Available densities (formatted)
– Number of card insertions/removals: >
10,000
– 32 Mbytes to 512 Mbytes
■ Hot swappable
Table 1.
Device summary
Part number
Reference
Package form factor
Operating voltage range
SMC032AF
SMC064AF(1)
SMC128AF(1)
SMC256AF(1)
SMC512AF(1)
SMCxxxAF
CF type I
3.3 V+-10%, 5 V+-10%
1. Obsolete part number.
January 2008
Rev 3
1/82
www.numonyx.com
1
Contents
SMCxxxAF
Contents
1
2
3
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Capacity specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Card physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
4.2
4.3
Electrical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
6
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Card configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1
Configuration Option register (base + 00h in attribute memory) . . . . . . . 31
6.1.1
6.1.2
LevlREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Conf5 - Conf0 (configuration index) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2
Card Configuration and Status register (base + 02h in attribute memory) 32
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SigChg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IOis8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PwrDwn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3
Pin Replacement register (base + 04h in attribute memory) . . . . . . . . . . 33
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
CReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CWProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
WProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
MReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
MWProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4
6.5
Socket and Copy register (base + 06h in attribute memory) . . . . . . . . . . 34
6.4.1
6.4.2
Drive # . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Attribute memory function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2/82
SMCxxxAF
Contents
6.6
6.7
6.8
I/O transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Common memory transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
True IDE mode I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
Software interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1
7.2
7.3
7.4
7.5
CF-ATA Drive register set definition and protocol . . . . . . . . . . . . . . . . . . . 39
Memory mapped addressing (conf = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Contiguous I/O mapped addressing (conf = 1) . . . . . . . . . . . . . . . . . . . . 41
I/O primary and secondary address configurations (conf = 2,3) . . . . . . . 42
True IDE mode addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8
CF-ATA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1
8.2
Data register (address 1F0h [170h]; offset 0, 8, 9) . . . . . . . . . . . . . . . . . . 44
Error register (address 1F1h [171h]; offset 1, 0Dh read only) . . . . . . . . . 44
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
Bit 7 (BBK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Bit 6 (UNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Bit 4 (IDNF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Bit 2 (abort) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Bit 0 (AMNF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.3
8.4
8.5
8.6
8.7
8.8
Feature register (address 1F1h [171h]; offset 1, 0Dh write only) . . . . . . . 45
Sector Count register (address 1F2h [172h]; offset 2) . . . . . . . . . . . . . . . 45
Sector Number (LBA 7-0) register (address 1F3h [173h]; offset 3) . . . . . 45
Cylinder Low (LBA 15-8) register (address 1F4h [174h]; offset 4) . . . . . . 46
Cylinder High (LBA 23-16) register (address 1F5h [175h]; offset 5) . . . . 46
Drive/Head (LBA 27-24) register (address 1F6h [176h]; offset 6) . . . . . . 46
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.8.7
Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bit 6 (LBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bit 4 (DRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bit 3 (HS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bit 2 (HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Bit 1 (HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3/82
Contents
SMCxxxAF
8.8.8
Bit 0 (HS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.9
Status & alternate status registers (address 1F7h [177h] & 3F6h [376h];
offsets 7 & Eh) 48
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
Bit 7 (BUSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Bit 6 (RDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Bit 5 (DWF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Bit 4 (DSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Bit 3 (DRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Bit 2 (CORR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Bit 1 (IDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Bit 0 (ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.10 Device control register (address 3F6h [376h]; offset Eh) . . . . . . . . . . . . . 49
8.10.1 Bit 7 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.10.2 Bit 2 (SW Rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.10.3 Bit 1 (–IEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.10.4 Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.11 Card (drive) address register (address 3f7h [377h]; offset Fh) . . . . . . . . 50
8.11.1 Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.2 Bit 6 (–WTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.3 Bit 5 (–HS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.4 Bit 4 (–HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.5 Bit 3 (–HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.6 Bit 2 (–HS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.7 Bit 1 (–nDS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.8 Bit 0 (–nDS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9
CF-ATA command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1
9.2
9.3
9.4
Check Power mode command (98h or E5h) . . . . . . . . . . . . . . . . . . . . . . 52
Execute Drive Diagnostic command (90h) . . . . . . . . . . . . . . . . . . . . . . . . 53
Erase Sector(s) command (C0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Identify Drive command (ECh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
Word 0: general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Word 1: default number of cylinders . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Word 3: default number of heads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Word 6: default number of sectors per track . . . . . . . . . . . . . . . . . . . . . 54
Word 7-8: number of sectors per card . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Word 10-19: memory card serial number . . . . . . . . . . . . . . . . . . . . . . . 55
4/82
SMCxxxAF
Contents
9.4.7
9.4.8
9.4.9
Word 23-26: firmware revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Word 27-46: model number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Word 47: read/write multiple sector count . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.10 Word 49: capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.11 Word 51: PIO data transfer cycle timing mode . . . . . . . . . . . . . . . . . . . 55
9.4.12 Word 53: translation parameter valid . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.13 Word 54-56: current number of cylinders, heads, sectors/track . . . . . . . 55
9.4.14 Word 57-58: current capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.15 Word 59: multiple sector setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.4.16 Word 60-61: total sectors addressable in LBA mode . . . . . . . . . . . . . . . 56
9.4.17 Word 64: advanced PIO transfer modes supported . . . . . . . . . . . . . . . . 56
9.4.18 Word 67: minimum PIO transfer cycle time without flow control . . . . . . 56
9.4.19 Word 68: minimum PIO transfer cycle time with IORDY . . . . . . . . . . . . 56
9.5
9.6
9.7
9.8
9.9
Idle command (97h or E3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Idle Immediate command (95h or E1h) . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Initialize Drive Parameters command (91h) . . . . . . . . . . . . . . . . . . . . . . . 59
NOP command (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Read Buffer command (E4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.10 Read Multiple command (C4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.11 Read Sector(s) command (20h or 21h) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.12 Read Verify Sector(s) command (40h or 41h) . . . . . . . . . . . . . . . . . . . . . 62
9.13 Recalibrate command (1Xh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.14 Request Sense command (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.15 Seek command (7Xh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.16 Set Features command (EFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.17 Set Multiple mode command (C6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.18 Set Sleep mode command (99h or E6h) . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.19 Standby command (96h or E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.20 Standby Immediate command (94h or E0h) . . . . . . . . . . . . . . . . . . . . . . . 68
9.21 Translate Sector command (87h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.22 Wear Level command (F5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.23 Write Buffer command (E8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.24 Write Multiple command (C5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.25 Write Multiple without Erase command (CDh) . . . . . . . . . . . . . . . . . . . . . 72
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Contents
SMCxxxAF
9.26 Write Sector(s) command (30h or 31h) . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.27 Write Sector(s) without Erase command (38h) . . . . . . . . . . . . . . . . . . . . 73
9.28 Write Verify command (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10
11
12
13
CIS information (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6/82
SMCxxxAF
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Environmental specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CF capacity specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System reliability and maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin assignment and pin type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output drive type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output drive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Attribute memory Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configuration register (attribute memory) Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Common memory Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Common memory Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I/O Read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I/O Write timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
True IDE mode I/O Read/Write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CompactFlash memory card registers and memory space decoding. . . . . . . . . . . . . . . . . 30
CompactFlash memory card configuration registers decoding. . . . . . . . . . . . . . . . . . . . . . 31
Configuration Option register (default value: 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CompactFlash memory card configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Card Configuration and Status register (default value: 00h). . . . . . . . . . . . . . . . . . . . . . . . 32
Pin Replacement register (default value: 0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin Replacement Changed bit/Mask bit values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Socket and Copy register (default value: 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Attribute memory function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Common memory function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
True IDE mode I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Memory mapped decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Contiguous I/O decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Primary and secondary I/O decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
True IDE mode I/O decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data register access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Error register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Drive/Head register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Status & alternate status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Device control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Card (drive) address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CF-ATA command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Check Power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Execute Drive Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
7/82
List of tables
SMCxxxAF
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Diagnostic codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Erase Sector(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Identify drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Identify drive information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Idle Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Initialize Drive Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Read Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Read Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Read Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Read Verify Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Recalibrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Request Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Extended Error codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Set Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Features supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Transfer mode values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Set Multiple mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Set Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Standby Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Translate Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Translate Sector information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Wear Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Write Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Write Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Write Multiple without Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Write Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Write Sector(s) without Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Write Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8/82
SMCxxxAF
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
CompactFlash memory card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Attribute memory Read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configuration register (attribute memory) Write timing diagram . . . . . . . . . . . . . . . . . . . . . 23
Common memory Read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Common memory Write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I/O Read timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I/O Write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
True IDE mode I/O timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Type I CompactFlash memory card dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9/82
Description
SMCxxxAF
1
Description
The CompactFlash is a small form factor non-volatile memory card which provides high
capacity data storage. Its aim is to capture, retain and transport data, audio and images,
facilitating the transfer of all types of digital information between a large variety of digital
systems.
The card operates in three basic modes,
■
■
■
PCMCIA I/O mode
PCMCIA memory mode
True IDE mode
It conforms to the PC card specification when operating in the PCMCIA I/O mode and
PCMCIA memory mode (Personal Computer Memory Card International Association
standard, JEIDA in Japan) and to the ATA specification when operating in True IDE mode.
CompactFlash cards can be used with passive adapters in a PC-card type II or type III
socket.
The card has an internal intelligent controller which manages interface protocols, data
storage and retrieval as well as error correcting code (ECC), defect handling, diagnostics
and clock control. Once the card has been configured by the host, it behaves as a standard
ATA (IDE) disk drive.
The card has a super cap on V and a powerful power-loss management feature to
CC
prevent data corruption after power-down.
The specification has been realized and approved by the CompactFlash association (CFA).
This non-proprietary specification enables users to develop CF products that function
correctly and are compatible with future CF design.
The system highlights are shown in Table 2, Table 3, Table 4, Table 5, Table 6 and Table 7.
Related documentation
■
■
■
PCMCIA PC card standard, 1995
PCMCIA PC card ATA specification, 1995
AT attachment interface document, American National Standards Institute, X3.221-
1994
■
CF+ and CompactFlash specification revision 2.0.
10/82
SMCxxxAF
Description
Unit
Table 2.
System performance
System performance
Max
Sleep to write
Sleep to read
2.2
2.4
ms
ms
Power-up to ready
Data transfer rate (burst)
Sustained Read
80
ms
16.6 (113X)(1)
12.2 (83X)(1)
7.2 (49X)(1)
180
Mbit/s
Mbit/s
Mbit/s
Sustained Write
Read
Write
Command to DRQ
µs
40
1. 113X, 83X and 49X, speed grade markings where 1X = 150 Kbytes/s. All values refer to the 256-Mbyte
CompactFlash card in PIO mode 4, cycle time 120 ns.
(1)
Table 3.
Current consumption
Current consumption (typ)
3.3 V
5 V
Unit
Read
57
70
60
71
1
mA
mA
mA
mA
Write
Standby
0.4
0.4
Sleep mode
1
1. All values are typical at 25 °C and nominal supply voltage and refer to 256-Mbyte CompactFlash card.
Table 4.
Environmental specifications
Temperature
Environmental specifications
Operating
–40 to 85 °C
Non-operating
–50 to 100 °C
Humidity (non-condensing)
Salt water spray
N/A
N/A
N/A
N/A
85% RH, at 85 °C
3% NaCl at 35 °C(1)
30 Gmax
Vibration (peak -to-peak)
Shock
3,000 Gmax
1. MIL STD METHOD 1009.
Table 5.
Physical dimensions
Physical dimensions
Unit
Width
42.8
36.4
3.3
mm
mm
mm
g
Height
Thickness
Weight (typ)
10
11/82
Capacity specification
SMCxxxAF
2
Capacity specification
Table 6 shows the specific capacity for the various CF models and the default number of
heads, sector/tracks and cylinders.
Table 6.
CF capacity specification
Total
addressable
capacity
(byte)
Default_sectors_
track
Model No Capacity Default_cylinders Default_heads
Sectors_card
SMC032
SMC064
SMC128
SMC256
SMC512
32 Mbyte
64 Mbyte
128 Mbyte
256 Mbyte
512 Mbyte
492 (0x1EC)
496 (0x1F0)
498 (0x1F2)
998 (0x3E6)
1014 (0x3F6)
8 (0x08)
8 (0x08)
16 (0x10)
32 (0x20)
32 (0x20)
32 (0x20)
63 (0x3F)
62976
126976
254976
510976
1022112
32243712
65011712
130547712
261619712
523321344
16 (0x10)
16 (0x10)
16 (0x10)
Table 7.
System reliability and maintenance
MTBF (at 25 °C)
> 3,000,000 hours
Insertions/removals
Preventive maintenance
Data reliability
> 10,000
None
< 1 non-recoverable error per 1014 bits Read
0 + 70 C > 2,000,000 Erase/Program cycles(1)
-40 + 85 C > 600,000 Erase/Program cycles(1)
Endurance
1. Dependent on final system qualification data.
12/82
SMCxxxAF
Card physical description
3
Card physical description
The CompactFlash memory card contains a single chip controller and Flash memory
module(s). The controller interfaces with a host system allowing data to be written to and
read from the Flash memory module(s). Figure 1 shows the block diagram of the
CompactFlash memory card.
The card is offered in a type I package with a 50-pin connector consisting of two rows of 25
female contacts on 50 mil (1.27 mm) centers. Figure 9 shows type I card dimensions.
Figure 1.
CompactFlash memory card block diagram
Data
In/Out
Host
interface
Flash
module(s)
Controller
Control
CompactFlash storage card
AI04300
13/82
Electrical interface
SMCxxxAF
4
Electrical interface
4.1
Electrical description
The CompactFlash memory card operates in three basic modes:
■
■
■
PC card ATA using I/O mode,
PC card ATA using memory mode,
True IDE mode, which is compatible with most disk drives.
The signal/pin assignments are listed in Table 8 where Low active signals have a ‘–’ prefix.
Pin types are Input, Output or Input/Output.
The configuration of the card is controlled using the standard PCMCIA Configuration
registers starting at address 200h in the attribute memory space of the memory card. For
True IDE mode, pin 9 is grounded.
Table 9 describes the I/O signals. Inputs are signals sourced from the host while outputs are
signals sourced from the card. The signals are described for each of the three operating
modes.
All outputs from the card are totem pole except the data bus signals that are bi-directional
tri-state. Refer to Section 4.2: Electrical specification for definitions of Input and Output type.
Table 8.
Pin assignment and pin type
PC card memory mode
PC card I/O mode
True IDE mode
Pin
Signal
name
Pin
In, Out
type
Signal
Pin
In, Out
Signal
name
Pin
In, Out
type
num
type
name
type
type
type
1
2
GND
D03
D04
D05
D06
D07
–CE1
A10
–OE
A09
A08
A07
VCC
A06
A05
A04
A03
A02
A01
Ground
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I3U
GND
D03
D04
D05
D06
D07
–CE1
A10
–OE
A09
A08
A07
VCC
A06
A05
A04
A03
A02
A01
Ground
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I3U
GND
D03
Ground
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I3Z
I/O
I/O
I/O
3
I/O
I/O
D04
I/O
4
I/O
I/O
D05
I/O
5
I/O
I/O
D06
I/O
6
I/O
I/O
D07
I/O
7
I
I
I
I
I
I
I
I
I
I
I
I
–CS0
A10(1)
–ATASEL
A09(1)
A08(1)
A07(1)
VCC
A06(1)
A05(1)
A04(1)
A03(1)
A02
I
I
I
I
I
I
8
I1Z
I1Z
I1Z
9
I3U
I3U
I3U
10
11
12
13
14
15
16
17
18
19
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
Power
I1Z
Power
I1Z
Power
I1Z
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
A01
I1Z
14/82
SMCxxxAF
Electrical interface
Table 8.
Pin
Pin assignment and pin type (continued)
PC card memory mode PC card I/O mode
True IDE mode
Signal
Pin
In, Out
type
Signal
name
Pin
In, Out
type
Signal
name
Pin
In, Out
type
num
name
type
type
type
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A00
D00
I
I1Z
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
OT3
A00
D00
I
I1Z
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
OT3
A00
D00
I
I1Z
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
ON3
I/O
I/O
I/O
O
I/O
I/O
I/O
O
I/O
I/O
I/O
O
D01
D01
D01
D02
D02
D02
WP
–IOIS16
–CD2
–CD1
D11(2)
D12(2)
D13(2)
D14(2)
D15(2)
–CE2(2)
–VS1
–IOIS16
–CD2
–CD1
D11(2)
D12(2)
D13(2)
D14(2)
D15(2)
–CS1(2)
–VS1
–CD2
–CD1
D11(2)
D12(2)
D13(2)
D14(2)
D15(2)
–CE2(2)
–VS1
O
Ground
Ground
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I3U
O
Ground
Ground
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I3U
O
Ground
Ground
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
I3Z
O
O
O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
O
Ground
I3U
O
Ground
I3U
O
Ground
I3Z
–IORD
–IOWR
–WE
I
–IORD
–IOWR
–WE
I
–IORD
–IOWR
–WE(3)
INTRQ
VCC
I
I
I3U
I
I3U
I
I3Z
I
I3U
I
I3U
I
I3U
READY
VCC
–CSEL(2)(4)
O
OT1
IREQ
O
OT1
O
OZ1
Power
I2Z
VCC
Power
I2Z
Power
I2U
I
–CSEL
–VS2
I
O
I
–CSEL
–VS2
I
–VS2
O
OPEN
I2Z
OPEN
I2Z
O
OPEN
I2Z
RESET
–WAIT
–INPACK
–REG
BVD2
BVD1
D08(2)
D09(2)
D10(2)
GND
I
RESET
–WAIT
–INPACK
–REG
–SPKR
-RESET
IORDY
RFU
I
O
OT1
O
O
I
OT1
O
ON1
O
OT1
OT1
O
OZ1
I
I3U
I3U
RFU(5)
–DASP
–PDIAG
D08(2)
D09(2)
D10(2)
GND
I
I3U
I/O
I/O
I/O
I/O
I/O
I1U,OT1
I/O
I1U,OT1
I1U,OT1
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
Ground
I/O
I/O
I/O
I/O
I/O
I1U,ON1
I1U,ON1
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
Ground
I1U,OT1 –STSCHG I/O
I1Z,OZ3
I1Z,OZ3
I1Z,OZ3
Ground
D08(2)
D09(2)
D10(2)
GND
I/O
I/O
I/O
1. The signal should be grounded by the host.
2. These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow
for 3-state signals not to consume current.
3. The signal should be tied to VCC by the host.
4. The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled up on the card in these
modes it should not be left floating by the host in PC Card modes. In these modes, the pin is normally connected by the
host to PC Card A25 or grounded by the host.
5. The signal should be held High or tied to VCC by the host and RFU is Reserved for Future Use.
15/82
Electrical interface
SMCxxxAF
Table 9.
Signal description
Direction
Signal name
Pin
Description
Used (with –REG) to select: the I/O Port Address
registers, the memory mapped Port Address registers, a
byte in the card's information structure and its
Configuration Control and Status registers.
A10 to A0
(PC card memory mode)
8,10,11,12,
14,15,16,17,
18,19,20
I
A10 to A0
Same as PC card memory mode.
(PC card I/O mode)
A2 to A0
Only A2 to A0 are used to select the one of eight registers
in the task file, the remaining lines should be grounded.
(True IDE mode)
BVD1
The battery voltage status of the card, as no battery is
required it is asserted High.
(PC card memory mode)
Alerts the host to changes in the READY and Write
Protect states. Its use is controlled by the Card
Configuration and Status register.
–STSCHG
I/O
I/O
46
45
(PC card I/O mode)
–PDIAG
The Pass Diagnostic signal in the master/slave handshake
protocol.
(True IDE mode)
BVD2
The battery voltage status of the card, as no battery is
required it is asserted High.
(PC card memory mode)
–SPKR
The binary audio output from the card. It is asserted High
as audio functions are not supported.
(PC card I/O mode)
–DASP
This input/output is the disk active/slave present signal in
the master/slave handshake protocol.
(True IDE mode)
Carry the data, commands and status information
between the host and the controller. D00 is the LSB of the
even byte of the word. D08 is the LSB of the odd byte of
the word.
D15-D00
(PC card memory mode)
31,30,29,28,
27,49,48,47,
6,5,4,3,2,
I/O
D15-D00
Same as PC card memory mode.
(PC card I/O mode)
23,22,21
D15-D00
All task file operations occur in byte mode on D00 to D07
while all data transfers are 16 bit using D00 to D15.
(True IDE mode)
GND
Ground.
(PC card memory mode)
GND
1,50
Same for all modes.
(PC card I/O mode)
GND
Same for all modes.
(True IDE mode)
–INPACK
Not used, should not be connected to the host.
(PC card memory mode)
The Input Acknowledge is asserted when the Card is
selected and responding to an I/O read cycle at the
current address on the bus. It is used by the host to control
the enable of any input data buffers between the Card and
CPU.
–INPACK
O
43
(PC card I/O mode)
Reserved
Not used, should not be connected to the host.
(True IDE mode)
16/82
SMCxxxAF
Table 9.
Electrical interface
Signal description (continued)
Direction Pin
Signal name
Description
–IORD
Not used.
(PC card memory mode)
–IORD
I/O Read strobe generated by the host. It gates I/O data
onto the bus.
I
34
(PC card I/O mode)
–IORD
Same as PC card I/O mode.
(True IDE mode)
These are connected to ground on the card. They are
used by the host to determine that the card is fully inserted
into its socket.
–CD1, –CD2
(PC card memory mode)
–CD1, –CD2
O
26,25
Same for all modes.
Same for all modes.
(PC card I/O mode)
–CD1, –CD2
(True IDE mode)
Used to select the card and to indicate whether a byte or a
word operation is being performed. –CE2 accesses the
odd byte, –CE1 accesses the even byte or the odd byte
depending on A0 and –CE2. A multiplexing scheme based
on A0, –CE1, –CE2 allows 8 bit hosts to access all data on
D0 to D7.
–CE1, –CE2
(PC card memory mode)
I
7,32
–CE1, –CE2
Same as PC card memory mode.
(PC card I/O mode)
CS0 is the chip select for the task file registers, while CS1
selects the Alternate Status register and the Device
Control register.
–CS0, –CS1
(True IDE mode)
–CSEL
Not used.
Not used.
(PC card memory mode)
–CSEL
I
39
(PC card I/O mode)
This internally pulled up signal is used to configure the
card as a master or slave. When grounded it is configured
as a master, when open it is configured as a slave.
–CSEL
(True IDE mode)
–IOWR
Not used.
(PC card memory mode)
The I/O Write strobe pulse is used to clock I/O data on the
bus into the Card Controller registers. Clocking occurs on
the rising edge.
–IOWR
I
35
(PC card I/O mode)
–IOWR
Same as PC card I/O mode.
(True IDE mode)
This is an Output Enable strobe generated by the host
interface. It reads data and the CIS and Configuration
registers.
–OE
(PC card memory mode)
–OE
I
9
Reads the CIS and Configuration registers.
Grounded by the host.
(PC card I/O mode)
–ATASEL
(True IDE mode)
17/82
Electrical interface
SMCxxxAF
Table 9.
Signal description (continued)
Signal name
Direction
Pin
Description
Indicates whether the card is busy (Low), or ready to
accept a new data transfer operation (High). The Host
socket must provide a pull-up resistor. At power-up and
reset, the READY signal is held Low until the commands
are completed. No access should be made during this
time. The READY signal is held High whenever the card
has been powered up with RESET continuously
disconnected or asserted.
READY
(PC card memory mode)
O
37
–IREQ
Interrupt request. It is strobed Low to generate a pulse
mode interrupt or held Low for a level mode interrupt.
(PC card I/O mode)
INTRQ
Active High Interrupt request to the host.
(True IDE mode)
Used to distinguish between common memory and
register (attribute) memory accesses. High for common
memory, Low for attribute memory.
–REG
(PC card memory mode)
I
44
–REG
Must be Low during I/O cycles when the I/O address is on
the bus.
(PC card I/O mode)
Reserved
Not used, should be connected to VCC by the host.
(True IDE mode)
RESET
Resets the card (active High). The card is reset at power-
up only if this pin is left High or unconnected.
(PC card memory mode)
RESET
I
41
Same as PC card memory mode.
Hardware Reset from the host (active Low).
+5 V, +3.3 V power.
(PC card I/O mode)
–RESET
(True IDE mode)
VCC
(PC card memory mode)
VCC
13,38
Same for all modes.
(PC card I/O mode)
VCC
Same for all modes.
(True IDE mode)
Voltage sense signals.–VS1 is grounded so that the CIS
can be read at 3.3 volts and –VS2 is reserved by PCMCIA
for a secondary voltage.
–VS1, –VS2
(PC card memory mode)
–VS1, –VS2
O
O
33,40
Same for all modes.
Same for all modes.
(PC card I/O mode)
–VS1, –VS2
(True IDE mode)
–WAIT
(PC card memory mode)
–WAIT
42
ST CF does not assert the WAIT (IORDY) signal.
(PC card I/O mode)
IORDY
(True IDE mode)
18/82
SMCxxxAF
Table 9.
Electrical interface
Signal description (continued)
Direction Pin
Signal name
Description
–WE
Driven by the host to strobe memory write data to the
registers.
(PC card memory mode)
–WE
I
36
24
Used for writing to the configuration registers.
(PC card I/O mode)
–WE
Not used, should be connected to VCC by the host.
(True IDE mode)
WP
No write protect switch available. It is held Low after the
completion of the reset initialization sequence.
(PC card memory mode)
Used for the 16 bit port (–IOIS16) function. Low indicates
that a 16 bit or odd byte only operation can be performed
at the addressed port.
–IOIS16
O
(PC card I/O mode)
–IOCS16
Asserted Low when the card is expecting a word data
transfer cycle.
(True IDE mode)
19/82
Electrical interface
SMCxxxAF
4.2
Electrical specification
Table 10 defines the DC characteristics for the CompactFlash memory card. Unless
otherwise stated, conditions are:
■
■
■
V
V
= 5 V ± 10%
CC
CC
= 3.3 V ± 10%
-40 °C to 85 °C
Table 11 shows that the card operates correctly in both the voltage ranges and that the
current requirements must not exceed the maximum limit shown.
Table 10. Absolute maximum conditions
Parameter
Symbol
VCC
Conditions
–0.3 V to 6.5 V
Input power
Voltage on any pin except VCC with respect to GND
V
–0.5 V to VCC + 0.5 V
Table 11. Input power
Voltage
3.3 V ± 10%
Maximum average RMS current
Measurement conditions
79 mA
82 mA
-40 + 85 °C
-40 + 85 °C
5 V ± 10%
4.3
Current measurement
The current is measured by connecting an amp meter in series with the V supply. The
CC
meter should be set to the 2 A scale range, and have a fast current probe with an RC filter
with a time constant of 0.1 ms. Current measurements are taken while looping on a data
transfer command with a sector count of 128. Current consumption values for both read and
write commands are not to exceed the maximum average RMS current specified in
Table 11. Table 12 shows the Input leakage current, Table 13 the Input characteristics,
Table 14 the Output drive type and Table 15 the Output drive characteristics.
(1)
Table 12. Input leakage current
Type
Parameter
Symbol
Conditions
IH = VCC
Min
Typ
Max
Units
V
IxZ
Input leakage current
IL
–1
1
µA
VIL = GND
VCC = 5.0 V
VCC = 5.0 V
IxU
IxD
Pull up resistor
RPU1
RPD1
50
50
500
500
kW
kW
Pull down resistor
1. x refers to the characteristics described in Table 13. For example, I1U indicates a pull up resistor with a type 1 input
characteristic.
20/82
SMCxxxAF
Electrical interface
Table 13. Input characteristics
Min
Typ
Max
Min
Typ
Max
Type
Parameter
Symbol
Units
VCC = 3.3 V
VCC = 5.0 V
VIH
VIL
2.4
1.5
2.4
2.0
Input voltage
CMOS
1
2
3
V
V
V
0.6
0.6
0.8
0.8
VIH
VIL
Input voltage
CMOS
VTH
VTL
1.8
1.0
2.8
2.0
Input voltage CMOS
Schmitt Trigger
(1)
Table 14. Output drive type
Type
Output type
Valid conditions
OH & IOL
OTx
OZx
OPx
ONx
Totem pole
I
Tri-state N-P channel
P-channel only
IOH & IOL
IOH only
IOL only
N-channel only
1. x refers to the characteristics described in Table 15. For example, OT3 refers to totem pole output with a type 3 output
drive characteristic.
Table 15. Output drive characteristics
Type
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VOH
VOL
VOH
VOL
VOH
VOL
IOZ
IOH = –4 mA
IOL = 4 mA
IOH = –8 mA
IOL = 8 mA
IOH = –8 mA
IOL = 8 mA
VOL = Gnd
VOH = VCC
VCC – 0.8 V
1
Output voltage
V
Gnd + 0.4 V
Gnd + 0.4 V
VCC – 0.8 V
VCC – 0.8 V
2
3
X
Output voltage
Output voltage
V
V
Gnd + 0.4 V
10
Tri-state
–10
µA
leakage current
21/82
Command interface
SMCxxxAF
5
Command interface
There are two types of bus cycles and timing sequences that occur in the PCMCIA type
interface, direct mapped I/O transfer and memory access. Table 16, Table 17, Table 18,
Table 19, Table 20, Table 21 and Table 22 show the read and write timing parameters.
Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8 show the read and
write timing diagrams.
Note, the wait width time is intentionally less than the PCMCIA specification of 12 µs. Its
maximum value can be determined from the card information structure.
Figure 2.
Attribute memory Read timing diagram
tc(R)
Address Inputs
VALID
ta(A)
tv(A)
–REG
tsu(A)
ta(CE)
–CE2/–CE1
tdis(CE)
tdis(OE)
ta(OE)
ten(CE)
–OE
ten(OE)
D0 to D15 (DOUT
)
VALID
AI10080
1. DOUT signifies data provided by the CompactFlash memory card to the system. The -CE signal or both the -OE signal and
the -WE signal must be de-asserted between consecutive cycle operations.
Table 16. Attribute memory Read timing
Speed version
300 ns
Max
Symbol
tc(R)
IEEE symbol
tAVAV
Parameter
Read Cycle time
Min
Unit
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tELQNZ
tGLQNZ
tAXQX
tAVGL
Address Access time
300
300
150
100
100
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tv(A)
CE Access time
OE Access time
Output Disable time from CE
Output Disable time from OE
Output Enable time from CE
Output Enable time from OE
Data Valid from Address Change
Address Setup time
5
5
0
tsu(A)
30
22/82
SMCxxxAF
Figure 3.
Command interface
Configuration register (attribute memory) Write timing diagram
tc(W)
–REG
Address Inputs
VALID
tsu(A)
tw(WE)
trec(WE)
th(D)
–WE
tsu(D-WEH)
–CE2/–CE1
–OE
D0 to D15 (DIN
)
DATA IN VALID
AI10081
1. DIN signifies data provided by the system to the CompactFlash card.
Table 17. Configuration register (attribute memory) Write timing
Speed version
250 ns
Symbol
tc(W)
IEEE symbol
tAVAV
Parameter
Min
Max
Unit
Write Cycle time
Write Pulse width
250
150
30
ns
ns
ns
ns
ns
ns
tw(WE)
tsu(A)
tWLWH
tAVWL
tDVWH
tWMDX
tWMAX
Address Setup time
Data Setup time from WE
Data Hold time
tsu(D-WEH)
th(D)
80
30
trec(WE)
Write Recovery time
30
23/82
Command interface
SMCxxxAF
Figure 4.
Common memory Read timing diagram
Address Inputs
VALID
tsu(A)
th(A)
–REG
–CE2/–CE1
–OE
th(CE)
tsu(CE)
ta(OE)
tdis(OE)
tv(WT)
D0 to D15 (DOUT
)
VALID
AI10083b
1. DOUT means data provided by the CompactFlash memory card to the system.
(1)
Table 18. Common memory Read timing
Cycle time mode
250 ns
Symbol
ta(OE)
IEEE symbol
Parameter
Min
Max
Unit
tGLQV
Output Enable Access time
Output Disable time from OE
Address Setup time
Address Hold time
125
100
ns
ns
ns
ns
ns
ns
tdis(OE)
tsu(A)
tGHQZ
tAVGL
30
20
0
th(A)
tGHAX
tELGL
tGHEH
tsu(CE)
th(CE)
CE Setup time
CE Hold time
20
1. ST CF does not assert the WAIT signal.
24/82
SMCxxxAF
Figure 5.
Command interface
Common memory Write timing diagram
Address Inputs
VALID
tsu(A)
th(A)
–REG
tsu(CE)
trec(WE)
th(CE)
–CE2/–CE1
–WE
tw(WE)
tsu(D-WEH)
th(D)
D0 to D15 (DIN
)
DATA IN VALID
AI10082b
1. DIN signifies data provided by the system to the CompactFlash memory card.
(1)
Table 19. Common memory Write timing
Cycle time mode
250 ns
Max
Symbol
IEEE symbol
tDVWH
Parameter
Data setup time from WE
Min
Unit
tsu(D-WEH)
th(D)
80
30
150
30
0
ns
ns
ns
ns
ns
ns
ns
ns
tWMDX
tWLWH
tAVGL
Data hold time
tw(WE)
tsu(A)
WE pulse width
Address setup time
CE setup time before WE
Write recovery time
Address hold time
CE hold following WE
tsu(CE)
trec(WE)
th(A)
tELWL
tWMAX
tGHAX
tGHEH
30
20
20
th(CE)
1. ST CF does not assert the WAIT signal.
25/82
Command interface
SMCxxxAF
Figure 6.
I/O Read timing diagram
Address Inputs
VALID
tsuREG(IORD)
tsuCE(IORD)
thA(IORD)
–REG
–CE2/–CE1
–IORD
thREG(IORD)
tsuA(IORD)
tw(IORD)
td(IORD)
thCE(IORD)
tdrINPACK(IORD)
tdrIOIS16(ADR)
–INPACK
tdfIOIS16(ADR)
tdfINPACK(IORD)
–IOIS16
th(IORD)
D0 to D15
VALID
AI10084b
1. DOUT signifies data provided by the CompactFlash memory card or to the system.
(1)
Table 20. I/O Read timing
Cycle time mode
250 ns
Symbol
td(IORD)
IEEE symbol
Parameter
Min
Max
Unit
tIGLQV
tIGHQX
tIGLIGH
tAVIGL
Data Delay after IORD
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(IORD)
Data Hold following IORD
IORD Width time
0
165
70
20
5
tw(IORD)
tsuA(IORD)
Address Setup before IORD
Address Hold following IORD
CE Setup before IORD
thA(IORD)
tIGHAX
tELIGL
tsuCE(IORD)
thCE(IORD)
tsuREG(IORD)
thREG(IORD)
tdfINPACK(IORD)
tdrINPACK(IORD)
tdfIOIS16(A)
tdrIOIS16(A)
tIGHEH
tRGLIGL
tIGHRGH
tIGLIAL
tIGHIAH
tAVISL
CE Hold following IORD
20
5
REG Setup before IORD
REG Hold following IORD
INPACK Delay Falling from IORD
INPACK Delay Rising from IORD
IOIS16 Delay Falling from Address
IOIS16 Delay Rising from Address
0
0
45
45
35
35
tAVISH
1. ST CF does not assert the WAIT signal.
26/82
SMCxxxAF
Figure 7.
Command interface
I/O Write timing diagram
Address Inputs
VALID
tsuREG(IOWR)
thA(IOWR)
thREG(IOWR)
–REG
tsuCE(IOWR)
thCE(IOWR)
–CE2/–CE1
–IOWR
tsuA(IOWR)
tw(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
–IOIS16
tsu(IOWR)
th(IOWR)
D0 to D15 (DIN
)
DIN VALID
AI10085b
1. DIN signifies data provided by the system to the CompactFlash memory card or CF+ card.
(1)
Table 21. I/O Write timing
Cycle time mode
250 ns
Max
Symbol
tsu(IOWR)
IEEE symbol
Parameter
Min
Unit
tQVIWH
tIWHQX
tIWLIWH
tAVIWL
tIWHAX
tELIWL
Data Setup before IOWR
Data Hold following IOWR
IOWR Width time
60
30
165
70
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(IOWR)
tw(IOWR)
tsuA(IOWR)
thA(IOWR)
Address Setup before IOWR
Address Hold following IOWR
CE Setup before IOWR
tsuCE(IOWR)
thCE(IOWR)
tsuREG(IOWR)
thREG(IOWR)
tdfIOIS16(A)
tdrIOIS16(A)
tIWHEH
tRGLIWL
tIWHRGH
tAVISL
CE Hold following IOWR
REG Setup before IOWR
REG Hold following IOWR
IOIS16 Delay Falling from Address
IOIS16 Delay Rising from Address
20
5
0
35
35
tAVISH
1. ST CF does not assert the WAIT signal.
27/82
Command interface
SMCxxxAF
The timing diagram for True IDE mode of operation in this section is drawn using the
conventions in the ATA-4 specification, which are different than the conventions used in the
PCMCIA specification and earlier versions of this specification. Signals are shown with their
asserted state as High regardless of whether the signal is actually negative or positive true.
Consequently, the -IORD, the -IOWR and the -IOCS16 signals are shown in the diagram
inverted from their electrical states on the bus.
Figure 8.
True IDE mode I/O timing diagram
t0
A0-A2, −CS0, −CS1(1)
ADDRESS VALID
t1
t2
t9
t8
−IORD/−IOWR
t2i
Write Data D0-D15(2)
Read Data D0-D15(2)
VALID
VALID
t3
t5
t4
t6
t6z
t7
−IOCS16(3)
ai10086b
1. The device addresses consists of −CS0, −CS1, and A2-A0.
2. The Data I/O consist of D15-D0 (16 bit) or D7-D0 (8 bit).
3. −IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
28/82
SMCxxxAF
Command interface
Table 22. True IDE mode I/O Read/Write timing diagram
Symbol
Parameter(1)
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Unit
(2)
t0
Cycle time (min)
600
383
240
180
120
ns
Address Valid to -IORD/-IOWR
setup (min)
t1
70
50
30
30
80
80
25
70
70
ns
ns
ns
(2)
t2
-IORD/-IOWR (min)
165
290
125
290
100
290
-IORD/-IOWR (min) register (8
bit)
(2)
t2
(2)
t2i
-IORD/-IOWR recovery time (min)
-IOWR data setup (min)
-IOWR data hold (min)
-
-
-
70
30
10
20
5
25
20
10
20
5
ns
ns
ns
ns
ns
ns
t3
t4
t5
t6
60
30
50
5
45
20
35
5
30
15
20
5
-IORD data setup (min)
-IORD data hold (min)
(3)
t6Z
-IORD data tri-state (max)
30
30
30
30
30
Address valid to -IOCS16
assertion (max)
(4)
t7
90
60
20
50
45
15
40
30
10
N/A
N/A
10
N/A
N/A
10
ns
ns
ns
Address valid to -IOCS16
released (max)
(4)
t8
-IORD/-IOWR to address valid
hold
t9
1. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF total load.
2. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time
or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual
command inactive time. The three timing requirements of t0, t2, and t2i have to be met. The minimum total cycle time
requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to
ensure that t0 is equal to or greater than the value reported in the device's identify drive data. A CompactFlash memory
card implementation should support any legal host implementation.
3. This parameter specifies the time from the falling edge of -IORD to the moment when the data bus is no longer driven by
the CompactFlash memory card (tri-state).
4. t7 and t8 apply only to modes 0, 1 and 2. This signal is not valid for other modes.
29/82
Card configuration
SMCxxxAF
6
Card configuration
The CompactFlash memory card is identified by information in the card information structure
(CIS). The card has four Configuration registers (Table 23 and Table 24).
■
■
■
■
Configuration Option register
Pin Replacement register
Card Configuration and Status register
Socket and Copy register
They are used to coordinate the I/O spaces and the Interrupt level of cards that are located
in the system. In addition, in I/O Card mode these registers provide a method for accessing
status information that would normally appear on dedicated pins in Memory Card mode. The
location of the Card Configuration registers should always be read from the CIS.These
registers cannot be used in True IDE mode.
No writes should be performed to the attribute memory except to the Configuration register
addresses. All other attribute memory locations are reserved. See Section 6.5: Attribute
memory function.
Table 23. CompactFlash memory card registers and memory space decoding
–CE2 –CE1 –REG –OE –WE A10 A9 A8-A4 A3 A2 A1 A0 Selected space
1
X
1
0
0
X
1
0
0
X
1
1
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
1
X
0
1
1
1
0
1
1
1
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
0
1
0
1
0
1
X
1
1
1
1
0
0
0
0
1
0
1
0
1
0
X
0
X
1
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
XXX XX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
0
0
X
X
0
0
0
1
1
X
X
Standby
Configuration registers Read
X
X
X
0
X
X
X
1
Common Memory Read (D7 to D0)
Common Memory Read (D15 to D8)
Common Memory Read (D15 to D0)
Configuration registers Write
X
X
X
0
X
X
X
0
Common Memory Write (D7 to D0)
Common Memory Write (D15 to D8)
Common Memory Write (D15 to D0)
Card Information Structure Read
Invalid Access (CIS Write)
0
0
X
X
X
X
X
X
X
X
Invalid Access (Odd Attribute Read)
Invalid Access (Odd Attribute Write)
Invalid Access (Odd Attribute Read)
Invalid Access (Odd Attribute Write)
30/82
SMCxxxAF
Card configuration
Table 24. CompactFlash memory card configuration registers decoding
A8-
–CE2 –CE1 –REG –OE –WE A10 A9
A3 A2 A1 A0
Selected register
A4
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
Configuration Option register Read
Configuration Option register Write
Card Status register Read
Card Status register Write
Pin Replacement register Read
Pin Replacement register Write
Socket and Copy register Read
Socket and Copy register Write
6.1
Configuration Option register (base + 00h in attribute
memory)
The Configuration Option register is used to configure the card’s interface, address
decoding and interrupt to the card (see Table 25).
6.1.1
6.1.2
LevlREQ
This bit is set to one (1) when level mode interrupt is selected, and zero (0) when pulse
mode is selected. Set to zero (0) after power-up.
Conf5 - Conf0 (configuration index)
These bits are used to select the operation mode of the card as shown in Table 26. This bit
is set to ‘0’ after power-up.
Table 25. Configuration Option register (default value: 00h)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
LevlREQ
Conf5
Conf4
Conf3
Conf2
Conf1
Conf0
Table 26. CompactFlash memory card configurations
Conf Conf Conf Conf Conf Conf
Mapping
mode
Card
mode
Task file register address
5
4
3
2
1
0
0
0
0
0
0
0
Memory
Memory
I/O
0h - Fh, 400h - 7FFh
xx0h - xxFh
Contiguous
I/O
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
1
Primary I/O
I/O
I/O
1F0h - 1F7h, 3F6h - 3F7h
170h - 177h, 376h - 377h
Secondary I/O
31/82
Card configuration
SMCxxxAF
6.2
Card Configuration and Status register (base + 02h in
attribute memory)
The Card Configuration and Status register contains information about the card’s status
(see Table 27).
6.2.1
6.2.2
Changed
Indicates that one or both of the pin replacement register (CRDY, or CWProt) bits are set to
‘1’. When the Changed bit is set, –STSCHG (pin 46) is held Low and if the SigChg bit is ‘1’
the card is configured for the I/O interface.
SigChg
This bit is set and reset by the host to enable and disable a state-change signal from the
Status register (issued on Status Changed pin 46). If no state change signal is desired, this
bit should be set ‘0’ and pin 46 (–STSCHG) will be held High while the card is configured for
I/O.
6.2.3
6.2.4
IOis8
The host sets this bit to ‘1’ if the card is to be configured in 8 bit I/O mode. The card is
always configured for both 8 and 16 bit I/O, so this bit is ignored.
PwrDwn
This bit indicates whether the card is in the power saving mode or active mode. When the
PwrDwn bit is set to ‘1’, the card enters power-down mode. When set to ‘0’, the card enters
active mode. The READY value on Pin Replacement register becomes BUSY when this bit
is changed. READY will not become Ready until the power state requested has been
entered. The card automatically powers down when it is idle and powers back up when it
receives a command.
6.2.5
Int
This bit represents the internal state of the interrupt request. It is available whether or not
the I/O interface has been configured. It remains valid until the condition which caused the
interrupt request has been serviced. If interrupts are disabled by the –IEN bit in the Device
Control register, this bit is ‘0’.
Table 27. Card Configuration and Status register (default value: 00h)
Operation
D7
Changed SigChg
SigChg
D6
D5
D4
D3
D2
D1
D0
Read
Write
IOIS8
IOIS8
0
0
0
0
PwrDwn
PwrDwn
Int
0
0
0
0
32/82
SMCxxxAF
Card configuration
6.3
Pin Replacement register (base + 04h in attribute memory)
This register contains information on the state of the READY signal when configured in
memory mode and the IREQ signal in I/O mode. See Table 28 and Table 29.
6.3.1
6.3.2
6.3.3
CReady
This bit is set to ‘1’ when the bit RReady changes state. This bit can also be written by the
host.
CWProt
This bit is set to '1' when the bit RWProt changes state. This bit can also be written by the
host.
RReady
This bit is used to determine the internal state of the Ready signal. In I/O mode it is used as
an interrupt request. When written, this bit acts as a mask (MReady) for writing the
corresponding bit CReady.
6.3.4
WProt
This bit is always ‘0’ since the CompactFlash memory card does not have a Write Protect
switch. When written, this bit acts as a mask for writing the corresponding CWProt bit.
6.3.5
6.3.6
MReady
This bit acts as a mask for writing the corresponding CReady bit.
MWProt
This bit when written acts as a mask for writing the corresponding CWProt bit.
Table 28. Pin Replacement register (default value: 0Ch)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Read
Write
0
0
0
0
CReady CWProt
CReady CWProt
1
0
1
0
RReady
WProt
RReady MWProt
Table 29. Pin Replacement Changed bit/Mask bit values
Written by host
Initial value of
Final ‘C’ bit
Comments
‘C’ status
‘C’ bit
‘M’ bit
0
1
X
X
0
1
0
0
1
1
0
1
0
1
Unchanged
Unchanged
X
X
Cleared by host
Set by host
33/82
Card configuration
SMCxxxAF
6.4
Socket and Copy register (base + 06h in attribute memory)
This register contains additional configuration information which identifies the card from
other cards. This register is always written by the system before writing the Configuration
Option register (see Table 30).
6.4.1
6.4.2
Drive #
This value can be used to address two different cards in the case of twin card configuration.
X
The socket number is ignored by the card.
Table 30. Socket and Copy register (default value: 00h)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Read
Write
Reserved
0
0
0
0
0
Drive #
Drive #
0
0
0
0
X
X
X
X
34/82
SMCxxxAF
Card configuration
6.5
Attribute memory function
Attribute memory is a space where identification and configuration information are stored,
and is limited to 8 bit wide accesses at even addresses. The Card Configuration registers
are also located here, the base address of the configuration registers is 200h.
For the attribute memory Read function, signals –REG and –OE must be active and –WE
inactive during the cycle. As in the main memory read functions, the signals –CE1 and –CE2
control the even and odd byte address, but only the even byte data is valid during the
attribute memory access. Refer to Table 31 for signal states and bus validity.
(1)
Table 31. Attribute memory function
Function mode
Standby
–REG –CE2 –CE1 A10
A9
A0
–OE –WE D15 to D8 D7 to D0
X
L
H
H
H
L
X
L
X
X
X
L
X
H
High-Z
High-Z
High-Z
Read Byte Access CIS
(8 bits)
L
L
L
L
Even byte
Write Byte Access CIS
(8 bits) Invalid
L
L
H
H
L
L
L
L
H
L
L
Don’t care Even byte
Read Byte Access
Configuration
H
H
L
L
H
High-Z
Even byte
(8 bits)
Write Byte Access
Configuration
L
H
L
L
H
L
Don’t care Even byte
(8 bits)
Read Byte Access
L
L
H
L
L
L
X
L
X
L
L
L
L
H
H
High-Z
Even byte
Even byte
Configuration CF+ (8
bits)
Read Word Access CIS
(16 bits)
X
Not valid
Write Word Access CIS
(16 bits) Invalid
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
X
X
H
L
L
H
L
Don’t care Even byte
Read Word Access
Configuration (16 bits)
Not valid
Even byte
Write Word Access
Configuration (16 bits)
H
Don’t care Even byte
1. The –CE signal or both the –OE signal and the –WE signal must be de-asserted between consecutive cycle operations.
35/82
Card configuration
SMCxxxAF
6.6
I/O transfer function
The I/O transfer to or from the card can be either 8 or 16 bits. When a 16 bit accessible port
is addressed, the –IOIS16 signal is asserted by the card, otherwise it is de-asserted. When
a 16 bit transfer is attempted, and the –IOIS16 signal is not asserted, the system must
generate a pair of 8 bit references to access the word’s even and odd bytes. The card
permits both 8 and 16 bit accesses to all of its I/O addresses, so –IOIS16 is asserted for all
addresses (see Table 32).
Table 32. I/O function
Function code
–REG –CE2
–CE1 A0
–IORD
–IOWR
D15 to D8
D7 to D0
Standby mode
X
H
H
X
X
X
High Z
High Z
Byte input access
(8 bits)
L
L
H
H
L
L
L
L
L
H
H
High Z
High Z
Even byte
Odd byte
H
Byte output access
(8 bits)
L
L
H
H
L
L
L
H
H
L
L
Don’t care
Don’t care
Even byte
Odd byte
H
Word input access
(16 bits)
L
L
L
L
L
L
L
L
L
H
L
Odd byte
Odd byte
Even byte
Even byte
Word output access
(16 bits)
H
I/O Read Inhibit
I/O Write inhibit
H
H
X
X
X
X
X
X
L
H
L
Don’t care
High Z
Don’t care
High Z
H
High byte input only
(8 bits)
L
L
L
L
H
H
X
X
L
H
L
Odd byte
Odd byte
High Z
High byte output only
(8 bits)
H
Don’t care
36/82
SMCxxxAF
Card configuration
6.7
Common memory transfer function
The common memory transfer to or from the card permits both 8 or 16 bit access to all of the
common memory addresses. (see Table 33).
Table 33. Common memory function
Function code –REG –CE2 –CE1 A0
Standby mode
–OE
–WE
D15 to D8
High Z
D7 to D0
High Z
X
H
H
X
X
X
Byte Read access
(8 bits)
H
H
H
H
L
L
L
L
L
H
H
High Z
High Z
Even byte
Odd byte
H
Byte Write access
(8 bits)
H
H
H
H
L
L
L
H
H
L
L
Don’t care
Don’t care
Even byte
Odd byte
H
Word Read access
(16 bits)
H
H
H
H
L
L
L
L
L
X
X
X
X
L
H
L
Odd byte
Odd byte
Odd byte
Odd byte
Even byte
Even byte
High Z
Word Write access
(16 bits)
L
H
L
Odd byte read only
(8 bits)
H
H
H
L
Odd byte write only
(8 bits)
H
Don’t care
37/82
Card configuration
SMCxxxAF
6.8
True IDE mode I/O function
The card can be configured in a True IDE mode of operation. It is configured in this mode
only when the –OE signal is grounded by the host during the power-off to power-on cycle. In
this True IDE mode the PCMCIA protocol and configuration are disabled and only I/O
operations to the task file and data register are allowed. No memory or attribute registers
are accessible to the host. The Set Feature command can be used to put the device in 8 bit
mode (see Table 34).
Removing and reinserting the card while the host computer’s power is on will reconfigure
the card to PC Card ATA mode.
Table 34. True IDE mode I/O function
Function code
–CE2
–CE1 A2 to A0
–IORD
–IOWR
D15 to D8
High Z
D7 to D0
High Z
Invalid mode
L
L
X
X
X
H
L
X
Standby mode
H
H
H
H
H
L
H
L
X
X
L
High Z
High Z
Task File Write
1h-7h
1h-7h
L
Don’t care
High Z
Data In
Task File Read
L
H
L
Data Out
Even-byte In
Data Register Write
Data Register Read
Control Register Write
Alternate Status Read
Drive Address
L
H
L
Odd-byte In
L
L
H
L
Odd-byte Out Even-byte Out
H
H
H
6h
6h
7h
H
L
Don’t care
High Z
Control In
Status Out
Data Out
L
H
H
L
L
High Z
38/82
SMCxxxAF
Software interface
7
Software interface
7.1
CF-ATA Drive register set definition and protocol
The CompactFlash memory card can be configured as a high performance I/O device
through:
■
Standard PC-AT disk I/O address spaces
–
–
1F0h-1F7h, 3F6h-3F7h (primary);
170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ).
■
■
Any system decoded 16 byte I/O block using any available IRQ.
Memory space.
Communication to or from the card is done using the Task File registers which provide all
the necessary registers for control and status information. The PCMCIA interface connects
peripherals to the host using four-register mapping methods. Table 35 is a detailed
description of these methods:
Table 35. I/O configurations
Standards configurations
Config index
I/O or memory
Address
Description
0
1
2
3
Memory
I/O
0h-Fh, 400h-7FFh
xx0h-xxFh
Memory mapped
I/O mapped 16 continuous registers
Primary I/O mapped
I/O
1F0-1F7h, 3F6h-3F7h
170-177h, 376h-377h
I/O
Secondary I/O mapped
7.2
Memory mapped addressing (conf = 0)
When the card registers are accessed via memory references, the registers appear in the
common memory space window: 0-2 Kbytes as shown in Table 36. This window accesses
the Data register FIFO. It does not allow random access to the data buffer within the card.
Register 0 is accessed with –CE1 and –CE2 Low, as a word register on the combined Odd
and Even Data Bus (D15 to D0). It can also be accessed with –CE1 Low and –CE2 High, by
a pair of byte accesses to offset 0. The address space of this word register overlaps the
address space of the error and feature bytewide registers at offset 1. When accessed twice
as byte register with –CE1 Low, the first byte is the even byte of the word and the second is
the odd byte. A byte access to address 0 with –CE1 High and –CE2 Low accesses the error
(read) or feature (write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and
1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if
the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte
then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even
then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will
access consecutive words from the data buffer, however repeated byte accesses to register
9 are not supported. Repeated alternating byte accesses to registers 8 then 9 will access
consecutive (even then odd) bytes from the data buffer.
39/82
Software interface
SMCxxxAF
Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd
addresses between 400h and 7FFh access register 9. This 1 Kbyte memory window to the
data register is provided so that hosts can perform memory-to-memory block moves to the
data register when the register lies in memory space. Some hosts, such as the X86
processors, must increment both the source and destination addresses when executing the
memory-to-memory block move instruction. Some PCMCIA socket adapters also have an
embedded auto incrementing address logic.
A word access to address at offset 8 will provide even data on the least significant byte of
the data bus, along with odd data at offset 9 on the most significant byte of the data bus.
Table 36. Memory mapped decoding
–REG A10 A9 to A4 A3 A2 A1 A0 Offset
–OE=0
–WE=0
1
1
1
1
1
1
0
0
0
0
0
0
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0h
1h
2h
3h
4h
5h
Even Data register
Error register
Even Data register
Feature register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Select Card/Head
register
1
0
X
0
1
1
0
6h
Select card/Head register
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
X
X
X
X
X
X
X
X
0
1
1
1
1
1
X
X
1
0
0
1
1
1
X
X
1
0
0
0
1
1
X
X
1
0
1
1
0
1
0
1
7h
8h
9h
Dh
Eh
Fh
8h
9h
Status register
Dup. Even Data register
Dup. Odd Data register
Dup. Error register
Command register
Dup. Even Data register
Dup. Odd Data register
Dup. Feature register
Device Control register
Reserved
Alternate Status register
Drive Address register
Even Data register
Even Data register
Odd Data register
Odd Data register
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SMCxxxAF
Software interface
7.3
Contiguous I/O mapped addressing (conf = 1)
When the system decodes a contiguous block of I/O registers to select the card, the
registers are accessed in the block of I/O space decoded by the system as shown in
Table 37.
As for the memory mapped addressing, register 0 is accessed with –CE1 Low and –CE2
Low (and A0 Don’t care) as a word register on the combined odd and even data bus (D15 to
D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of byte
accesses to offset 0. The address space of this word register overlaps the address space of
the error and feature bytewide registers at offset 1. When accessed twice as byte register
with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A
byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature
(write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and
1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if
the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte
then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even
than odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will
access consecutive words from the data buffer, however repeated byte accesses to register
9 are not supported. Repeated alternating byte accesses to registers 8 then 9 will access
consecutive (even then odd) bytes from the data buffer.
Table 37. Contiguous I/O decoding
–REG A10 to A4 A3
A2
A1
A0 Offset
–IORD=0
–IOWR=0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Dh
Eh
Fh
Even Data register
Error register
Even Data register
Feature register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Select Card/Head register
Status register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Select Card/Head register
Command register
Dup. Even Data register
Dup. Odd Data register
Dup. Error register
Dup. Even Data register
Dup. Odd Data register
Dup. Feature register
Device Control register
Reserved
Alternate Status register
Drive Address register
41/82
Software interface
SMCxxxAF
7.4
I/O primary and secondary address configurations
(conf = 2,3)
When the system decodes the primary and secondary address configurations, the registers
are accessed in the block of I/O space as shown in Table 38.
As for the memory mapped addressing, register 0 is accessed with –CE1 Low and –CE2
Low (and A0 Don’t care) as a word register on the combined odd and even data bus (D15 to
D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of byte
accesses to offset 0. The address space of this word register overlaps the address space of
the error and feature bytewide registers at offset 1. When accessed twice as byte register
with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A
byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature
(write) register.
Table 38. Primary and secondary I/O decoding
–REG
A9 to A4 A3 A2 A1 A0
–IORD=0
–IOWR=0
0
0
0
0
0
0
0
0
0
0
1F(17)h
1F(17)h
1F(17)h
1F(17)h
1F(17)h
1F(17)h
1F(17)h
1F(17)h
3F(37)h
3F(37)h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
Even Data register
Error register
Even Data register
Feature register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Select Card/Head register
Status register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Select Card/Head register
Command register
Device Control register
Reserved
Alternate Status register
Drive Address register
42/82
SMCxxxAF
Software interface
7.5
True IDE mode addressing
When the card is configured in the True IDE mode, the I/O decoding is as shown in Table 39.
Table 39. True IDE mode I/O decoding
–CE2
–CE1
A2
A1
A0
–IORD=0
–IOWR=0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
Data register
Error register
Data register
Feature register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Select Card/Head register
Status register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Select Card/Head register
Command register
Device Control register
Reserved
Alternate Status register
Drive Address
43/82
CF-ATA registers
SMCxxxAF
8
CF-ATA registers
The following section describes the hardware registers used by the host software to issue
commands to the card. These registers are collectively referred to as the ‘task file’.
8.1
Data register (address 1F0h [170h]; offset 0, 8, 9)
The data register is a 16-bit register used to transfer data blocks between the card data
buffer and the host. This register overlaps the error register. Table 40 describes the
combinations of data register access and explains the overlapped data and error/feature
registers. Because of the overlapped registers, access to the 1F1h, 171h or offset 1 are not
defined for word (–CE2 and –CE1 set to ‘0’) operations, and are treated as accesses to the
word data register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on
the operations that can be performed.
Table 40. Data register access
Data register
–CE2
–CE1
A0
Offset
Data Bus
Word Data register
Even Data register
Odd Data register
0
1
1
0
1
0
0
0
0
0
1
0
1
0
X
0
0, 8, 9
0, 8
9
D15 to D0
D7 to D0
D7 to D0
D15 to D8
D7 to D0
D15 to D8
D15 to D8
1
Odd Data register
X
1
8, 9
1, Dh
1
Error/Feature register
Error/Feature register
Error/Feature register
X
X
Dh
8.2
Error register (address 1F1h [171h]; offset 1, 0Dh read only)
This read only register contains additional information about the source of an error when an
error is indicated in bit 0 of the status register. The bits are defined in Table 41. This register
is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and –
CE1 High.
8.2.1
8.2.2
8.2.3
Bit 7 (BBK)
This bit is set when a bad block is detected.
Bit 6 (UNC)
This bit is set when an uncorrectable error is encountered.
Bit 5
This bit is ‘0’.
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SMCxxxAF
CF-ATA registers
8.2.4
Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
8.2.5
8.2.6
Bit 3
This bit is ‘0’.
Bit 2 (abort)
This bit is set if the command has been aborted because of a card status condition (Not
Ready, Write Fault, etc.) or when an invalid command has been issued.
8.2.7
8.2.8
Bit 1
This bit is ‘0’.
Bit 0 (AMNF)
This bit is set when there is a general error.
Table 41. Error register
D7
D6
D5
D4
D3
D2
D1
D0
BBK
UNC
0
IDNF
0
ABRT
0
AMNF
8.3
8.4
Feature register (address 1F1h [171h]; offset 1, 0Dh write
only)
This write-only register provides information on features that the host can utilize. It is
accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and –
CE1 High.
Sector Count register (address 1F2h [172h]; offset 2)
This register contains the number of sectors of data to be transferred on a read or write
operation between the host and card. If the value in this register is zero, a count of 256
sectors is specified. If the command was successful, this register is zero at completion. If
not successfully completed, the register contains the number of sectors that need to be
transferred in order to complete the request. The default value is 01h.
8.5
Sector Number (LBA 7-0) register (address 1F3h [173h];
offset 3)
This register contains the starting sector number or bits 7 to 0 of the logical block address
(LBA), for any data access for the subsequent sector transfer command.
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CF-ATA registers
SMCxxxAF
8.6
8.7
8.8
Cylinder Low (LBA 15-8) register (address 1F4h [174h];
offset 4)
This register contains the least significant 8 bits of the starting cylinder address or bits 15 to
8 of the logical block address.
Cylinder High (LBA 23-16) register (address 1F5h [175h];
offset 5)
This register contains the most significant bits of the starting cylinder address or bits 23 to
16 of the logical block address.
Drive/Head (LBA 27-24) register (address 1F6h [176h]; offset
6)
The Drive/Head register is used to select the drive and head. It is also used to select LBA
addressing instead of cylinder/head/sector addressing. The bits are defined in Table 42.
8.8.1
8.8.2
Bit 7
This bit is set to ‘1’.
Bit 6 (LBA)
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address mode
(LBA). When LBA is set to ‘0’, Cylinder/Head/Sector mode is selected. When LBA is set to
’1’, Logical Block Address mode is selected. In Logical Block Address mode, the logical
block address is interpreted as follows:
■
■
■
■
LBA7-LBA0: Sector Number register D7 to D0.
LBA15-LBA8: Cylinder Low register D7 to D0.
LBA23-LBA16: Cylinder High register D7 to D0.
LBA27-LBA24: Drive/Head register bits HS3 to HS0.
8.8.3
8.8.4
Bit 5
This bit is set to ‘1’.
Bit 4 (DRV)
DRV is the drive number. When DRV is ‘0’, drive/card 0 is selected (master). When DRV is
‘1’, drive/card 1 is selected (slave). The card is set to card 0 or 1 using the copy field (Drive
#) of the PCMCIA Socket & Copy configuration register.
8.8.5
Bit 3 (HS3)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is bit
27 in the Logical Block Address mode.
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SMCxxxAF
CF-ATA registers
8.8.6
Bit 2 (HS2)
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is bit
26 in the Logical Block Address mode.
8.8.7
8.8.8
Bit 1 (HS1)
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is bit
25 in the Logical Block Address mode.
Bit 0 (HS0)
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is bit
24 in the Logical Block Address mode.
Table 42. Drive/Head register
D7
D6
D5
D4
D3
D2
D1
D0
1
LBA
1
DRV
HS3
HS2
HS1
HS0
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CF-ATA registers
SMCxxxAF
8.9
Status & alternate status registers (address 1F7h [177h] &
3F6h [376h]; offsets 7 & Eh)
These registers return the card status when read by the host.
Reading the status register clears a pending interrupt. Reading the auxiliary status register
does not clear a pending interrupt.
The status register should be accessed in Byte mode; in Word mode it is recommended that
alternate status register is used. The status bits are described as follows
8.9.1
8.9.2
Bit 7 (BUSY)
The busy bit is set when only the card can access the command register and buffer. The
host is denied access. No other bits in this register are valid when this bit is set to ‘1’.
Bit 6 (RDY)
This bit indicates whether the device is capable of performing CompactFlash memory card
operations. This bit is cleared at power-up and remains cleared until the card is ready to
accept a command.
8.9.3
8.9.4
8.9.5
Bit 5 (DWF)
When set this bit indicates a write fault has occurred.
Bit 4 (DSC)
This bit is set when the card is ready.
Bit 3 (DRQ)
The data request is set when the card requires information be transferred either to or from
the host through the data register. The bit is cleared by the next command.
8.9.6
Bit 2 (CORR)
This bit is set when a correctable data error has been encountered and the data has been
corrected. This condition does not terminate a multi-sector read operation.
8.9.7
8.9.8
Bit 1 (IDX)
This bit is always set to ‘0’.
Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in the
error register contain additional information describing the error. In case of read or write
access commands that end with an error, the address of the first sector with an error is in
the command block registers. This bit is cleared by the next command.
48/82
SMCxxxAF
CF-ATA registers
Table 43. Status & alternate status register
D7
D6
D5
D4
D3
D2
D1
D0
BUSY
RDY
DWF
DSC
DRQ
CORR
0
ERR
8.10
Device control register (address 3F6h [376h]; offset Eh)
This write-only register is used to control the CompactFlash memory card interrupt request
and to issue an ATA soft reset to the card. This register can be written even if the device is
BUSY. The bits are defined as follows:
8.10.1
8.10.2
Bit 7 to 3
Don’t care. The host should reset this bit to ‘0’.
Bit 2 (SW Rst)
This bit is set to ‘1’ in order to force the CompactFlash storage card to perform an AT Disk
controller Soft Reset operation. This clears status register and writes diagnostic code in
error register after a write or read sector error. The card remains in reset until this bit is reset
to ‘0.’
8.10.3
8.10.4
Bit 1 (–IEn)
When the Interrupt Enable bit is set to ‘0’, –IREQ interrupts are enabled. When the bit is set
to ‘1’, interrupts from the card are disabled. This bit also controls the Int bit in the card
configuration and status register. It is set to ‘0’ at power-on.
Bit 0
This bit is set to ‘0’.
Table 44. Device control register
D7
D6
D5
D4
D3
D2
D1
D0
X(0)
X(0)
X(0)
X(0)
X(0)
SW Rst
–IEn
0
49/82
CF-ATA registers
SMCxxxAF
8.11
Card (drive) address register (address 3f7h [377h]; offset Fh)
This read-only register is provided for compatibility with the AT disk drive interface and can
be used for confirming the drive status. It is recommended that this register is not mapped
into the host’s I/O space because of potential conflicts on bit 7. The bits are defined as
follows:
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.11.6
8.11.7
8.11.8
Bit 7
This bit is Don’t care.
Bit 6 (–WTG)
This bit is ‘0’ when a write operation is in progress, otherwise, it is ‘1’.
Bit 5 (–HS3)
This bit is the negation of bit 3 in the drive/head register.
Bit 4 (–HS2)
This bit is the negation of bit 2 in the drive/head register.
Bit 3 (–HS1)
This bit is the negation of bit 1 in the drive/head register.
Bit 2 (–HS0)
This bit is the negation of bit 0 in the drive/head register.
Bit 1 (–nDS1)
This bit is ‘0’ when drive 1 is active and selected.
Bit 0 (–nDS0)
This bit is ‘0’ when the drive 0 is active and selected.
Table 45. Card (drive) address register
D7
D6
D5
D4
D3
D2
D1
D0
X
–WTG
–HS3
–HS2
–HS1
–HS0
–nDS1
–nDS0
50/82
SMCxxxAF
CF-ATA command description
9
CF-ATA command description
This section defines the software requirements and the format of the commands the host
sends to the card. Commands are issued to the card by loading the required registers in the
command block with the supplied parameters, and then writing the command code to the
command register. There are three classes of command acceptance, all dependent on the
host not issuing commands unless the card is not busy (BSY is ‘0’).
■
■
Class 1. Upon receipt of a class 1 command, the card sets BSY within 400 ns.
Class 2. Upon receipt of a class 2 command, the card sets BSY within 400 ns, sets up
the sector buffer for a write operation, sets DRQ within 700 µs, and clears BSY within
400 ns of setting DRQ.
■
Class 3. Upon receipt of a class 3 command, the card sets BSY within 400 ns, sets up
the sector buffer for a write operation, sets DRQ within 20 ms (assuming no re-
assignments), and clears BSY within 400 ns of setting DRQ.
For reasons of backward compatibility some commands are implemented as ‘no operation’
NOP.
Table 46 summarizes the CF-ATA command set with the paragraphs that follow describing
the individual commands and the task file for each.
(1)
Table 46. CF-ATA command set
Class
Command
Code
FR SC SN
CY
DH
LBA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Check Power mode
Execute Drive Diagnostic
Erase Sector(s)
Identify Drive
E5h or 98h
90h
D
YD
Y
C0h
Y
Y
Y
Y
Y
Y
ECh
D
D
D
Y
Idle
E3h or 97h
E1h or 95h
91h
Idle immediate
Initialize Drive Parameters
NOP
00h
D
D
Y
Read Buffer
E4h
Read Multiple
Read Sector(s)
Read Verify Sector(s)
Recalibrate
C4h
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
20h or 21h
40h or 41h
1Xh
Y
Y
D
D
Y
Request Sense
Seek
03h
7Xh
Y
Y
Y
Set Features
EFh
Y
D
D
D
D
Set Multiple mode
Set Sleep mode
Standby
C6h
Y
E6h or 99h
E2h or 96h
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CF-ATA command description
SMCxxxAF
(1)
Table 46. CF-ATA command set (continued)
Class
Command
Code
FR SC SN
CY
DH
LBA
1
1
1
2
3
3
2
2
3
Standby immediate
Translate Sector
Wear Level
E0h or 94h
87h
D
Y
Y
D
Y
Y
Y
Y
Y
Y
Y
Y
Y
F5h
Write Buffer
E8h
Write Multiple
C5h
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Write Multiple w/o Erase
Write Sector(s)
CDh
30h or 31h
38h
Write Sector(s) w/o Erase
Write Verify
3Ch
1. FR = Features Register, SC = Sector Count Register, SN = Sector Number Register, CY = Cylinder
Registers, DH = Card/Drive/Head Register, LBA = Logical Block Address Mode Supported (see command
descriptions for use),
Y - The register contains a valid parameter for this command. For the drive/head register Y means both the
Compact Flash memory card and head parameters are used.
D - only the Compact Flash memory card parameter is valid and not the head parameter
C - the register contains command specific data (see command descriptors for use).
9.1
Check Power mode command (98h or E5h)
This command checks the power mode.
Issuing the command while the card is in Standby mode, is about to enter Standby, or is
exiting Standby, the command will set BSY, set the Sector Count register to 00h, clear BSY
and generate an interrupt.
Issuing the command when the card is in Idle mode will set BSY, set the Sector Count
register to FFh, clear BSY and generate an interrupt.
Table 47 defines the byte sequence of the Check Power mode command.
Table 47. Check Power mode
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
98h or E5h
Drive
X
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
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SMCxxxAF
CF-ATA command description
9.2
Execute Drive Diagnostic command (90h)
This command performs the internal diagnostic tests implemented by the card.
In PCMCIA configuration, this command only runs on the card which is addressed by the
drive/head register when the command is issued. This is because PCMCIA card interface
does not allow for direct inter-drive communication.
In True IDE mode, the Drive bit is ignored and the diagnostic command is executed by both
the master and the slave with the master responding with the status for both devices.
Table 48 defines the Execute Drive Diagnostic command byte sequence. The diagnostic
codes shown in Table 49 are returned in the error register at the end of the command.
Table 48. Execute Drive Diagnostic
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
90h
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
Table 49. Diagnostic codes
Code
Error type
01h
02h
03h
04h
05h
8Xh
No error detected
Formatter device error
Sector buffer error
ECC circuitry error
Controlling microprocessor error
Slave error in True IDE mode
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CF-ATA command description
SMCxxxAF
9.3
Erase Sector(s) command (C0h)
This command is used to pre-erase and condition data sectors prior to a Write Sector
Without Erase command or a Write Multiple Without Erase command. There is no data
transfer associated with this command but a Write Fault error status can occur. Table 50
defines the byte sequence of the Erase Sector command.
Table 50. Erase Sector(s)
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
C0h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
X
9.4
Identify Drive command (ECh)
The Identify Drive command enables the host to receive parameter information from the
card. This command has the same protocol as the Read Sector(s) command. Table 51
defines the Identify Drive command byte sequence. All reserved bits or words are zero.
Table 52 shows the definition of each field in the identify drive information.
9.4.1
9.4.2
Word 0: general configuration
This field indicates that the device is a CompactFlash memory card.
Word 1: default number of cylinders
This field contains the number of translated cylinders in the default translation mode. This
value will be the same as the number of cylinders.
9.4.3
9.4.4
9.4.5
Word 3: default number of heads
This field contains the number of translated heads in the default translation mode.
Word 6: default number of sectors per track
This field contains the number of sectors per track in the default translation mode.
Word 7-8: number of sectors per card
This field contains the number of sectors per card. This double word value is also the first
invalid address in LBA translation mode.
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SMCxxxAF
CF-ATA command description
9.4.6
Word 10-19: memory card serial number
The contents of this field are right justified and padded with spaces (20h).
9.4.7
9.4.8
Word 23-26: firmware revision
This field contains the revision of the firmware for this product.
Word 27-46: model number
This field contains the model number for this product and is left justified and padded with
spaces (20h).
9.4.9
Word 47: read/write multiple sector count
This field contains the maximum number of sectors that can be read or written per interrupt
using the Read Multiple or Write Multiple commands.
9.4.10
Word 49: capabilities
■
Bit 13 Standby timer: it is set to ’0’ to indicate that the Standby timer operation is
defined by the manufacturer.
■
■
Bit 9 LBA support: CompactFlash memory cards support LBA mode addressing.
Bit 8 DMA Support: DMA mode is not supported.
9.4.11
9.4.12
Word 51: PIO data transfer cycle timing mode
This field defines the mode for PIO data transfer. For backward compatibility with BIOSs
written before word 64 was defined for advanced modes, a device reports in word 51, the
highest original PIO mode it can support (PIO mode 0, 1 or 2).
Bits 15-8: are set to 02H.
Word 53: translation parameter valid
■
■
Bit 1: is set to '1' to indicate that words 64 to 70 are valid
Bit 0: is set to '1' to indicate that words 54 to 58 are valid
9.4.13
9.4.14
Word 54-56: current number of cylinders, heads, sectors/track
These fields contains the current number of user addressable cylinders, heads, and
sectors/track in the current translation mode.
Word 57-58: current capacity
This field contains the product of the current cylinders, heads and sectors.
55/82
CF-ATA command description
SMCxxxAF
9.4.15
Word 59: multiple sector setting
■
■
■
Bits 15-9 are reserved and must be set to ‘0’.
Bit 8 is set to ‘1’, to indicate that the multiple sector setting is valid.
Bits 7-0 are the current setting for the number of sectors to be transferred for every
interrupt, on Read/Write Multiple commands; the only values returned are 00h or 01h.
9.4.16
9.4.17
Word 60-61: total sectors addressable in LBA mode
This field contains the number of sectors addressable for the card in LBA mode only.
Word 64: advanced PIO transfer modes supported
This field is bit significant. Any number of bits may be set to ‘1’ in this field by the
CompactFlash memory card to indicate the advanced PIO modes it is capable of
supporting.
■
■
■
Bits 7-2 are reserved for future advanced PIO modes.
Bit 1 is set to ‘1’, indicates that the CompactFlash memory card supports PIO mode 4.
Bit 0 is set to ‘1’ to indicate that the CompactFlash memory card supports PIO mode 3.
9.4.18
9.4.19
Word 67: minimum PIO transfer cycle time without flow control
This field gives the minimum cycle time (in ns) that the host should use for the
CompactFlash memory card to provide data integrity during transfer when flow control is not
used. The value returned is 78h (for cycle time values refer to Table 22).
Word 68: minimum PIO transfer cycle time with IORDY
This field gives the minimum cycle time (in ns) supported by the CompactFlash memory
card to perform data transfers using IORDY flow control. The value returned is 78h (for
cycle time values refer to Table 22).
Table 51. Identify drive
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
ECh
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
56/82
SMCxxxAF
CF-ATA command description
Table 52. Identify drive information
Word
address
Default
value
Total
bytes
Data field type information
General configuration (signature for the CompactFlash
memory card)
0
848Ah
2
1
2
XXXXh
0000h
00XXh
0000h
0000h
XXXXh
XXXXh
0000h
aaaa
2
2
Default number of cylinders
Reserved
3
2
Default number of heads
4
2
Obsolete
5
2
Obsolete
6
2
Default number of sectors per track
7-8
9
4
Number of sectors per card (word 7 = MSW, word 8 = LSW)
2
Obsolete
10-19
20
21
22
23-26
20
2
Serial number in ASCII (right justified)
0000h
0000h
0004h
aaaa
Obsolete
2
Obsolete
2
Reserved
8
Firmware revision in ASCII. Big endian byte order in word
Model number in ASCII (right justified) big endian byte order
in word
27-46
47
aaaa
40
2
Maximum number of sectors on read/write multiple
command
0001h
48
49
50
51
52
53
54
55
56
0000h
0200h
0000h
0200h
0000h
0003h
XXXXh
XXXXh
XXXXh
2
2
2
2
2
2
2
2
2
Reserved
Capabilities
Reserved
PIO data transfer cycle timing mode
Obsolete
Field validity
Current numbers of cylinders
Current numbers of heads
Current sectors per track
Current capacity in sectors (LBAs) (word 57 = LSW, word 58
= MSW)
57-58
XXXXh
4
59
60-61
62-63
64
01XXh
XXXXh
0000h
0003h
0000h
0078h
0078h
0000h
0000h
0000h
2
4
Multiple sector setting
Total number of sectors addressable in LBA mode
4
Reserved
2
Advanced PIO modes supported
65-66
67
4
Reserved
2
Minimum PIO transfer cycle time without flow control
68
2
Minimum PIO transfer cycle time with IORDY flow control
69-128
129-159
160-255
120
62
192
Reserved
Manufacturer unique bytes
Reserved
57/82
CF-ATA command description
SMCxxxAF
9.5
Idle command (97h or E3h)
This command causes the card to set BSY, enter the Idle mode, clear BSY and generate an
interrupt. If the sector count is non-zero, it is interpreted as a timer count (each count is
5 ms) and the automatic power down mode is enabled. If the sector count is zero, the
automatic power-down mode is disabled. Note that this time base (5 ms) is different from
the ATA specification. Table 53 defines the byte sequence of the Idle command.
Table 53. Idle
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
97h or E3h
Drive
X
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
Timer Count (5 ms increments)
X
58/82
SMCxxxAF
CF-ATA command description
9.6
Idle Immediate command (95h or E1h)
This command causes the card to set BSY, enter the Idle mode, clear BSY and generate an
interrupt. Table 54 defines the Idle Immediate command byte sequence.
Table 54. Idle Immediate
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
95h or E1h
Drive
X
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
9.7
Initialize Drive Parameters command (91h)
This command enables the host to set the number of sectors per track and the number of
heads per cylinder. Only the Sector Count and the Card/Drive/Head registers are used by
this command. Table 55 defines the Initialize Drive Parameters command byte sequence.
Table 55. Initialize Drive Parameters
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
91h
X
0
X
Drive
Max Head (no. of heads 1)
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
Number of sectors
X
59/82
CF-ATA command description
SMCxxxAF
9.8
NOP command (00h)
This command always fails with the CompactFlash memory card returning command
aborted. Table 56 defines the byte sequence of the NOP command.
Table 56. NOP
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
00h
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
9.9
Read Buffer command (E4h)
The Read Buffer command enables the host to read the current contents of the card’s sector
buffer. This command has the same protocol as the Read Sector(s) command. Table 57
defines the Read Buffer command byte sequence.
Table 57. Read Buffer
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
E4h
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
60/82
SMCxxxAF
CF-ATA command description
9.10
Read Multiple command (C4h)
The Read Multiple command performs similarly to the Read Sectors command. Interrupts
are not generated on every sector, but on the transfer of a block which contains the number
of sectors defined by a Set Multiple command.
Command execution is identical to the Read Sectors operation except that the number of
sectors defined by a Set Multiple command are transferred without intervening interrupts.
DRQ qualification of the transfer is required only at the start of the data block, not on each
sector.
The block count of sectors to be transferred without intervening interrupts is programmed by
the Set Multiple mode command, which must be executed prior to the Read Multiple
command. When the Read Multiple command is issued, the Sector Count register contains
the number of sectors (not the number of blocks or the block count) requested. If the
number of requested sectors is not evenly divisible by the block count, as many full blocks
as possible are transferred, followed by a final, partial block transfer. The partial block
transfer is for n sectors, where:
n = (sector count) module (block count).
If the Read Multiple command is attempted before the Set Multiple mode command has
been executed or when Read Multiple commands are disabled, the Read Multiple operation
is rejected with an aborted command error. Disk errors encountered during Read Multiple
commands are posted at the beginning of the block or partial block transfer, but DRQ is still
set and the data transfer will take place as it normally would, including transfer of corrupted
data, if any.
Interrupts are generated when DRQ is set at the beginning of each block or partial block.
The error reporting is the same as that on a Read Sector(s) command. This command reads
from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests
256 sectors. The transfer begins at the sector specified in the Sector Number register.
If an error occurs, the read terminates at the sector where the error occurred. The
Command Block registers contain the cylinder, head and sector number of the sector where
the error occurred. The flawed data is pending in the sector buffer.
Subsequent blocks or partial blocks are transferred only if the error was a correctable data
error. All other errors cause the command to stop after transfer of the block which contained
the error.
Table 58 defines the Read Multiple command byte sequence.
Table 58. Read Multiple
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
C4h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
X
61/82
CF-ATA command description
SMCxxxAF
9.11
Read Sector(s) command (20h or 21h)
This command reads from 1 to 256 sectors as specified in the Sector Count register. A
sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the
Sector Number register. When this command is issued and after each sector of data (except
the last one) has been read by the host, the card sets BSY, puts the sector of data in the
buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512
bytes of data from the buffer.
If an error occurs, the read terminates at the sector where the error occurred. The
Command Block registers contain the cylinder, head, and sector number of the sector
where the error occurred. The flawed data is pending in the sector buffer. Table 59 defines
the Read Sector command byte sequence.
Table 59. Read Sector(s)
Bit
7
6
5
4
3
2
1
0
Command
(7)
20h or 21h
C/D/H (6)
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High
(5)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Cyl Low (4)
Sect Num
(3)
Sect Cnt
(2)
Sector Count
X
Feature (1)
9.12
Read Verify Sector(s) command (40h or 41h)
This command is identical to the Read Sectors command, except that DRQ is never set and
no data is transferred to the host. When the command is accepted, the card sets BSY.
When the requested sectors have been verified, the card clears BSY and generates an
interrupt.
If an error occurs, the verify terminates at the sector where the error occurs. The Command
Block registers contain the cylinder, head and sector number of the sector where the error
occurred. The Sector Count register contains the number of sectors not yet verified.
Table 60 defines the Read Verify Sector command byte sequence.
62/82
SMCxxxAF
CF-ATA command description
Table 60. Read Verify Sector(s)
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
40h or 41h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
X
9.13
Recalibrate command (1Xh)
This command is effectively a NOP command to the card and is provided for compatibility
purposes. Table 61 defines the Recalibrate command byte sequence.
Table 61. Recalibrate
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
1Xh
1
LBA
1
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
9.14
Request Sense command (03h)
This command requests extended error information for the previous command. Table 62
defines the Request Sense command byte sequence. Table 63 defines the valid extended
error codes. The extended error code is returned to the host in the Error register.
63/82
CF-ATA command description
SMCxxxAF
Table 62. Request Sense
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
03h
1
X
1
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
Table 63. Extended Error codes
Extended error code
Description
00h
No error detected
01h
Self test OK (no error)
Miscellaneous error
09h
21h
Invalid address (requested head or sector invalid)
Address overflow (address too large)
Supply or generated voltage out of tolerance
Uncorrectable ECC Error
2Fh
35h, 36h
11h
18h
Corrected ECC Error
05h, 30-34h, 37h, 3Eh
Self test or diagnostic failed
ID not found
10h, 14h
3Ah
Spare sectors exhausted
1Fh
0Ch, 38h, 3Bh, 3Ch, 3Fh
03h
Data transfer error / aborted command
Corrupted media format
Write / Erase failed
64/82
SMCxxxAF
CF-ATA command description
9.15
Seek command (7Xh)
This command is effectively a NOP command to the card although it does perform a range
check of cylinder and head or LBA address and returns an error if the address is out of
range. Table 64 shows the Seek command byte sequence.
Table 64. Seek
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
7Xh
Drive
1
LBA
1
Head (LBA 27-24)
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
X (LBA 7-0)
X
X
9.16
Set Features command (EFh)
This command is used by the host to establish or select certain features. Table 65 shows the
Set Features command byte sequence. Table 66 defines all features that are supported.
Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE
mode. If the 01h Feature command is issued all data transfers will occur on the low order
D7D0 data bus and the –IOIS16 signal will not be asserted for data register accesses.
Feature 03h allows the host to select the PIO transfer mode by specifying a value in the
Sector Count register (see Table 67 for values). The upper 5 bits define the type of transfer
and the low order 3 bits encode the mode value. One PIO mode should be selected at all
times. The host may change the selected mode by issuing the Set Features command.
Feature code 9Ah enables the host to configure the card to best meet the host system's
power requirements. The host sets a value in the Sector Count register that is equal to one-
fourth of the desired maximum average current (in mA) that the card should consume. For
example, if the Sector Count register were set to 6, the card would be configured to provide
the best possible performance without exceeding 24 mA. Upon completion of the command,
the card responds to the host with the range of values supported by the card. The minimum
value is set in the Cylinder Low register, and the maximum value is set in the Cylinder Hi
register. The default value, after a power on reset, is to operate at the highest performance
and therefore the highest current mode.
The card will accept values outside this programmable range, but will operate at either the
lowest power or highest performance as appropriate.
65/82
CF-ATA command description
SMCxxxAF
Table 65. Set Features
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
EFh
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
Config
Feature
Table 66. Features supported
Feature
Operation
01h
03h
55h
69h
81h
96h
97h
Enable 8 bit data transfers.
Set transfer mode based on value in Sector Count register.
Disable Read Look Ahead.
NOP Accepted for backward compatibility.
Disable 8 bit data transfer.
NOP accepted for backward compatibility.
Accepted for backward compatibility. Use of this feature is not recommended.
Set the host current source capability. Allows trade-off between current drawn and
read/write speed.
9Ah
Table 67. Transfer mode values
Mode
Bits (7:3)
Bits (2:0)
PIO default mode
00000b
00000b
000b
PIO default mode, disable
IORDY
001b
PIO flow control transfer
mode
00001b
Mode(1)
1. Mode = transfer mode number.
66/82
SMCxxxAF
CF-ATA command description
9.17
Set Multiple mode command (C6h)
This command enables the card to perform Read and Write Multiple operations and
establishes the block count for these commands. The Sector Count register is loaded with
the number of sectors per block. Upon receipt of the command, the card sets BSY and
checks the Sector Count register.
If the Sector Count register contains a valid value and the block count is supported, the
value is loaded for all subsequent Read Multiple and Write Multiple commands and
execution is enabled. If a block count is not supported, an aborted command error is posted,
and Read Multiple and Write Multiple commands are disabled. If the Sector Count register
contains ‘0’ when the command is issued, Read and Write Multiple commands are disabled.
At power-on the default mode is Read and Write Multiple disabled, unless it is disabled by a
Set Feature command. Table 68 defines the Set Multiple Mode command byte sequence.
Table 68. Set Multiple mode
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
C6h
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
Sector Count
X
9.18
Set Sleep mode command (99h or E6h)
This command causes the CompactFlash memory card to set BSY, enter the Sleep mode,
clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply
issuing another command. Sleep mode is also entered when internal timers expire so the
host does not need to issue this command except when it wishes to enter Sleep mode
immediately. The default value for the timer is 5 milliseconds. Note that this time base
(5 ms) is different from the ATA specification. Table 69 defines the Set Sleep mode
command byte sequence.
Table 69. Set Sleep mode
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
99h or E6h
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
67/82
CF-ATA command description
SMCxxxAF
9.19
Standby command (96h or E2)
This command causes the card to set BSY, enter the Sleep mode (which corresponds to the
ATA ‘Standby’ mode), clear BSY and return the interrupt immediately. Recovery from Sleep
mode is accomplished by issuing another command. Table 70 defines the Standby
command byte sequence.
Table 70. Standby
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
96h or E2h
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
9.20
Standby Immediate command (94h or E0h)
This command causes the card to set BSY, enter the Sleep mode (which corresponds to the
ATA Standby mode), clear BSY and return the interrupt immediately.
Recovery from Sleep mode is accomplished by issuing another command. Table 71 defines
the Standby Immediate byte sequence.
Table 71. Standby Immediate
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
94h or E0h
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
68/82
SMCxxxAF
CF-ATA command description
9.21
Translate Sector command (87h)
This command allows the host a method of determining the exact number of times a user
sector has been erased and programmed. The controller responds with a 512-byte buffer of
information containing the desired cylinder, head and sector, including its logical address,
and the hot count, if available, for that sector. Table 72 defines the Translate Sector
command byte sequence. Table 73 represents the information in the buffer.
Table 72. Translate Sector
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
87h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
X
X
Table 73. Translate Sector information
Address
Information
00h-01h
02h
Cylinder MSB (00), Cylinder LSB (01)
Head
03h
Sector
04-06h
07-12h
13h
LBA MSB (04) - LSB (06)
Reserved
Erased Flag (FFh) = Erased; 00h = Not Erased
14h-17h
18h-1Ah
1Bh-1FFh
Reserved
Hot Count MSB (18) - LSB (1A); 0 = Hot Count not supported
Reserved
69/82
CF-ATA command description
SMCxxxAF
9.22
Wear Level command (F5h)
This command is effectively a NOP command and only implemented for backward
compatibility. The Sector Count register will always be returned with a 00h indicating Wear
Level is not needed.
Table 74 defines the Wear Level command byte sequence.
Table 74. Wear Level
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
F5h
X
Drive
Flag
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
Completion Status
X
9.23
Write Buffer command (E8h)
The Write Buffer command enables the host to overwrite contents of the card’s sector buffer
with any data pattern desired. This command has the same protocol as the Write Sector(s)
command and transfers 512 bytes.
Table 75 defines the Write Buffer command byte sequence.
Table 75. Write Buffer
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
E8h
X
Drive
X
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
X
X
X
X
X
70/82
SMCxxxAF
CF-ATA command description
9.24
Write Multiple command (C5h)
This command is similar to the Write Sectors command. The card sets BSY within 400 ns of
accepting the command. Interrupts are not presented on each sector but on the transfer of a
block which contains the number of sectors defined by Set Multiple. Command execution is
identical to the Write Sectors operation except that the number of sectors defined by the Set
Multiple command is transferred without intervening interrupts.
DRQ qualification of the transfer is required only at the start of the data block, not on each
sector. The block count of sectors to be transferred without intervening interrupts is
programmed by the Set Multiple Mode command, which must be executed prior to the Write
Multiple command.
When the Write Multiple command is issued, the Sector Count register contains the number
of sectors (not the number of blocks or the block count) requested. If the number of
requested sectors is not evenly divisible by the sector/block, as many full blocks as possible
are transferred, followed by a final, partial block transfer. The partial block transfer is for n
sectors, where:
n = (sector count) module (block count).
If the Write Multiple command is attempted before the Set Multiple Mode command has
been executed or when Write Multiple commands are disabled, the Write Multiple operation
will be rejected with an aborted command error.
Errors encountered during Write Multiple commands are posted after the attempted writes
of the block or partial block transferred. The Write command ends with the sector in error,
even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an
error. Interrupts are generated when DRQ is set at the beginning of each block or partial
block.
The Command Block registers contain the cylinder, head and sector number of the sector
where the error occurred and the Sector Count register contains the residual number of
sectors that need to be transferred for successful completion of the command. For example,
each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third
sector. The Sector Count register contains 6 and the address is that of the third sector.
Note: The current revision of the CompactFlash memory card only supports a block count of
1 as indicated in the Identify Drive command information. The Write Multiple command is
provided for compatibility with future products which may support a larger block count.
Table 76 defines the Write Multiple command byte sequence.
Table 76. Write Multiple
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
C5h
1
LBA
1
Drive
Head
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High
Cylinder Low
Sector Number
Sector Count
X
71/82
CF-ATA command description
SMCxxxAF
9.25
Write Multiple without Erase command (CDh)
This command is similar to the Write Multiple command with the exception that an implied
erase before write operation is not performed. The sectors should be pre-erased with the
Erase Sector(s) command before this command is issued. Table 77 defines the Write
Multiple without Erase command byte sequence.
Table 77. Write Multiple without Erase
Bit
7
6
5
4
3
2
1
0
Command (7)
CDh
Driv
e
C/D/H (6)
X
LBA
1
Head
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High
Cylinder Low
Sector Number
Sector Count
X
9.26
Write Sector(s) command (30h or 31h)
This command writes from 1 to 256 sectors as specified in the Sector Count register. A
sector count of zero requests 256 sectors. The transfer begins at the sector specified in the
Sector Number register. When this command is accepted, the Card sets BSY, sets DRQ
and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No
interrupt is generated to start the first host transfer operation. No data should be transferred
by the host until BSY has been cleared by the host.
For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ
will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an
interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is
cleared. It will remain in this state until the command is completed at which time BSY is
cleared and an interrupt is generated. If an error occurs during a write of more than one
sector, writing terminates at the sector where the error occurred. The Command Block
registers contain the cylinder, head and sector number of the sector where the error
occurred. The host may then read the command block to determine what error has
occurred, and on which sector. Table 78 defines the Write Sector(s) command byte
sequence.
Table 78. Write Sector(s)
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
30h or 31h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
X
72/82
SMCxxxAF
CF-ATA command description
9.27
Write Sector(s) without Erase command (38h)
This command is similar to the Write Sector(s) command with the exception that an implied
erase before write operation is not performed. This command has the same protocol as the
Write Sector(s) command. The sectors should be pre-erased with the Erase Sector(s)
command before this command is issued. If the sector is not pre-erased a normal write
sector operation will occur. Table 79 defines the Write Sector(s) without Erase command
byte sequence.
M
Table 79. Write Sector(s) without Erase
Bit
7
6
5
4
3
2
1
0
Command (7)
38h
LB
A
C/D/H (6)
1
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
X
9.28
Write Verify command (3Ch)
This command is similar to the Write Sector(s) command, except each sector is verified
immediately after being written. This command has the same protocol as the Write Sector(s)
command. Table 80 defines the Write Verify command byte sequence.
Table 80. Write Verify
Bit
7
6
5
4
3
2
1
0
Command (7)
C/D/H (6)
3Ch
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cyl Low (4)
Sect Num (3)
Sect Cnt (2)
Feature (1)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
X
73/82
CIS information (typical)
SMCxxxAF
10
CIS information (typical)
--------
0000: Code 01, link 04
DF 79 01 FF
--------
–
–
–
–
–
–
Tuple CISTPL_DEVICE (01), length 4 (04)
Device type is FUNCSPEC
Extended speed byte used
Device speed is 80 ns
Write protect switch is not in control
Device size is 2 Kbytes
--------
000C: Code 1C, link 05
02 DF 79 01 FF
--------
–
–
–
–
–
–
–
Tuple CISTPL_DEVICE_OC (1C), length 5 (05)
Device conditions: V = 3.3 V
CC
Device type is FUNCSPEC
Extended speed byte used
Device speed is 80 ns
Write protect switch is not in control
Device size is 2 Kbytes
--------
001A: Code 18, link 02
DF 01
--------
–
–
Tuple CISTPL_JEDEC_C (18), length 2 (02)
Device 0 JEDEC id: Manufacturer DF, ID 01
--------
0022: Code 20, link 04
0A 00 00 00
--------
– Tuple CISTPL_MANFID (20), length 4 (04)
– Manufacturer # 0x000A hardware rev 0.00
--------
002E: Code 15, link 12
04 01 53 54 4D 00 53 54 4D 2D x x x x 42 00
00 FF
74/82
SMCxxxAF
CIS information (typical)
--------
–
–
–
–
Tuple CISTPL_VERS_1 (15), length 18 (12)
Major version 4, minor version 1
Product Information: Manufacturer: "STM",
Product name: "STM-xxxxB"
--------
0056: Code 21, link 02
04 01
--------
–
–
Tuple CISTPL_FUNCID (21), length 2 (02)
Function code 04 (Fixed Disk), system init 01
--------
005E: Code 22, link 02
01 01
--------
–
–
Tuple CISTPL_FUNCE (22), length 2 (02)
This is a PC Card ATA Disk
--------
0066: Code 22, link 03
02 0C 0F
--------
–
–
–
–
–
–
–
–
–
Tuple CISTPL_FUNCE (22), length 3 (03)
is not required
V
PP
This is a silicon device
Identify drive model/serial number is guaranteed unique
Low-power modes supported: Sleep Standby Idle
Drive automatically minimizes power
All modes include 3F7 or 377
Index bit is not supported
-IOIS16 is unspecified in twin configurations
--------
0070: Code 1A, link 05
01 03 00 02 0F
75/82
CIS information (typical)
SMCxxxAF
--------
–
–
–
–
–
–
–
Tuple CISTPL_CONFIG (1A), length 5 (05)
Last valid configuration index is 3
Configuration register base address is 200
Configuration registers present: configuration option register at 200
Card configuration and Status register at 202
Pin Replacement register at 204
Socket and Copy register at 206
--------
007E: Code 1B, link 08
C0 C0 A1 01 55 08 00 20
--------
–
–
–
–
–
–
–
–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 8 (08)
Configuration table index is 00 (default)
Interface type is memory
BVDs not active, WP not active, RdyBsy active
Wait signal support required
V
Power Description: Nom V = 5.0 V
CC
map 2048 bytes of memory to card address 0
Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
--------
0092: Code 1B, link 06
00 01 21 B5 1E 4D
--------
–
–
–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06)
Configuration table index is 00
power description: Nom V = 3.30 V, Peak I = 45.0 mA
V
CC
--------
00A2: Code 1B, link 0A
C1 41 99 01 55 64 F0 FF FF 20
--------
–
–
–
–
–
–
–
–
–
–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 10 (0A)
Configuration table index is 01 (default)
Interface type is I/O
BVDs not active, WP not active, RdyBsy active
Wait signal support not required
V
power description: Nom V = 5.0 V
CC
Decode 4 I/O lines, bus size 8 or 16
IRQ may be shared, pulse and level mode interrupts are supported
Interrupts in mask FFFF are supported
Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
76/82
SMCxxxAF
CIS information (typical)
--------
00BA: Code 1B, link 06
01 01 21 B5 1E 4D
--------
–
–
–
–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06)
Configuration Table Index is 01
power description: Nom V = 3.30 V,
V
CC
Peak I = 45.0 mA
--------
00CA: Code 1B, link 0F
C2 41 99 01 55 EA 61 F0 01 07 F6 03 01 EE 20
--------
–
–
–
–
–
–
–
–
–
–
–
–
–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F)
Configuration Table Index is 02 (default)
Interface type is I/O
BVDs not active, WP not active, RdyBsy active
Wait signal support not required
V
power description:
CC
Nom V = 5.0 V
Decode 10 I/O lines, bus size 8 or 16
I/O block at 01F0, length 8
I/O block at 03F6, length 2
IRQ may be shared, pulse and level mode interrupts are supported
Only IRQ14 is supported
Miscellaneous features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
--------
00EC: Code 1B, link 06
02 01 21 B5 1E 4D
--------
–
–
–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06)
Configuration table index is 02
power description: Nom V = 3.30 V, Peak I = 45.0 mA
V
CC
--------
00FC: Code 1B, link 0F
C3 41 99 01 55 EA 61 70 01 07 76 03 01 EE 20
77/82
CIS information (typical)
SMCxxxAF
--------
–
–
–
–
–
–
–
–
–
–
–
–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F)
Configuration table index is 03 (default)
Interface type is I/O
BVDs not active, WP not active, RdyBsy active
Wait signal support not required
V
power description: Nom V = 5.0 V
CC
Decode 10 I/O lines, bus size 8 or 16
I/O block at 0170, length 8
I/O block at 0376, length 2
IRQ may be shared, pulse and level mode interrupts are supported
Only IRQ14 is supported
Miscellaneous features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
--------
011E: Code 1B, link 06
03 01 21 B5 1E 4D
--------
–
–
–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06)
Configuration table index is 03
power description: Nom V = 3.30 V, Peak I = 45.0 mA
V
CC
--------
012E: Code 14, link 00
--------
–
Tuple CISTPL_NO_LINK (14), length 0 (00)
--------
0134: Code FF
--------
–
Tuple CISTPL_END (FF)
78/82
SMCxxxAF
Package mechanical
11
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
second-level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.numonyx.com.
Figure 9.
Type I CompactFlash memory card dimensions
1.60mm ± 0.5
(0.063in ± 0.002)
26
1
50
0.99mm± 0.05
(0.039in ± 0.002)
25
1.01mm ± 0.07
(0.039in ± 0.003)
3.30mm ± 0.10
(0.130in ± 0.004)
1.01mm ± 0.07
(0.039in ± 0.003)
2.44mm ± 0.07
(0.096in ± 0.003)
Optional
Configuration
(see note)
2.15mm ± 0.07
(0.085in ± 0.003)
0.76mm ± 0.07
(0.030in ± 0.003)
1.65mm
(0.130in)
41.66mm ± 0.13
(1.640in ± 0.005)
0.63mm ± 0.07
(0.025in ± 0.003)
42.80mm ± 0.10
(1.685in ± 0.004)
4X R 0.5mm ± 0.1
(4X R 0.020in ± 0.004)
AI04301b
79/82
Ordering information
SMCxxxAF
12
Ordering information
Table 81. Ordering information scheme
Example:
SMC
256
A
F
Y
6
E
Memory card standard
SMC = Storage Medium, CompactFlash
Density
032 = 32 Mbytes
064 = 64 Mbytes
128 = 128 Mbytes
256 = 256 Mbytes
512 = 512 Mbytes
Options of the standard
A = CF type I
Memory type
F = Flash memory
Card Version
Y= Version depending on device technology
Temperature range
6 = -40 to 85 °C
Packing
Blank = Standard packing (tray)
E = ECOPACK package, standard packing (tray)
Note:
Other digits may be added to the ordering code for preprogrammed parts or other options.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For further information on any aspect of the device, please contact your nearest Numonyx
Sales Office.
80/82
SMCxxxAF
Revision history
13
Revision history
Table 82. Document revision history
Date
Revision
Changes
22-Sep-2006
1
Initial release.
ECOPACK text added in Section 11: Package mechanical.
Minor text changes.
14-Nov-2007
12-Dec-2007
2
3
Applied Numonyx branding.
81/82
SMCxxxAF
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx B.V. All Rights Reserved.
82/82
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