TE28F256P33B95A [NUMONYX]
Flash, 16MX16, 95ns, PDSO56, 14 X 20 MM, TSOP-56;
| 型号： | TE28F256P33B95A |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 16MX16, 95ns, PDSO56, 14 X 20 MM, TSOP-56 光电二极管 内存集成电路 |
| 文件： | 总88页 (文件大小：942K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Numonyx® AxcellTM Flash Memory (P33-
65nm)
256-Mbit, 512-Mbit (256M/256M)
Datasheet
Product Features
High performance:
Security:
— 95ns initial access time for Easy BGA
— 105ns initial access time for TSOP
— 25ns 16-word asynchronous-page read
mode
— 52MHz (Easy BGA) with zero wait states,
17ns clock-to-data output synchronous-
burst read mode
— 4-, 8-, 16-, and continuous-word options
for burst mode
— One-Time Programmable Registers:
— 64 unique factory device identifier bits
— 2112 user-programmable OTP bits
— Absolute write protection: VPP = VSS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down capability
— Password Access feature
Software:
— Buffered Enhanced Factory Programming at
2.0MByte/s (typ) using 512-word buffer
— 3.0V buffered programming at 1.14 MByte/
s (Typ) using 512-word buffer
— 25µs (Typ) program suspend
— 25µs (Typ) erase suspend
— Numonyx™ Flash Data Integrator optimized
— Basic Command Set and Extended Function
Interface Command Set compatible
— Common Flash Interface capable
Architecture:
— Multi-Level Cell Technology: Highest
Density at Lowest Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte main blocks
— Blank Check to verify an erase block
Density and Packaging
— 56-Lead TSOP package (256-Mbit only)
— 64-Ball Easy BGA package (256, 512-Mbit)
— 16-bit wide data bus
Quality and Reliability
Voltage and Power:
— JESD47E Compliant
— VCC (core) voltage: 2.3 V – 3.6 V
— VCCQ (I/O) voltage: 2.3 V – 3.6 V
— Standby current: 65uA (Typ) for 256-Mbit
— Continuous synchronous read current: 21
mA (Typ)/24 mA (Max) at 52 MHz
— Operating temperature: –40 °C to +85 °C
— Minimum 100,000 erase cycles per block
— 65nm ETOX™ X process technology
Datasheet
1
Mar 2010
Order Number: 320003-09
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and Axcell are trademarks or registered trademarks of Numonyx, B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2010, Numonyx, B.V., All Rights Reserved.
Datasheet
2
Mar 2010
Order Number: 320003-09
P33-65nm
Contents
1.0 Functional Description...............................................................................................5
1.1
1.2
1.3
1.4
Introduction .......................................................................................................5
Overview ...........................................................................................................5
Virtual Chip Enable Description..............................................................................6
Memory Maps .....................................................................................................7
2.0 Package Information.................................................................................................8
2.1
2.2
56-Lead TSOP.....................................................................................................8
64-Ball Easy BGA Package....................................................................................9
3.0 Ballouts................................................................................................................... 11
4.0 Signals .................................................................................................................... 13
4.1
Dual-Die Configurations ..................................................................................... 14
5.0 Bus Operations........................................................................................................ 15
5.1
5.2
5.3
5.4
5.5
Read ............................................................................................................... 15
Write............................................................................................................... 15
Output Disable.................................................................................................. 15
Standby........................................................................................................... 16
Reset............................................................................................................... 16
6.0 Command Set .......................................................................................................... 17
6.1
6.2
Device Command Codes..................................................................................... 17
Device Command Bus Cycles .............................................................................. 18
7.0 Read Operation........................................................................................................ 21
7.1
7.2
7.3
7.4
Asynchronous Page-Mode Read........................................................................... 21
Synchronous Burst-Mode Read............................................................................ 21
Read Device Identifier........................................................................................ 22
Read CFI.......................................................................................................... 22
8.0 Program Operation.................................................................................................. 23
8.1
8.2
8.3
8.4
8.5
8.6
Word Programming ........................................................................................... 23
Buffered Programming....................................................................................... 23
Buffered Enhanced Factory Programming.............................................................. 24
Program Suspend.............................................................................................. 26
Program Resume............................................................................................... 27
Program Protection............................................................................................ 27
9.0 Erase Operation....................................................................................................... 28
9.1
9.2
9.3
9.4
9.5
Block Erase ...................................................................................................... 28
Blank Check ..................................................................................................... 28
Erase Suspend.................................................................................................. 29
Erase Resume................................................................................................... 29
Erase Protection................................................................................................ 29
10.0 Security................................................................................................................... 30
10.1 Block Locking.................................................................................................... 30
10.2 Selectable OTP Blocks........................................................................................ 32
10.3 Password Access ............................................................................................... 32
11.0 Status Register........................................................................................................ 33
11.1 Read Configuration Register................................................................................ 34
11.2 One-Time Programmable (OTP) Registers............................................................. 40
12.0 Power and Reset Specifications............................................................................... 43
Datasheet
3
Mar 2010
Order Number: 320003-09
P33-65nm
12.1 Power-Up and Power-Down.................................................................................43
12.2 Reset Specifications ...........................................................................................43
12.3 Power Supply Decoupling....................................................................................44
13.0 Maximum Ratings and Operating Conditions ............................................................45
13.1 Absolute Maximum Ratings .................................................................................45
13.2 Operating Conditions..........................................................................................45
14.0 Electrical Specifications ...........................................................................................46
14.1 DC Current Characteristics..................................................................................46
14.2 DC Voltage Characteristics..................................................................................47
15.0 AC Characteristics....................................................................................................48
15.1 AC Test Conditions.............................................................................................48
15.2 Capacitance ......................................................................................................49
15.3 AC Read Specifications .......................................................................................49
15.4 AC Write Specifications.......................................................................................54
15.5 Program and Erase Characteristics .......................................................................58
16.0 Ordering Information...............................................................................................59
16.1 Discrete Products...............................................................................................59
16.2 SCSP Products...................................................................................................60
A
Supplemental Reference Information.......................................................................61
A.1
A.2
A.3
Common Flash Interface.....................................................................................61
Flowcharts........................................................................................................72
Write State Machine...........................................................................................81
B
C
Conventions - Additional Documentation .................................................................87
B.1
B.2
Acronyms .........................................................................................................87
Definitions and Terms ........................................................................................87
Revision History.......................................................................................................89
Datasheet
4
Mar 2010
Order Number: 320003-09
P33-65nm
1.0
Functional Description
1.1
Introduction
This document provides information about the Numonyx® Axcell™ Flash Memory (P33-
65nm) device and describes its features, operations, and specifications.
P33-65nm is the latest generation of Numonyx® Axcell™ Flash Memory (P33-65nm)
devices. P33-65nm device will be offered in 64-Mbit up through 2-Gbit densities. This
document covers specifically 256-Mbit and 512-Mbit (256M/256M) product information.
Benefits include more density in less space, high-speed interface NOR device, and
support for code and data storage. Features include high-performance synchronous-
burst read mode, fast asynchronous access times, low power, flexible security options,
and two industry-standard package choices.
P33-65nm is manufactured using Numonyx™ 65nm process technology.
1.2
Overview
This family of devices provides high performance at low voltage on a 16-bit data bus.
Individually erasable memory blocks are sized for optimum code and data storage.
Upon initial power-up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the RCR enables synchronous burst-mode reads. In
synchronous burst mode, output data is synchronized with a user-supplied clock signal.
A WAIT signal provides an easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast factory program and erase operations. Designed for low-
voltage systems, the P33 Family Flash memory supports read operations with VCC at
3.0V, and erase and program operations with VPP at 3.0V or 9.0V. Buffered Enhanced
Factory Programming provides the fastest flash array programming performance with
VPP at 9.0V, which increases factory throughput. With VPP at 3.0V, VCC and VPP can be
tied together for a simple, ultra low power design. In addition to voltage flexibility, a
dedicated VPP connection provides complete data protection when VPP ≤ VPPLK
.
The Command User Interface is the interface between the system processor and all
internal operations of the device. An internal Write State Machine automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each
erase operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations. Data is
programmed in word increments (16 bits).
The P33 Family Flash memory one-time-programmable (OTP) register allows unique
flash device identification that can be used to increase system security. The individual
Block Lock feature provides zero-latency block locking and unlocking. The P33-65nm
device adds enhanced protection via Password Access Mode which allows user to
protect write and/or read access to the defined blocks. In addition, the P33 Family
Flash memory may also provide the OTP permanent lock feature backward compatible
to the P33-130nm device.
Datasheet
5
Mar 2010
OrderNumber:320003-09
P33-65nm
1.3
Virtual Chip Enable Description
The 512-Mbit P33 Family Flash memory employs a Virtual Chip Enable which combines
two 256-Mbit die with a common chip enable, CE# for Easy BGA packages. Address
A25 is then used to select between the die pair with CE# asserted, depending upon the
package option used. When chip enable is asserted and A25 is low (VIL), The lower
parameter die is selected; when chip enable is asserted and A25 is high (VIH), the
upper parameter die is selected.
Table 1:
Flash Die Virtual Chip Enable Truth Table for 512 Mbit Easy BGA Package
Die Selected
CE#
A25
Lower Param Die
Upper Param Die
L
L
L
H
Datasheet
6
Mar 2010
Order Number: 320003-09
P33-65nm
1.4
Memory Maps
Figure 1: P33-65nm Memory Map
A<24:1> 256 Mbit
:
A<24:1> 256 Mbit
16- Kword Block 258
FFC 000– FFFFFF
FF 8000– FFBFFF
FF 4000– FF7 FFF
FF 0000– FF3 FFF
FF 0000 - FFFFFF
64- Kword Block
258
16- Kword Block
16- Kword Block
257
256
16- Kword Block 255
64- Kword Block 254
FE 0000– FEFFFF
64- Kword Block 130
64- Kword Block 66
7F 0000 - 7FFFFF
3 F0000 - 3FFFFF
020000 – 02 FFFF
010000 – 01 FFFF
64- Kword Block
64- Kword Block
5
4
3
00C000 – 00 FFFF
16- Kword Block
16- Kword Block
16- Kword Block
16- Kword Block
008000– 00 BFFF
004000 – 007FFF
2
1
64- Kword Block
64- Kword Block
1
0
010000 – 01 FFFF
000000 – 00 FFFF
0
000000 – 003FFF
Bottom Boot 256 Mbit
Word Wide (x16) Mode
Top Boot 256 Mbit
Word Wide (x16) Mode
A<25:1> 512 Mbit (256/256)
1FFC000 - 1FFFFFF
16- Kword Block 517
516
16- Kword Block
1FF8000 - 1FFBFFF
1FF4000 - 1FF7FFF
1FF0000 - 1FF3FFF
16- Kword Block 515
16- Kword Block 514
1FE0000 - 1FEFFFF
1FD0000 - 1FDFFFF
64- Kword Block 513
512
64- Kword Block
0020000 - 002FFFF
0010000 - 001FFFF
64- Kword Block
64- Kword Block
5
4
000C000 - 000FFFF
0008000 - 000BFFF
0004000 - 0007FFF
0000000 - 0003FFF
16- Kword Block
16- Kword Block
16- Kword Block
16- Kword Block
3
2
1
0
512 Mbit (256/256)
Word Wide (x16) Mode
Datasheet
7
Mar 2010
OrderNumber:320003-09
P33-65nm
2.0
Package Information
2.1
56-Lead TSOP
Figure 2: TSOP Mechanical Specifications (256-Mbit)
Z
A
2
See Note 2
See Notes 1 and 3
Pin 1
e
See Detail B
E
Y
D
1
A
1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
0
b
L
Table 2:
TSOP Package Dimensions (Sheet 1 of 2)
Millimeters
Inches
Nom
Product Information
Symbol
Note
Min
Nom
Max
Min
Max
Package Height
Standoff
A
-
-
1.200
-
-
-
0.047
-
A
A
0.050
0.965
0.100
0.100
18.200
13.800
-
-
0.002
0.038
0.004
0.004
0.717
0.543
-
-
1
2
Package Body Thickness
Lead Width
0.995
0.150
0.150
18.400
14.000
0.500
20.00
0.600
1.025
0.200
0.200
18.600
14.200
-
0.039
0.006
0.006
0.724
0.551
0.0197
0.787
0.024
0.040
0.008
0.008
0.732
0.559
-
b
Lead Thickness
Package Body Length
Package Body Width
Lead Pitch
c
D
Note
Note
1
E
e
Terminal Dimension
Lead Tip Length
D
L
19.800
0.500
20.200
0.700
0.780
0.020
0.795
0.028
Datasheet
8
Mar 2010
Order Number: 320003-09
P33-65nm
Table 2:
TSOP Package Dimensions (Sheet 2 of 2)
Millimeters
Inches
Nom
Product Information
Symbol
Note
Min
Nom
Max
Min
Max
Lead Count
N
θ
-
0°
56
3°
-
-
0°
56
3°
-
Lead Tip Angle
5°
5°
Seating Plane Coplanarity
Lead to Package Offset
Notes:
Y
Z
-
-
0.100
0.350
-
-
0.004
0.014
0.150
0.250
0.006
0.010
1.
2.
3.
One dimple on package denotes Pin 1.
If two dimples, then the larger dimple denotes Pin 1.
Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
2.2
64-Ball Easy BGA Package
Figure 3: Easy BGA Mechanical Specifications (256-Mbit, 512-Mbit)
Ball A1
Ball A1
Corner
Corner
D
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
F
A
B
C
D
E
F
b
e
E
G
H
G
H
Top View - Ball side down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Note: Drawing not to scale
Datasheet
9
Mar 2010
OrderNumber:320003-09
P33-65nm
Table 3:
Easy BGA Package Dimensions
Millimeters
Nom
Inches
Nom
Product Information
Symbol
Notes
Min
Max
Min
Max
Package Height
A
A1
A2
b
-
0.250
-
-
1.200
-
-
-
0.0472
-
Ball Height
-
0.0098
-
-
Package Body Thickness
Ball (Lead) Width
0.780
0.430
10.000
13.000
1.000
64
-
0.0307
0.0169
0.3937
0.5118
0.0394
64
-
0.330
9.900
12.900
-
0.530
10.100
13.100
-
0.0130
0.3898
0.5079
-
0.0209
0.3976
0.5157
-
Package Body Width
Package Body Length
Pitch
D
Note
Note
E
[e]
N
Ball (Lead) Count
-
-
-
-
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
Y
-
-
0.100
1.600
3.100
-
-
0.0039
0.0630
0.1220
S1
S2
1.400
2.900
1.500
3.000
0.0551
0.1142
0.0591
0.1181
Note
Note
Note: Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology http://
developer.numonyx.com/design/flash/packtech.
Datasheet
10
Mar 2010
Order Number: 320003-09
P33-65nm
3.0
Ballouts
Figure 4: 56-Lead TSOP Pinout (256-Mbit)
WAIT
A17
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
A16
A15
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
ADV#
CLK
RST#
VPP
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE#
A14
A13
A12
A11
A10
A9
A23
A22
A21
VSS
VCC
WE#
WP#
A20
A19
A18
A8
A7
A6
A5
A4
A3
A2
A24
RFU
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Numonyx®
Axcell™Flash Memory (P33)
56-Lead TSOP Pinout
14 mm x 20 mm
Top View
VSS
CE#
A1
Notes:
1.
2.
3.
4.
A1 is the least significant address bit.
A24 is valid for 256-Mbit densities; otherwise, it is a no connect (NC).
No Internal Connection on VCC Pin 13; it may be driven or floated. For legacy designs, pin can be tied to Vcc.
One dimple on package denotes Pin 1, which will always be in the upper left corner of the package, in reference to the
product mark.
Datasheet
11
Mar 2010
OrderNumber:320003-09
P33-65nm
Figure 5: 64-Ball Easy BGA Ballout (256-Mbit, 512-Mbit)
5
8
8
5
1
2
3
4
6
7
7
6
4
3
2
1
A
A
B
C
D
E
A1
A2
A3
A4
A6
VSS
A7
A8
VPP A13 VCC A18 A22
A22 A18 VCC A13
VPP
A8
A9
A6
VSS
A7
A1
A2
B
C
D
A9 CE# A14 A25 A19 RFU
A10 A12 A15 WP# A20 A21
A11 RST# VCCQ VCCQ A16 A17
RFU A19 A25 A14 CE#
A21 A20 WP# A15 A12 A10
A17 A16 VCCQ VCCQ RST# A11
A3
A5
A5
A4
E
F
DQ8 DQ1 DQ9 DQ3 DQ4 CLK DQ15 RFU
RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE#
A23 RFU DQ2 VCCQ DQ5 DQ6 DQ14 WE#
RFU DQ15 CLK DQ4 DQ3 DQ9 DQ1
DQ8
F
OE# WAIT ADV# DQ12 DQ11 DQ10 DQ0 RFU
WE# DQ14 DQ6 DQ5 VCCQ DQ2 RFU A23
G
G
H
H
RFU VSS VCC VSS DQ13 VSS DQ7 A24
A24 DQ7 VSS DQ13 VSS VCC VSS RFU
Easy BGA
Easy BGA
Top View- Ball side down
Bottom View- Ball side up
Notes:
1.
2.
3.
4.
A1 is the least significant address bit.
A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect.
A25 is valid for 512-Mbit densities; otherwise, it is a no connect.
One dimple on package denotes A1 Pin, which will always be in the upper left corner of the package, in reference to the
product mark.
Datasheet
12
Mar 2010
Order Number: 320003-09
P33-65nm
4.0
Signals
Table 4:
TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)
Symbol
Type
Name and Function
ADDRESS INPUTS: Device address inputs. 256-Mbit: A[24:1]; 512-Mbit: A[25:1]. Note: The
A[MAX:1]
DQ[15:0]
Input
virtual selection of the 256-Mbit “Top parameter” die in the dual-die 512-Mbit configuration is
accomplished by setting A25 high (V ).
IH
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
reads of memory, status register, OTP register, and read configuration register. Data balls float when
the CE# or OE# are deasserted. Data is internally latched during writes.
Input/
Output
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#
Input
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted,
flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
CE#
CLK
Input
Input
WARNING: All chip enables must be high when device is not in use.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
OE#
Input
Input
cycles. OE# high places the data outputs and WAIT in High-Z.
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
RST#
WAIT: Indicates data valid in synchronous array or non-array burst reads. RCR[10], (WT)
determines its polarity when asserted. WAIT’s active output is V or V
when CE# and OE# are
OL
OH
V . WAIT is high-Z if CE# or OE# is V
.
IL
IH
WAIT
Output
•
In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
•
In asynchronous page mode, and all write modes, WAIT is deasserted.
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WE#
WP#
Input
Input
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when VPP ≤ V
voltages should not be attempted.
. Block erase and program at invalid VPP
PPLK
Set VPP = V
for in-system program and erase operations. To accommodate resistor or diode drops
PPL
Power/
Input
VPP
from the system supply, the V level of VPP can be as low as V
min. VPP must remain above V
IH
PPL PPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
PPH
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
VCC
Power
when VCC ≤ V
. Operations at invalid VCC voltages should not be attempted.
LKO
VCCQ
VSS
Power
Power
OUTPUT POWER SUPPLY: Output-driver source voltage.
GROUND: Connect to system ground. Do not float any VSS connection.
Datasheet
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Mar 2010
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P33-65nm
Table 4:
TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)
Symbol
Type
Name and Function
RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and
enhancement. These should be treated in the same way as a Don’t Use (DU) signal.
RFU
—
DU
NC
—
—
DON’T USE: Do not connect to any other signal, or power supply; must be left floating.
NO CONNECT: No internal connection; can be driven or floated.
4.1
Dual-Die Configurations
Figure 6: 512-Mbit Easy BGA Block Diagram
Easy BGA 512-Mbit (Dual-Die) Configuration
CE#
Top Param Die
(256-Mbit)
RST#
VCC
VPP
WP#
OE#
WE#
VCCQ
VSS
CLK
ADV#
Bottom Param Die
(256-Mbit)
DQ[15:0]
WAIT
A[MAX:1]
Note:
Amax = VIH selects the Top parameter Die; Amax = VIL selects the Bottom Parameter
Die.
Datasheet
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Mar 2010
Order Number: 320003-09
P33-65nm
5.0
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE#
and RST# must be VIH; CE# must be VIL).
Bus cycles to/from the P33-65nm device conform to standard microprocessor bus
operations. Table 5, “Bus Operations Summary”summarizes the bus operations and the
logic levels that must be applied to the device control signal inputs.
Table 5:
Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0] Notes
Asynchronous
Synchronous
V
V
V
V
V
X
L
L
L
L
L
L
H
H
L
Output
Output
IH
Deasserted
Driven
Read
Write
Running
IH
IH
IH
IH
X
X
X
X
L
L
H
H
X
X
High-Z
High-Z
High-Z
High-Z
Input
High-Z
High-Z
High-Z
1
2
Output Disable
Standby
Reset
X
X
X
L
H
X
X
H
X
2
V
2,3
IL
Notes:
1.
Refer to the Table 7, “Command Bus Cycles” on page 19 for valid DQ[15:0] during a write
operation.
2.
3.
X = Don’t Care (H or L).
RST# must be at V ± 0.2 V to meet the maximum specified power-down current.
SS
5.1
5.2
Read
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
Write
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 7, “Command Bus Cycles” on page 19
shows the bus cycle sequence for each of the supported device commands, while
Table 6, “Command Codes and Definitions” on page 17 describes each command. See
Section 15.0, “AC Characteristics” on page 48 for signal-timing details.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
5.3
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
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5.4
5.5
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5 μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
Numonyx allow proper CPU initialization following a system reset through the use of the
RST# input. RST# should be controlled by the same low-true reset signal that resets
the system CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array mode,
and the Status Register is set to 0x80. Asserting RST# de-energizes all internal
circuits, and places the output drivers in High-Z. When RST# is asserted, the device
shuts down the operation in progress, a process which takes a minimum amount of
time to complete. When RST# has been deasserted, the device is reset to
asynchronous Read Array state.
Note:
If RST# is asserted during a program or erase operation, the operation is terminated
and the memory contents at the aborted location (for a program) or block (for an
erase) are no longer valid, because the data may have been only partially written or
erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a write cycle can be initiated. After this wake-up interval passes, normal
operation is restored. See Section 15.0, “AC Characteristics” on page 48 for details
about signal-timing.
Datasheet
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Mar 2010
Order Number: 320003-09
P33-65nm
6.0
Command Set
6.1
Device Command Codes
The system Central Processing Unit provides control of all in-system read, write, and
erase operations of the device via the system bus. The on-chip WSM manages all block-
erase and word-program algorithms.
Device commands are written to the CUI to control all flash memory device operations.
The CUI does not occupy an addressable memory location; it is the mechanism through
which the flash device is controlled. Table 6 shows valid device command codes and
descriptions.
Table 6:
Command Codes and Definitions (Sheet 1 of 2)
Mode
Code
Device Mode
Read Array
Description
0xFF
Places the device in Read Array mode. Array data is output on DQ[15:0].
Read Status
Register
Places the device in Read Status Register mode. The device enters this mode
after a program or erase command is issued. SR data is output on DQ[7:0].
0x70
0x90
Read Device ID
or Configuration
Register
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status,
or OTP register data on DQ[15:0].
Read
Places the device in Read Query mode. Subsequent reads output Common
Flash Interface information on DQ[7:0].
0x98
0x50
Read Query
Clear Status
Register
The WSM can only set SR error bits. The Clear Status Register command is
used to clear the SR error bits.
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. CE# or ADV# must be toggled to
update the SR Data for synchronous Non-array reads. The Read Array
command must be issued to read array data after programming has finished.
Word Program
Setup
0x40
This command loads a variable number of words up to the buffer size of 512
words onto the program buffer.
0xE8
0xD0
Buffered Program
Write
The confirm command is Issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, writing the data from the buffer to the flash memory array.
Buffered Program
Confirm
First cycle of a 2-cycle command; initiates the BEFP mode. The CUI then
waits for the BEFP Confirm command, 0xD0, that initiates the BEFP
algorithm. All other commands are ignored when BEFP mode begins.
0x80
0xD0
BEFP Setup
If the previous command was BEFP Setup (0x80), the CUI latches the
address and data, and prepares the device for BEFP mode.
BEFP Confirm
First cycle of a 2-cycle command; prepares the CUI for a block-erase
operation. The WSM performs the erase algorithm on the block addressed by
the Erase Confirm command. If the next command is not the Erase Confirm
(0xD0) command, the CUI sets Status Register bits SR [5,4], and places the
device in Read Status Register mode.
0x20
0xD0
Block Erase Setup
Erase
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During block-
erase operations, the device responds only to Read Status Register and Erase
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
SR Data for synchronous Non-array reads.
Block Erase Confirm
Datasheet
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OrderNumber:320003-09
P33-65nm
Table 6:
Command Codes and Definitions (Sheet 2 of 2)
Mode
Code
Device Mode
Description
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR.2 (program
suspended) or SR 6 (erase suspended), along with SR.7 (ready). The WSM
remains in the suspend mode regardless of control signal states (except for
RST# asserted).
Program or Erase
Suspend
0xB0
Suspend
This command issued to any device address resumes the suspended program
or block-erase operation.
0xD0
0x60
Suspend Resume
Block lock Setup
First cycle of a 2-cycle command; prepares the CUI for block lock
configuration changes. If the next command is not Block Lock (0x01), Block
Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets SR.5 and SR.4,
indicating a command sequence error.
If the previous command was Block Lock Setup (0x60), the addressed block
is locked.
0x01
0xD0
0x2F
Block lock
If the previous command was Block Lock Setup (0x60), the addressed block
is unlocked. If the addressed block is in a lock-down state, the operation has
no effect.
Protection
Unlock Block
Lock-Down Block
If the previous command was Block Lock Setup (0x60), the addressed block
is locked down.
First cycle of a 2-cycle command; prepares the device for a OTP register or
Lock Register program operation. The second cycle latches the register
address and data, and starts the programming algorithm to program data the
the OTP array.
Protection program
setup
0xC0
0x60
0x03
First cycle of a 2-cycle command; prepares the CUI for device read
configuration. If the Set Read Configuration Register command (0x03) is not
the next command, the CUI sets Status Register bits SR.5 and SR.4,
indicating a command sequence error.
Read Configuration
Register Setup
Configuration
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[15:0]to the Read Configuration
Register. Following a Configure RCR command, subsequent read operations
access array data.
Read Configuration
Register
First cycle of a 2-cycle command; initiates the Blank Check operation on a
main block.
0xBC
0xD0
Blank Check
blank check
other
Blank Check
Confirm
Second cycle of blank check command sequence; it latches the block address
and executes blank check on the main array block.
This command is used in extended function interface. first cycle of a multiple-
cycle command second cycle is a Sub-Op-Code, the data written on third
cycle is one less than the word count; the allowable value on this cycle are 0
through 511. The subsequent cycles load data words into the program buffer
at a specified address until word count is achieved.
Extended Function
Interface command
0xEB
6.2
Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the CUI. See
Table 7, “Command Bus Cycles” on page 19. Several commands are used to modify
array data including Word Program and Block Erase commands. Writing either
command to the CUI initiates a sequence of internally-timed functions that culminate in
the completion of the requested task. However, the operation can be aborted by either
asserting RST# or by issuing an appropriate suspend command.
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Table 7:
Command Bus Cycles (Sheet 1 of 2)
First Bus Cycle
Second Bus Cycle
(1)
Bus
Cycles
Mode
Command
(1)
(2)
(2)
Oper
Addr
Data
Oper
Addr
Data
Read Array
1
Write
DnA
DnA
0xFF
-
-
-
Read Device
Identifier
≥ 2
Write
0x90
Read
DBA + IA
ID
Read
Read CFI
≥ 2
2
Write
Write
Write
Write
Write
DnA
DnA
DnA
WA
0x98
0x70
0x50
0x40
0xE8
Read
Read
-
DBA + CFI-A
CFI-D
SRD
-
Read Status Register
Clear Status Register
Word Program
DnA
-
1
2
Write
Write
WA
WA
WD
(3)
Buffered Program
> 2
WA
N - 1
Program
Buffered Enhanced
Factory Program
> 2
Write
WA
0x80
Write
WA
0xD0
(4)
(BEFP)
Erase
Block Erase
2
1
Write
Write
BA
0x20
0xB0
Write
-
BA
-
0xD0
-
Program/Erase
Suspend
DnA
Suspend
Program/Erase
Resume
1
Write
DnA
0xD0
-
-
-
Lock Block
2
2
2
2
Write
Write
Write
Write
BA
BA
0x60
0x60
0x60
0xC0
Write
Write
Write
Write
BA
BA
0x01
0xD0
0x2F
Unlock Block
Lock-down Block
Program OTP register
BA
BA
Protection
PRA
OTP-RA
OTP-D
Program Lock
Register
2
2
Write
Write
LRA
0xC0
0x60
Write
Write
LRA
LRD
Program Read
Configuration Configuration
RCD
RCD
0x03
Register
Datasheet
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Table 7:
Command Bus Cycles (Sheet 2 of 2)
First Bus Cycle
Second Bus Cycle
Bus
Mode
Command
Cycles
(1)
(2)
(1)
(2)
Oper
Addr
Data
Oper
Addr
Data
Blank Check
2
Write
BA
0xBC
Write
BA
D0
Extended Function
Interface
Others
Sub-Op
code
>2
Write
WA
0xEB
Write
WA
(5)
command
Notes:
1.
First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address (NOTE: needed for dual-die 512Mbit device)
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Read CFI address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
OTP-RA = OTP register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[16:1].
ID = Identifier data.
2.
3.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
OTP-D = OTP register data.
LRD = Lock Register data.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
is followed by up to 512 words of data.Then the confirm command (0xD0) is issued, triggering the array programming
operation.
4.
5.
The confirm command (0xD0) is followed by the buffer data.
The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1=< N <=512. The subsequent cycles load
data words into the program buffer at a specified address until word count is achieved, after the data words are loaded,
the final cycle is the confirm cycle 0xD0)
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7.0
Read Operation
The device can be in any of four read states: Read Array, Read Identifier, Read Status
or Read Query. Upon power-up, or after a reset, the device defaults to Read Array
mode. To change the read state, the appropriate read command must be written to the
device (see Section 6.2, “Device Command Bus Cycles” on page 18). The following
sections describe read-mode operations in detail.
The device supports two read modes: asynchronous page mode and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a
reset. The RCR must be configured to enable synchronous burst reads of the flash
memory array (see Section 11.1, “Read Configuration Register” on page 34).
7.1
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read
mode and the device is set to Read Array mode. However, to perform array reads after
any other device operation (e.g. write operation), the Read Array command must be
issued in order to read from the flash memory array.
Note:
Asynchronous page-mode reads can only be performed when RCR.15 is set
The Clear Status Register command clears the status register. It functions independent
of VPP. The WSM sets and clears SR[7,6,2], but it sets bits SR[5,3,1] without clearing
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.
To perform an asynchronous page-mode read, an address is driven onto the address
bus, and CE# and ADV# are asserted. WE# and RST# must already have been
deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven
high to latch the address, or it must be held low throughout the read cycle. CLK is not
used for asynchronous page-mode reads, and is ignored. If only asynchronous reads
are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated
and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial
access time tAVQV delay. (see Section 15.0, “AC Characteristics” on page 48).
In asynchronous page mode, sixteen data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address on the Address bus is driven onto DQ[15:0] after
the initial access delay. The lowest four address bits determine which word of the
16-word page is output from the data buffer at any given time.
7.2
Synchronous Burst-Mode Read
To perform a synchronous burst-read, an initial address is driven onto the address bus,
and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.
ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can
remain asserted throughout the burst access, in which case the address is latched on
the next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay (see Section
11.1.2, “Latency Count” on page 35). Subsequent data is output on valid CLK edges
following a minimum delay. However, for a synchronous non-array read, the same word
of data will be output on successive clock edges until the burst length requirements are
satisfied. Refer to the following waveforms for more detailed information:
• Figure 20, “Synchronous Single-Word Array or Non-array Read Timing” on page 53
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• Figure 21, “Continuous Burst Read, showing an Output Delay Timing” on page 53
• Figure 22, “Synchronous Burst-Mode Four-Word Read Timing” on page 54
7.3
Read Device Identifier
The Read Device Identifier command instructs the device to output manufacturer code,
device identifier code, block-lock status, OTP register data, or configuration register
data (see Section 6.2, “Device Command Bus Cycles” on page 18 for details on issuing
the Read Device Identifier command). Table 8, “Device Identifier Information” on
page 22 and Table 9, “Device ID codes” on page 22 show the address offsets and data
values for this device.
Table 8:
Device Identifier Information
(1,2)
Item
Address
Data
Manufacturer Code
0x00
0x01
0x89h
ID (see Table 9)
Lock Bit:
Device ID Code
Block Lock Configuration:
• Block Is Unlocked
DQ0 = 0b0
• Block Is Locked
BBA + 0x02
DQ0 = 0b1
• Block Is not Locked-Down
• Block Is Locked-Down
Read Configuration Register
DQ1 = 0b0
DQ1 = 0b1
0x05
DBA + 0x07
0x80
RCR Contents
(3)
General Purpose Register
Lock Register 0
general data
PR-LK0
64-bit Factory-Programmed OTP register
64-bit User-Programmable OTP Register
Lock Register 1
0x81–0x84
0x85–0x88
0x89
Factory OTP register data
User OTP register data
OTP register lock data
User OTP register data
128-bit User-Programmable OTP registers
Notes:
0x8A–0x109
1.
2.
3.
BBA = Block Base Address.
DBA = Device base Address, Numonyx reserves other configuration address locations
In P33-65nm, the GPR is used as read out register for Extended Functional interface command.
Table 9:
Device ID codes
Device Identifier Codes
ID Code Type
Device Density
–T
–B
(Top Parameter)
(Bottom Parameter)
Device Code
256-Mbit
891F
8922
Note: The 512-Mbit devices do not have a Device ID associated with them. Each die within the stack can be identified by either
of the 256-Mbit Device ID codes depending on its parameter option.
7.4
Read CFI
The Read CFI command instructs the device to output Common Flash Interface data
when read.
Datasheet
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P33-65nm
8.0
Program Operation
The device supports three programming methods: Word Programming (40h or 10h),
Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h,
D0h). The following sections describe device programming in detail.
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be deasserted and the block must be unlocked before
attempting to program the block. Attempting to program a locked block causes a
program error (SR.4 and SR.1 set) and termination of the operation. See Section 10.0,
“Security” on page 30 for details on locking and unlocking blocks.
8.1
Word Programming
Word programming operations are initiated by writing the Word Program Setup
command to the device. This is followed by a second write to the device with the
address and data to be programmed. The device outputs Status Register data when
read. See Figure 31, “Word Program Flowchart” on page 72. VPP must be above VPPLK
,
and within the specified VPPL min/max values.
During programming, the WSM executes a sequence of internally-timed events that
program the desired data bits at the addressed location, and verifies that the bits are
sufficiently programmed. Programming the flash memory array changes “ones” to
“zeros”. Memory array bits that are zeros can be changed to ones only by erasing the
block.
The Status Register can be examined for programming progress and errors by reading
at any address. The device remains in the Read Status Register state until another
command is written to the device.
Status Register bit SR.7 indicates the programming status while the sequence
executes. Commands that can be issued to the device during programming are
Program Suspend, Read Status Register, Read Device Identifier, Read CFI, and Read
Array (this returns unknown data).
When programming has finished, Status Register bit SR.4 (when set) indicates a
programming failure. If SR.3 is set, the WSM could not perform the word programming
operation because VPP was outside of its acceptable limits. If SR.1 is set, the word
programming operation attempted to program a locked block, causing the operation to
abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow,
when word programming has completed.
8.2
Buffered Programming
The device features a 512-word buffer to enable optimum programming performance.
For Buffered Programming, data is first written to an on-chip write buffer. Then the
buffer data is programmed into the flash memory array in buffer-size increments. This
can improve system programming performance significantly over non-buffered
programming. (see Figure 33, “Buffer Program Flowchart” on page 74).
When the Buffered Programming Setup command is issued, Status Register information
is updated and reflects the availability of the buffer. SR.7 indicates buffer availability: if
set, the buffer is available; if cleared, the buffer is not available.
Note:
The device default state is to output SR data after the Buffer Programming Setup
Command. CE# and OE# toggle drive device to update Status Register. It is not
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allowed to issue 70h to read SR data after E8h command otherwise 70h would be
counted as Word Count.
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. Subsequent writes provide additional device addresses and
data. All data addresses must lie within the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the starting address at the beginning of a 512-word boundary (A[9:1] = 0x00). The
maximum buffer size would be 256-word if the misaligned address range is crossing a
512-word boundary during programming.
After the last data is written to the buffer, the Buffered Programming Confirm command
must be issued to the original block address. The WSM begins to program buffer
contents to the flash memory array. If a command other than the Buffered
Programming Confirm command is written to the device, a command sequence error
occurs and SR[7,5,4] are set. If an error occurs while writing to the array, the device
stops programming, and SR[7,4] are set, indicating a programming failure.
When Buffered Programming has completed, additional buffer writes can be initiated by
issuing another Buffered Programming Setup command and repeating the buffered
program sequence. Buffered programming may be performed with VPP = VPPL or VPPH
(see Section 13.2, “Operating Conditions” on page 45 for limitations when operating
the device with VPP = VPPH).
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and SR[5,4] are set.
If Buffered programming is attempted while VPP is below VPPLK, SR[4,3] are set. If any
errors are detected that have set Status Register bits, the Status Register should be
cleared using the Clear Status Register command.
8.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash
programming. The enhanced programming algorithm used in BEFP eliminates
traditional programming elements that drive up overhead in device programmer
systems. (see Figure 34, “BEFP Flowchart” on page 75).
BEFP consists of three phases: Setup, Program/Verify, and Exit It uses a write buffer to
spread MLC program performance across 512 data words. Verification occurs in the
same phase as programming to accurately program the flash memory cell to the
correct bit state.
A single two-cycle command sequence programs the entire block of data. This
enhancement eliminates three write cycles per buffer: two commands and the word
count for each set of 512 data words. Host programmer bus cycles fill the device’s write
buffer followed by a status check. SR.0 indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 512-word array
boundary. This aspect of BEFP saves host programming equipment the address-bus
setup overhead.
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With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
8.3.1
BEFP Requirements and Considerations
BEFP requirements:
• Case temperature: TC = 30 °C ± 10 °C
• Nominal VCC
• VPP driven to VPPH
• Target block must be unlocked before issuing the BEFP Setup and Confirm
commands
• The first-word address for the block to be programmed must be held constant from
the setup phase through all data streaming into the target block, until transition to
the exit phase is desired.
• The first-word address must align with the start of an array buffer boundary. Word
buffer boundaries in the array are determined by A[8:0] (0x000 through 01FF); the
alignment start point is A[8:0] = 0x000.
BEFP considerations:
• For optimum performance, cycling must be limited below 50 erase cycles per block.
Some degradation in performance may occur is this limit is exceeded, but the
internal algorithm continues to work properly.
• BEFP programs one block at a time; all buffer data must fall within a single block. If
the internal address counter increments beyond the block’s maximum address,
addressing wraps around to the beginning of the block.
• BEFP cannot be suspended
• Programming to the flash memory array can occur only when the buffer is full. If
the number of words is less than 512, remaining locations must be filled with
0xFFFF.
8.3.2
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR.7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A
delay before checking SR.7 is required to allow the WSM enough time to perform all of
its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR.4
is set and BEFP operation terminates. If the block was found to be locked, SR.1 is also
set. SR.3 is set if the error occurred due to an incorrect VPP level.
Note:
Reading from the device after the BEFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be
interpreted as data to be loaded into the buffer.
8.3.3
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR.7
cleared indicates the device is busy and the BEFP program/verify phase is activated.
SR.0 indicates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For BEFP, the count value for buffer loading is always
the maximum buffer size of 512 words. During the buffer-loading sequence, data is
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stored to sequential buffer locations starting at address 0x00. Programming of the
buffer contents to the flash memory array starts as soon as the buffer is full. If the
number of words is less than 512, the remaining buffer locations must be filled with
0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an
address outside of the current block's range during a buffer-fill sequence
causes the algorithm to exit immediately. Any data previously loaded into the
buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the BEFP
algorithm will be aborted and the program fails and (SR.4) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the
flash memory array; programming continues from where the previous buffer sequence
ended. The host programming system must poll SR.0 to determine when the buffer
program sequence completes. SR.0 cleared indicates that all buffer data has been
transferred to the flash array; SR.0 set indicates that the buffer is not available yet for
the next fill cycle. The host system may check full status for errors at any time, but it is
only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write
cycles should be issued to the device until SR.0 = 0 and the device is ready for the next
buffer fill.
Note:
Any spurious writes are ignored after a buffer fill operation and when internal program
is proceeding.
The host programming system continues the BEFP algorithm by providing the next
group of data words to be written to the buffer. Alternatively, it can terminate this
phase by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the BEFP Exit phase.
8.3.4
8.4
BEFP Exit Phase
When SR.7 is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed
successfully. When exiting the BEFP algorithm with a block address change, the read
mode will not change. After BEFP exit, any valid command can be issued to the device.
Program Suspend
Issuing the Program Suspend command while programming suspends the
programming operation. This allows data to be accessed from the device other than the
one being programmed. The Program Suspend command can be issued to any device
address. A program operation can be suspended to perform reads only. Additionally, a
program operation that is running during an erase suspend can be suspended to
perform a read operation (see Figure 32, “Program Suspend/Resume Flowchart” on
page 73).
When a programming operation is executing, issuing the Program Suspend command
requests the WSM to suspend the programming algorithm at predetermined points. The
device continues to output Status Register data after the Program Suspend command is
issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend
latency is specified in Section 15.5, “Program and Erase Characteristics” on page 58.
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To read data from the device, the Read Array command must be issued. Read Array,
Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid
commands during a program suspend.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at its programming level, and WP# must remain
unchanged while in program suspend. If RST# is asserted, the device is reset.
8.5
8.6
Program Resume
The Resume command instructs the device to continue programming, and
automatically clears Status Register bits SR[7,2]. This command can be written to any
address. If error bits are set, the Status Register should be cleared before issuing the
next instruction. RST# must remain deasserted (see Figure 32, “Program Suspend/
Resume Flowchart” on page 73).
Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If
VPP is at or below VPPLK, programming operations halt and SR.3 is set indicating a VPP-
level error. Block lock registers are not affected by the voltage level on VPP; they may
still be programmed and read, even if VPP is less than VPPLK
.
Figure 7: Example VPP Supply Connections
VCC
VCC
VPP
VCC
VPP
VCC
VPP
PROT #
≤ 10K Ω
• Low-voltage Programming only
• Logic Control of Device Protection
• Factory Programming with VPP = VPPH
• Complete write/Erase Protection when VPP ≤ VPPLK
VCC
VCC
VCC
VCC
VPP
VPP=VPPH
VPP
• Low Voltage Programming Only
• Full Device Protection Unavailable
• Low Voltage and Factory Programming
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9.0
Erase Operation
Flash erasing is performed on a block basis. An entire block is erased each time an
erase command sequence is issued, and only one block is erased at a time. When a
block is erased, all bits within that block read as logical ones. The following sections
describe block erase operations in detail.
9.1
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the
address of the block to be erased (see Section 6.2, “Device Command Bus Cycles” on
page 18). Next, the Block Erase Confirm command is written to the address of the
block to be erased. If the device is placed in standby (CE# deasserted) during an erase
operation, the device completes the erase operation before entering standby. VPP must
be above VPPLK and the block must be unlocked (see Figure 35, “Block Erase Flowchart”
on page 76).
During a block erase, the WSM executes a sequence of internally-timed events that
conditions, erases, and verifies all bits within the block. Erasing the flash memory array
changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros
only by programming the block.
The Status Register can be examined for block erase progress and errors by reading
any address. The device remains in the Read Status Register state until another
command is written. SR.0 indicates whether the addressed block is erasing. Status
Register bit SR.7 is set upon erase completion.
Status Register bit SR.7 indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR.5 indicates an erase
failure if set. SR.3 set would indicate that the WSM could not perform the erase
operation because VPP was outside of its acceptable limits. SR.1 set indicates that the
erase operation attempted to erase a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase operation has completed.
9.2
Blank Check
The Blank Check operation determines whether a specified main block is blank (i.e.
completely erased). Without Blank Check, Block Erase would be the only other way to
ensure a block is completely erased. so Blank Check can be used to determine whether
or not a prior erase operation was successful; this includes erase operations that may
have been interrupted by power loss.
Blank check can apply to only one block at a time, and no operations other than Status
Register Reads are allowed during Blank Check (e.g. reading array data, program,
erase etc). Suspend and resume operations are not supported during Blank Check, nor
is Blank Check supported during any suspended operations.
Blank Check operations are initiated by writing the Blank Check Setup command to the
block address. Next, the Check Confirm command is issued along with the same block
address. When a successful command sequence is entered, the device automatically
enters the Read Status State. The WSM then reads the entire specified block, and
determines whether any bit in the block is programmed or over-erased.
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The status register can be examined for Blank Check progress and errors by reading
any address within the block being accessed. During a blank check operation, the
Status Register indicates a busy status (SR.7 = 0). Upon completion, the Status
Register indicates a ready status (SR.7 = 1). The Status Register should be checked for
any errors, and then cleared. If the Blank Check operation fails, which means the block
is not completely erased, the Status
9.3
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend command can be issued to any device address. A block
erase operation can be suspended to perform a word or buffer program operation, or a
read operation within any block except the block that is erase suspended (see
Figure 37, “Erase Suspend/Resume Flowchart” on page 78).
When a block erase operation is executing, issuing the Erase Suspend command
requests the WSM to suspend the erase algorithm at predetermined points. The device
continues to output Status Register data after the Erase Suspend command is issued.
Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in Section 15.5, “Program and Erase Characteristics” on page 58.
To read data from the device (other than an erase-suspended block), the Read Array
command must be issued. During Erase Suspend, a Program command can be issued
to any block other than the erase-suspended block. Block erase cannot resume until
program operations initiated during erase suspend complete. Read Array, Read Status
Register, Read Device Identifier, Read CFI, and Erase Resume are valid commands
during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend,
Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase
Suspend.
During an erase suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at a valid level, and WP# must remain unchanged
while in erase suspend. If RST# is asserted, the device is reset.
9.4
9.5
Erase Resume
The Erase Resume command instructs the device to continue erasing, and
automatically clears SR[7,6]. This command can be written to any address. If status
register error bits are set, the Status Register should be cleared before issuing the next
instruction. RST# must remain deasserted.
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If
VPP is at or below VPPLK, erase operations halt and SR.3 is set indicating a VPP-level
error.
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10.0
Security
The device features security modes used to protect the information stored in the flash
memory array. The following sections describe each security mode in detail.
10.1
Block Locking
Individual instant block locking is used to protect user code and/or data within the flash
memory array. All blocks power up in a locked state to protect array data from being
altered during power transitions. Any block can be locked or unlocked with no latency.
Locked blocks cannot be programmed or erased; they can only be read.
Software-controlled security is implemented using the Block Lock and Block Unlock
commands. Hardware-controlled security can be implemented using the Block Lock-
Down command along with asserting WP#. Also, VPP data security can be used to
inhibit program and erase operations (see Section 8.6, “Program Protection” on
page 27 and Section 9.5, “Erase Protection” on page 29).
The P33-65nm device also offers four pre-defined areas in the main array that can be
configured as One-Time Programmable (OTP) for the highest level of security. These
include the four 32 KB parameter blocks together as one and the three adjacent 128 KB
main blocks. This is available for top or bottom parameter devices.
10.1.1
Lock Block
To lock a block, issue the Lock Block Setup command. The next command must be the
Lock Block command issued to the desired block’s address (see Section 6.2, “Device
Command Bus Cycles” on page 18 and Figure 36, “Block Lock Operations Flowchart” on
page 77). If the Set Read Configuration Register command is issued after the Block
Lock Setup command, the device configures the RCR instead.
Block lock and unlock operations are not affected by the voltage level on VPP. The block
lock bits may be modified and/or read even if VPP is at or below VPPLK
.
10.1.2
10.1.3
Unlock Block
The Unlock Block command is used to unlock blocks (see Section 6.2, “Device
Command Bus Cycles” on page 18). Unlocked blocks can be read, programmed, and
erased. Unlocked blocks return to a locked state when the device is reset or powered
down. If a block is in a lock-down state, WP# must be deasserted before it can be
unlocked (see Figure 8, “Block Locking State Diagram” on page 31).
Lock-Down Block
A locked or unlocked block can be locked-down by writing the Lock-Down Block
command sequence (see Section 6.2, “Device Command Bus Cycles” on page 18).
Blocks in a lock-down state cannot be programmed or erased; they can only be read.
However, unlike locked blocks, their locked state cannot be changed by software
commands alone. A locked-down block can only be unlocked by issuing the Unlock
Block command with WP# deasserted. To return an unlocked block to locked-down
state, a Lock-Down command must be issued prior to changing WP# to VIL. Locked-
down blocks revert to the locked state upon reset or power up the device (see Figure 8,
“Block Locking State Diagram” on page 31).
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10.1.4
Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see
Section 7.3, “Read Device Identifier” on page 22). Data bits DQ[1:0] display the
addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the
addressed block’s lock-down bit.
Figure 8: Block Locking State Diagram
P G M /E R A S E
A L L O W E D
P G M /E R A S E
P R E V E N T E D
L K /
D 0 h
L K /
0 1 h
[0 0 0 ]
[0 0 1 ]
P o w e r-U p /
R e s e t D e fa u lt
L K /
2 F h
W P # = V IL = 0
[0 1 1 ]
V irtu a l lo c k -
d o w n
[0 1 0 ]
L o c k e d -d o w n
A n y L o c k
c o m m a n d s
W P # to g g le
L K /
D 0 h
L K /
0 1 h o r 2 F h
L o c k e d -d o w n
is d is a b le d b y
W P # = V IH
[1 1 0 ]
[1 1 1 ]
W P # = V IH = 1
L K /
2 F h
L K /
2 F h
P o w e r-U p /
R e s e t D e fa u lt
L K /
D 0 h
L K /
0 1 h
[1 0 0 ]
[1 0 1 ]
Note: LK: Lock Setup Command, 60h; LK/D0h: Unlock Command; LK/01h: Lock Command; LK/2Fh: Lock-Down Command.
10.1.5
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change
block locking during an erase operation, first issue the Erase Suspend command.
Monitor the Status Register until SR.7 and SR.6 are set, indicating the device is
suspended and ready to accept another command.
Next, write the desired lock command sequence to a block, which changes the lock
state of that block. After completing block lock or unlock operations, resume the erase
operation using the Erase Resume command.
Note:
A Lock Block Setup command followed by any command other than Lock Block, Unlock
Block, or Lock-Down Block produces a command sequence error and set Status
Register bits SR.4 and SR.5. If a command sequence error occurs during an erase
suspend, SR.4 and SR.5 remains set, even after the erase operation is resumed. Unless
the Status Register is cleared using the Clear Status Register command before
resuming the erase operation, possible erase errors may be masked by the command
sequence error.
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If a block is locked or locked-down during an erase suspend of the same block, the lock
status bits change immediately. However, the erase operation completes when it is
resumed. Block lock operations cannot occur during a program suspend. See Appendix
A, “Write State Machine” on page 81, which shows valid commands during an erase
suspend.
10.2
10.3
Selectable OTP Blocks
Blocks from the main array may be optionally configured as OTP. Ask your local
Numonyx representative for details about any of these selectable OTP implementations.
Password Access
Password Access is a security enhancement offered on the P33-65nm device. This
feature protects information stored in main-array memory blocks by preventing content
alteration or reads until a valid 64-bit password is received. Password Access may be
combined with Non-Volatile Protection and/or Volatile Protection to create a multi-
tiered solution. Please contact your Numonyx Sales for further details concerning
Password Access.
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11.0
Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. SRD is automatically made available
following a Word Program, Block Erase, or Block Lock command sequence. Reads from
the device after any of these command sequences outputs the device’s status until
another valid command is written (e.g. the Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. SRD is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, when reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update SRD.
The Device Write Status bit (SR.7) provides overall status of the device. SR[6:1]
present status and error information about the program, erase, suspend, VPP, and
block-locked operations.
Table 10: Status Register Description
Status Register (SR)
Default Value = 0x80
Erase
Suspend
Status
Program
Suspend
Status
BEFP
Device Write
Status
Program
Status
Block-Locked
Erase Status
VPP Status
Write
Status
Status
DWS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
BWS
0
Bit
Name
Description
0 = Device is busy; program or erase cycle in progress; SR.0 valid.
1 = Device is ready; SR[6:1] are valid.
7
6
5
Device Write Status (DWS)
Erase Suspend Status (ESS)
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
Erase Status
(ES)
SR.5
SR.4
Description
Command
Sequence
Error
0
0
1
1
0
1
0
1
Program or Erase operation successful.
Program error - operation aborted.
Erase error - operation aborted.
Program
Status (PS)
4
Command sequence error - command aborted.
0 = VPP within acceptable limits during program or erase operation.
1 = VPP < V during program or erase operation.
3
2
1
VPP Status (VPPS)
PPLK
0 = Program suspend not in effect.
1 = Program suspend in effect.
Program Suspend Status
(PSS)
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
Block-Locked Status (BLS)
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
0
BEFP Write Status (BWS)
1 = BEFP in-progress.
Notes:
1.
Always clear the Status Register prior to resuming erase operations. It avoids Status Register ambiguity when issuing
commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register
contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible
errors during the erase operation cannot be detected via the Status Register because it contains the previous error status
BEFP mode is only valid in main array.
2.
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11.0.1
11.1
Clear Status Register
The Clear Status Register command clears the status register. It functions independent
of VPP. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.
Read Configuration Register
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see Section 6.2, “Device Command
Bus Cycles” on page 18).
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see Section 7.3, “Read Device Identifier” on page 22).
The RCR is shown in Table 11. The following sections describe each RCR bit.
Table 11: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
WAIT
Delay
Burst
Wrap
Read
Mode
WAIT
Burst
Seq
CLK
Latency Count
LC[3:0]
RES
RES
RES
Burst Length
Polarity
Edge
RM
15
Bit
WP
10
R
9
WD
8
BS
7
CE
6
R
5
R
4
BW
3
BL[2:0]
1
14
13
12
11
2
0
Name
Description
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
15
Read Mode (RM)
0010 =Code 2
0011 =Code 3
0100 =Code 4
0101 =Code 5
0110 =Code 6
0111 =Code 7
1000 =Code 8
14:11
Latency Count (LC[3:0])
1001 =Code 9
1010 =Code 10
1011 =Code 11
1100 =Code 12
1101 =Code 13
1110 =Code 14
1111 =Code 15 (default)
(Other bit settings are reserved)
0 =WAIT signal is active low (default)
1 =WAIT signal is active high
WAIT Polarity (WP)
10
9
Reserved (R)
Default “0”, Non-changeable
0 =WAIT deasserted with valid data
8
WAIT Delay (WD)
Burst Sequence (BS)
1 =WAIT deasserted one data cycle before valid data (default)
7
Default “0”, Non-changeable
Clock Edge (CE)
Reserved (R)
0 = Falling edge
6
1 = Rising edge (default)
5:4
Default “0”, Non-changeable
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Table 11: Read Configuration Register Description (Sheet 2 of 2)
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
3
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
2:0
Burst Length (BL[2:0])
(Other bit settings are reserved)
11.1.1
11.1.2
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
Latency Count
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and Figure 9 shows the data output latency for the different
settings of LC. The maximum Latency Count for P33 would be Code 4 based on the Max
clock frequency specification of 52 MHz, and there will be zero WAIT States when
bursting within the word line. Please also refer to Section 11.1.3, “End of Word Line
(EOWL) Considerations” on page 37 for more information on EOWL.
Refer to Table 12, “LC and Frequency Support” on page 36 for Latency Code Settings.
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Figure 9: First-Access Latency Count
CLK [C]
Valid
Address
Address [A]
ADV#[V]
Code 0 (Reserved)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
Code 1
(Reserved
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 3
Code 4
Code 5
Code 6
Code 7
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Table 12: LC and Frequency Support
Latency Count Settings
Frequency Support (MHz)
5 (TSOP); 4 (Easy BGA)
5 (Easy BGA)
≤ 40
≤ 52
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Figure 10: Example Latency Count Setting Using Code 3
tData
0
1
2
3
4
CLK
CE#
ADV#
Address
A[MAX:1]
Code 3
High-Z
Data
D[15:0]
R103
11.1.3
End of Word Line (EOWL) Considerations
End of Wordline (EOWL) WAIT states can result when the starting address of the burst
operation is not aligned to a 16-word boundary; that is, A[3:0] of start address does
not equal 0x0. Figure 11, “End of Wordline Timing Diagram” on page 37 illustrates the
end of wordline WAIT state(s), which occur after the first 16-word boundary is reached.
The number of data words and the number of WAIT states is summarized in Table 13,
“End of Wordline Data and WAIT state Comparison” on page 38for both P33-130nm
and P33-65nm devices.
Figure 11: End of Wordline Timing Diagram
Latency Count
CLK
A[Max:1]
DQ[15:0]
Address
Data
Data
Data
ADV#
OE#
WAIT
EOWL
Datasheet
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Mar 2010
OrderNumber:320003-09
P33-65nm
Table 13: End of Wordline Data and WAIT state Comparison
P33-130nm
P33-65nm
Latency Count
Data States
WAIT States
Data States
WAIT States
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Not Supported
Not Supported
0 to 1
Not Supported
Not Supported
Not Supported
Not Supported
0 to 2
4
4
4
4
4
4
0 to 2
0 to 3
0 to 4
0 to 5
16
16
16
16
16
16
16
16
16
16
16
16
16
0 to 3
0 to 4
0 to 5
0 to 6
0 to 7
0 to 8
0 to 9
0 to 10
0 to 11
0 to 12
0 to 13
0 to 14
0 to 6
Not Supported
Not Supported
11.1.4
WAIT Polarity
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low
(default). WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
11.1.5
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read
status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid
on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word
read mode, and all write operations, WAIT is set to a deasserted state as determined
by RCR.10. See Figure 18, “Asynchronous Single-Word Read (ADV# Latch)” on
page 52, and Figure 19, “Asynchronous Page-Mode Read Timing” on page 52.
Datasheet
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Mar 2010
Order Number: 320003-09
P33-65nm
Table 14: WAIT Functionality Table
Condition
WAIT
Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
High-Z
Active
1
1
Synchronous Array Reads
Synchronous Non-Array Reads
All Asynchronous Reads
All Writes
Active
1
Active
1
Deasserted
High-Z
1
1,2
Notes:
1.
2.
Active: WAIT is asserted until data becomes valid, then deasserts.
When OE# = V during writes, WAIT = High-Z.
IH
11.1.6
11.1.7
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Table 15 shows the synchronous burst sequence for all burst
lengths, as well as the effect of the Burst Wrap (BW) setting.
Table 15: Burst Sequence Word Ordering (Sheet 1 of 2)
Burst Addressing Sequence (DEC)
Start
Addr.
(DEC)
Burst
Wrap
(RCR.3)
4-Word Burst
(BL[2:0] = 0b001)
8-Word Burst
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
(BL[2:0] = 0b010)
0
1
2
3
4
0
0
0
0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
0-1-2-3-4…14-15
1-2-3-4-5…15-0
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
2-3-4-5-6…15-0-1
3-4-5-6-7…15-0-1-2
4-5-6-7-8…15-0-1-2-3
5-6-7-8-9…15-0-1-2-3-
4
5
6
7
0
0
0
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
6-7-8-9-10…15-0-1-2-
3-4-5
7-8-9-10…15-0-1-2-3-
4-5-6
14-15-16-17-18-19-20-
…
14
15
0
0
14-15-0-1-2…12-13
15-0-1-2-3…13-14
15-16-17-18-19-20-21-
…
Datasheet
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Mar 2010
OrderNumber:320003-09
P33-65nm
Table 15: Burst Sequence Word Ordering (Sheet 2 of 2)
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
0-1-2-3-4…14-15
1-2-3-4-5…15-16
2-3-4-5-6…16-17
3-4-5-6-7…17-18
4-5-6-7-8…18-19
5-6-7-8-9…19-20
6-7-8-9-10…20-21
7-8-9-10-11…21-22
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
14-15-16-17-18-19-20-
…
14
15
1
1
14-15-16-17-18…28-29
15-16-17-18-19…29-30
15-16-17-18-19-20-21-
…
11.1.8
11.1.9
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
Burst Wrap
The Burst Wrap (BW) bit determines whether 4, 8, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries.
When BW is set, burst wrapping does not occur (default). When BW is cleared, burst
wrapping occurs.
11.1.10
Burst Length
The Burst Length bits (BL[2:0]) selects the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and
continuous word.
Continuous burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 15, “Burst Sequence Word Ordering” on page 39). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
11.2
One-Time Programmable (OTP) Registers
The device contains 17 one-time programmable (OTP) registers that can be used to
implement system security measures and/or device identification. Each OTP register
can be individually locked.
The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit
number. The other 64-bit segment, as well as the other sixteen 128-bit OTP Registers,
are blank. Users can program these registers as needed. Once programmed, users can
then lock the OTP Register(s) to prevent additional bit programming (see Figure 12,
“OTP Register Map” on page 41).
Datasheet
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Order Number: 320003-09
P33-65nm
The OTP Registers contain OTP bits; when programmed, PR bits cannot be erased. Each
OTP Register can be accessed multiple times to program individual bits, as long as the
register remains unlocked.
Each OTP Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated OTP Register can only be read; it can no longer be
programmed. Additionally, because the Lock Register bits themselves are OTP, when
programmed, Lock Register bits cannot be erased. Therefore, when a OTP Register is
locked, it cannot be unlocked.
.
Figure 12: OTP Register Map
0x109
128-bit Protection Register 16
(User-Programmable)
0x102
0x91
128-bit Protection Register 1
(User-Programmable)
0x8A
0x89
Lock Register 1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit Protection Register 0
64-bit Segment
(Factory-Programmed)
0x81
0x80
Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
11.2.1
Reading the OTP Registers
The OTP Registers can be read from any address. To read the OTP Register, first issue
the Read Device Identifier command at any address to place the device in the Read
Device Identifier state (see Section 6.2, “Device Command Bus Cycles” on page 18).
Next, perform a read operation using the address offset corresponding to the register
to be read. Table 8, “Device Identifier Information” on page 22 shows the address
offsets of the OTP Registers and Lock Registers. PR data is read 16 bits at a time.
Datasheet
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OrderNumber:320003-09
P33-65nm
11.2.2
Programming the OTP Registers
To program any of the OTP Registers, first issue the Program OTP Register command at
the parameter’s base address plus the offset to the desired OTP Register (see Section
6.2, “Device Command Bus Cycles” on page 18). Next, write the desired OTP Register
data to the same OTP Register address (see Figure 12, “OTP Register Map” on
page 41).
The device programs the 64-bit and 128-bit user-programmable OTP Register data 16
bits at a time (see Figure 38, “OTP Register Programming Flowchart” on page 79).
Issuing the Program OTP Register command outside of the OTP Register’s address
space causes a program error (SR.4 set). Attempting to program a locked OTP Register
causes a program error (SR.4 set) and a lock error (SR.1 set).
Note:
When programming the OTP bits in the OTP registers for a Top Parameter Device,
the following upper address bits must also be driven properly: A[Max:17] driven high
(VIH).
11.2.3
Locking the OTP Registers
Each OTP Register can be locked by programming its respective lock bit in the Lock
Register. To lock a OTP Register, program the corresponding bit in the Lock Register by
issuing the Program Lock Register command, followed by the desired Lock Register
data (see Section 6.2, “Device Command Bus Cycles” on page 18). The physical
addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These
addresses are used when programming the lock registers (see Table 8, “Device
Identifier Information” on page 22).
Bit 0 of Lock Register 0 is already programmed during the manufacturing process at the
“factory”, locking the lower, pre-programmed 64-bit region of the first 128-bit OTP
Register containing the unique identification number of the device. Bit 1 of Lock
Register 0 can be programmed by the user to lock the user-programmable, 64-bit
region of the first 128-bit OTP Register. When programming Bit 1 of Lock Register 0, all
other bits need to be left as ‘1’ such that the data programmed is 0xFFFD.
Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each of
the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit OTP
Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit OTP
Register.
Caution:
After being locked, the OTP Registers cannot be unlocked.
Datasheet
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Mar 2010
Order Number: 320003-09
P33-65nm
12.0
Power and Reset Specifications
12.1
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
12.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 16: Power and Reset
Num
Symbol
Parameter
RST# pulse width low
Min
Max
Unit
Notes
P1
t
100
-
-
ns
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
PLPH
RST# low to device reset during erase
RST# low to device reset during program
VCC Power valid to RST# de-assertion (high)
25
25
-
P2
t
t
PLRH
VCCPH
-
µs
P3
300
Notes:
1.
2.
3.
4.
5.
6.
7.
These specifications are valid for all device versions (packages and speeds).
The device may reset if t is < t Min, but this is not guaranteed.
PLPH
PLPH
Not applicable if RST# is tied to VCC.
Sampled, but not 100% tested.
When RST# is tied to the VCC supply, device will not be ready until t
after VCC ≥ V
VCCPH
.
VCCPH
CCMIN
When RST# is tied to the VCCQ supply, device will not be ready until t
Reset completes within t
after VCC ≥ V
.
CCMIN
if RST# is asserted while no erase or program operation is executing.
PLPH
Datasheet
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Mar 2010
OrderNumber:320003-09
P33-65nm
Figure 13: Reset Operation Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
read mode
RST# [P]
RST# [P]
RST# [P]
VCC
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
12.3
Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power
supply current considerations are: 1) standby current levels; 2) active current levels;
and 3) transient peaks produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of
these internal activities produce transient signals. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct
de-coupling capacitor selection suppress transient voltage peaks.
Because Numonyx MLC flash memory devices draw their power from VCC, VPP, and
VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High-
frequency, inherently low-inductance capacitors should be placed as close as possible
to package leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
Datasheet
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Mar 2010
Order Number: 320003-09
P33-65nm
13.0
Maximum Ratings and Operating Conditions
13.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the Absolute Maximum Ratings may cause permanent
damage. These are stress ratings only.
Table 17: Absolute Maximum Ratings
Parameter
Maximum Rating
Notes
Temperature under bias
Storage temperature
Voltage on any signal (except VCC, VPP and VCCQ)
VPP voltage
–40 °C to +85 °C
–65 °C to +125 °C
–0.5 V to +4.1 V
–0.2 V to +10 V
–0.2 V to +4.1 V
–0.2 V to +4.1 V
100 mA
-
-
1
1,2,3
1
VCC voltage
VCCQ voltage
1
Output short circuit current
Notes:
4
1.
Voltages shown are specified with respect to V . Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on
VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for periods less than 20 ns. Maximum DC
SS
voltage on VCC is VCC + 0.5 V, which, during transitions, may overshoot to VCC + 2.0 V for periods less than 20 ns.
Maximum DC voltage on input/output signals and VCCQ is VCCQ + 0.5 V, which, during transitions, may overshoot to
VCCQ + 2.0 V for periods less than 20 ns.
2.
3.
Maximum DC voltage on VPP may overshoot to +11.5 V for periods less than 20 ns.
Program/erase voltage is typically 2.3 V – 3.6 V. 9.0 V can be applied for 80 hours maximum total, to any blocks for
1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability.
Output shorted for no more than one second. No more than one output shorted at a time.
4.
13.2
Operating Conditions
Note:
Operation beyond the Operating Conditions is not recommended and extended
exposure beyond the Operating Conditions may affect device reliability.
Table 18: Operating Conditions
Symbol
Parameter
Min
Max
Units
Notes
T
Operating Temperature
VCC Supply Voltage
–40
2.3
+85
3.6
3.6
3.6
3.6
9.5
80
-
°C
1
-
C
VCC
CMOS inputs
TTL inputs
2.3
VCCQ
I/O Supply Voltage
-
2.4
V
V
V
Voltage Supply (Logic Level)
PP
1.5
PPL
PPH
PPH
V
Buffered Enhanced Factory Programming V
8.5
PP
t
Maximum V Hours
PP
VPP = V
-
Hours
Cycles
PPH
2
Main and Parameter Blocks
Main Blocks
VPP = V
100,000
100,000
100,000
PPL
Block
Erase
Cycles
VPP = V
VPP = V
-
PPH
PPH
Parameter Blocks
-
Notes:
1.
2.
T = Case Temperature.
C
In typical operation VPP program voltage is V
.
PPL
Datasheet
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Mar 2010
OrderNumber:320003-09
P33-65nm
14.0
Electrical Specifications
14.1
DC Current Characteristics
Table 19: DC Current Characteristics (Sheet 1 of 2)
CMOS
TTL Inputs
Inputs
(VCCQ =
(VCCQ =
2.4 V - 3.6
2.3 V - 3.6
V)
Sym
Parameter
Unit
Test Conditions
Notes
V)
Typ
Max
Typ
Max
VCC = VCC Max
VCCQ = VCCQ Max
= VCCQ or V
I
Input Load Current
-
±1
-
±2
µA
µA
LI
V
IN
SS
1,6
1,2
Output
Leakage
Current
VCC = VCC Max
VCCQ = VCCQ Max
= VCCQ or V
I
DQ[15:0], WAIT
-
±1
-
±10
210
LO
V
IN
SS
256-Mbit
512-Mbit
65
210
65
VCC = VCC Max
VCCQ = VCC Max
CE# =VCCQ
I
I
,
VCC Standby,
Power-Down
CCS
RST# = VCCQ (for I
)
µA
CCS
)
CCD
130
420
130
420
RST# = V (for I
SS
CCD
WP# = V
IH
Asynchronous Single-
Word f = 5 MHz (1 CLK)
16-Word
Read
26
31
26
31
mA
mA
Page-Mode Read
f = 13 MHz (17 CLK)
16-Word
Read
VCC = VCC
12
19
16
16
22
18
12
19
16
16
22
18
Max
Average
VCC
CE# = V
IL
I
mA 8-Word Read
1
OE# = V
CCR
IH
Read
Inputs: V or
Current
IL
16-Word
Read
Synchronous Burst
f = 52 MHz, LC=4
mA
V
IH
Continuous
Read
21
24
21
24
mA
35
35
65
50
50
35
35
65
50
50
VPP = V , Pgm/Ers in progress
1,3,5
1,3,5
PPL
I
I
VCC Program Current,
VCC Erase Current
CCW,
mA
µA
CCE
VPP = V
, Pgm/Ers in progress
PPH
VCC Program
Suspend Current,
VCC Erase
Suspend Current
256-Mbit
512-Mbit
210
210
I
CE# = VCCQ; suspend in
progress
CCWS,
1,3,4
I
CCES
70
225
5
70
225
5
I
VPP Standby Current,
VPP Program Suspend Current,
VPP Erase Suspend Current
PPS,
I
0.2
0.2
µA
VPP = V , suspend in progress
PPL
1,3,7
PPWS,
IPPES
I
VPP Read
2
15
2
15
µA
VPP = V
VPP = V
VPP = V
VPP = V
VPP = V
1,3
3
PPR
PPL
0.05
0.05
0.05
0.05
0.10
0.10
0.10
0.10
0.05
0.05
0.05
0.05
0.10
0.10
0.10
0.10
program in progress
program in progress
erase in progress
erase in progress
PPL,
PPH,
PPL,
PPH,
I
VPP Program Current
mA
PPW
I
V
Erase Current
PP
mA
3
PPE
Datasheet
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Mar 2010
Order Number: 320003-09
P33-65nm
Table 19: DC Current Characteristics (Sheet 2 of 2)
CMOS
TTL Inputs
Inputs
(VCCQ =
(VCCQ =
2.4 V - 3.6
2.3 V - 3.6
V)
Sym
Parameter
Unit
Test Conditions
Notes
V)
Typ
Max
Typ
Max
0.05
0.05
0.10
0.10
0.05
0.05
0.10
0.10
VPP = V
erase in progress
PPL,
I
VPP Blank Check
mA
3
PPBC
VPP = V
erase in progress
PPH,
Notes:
1.
2.
3.
4.
5.
All currents are RMS unless noted. Typical values at typical VCC, T = +25 °C.
C
I
is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.
CCS
Sampled, not 100% tested.
I
I
is specified with the device deselected. If device is read while in erase suspend, current is I
CCW CCE
plus I
.
CCR
CCES
, I
measured over typical or max times specified in Section 15.5, “Program and ECrCaEsSe
Characteristics” on page 58.
6.
7.
if V > VCC the input load current increases to 10uA max.
IN
the I
I
I
Will increase to 200uA when VPP/WP# is at V
.
PPS, PPWS, PPES
PPH
14.2
DC Voltage Characteristics
Table 20: DC Voltage Characteristics
(1)
CMOS Inputs
(VCCQ = 2.3 V – 3.6 V)
TTL Inputs
(VCCQ = 2.4 V – 3.6 V)
Sym
Parameter
Unit
Test Conditions
Notes
Min
Max
Min
Max
V
Input Low Voltage
Input High Voltage
-0.5
0.4
-0.5
2.0
0.6
V
V
IL
2
-
V
VCCQ – 0.4
VCCQ + 0.5
VCCQ + 0.5
IH
VCC = VCC Min
V
Output Low Voltage
Output High Voltage
-
0.2
-
-
0.2
-
V
V
VCCQ = VCCQ Min
OL
I
= 100 µA
OL
VCC = VCC Min
V
VCCQ – 0.2
VCCQ – 0.2
VCCQ = VCCQ Min
-
OH
I
= –100 µA
OH
V
VPP Lock-Out Voltage
VCC Lock Voltage
-
0.4
-
0.4
V
V
V
3
-
PPLK
V
1.5
0.9
-
-
1.5
0.9
-
-
LKO
V
VCCQ Lock Voltage
-
LKOQ
VPP Voltage Supply
(Logic Level)
V
1.5
8.5
3.6
9.5
1.5
8.5
3.6
9.5
V
V
PPL
Buffered Enhanced
Factory Programming
VPP
V
PPH
Notes:
1.
2.
Synchronous read mode is not supported with TTL inputs.
can undershoot to –1.0 V for duration of 2ns or less and V can overshoot to V
CCQ
V
less.
+ 1.0 V for durations of 2ns or
.
IL
IH
3.
VPP ≤ V
inhibits erase and program operations. Do not use V
and V
PPLK
PPL PPH
outside their valid ranges
Datasheet
47
Mar 2010
OrderNumber:320003-09
P33-65nm
15.0
AC Characteristics
15.1
AC Test Conditions
Figure 14: AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
IO_REF.WMF
Note: AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input
rise and fall times (10% to 90%) < 5 ns. Worst-case speed occurs at VCC = VCCMin.
Figure 15: Transient Equivalent Testing Load Circuit
Device
Out
Under Test
CL
Notes:
1.
2.
See the following table for component values.
Test configuration component value for worst case speed conditions.
3.
C includes jig capacitance
L
.
Table 21: Test Configuration Component Value for Worst Case Speed Conditions
Test Configuration
VCCQ Min Standard Test
C
(pF)
L
30
Figure 16: Clock Input AC Waveform
R201
VIH
CLK [C]
VIL
R202
R203
Datasheet
48
Mar 2010
Order Number: 320003-09
P33-65nm
15.2
Capacitance
Table 22: Capacitance
Symbol
Signal
Min
3
Typ
7
Max
8
Unit
Condition
Note
Input
Capacita
nce
Address, Data, CE#,
WE#, OE#, RST#,
CLK, ADV#, WP#
256-Mbit
256-Mbit/256Mbit
256-Mbit
Typ temp = 25 °C,
Max temp = 85 °C,
= (0 V - 2.0 V),
= (0 V - 3.6 V),
Discrete silicon die
6
14
5
16
7
pF
V
1
CC
Output
Capacita
nce
3
V
CCQ
Data, WAIT
256-Mbit/256Mbit
6
10
14
Notes:
1.
Sampled, not 100% tested.
15.3
AC Read Specifications
Table 23: AC Read Specifications - (Sheet 1 of 3)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Asynchronous Specifications
Easy BGA
TSOP
95
105
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
R1
R2
R3
t
Read cycle time
AVAV
-
Easy BGA
TSOP
95
105
95
105
25
150
-
-
-
t
Address to output valid
AVQV
Easy BGA
TSOP
-
-
t
CE# low to output valid
OE# low to output valid
ELQV
-
R4
R5
R6
R7
R8
R9
t
t
-
-
1,2
1
GLQV
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
PHQV
t
0
0
-
1,3
1,2,3
ELQX
GLQX
EHQZ
GHQZ
t
t
-
20
15
t
-
1,3
Output hold from first occurring address, CE#, or OE#
change
R10
t
0
-
ns
OH
R11
R12
R13
R15
R16
R17
t
CE# pulse width high
17
-
-
ns
ns
ns
ns
ns
ns
EHEL
1
t
CE# low to WAIT valid
CE# high to WAIT high-Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
17
20
17
-
ELTV
t
-
1,3
1
EHTZ
t
t
-
GLTV
GLTX
0
-
1,3
t
20
GHTZ
Latching Specifications
Datasheet
49
Mar 2010
OrderNumber:320003-09
P33-65nm
Table 23: AC Read Specifications - (Sheet 2 of 3)
Num
Symbol
Parameter
Address setup to ADV# high
Min
Max
Unit
Notes
R101
R102
t
10
10
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVVH
t
CE# low to ADV# high
ELVH
Easy BGA
TSOP
95
105
-
R103
t
ADV# low to output valid
1
VLQV
R104
R105
R106
R108
R111
t
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
10
10
9
VLVH
VHVL
VHAX
t
-
t
-
1,4
1
t
-
25
-
APA
t
RST# high to ADV# high
30
phvh
Clock Specifications
-
-
-
52
40
MHz
MHz
R200
R201
fCLK
CLK frequency
CLK period
TSOP
-
19.2
25
5
tCLK
-
ns
TSOP
-
1,3,5,6
R202
R203
tCH/CL
CLK high/low time
CLK fall/rise time
-
ns
ns
TSOP
9
tFCLK/RCLK
0.3
3
Datasheet
50
Mar 2010
Order Number: 320003-09
P33-65nm
Table 23: AC Read Specifications - (Sheet 3 of 3)
Num
Symbol
Parameter
Min
Max
Unit
Notes
(5)
Synchronous Specifications
R301
R302
R303
t
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
9
9
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVCH/L
t
VLCH/L
1,6
t
-
ELCH/L
-
17
20
-
R304
t
CLK to output valid
CHQV / tCLQV
TSOP
-
R305
R306
t
Output hold from CLK
Address hold from CLK
3
10
-
1,6
1,4,6
1,6
1,6
1
CHQX
t
-
CHAX
17
20
-
R307
t
CLK to WAIT valid
CHTV
TSOP
-
R311
R312
t
CLK Valid to ADV# Setup
WAIT Hold from CLK
3
3
CHVL
t
-
1,6
CHTX
Notes:
1.
See Figure 14, “AC Input/Output Reference Waveform” on page 48 for timing measurements and max
allowable input slew rate.
2.
3.
4.
5.
6.
OE# may be delayed by up to t
Sampled, not 100% tested.
Address hold in synchronous burst read mode is t
– t
after CE#’s falling edge without impact to t
ELQV
GLQV ELQV.
or t
, whichever timing specification is satisfied first.
VHAX
CHAX
Synchronous burst read mode is not supported with TTL level inputs.
Applies only to subsequent synchronous reads.
Figure 17: Asynchronous Single-Word Read (ADV# Low)
R1
R2
Address [A]
ADV#
R3
R8
CE# [E}
R4
R9
OE# [G]
R15
R17
WAIT [T]
R7
R6
Data [D/Q]
R5
RST# [P]
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Datasheet
51
Mar 2010
OrderNumber:320003-09
P33-65nm
Figure 18: Asynchronous Single-Word Read (ADV# Latch)
R1
R2
Address [A]
A[1:0][A]
R101
R105
R106
ADV#
CE# [E}
OE# [G]
WAIT [T]
R3
R8
R4
R9
R15
R17
R7
R6
R10
Data [D/Q]
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low)
Figure 19: Asynchronous Page-Mode Read Timing
R2
A[Max:4] [A]
A[3:0]
Valid Addres s
R10
R10
R10
R10
0
1
2
F
R101
R105
R106
ADV#
R3
R8
CE# [E]
R4
R9
OE# [G]
WAIT [T]
R6
R13
R108
Q2
R108
Q3
R108
Q16
DATA [D/Q]
Q1
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Datasheet
52
Mar 2010
Order Number: 320003-09
P33-65nm
.
Figure 20: Synchronous Single-Word Array or Non-array Read Timing
R301
R306
CLK [C]
R2
Address [A]
R101
R104
R106
R105
ADV# [V]
R303
R102
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R7
R9
R15
R307
R304
R17
R312
R4
R305
Data [D/Q]
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
2.
Figure 21: Continuous Burst Read, showing an Output Delay Timing
R301
R302
R306
R304
R304
R304
CLK [C]
Address [A]
ADV# [V]
R2
R101
R106
R105
R303
R102
R3
CE# [E]
OE# [G]
R15
R307
R304
R312
WAIT [T]
R4
R7
R305
R305
R305
R305
Data [D/Q]
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned. See Section 11.1.3, “End of Word Line (EOWL) Considerations” on
page 37 for more information
Datasheet
53
Mar 2010
OrderNumber:320003-09
P33-65nm
Figure 22: Synchronous Burst-Mode Four-Word Read Timing
R302
R301
R306
CLK [C]
Address [A]
ADV# [V]
R2
R101
A
R105
R102
R106
R303
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R9
R15
R307
R17
R4
R304
R305
Q0
R7
R304
R10
Data [D/Q]
Q1
Q2
Q3
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR.10=0, WAIT asserted low).
15.4
AC Write Specifications
Table 24: AC Write Specifications (Sheet 1 of 2)
Num
W1
Symbol
Parameter
Min
Max
Unit
Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RST# high recovery to WE# low
CE# setup to WE# low
150
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,3
PHWL
ELWL
W2
W3
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
50
50
50
0
1,2,4
WLWH
DVWH
AVWH
WHEH
WHDX
WHAX
WHWL
VPWH
QVVL
W4
1, 2, 12
W5
W6
1,2
W7
0
W8
0
W9
20
200
0
1,2,5
W10
W11
W12
W13
W14
W16
VPP setup to WE# high
VPP hold from Status read
WP# hold from Status read
WP# setup to WE# high
WE# high to OE# low
1,2,3,7
0
QVBL
1,2,3,7
200
0
BHWH
WHGL
WHQV
1,2,9
WE# high to read valid
t
+ 35
1,2,3,6,10
AVQV
Write to Asynchronous Read Specifications
W18
t
WE# high to Address valid
0
-
ns
1,2,3,6,8
WHAV
Datasheet
54
Mar 2010
Order Number: 320003-09
P33-65nm
Table 24: AC Write Specifications (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Write to Synchronous Read Specifications
W19
W20
W28
t
t
t
WE# high to Clock valid
19
19
7
-
-
-
ns
ns
ns
WHCH/L
WHVH
WHVL
WE# high to ADV# high
WE# high to ADV# low
1,2,3,6,10
Write Specifications with Clock Active
W21
W22
t
t
ADV# high to WE# low
Clock high to WE# low
-
-
20
20
ns
ns
VHWL
CHWL
1,2,3,11
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
or t
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
WLWH
ELEH
WLWH
(whichever occurs first). Hence, t
= t
= t
= t
.
ELWH
ELEH
WLEH
5.
Write pulse width high (t
or t
) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
WHWL
EHEL
(whichever occurs last). Hence, t
= t
= t
= t
).
EHWL
WHWL
EHEL
WHEL
6.
7.
8.
t
or t
must be met when transiting from a write cycle to a synchronous burst read.
WHVH
WHCH/L
VPP and WP# should be at a valid level until erase or program success is determined.
This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20
for synchronous read.
9.
10.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
Add 10 ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
11.
12.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
This specification must be complied with by customer’s writing timing. The result would be unpredictable if any violation
to this timing specification.
Figure 23: Write-to-Write Timing
W5
W8
W5
W8
Address [A]
W2
W6
W2
W6
CE# [E}
W3
W9
W3
WE# [W]
OE# [G]
W4
W7
W4
W7
Data [D/Q]
W1
RST# [P]
Datasheet
55
Mar 2010
OrderNumber:320003-09
P33-65nm
Figure 24: Asynchronous Read-to-Write Timing
R1
R2
W5
W8
Address [A]
R3
R8
R9
CE# [E}
R4
OE# [G]
W2
W3
W6
WE# [W]
R15
R17
R10
WAIT [T]
R7
R6
W7
W4
Data [D/Q]
RST# [P]
Q
D
R5
Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted.
Figure 25: Write-to-Asynchronous Read Timing
W5
W8
R1
Address [A]
ADV# [V]
W2
W6
R10
CE# [E}
WE# [W]
OE# [G]
WAIT [T]
W3
W18
W14
R15
R17
R4
R2
R3
R8
R9
W4
W7
Data [D/Q]
RST# [P]
D
Q
W1
Datasheet
56
Mar 2010
Order Number: 320003-09
P33-65nm
Figure 26: Synchronous Read-to-Write Timing
Latency Count
R301
R302
R306
CLK [C]
R2
W5
R101
W18
Address [A]
R105
R102
R106
R104
ADV# [V]
R303
R11
R13
R3
W6
CE# [E]
OE# [G]
R4
R8
W21
W22
W21
W22
W2
W8
W15
W3
W9
WE#
R16
R307
R304
R312
WAIT [T]
R7
R305
W7
Q
D
D
Data [D/Q]
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR 10=0, WAIT asserted low). Clock is
ignored during write operation.
Figure 27: Write-to-Synchronous Read Timing
R302
R301
R2
CLK
W5
W8
R306
R106
Address [A]
ADV#
R104
R303
W6
W2
R11
CE# [E}
W18
W19
W20
W3
WE# [W]
OE# [G]
WAIT [T]
R4
R15
R3
R307
W7
R304
R305
R304
W4
D
Q
Q
Data [D/Q]
RST# [P]
W1
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low).
Datasheet
57
Mar 2010
OrderNumber:320003-09
P33-65nm
15.5
Program and Erase Characteristics
Table 25: Program and Erase Specifications
V
V
PPH
PPL
Num
Symbol
Parameter
Unit
Note
Min
Conventional Word Programming
Single word 270
Buffered Programming
Typ
Max
Min
Typ
Max
Program
Time
W200
t
-
456
-
270
456
µs
1
PROG/W
Aligned 32-Wd, BP time
(32 Words)
-
-
-
-
-
310
310
375
505
900
716
900
-
-
-
-
-
310
310
375
505
900
716
900
Aligned 64-Wd, BP time
(64 Word)
Program
Time
Aligned 128-Wd, BP time
(128 Words)
W250
t
1140
1690
3016
1140
1690
3016
µs
1
PROG
Aligned 256-Wd, BP time
(256 Words)
one full buffer (512
Words)
Buffered Enhanced Factory Programming
W451
W452
t
t
Single byte
BEFP Setup
n/a
n/a
n/a
n/a
n/a
n/a
-
0.5
-
-
-
1,2
1
BEFP/B
Program
µs
5
BEFP/Setup
Erase and Suspend
W500
W501
W600
W601
W602
t
t
t
t
t
32-KByte Parameter
128-KByte Main
Program suspend
Erase suspend
-
0.8
0.8
25
4.0
4.0
30
30
-
-
-
-
-
-
0.8
0.8
25
4.0
4.0
30
30
-
ERS/PB
ERS/MB
SUSP/P
SUSP/E
ERS/SUSP
Erase Time
s
-
1
-
Suspend
Latency
-
25
25
µs
Erase to Suspend
-
blank check
-
500
500
1,3
W702
t
blank check Main Array Block
3.2
-
-
3.2
-
ms
BC/MB
Notes:
1.
Typical values measured at T = +25 °C and nominal voltages. Performance numbers are valid for all speed versions.
C
Excludes system overhead. Sampled, but not 100% tested.
2.
3.
Averaged over entire device.
W602 is the typical time between an initial block erase or erase resume command and the a subsequent erase suspend
command. Violating the specification repeatedly during any particular block erase may cause erase failures.
Datasheet
58
Mar 2010
Order Number: 320003-09
P33-65nm
16.0
Ordering Information
16.1
Discrete Products
Figure 28: Decoder for Discrete Products
J S 2 8 F 2 5 6 P 3 3 B F
*
Device Features*
Package Designator
TE=56 -Lead TSOP, leaded
JS =56-Lead TSOP, lead-free
RC =64-Ball Easy BGA, leaded
PC =64-Ball Easy BGA, lead-free
Device Details
65nm lithography
Parameter Location
B = Bottom Parameter
T = Top Parameter
Product Line Designator
28F =Numonyx™ Flash Memory
Product Family
Device Density
256=256-Mbit
P33 =Numonyx® Axcell™ Flash Memory (P33)
VCC =2. 3 – 3. 6 V
VCCQ =2. 3– 3. 6V
Note: The last digit is randomly assigned to cover packing media and/or features or other specific configuration.
Table 26: Valid Combinations for Discrete Products
256-Mbit
RC28F256P33TF*
RC28F256P33BF*
PC28F256P33TF*
PC28F256P33BF*
JS28F256P33TF*
JS28F256P33BF*
Datasheet
59
Mar 2010
OrderNumber:320003-09
P33-65nm
16.2
SCSP Products
Figure 29: Decoder for SCSP Devices
P C 4 8 F 4 4 0 0 P 0 T B 0 E
*
Package Designator
RC =64- Ball Easy BGA, leaded
PC=64- Ball Easy BGA, lead-free
Device Features*
Device Details
E = 65nm lithography
Product Designator
48F = Numonyx™ Flash Memory Only
Ballout Descriptor
0 = Discrete ballout
Device Density
0 = No die
4 =256-Mbit
Parameter Location
B = Bottom Parameter
T = Top Parameter
Product Family
Numonyx® Axcell™ Flash Memory (P33)
I/ O Voltage, CE# Configuration
P =
0 = No die
X =Individual Chip Enable(s)
T =Virtual Chip Enable(s)
VCC =2. 3 to 3.6 V
3. 6V
VCCQ =2. 3to
Table 27: Valid Combinations for Dual- Die Products
*
512-Mbit
RC48F4400P0TB0E*
PC48F4400P0TB0E*
Notes:
1.
2.
The “B” parameter is used for Top(Die1)/Bot(Die2) stack option in the 512-Mbit density.
The last digit is randomly assigned to cover packing media and/or features or other specific configuration.
Datasheet
60
Mar 2010
Order Number: 320003-09
P33-65nm
Appendix A Supplemental Reference Information
A.1
Common Flash Interface
The Common Flash Interface (CFI) is part of an overall specification for multiple
command-set and control-interface descriptions. This appendix describes the database
structure containing the data returned by a read operation after issuing the Read CFI
command (see Section 6.2, “Device Command Bus Cycles” on page 18). System
software can parse this database structure to obtain information about the flash device,
such as block size, density, bus width, and electrical specifications. The system
software will then know which command set(s) to use to properly perform flash writes,
block erases, reads and otherwise control the flash device.
A.1.1
Query Structure Output
The Query database allows system software to obtain information for controlling the
flash device. This section describes the device’s CFI-compliant interface that allows
access to Query data.
Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical
offset value is the address relative to the maximum bus width supported by the device.
On this family of devices, the Query table device starting address is a 10h, which is a
word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0
)
and 00h in the high byte (DQ15-8).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs have 00h on
the upper byte in this mode.
Table 28: Summary of Query Structure Output as a Function of Device and Mode
Hex
Hex
Code
51
52
59
ASCII
Value
"Q"
"R"
"Y"
Device
Offset
00010:
00011:
00012:
Device Addresses
Datasheet
61
Mar 2010
OrderNumber:320003-09
P33-65nm
Table 29: Example of Query Structure Output of x16 Devices
Offset
A -A
Hex Code
Value
D
-D
0
X
1
15
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
0051
0052
0059
“Q”
“R”
“Y”
P_ID
LO
PrVendor ID#
P_ID
HI
P
LO
PrVendor TblAdr
P
HI
A_ID
LO
AltVendor ID#
...
A_ID
...
HI
A.1.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or database. Table 30 summarizes the structure sub-sections and address
locations.
Table 30: Query Structure
00001-Fh Reserved
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
00010h
CFI query identification string
0001Bh System interface information
00027h
Device geometry definition
Vendor-defined additional information specific
to the Primary Vendor Algorithm
P(3)
Primary Numonyx-specific Extended Query
Note:
1.
Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of
device bus width and mode.
2.
3.
BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord).
Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table.
A.1.3
Read CFI Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
Datasheet
62
Mar 2010
Order Number: 320003-09
P33-65nm
Table 31: CFI Identification
Hex
Code
Offset
Length
Description
Add.
Value
10:
11:
12:
--51
--52
--59
“Q”
“R”
“Y”
10h
3
Query-unique ASCII string “QRY”.
Primary Vendor command set and control interface ID code.
16-bit ID code for Vendor-specified algorithms.
13:
14:
--01
--00
13h
15h
17h
19h
2
2
2
2
15:
16:
--0A
--01
Extended Query Table primay algorithm address.
Alernate vendor command set and control interface ID code.
0000h means no second vendor-specified alorithm exists.
17:
18:
--00
--00
Secondary algorithm Extended Query Table address.
0000h means none exists.
19:
1A:
--00
--00
Table 32: System Interface Information
Hex
Code
Offset
Length
Description
Add
Value
VCC logic supply minimum program/erase voltage
bits 0-3 BCD 100 mV
1Bh
1
1B:
--23
--36
2.3V
bits 4-7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1Ch
1Dh
1Eh
1
1
1
1C:
1D:
1E:
3.6V
8.5V
9.5V
VPP [programming] supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
--85
--95
VPP [programming] supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
n
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
“n” such that typical single word program time-out = 2 µ-sec
1F:
20:
21:
22:
23:
24:
25:
26:
--09
--0A
--0A
--00
--01
--02
--02
--00
512µs
1024µs
1s
n
“n” such that typical full buffer write time-out = 2 µ-sec
n
“n” such that typical block erase time-out = 2 m-sec
n
“n” such that typical full chip erase time-out = 2 m-sec
NA
n
“n” such that maximum word program time-out = 2 times typical
1024µs
4096µs
4s
n
“n” such that maximum buffer write time-out = 2 times typical
n
“n” such that maximum block erase time-out = 2 times typical
n
“n” such that maximum chip erase time-out = 2 times typical
NA
Datasheet
63
Mar 2010
OrderNumber:320003-09
P33-65nm
A.1.4
Device Geometry Definition
Table 33: Device Geometry Definition
Hex
Code
Offset
Length
Description
Add
Value
n
27h
1
“n” such that device size = 2 in number of bytes
27:
See Table Below
Flash device interface code assignment:
"n" such that n+1 specifies the bit field that represents the flash device width
capabilities as described in the table:
7
_
6
_
5
_
4
_
3
x64
11
_
2
x32
10
_
1
x16
9
0
x8
8
28h
2
28:
29:
--01
--00
x16
15
_
14
_
13
_
12
_
_
_
2A:
2B:
--0A
--00
1024
n
2Ah
2Ch
2
1
“n” such that maximum number of bytes in write buffer = 2
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or more contiguous
same-size erase blocks.
2C:
See Table Below
See Table Below
3. Symmetrically blocked partitions have one blocking region
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
Erase Block Region 1 Information
2D
31h
35h
4
4
4
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
Erase Block Region 2 Information
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
See Table Below
See Table Below
Reserved for future erase block region information
256-Mbit
-B
256-Mbit
-B
256-Mbit
Address
Address
Address
-T
-T
-B
-T
27:
28:
29:
2A:
2B:
2C:
--19
--01
--00
--0A
--00
--02
--19
--01
--00
--0A
--00
--02
2D:
2E:
2F:
30:
31:
32:
--03
--00
--80
--00
--FE
--00
--FE
--00
--00
--02
--03
--00
33:
34:
35:
36:
37:
38:
--00
--02
--00
--00
--00
--00
--80
--00
--00
--00
--00
--00
Datasheet
64
Mar 2010
Order Number: 320003-09
P33-65nm
A.1.5
Numonyx-Specific Extended Query Table
Table 34: Primary Vendor-Specific Extended Query
Offset(1) Length
P = 10Ah
Description
(Optional flash features and commands)
Hex
Add. Code Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
Primary extended query table
10A
10B:
10C:
10D:
10E:
10F:
110:
111:
112:
--50
--52
--49
--31
--35
--E6
--09
--00
--40
"P"
"R"
"I"
"1"
"5"
Unique ASCII string “PRI“
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 10–31 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of Optional features follows at
the end of the bit–30 field.
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
bit 8 Synchronous read supported
bit 9 Simultaneous operations supported
bit 10 Extended Flash Array Blocks supported
bit 11 Permanent Block Locking of up to Full Main Array supported
bit 12 Permanent Block Locking of up to Partial Main Array supported
bit 30 CFI Link(s) to follow
bit 0 = 0
No
Yes
Yes
No
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 1
bit 9 = 0
bit 10 = 0
bit 11 = 1
bit 12 = 0
bit 30 = 1
bit 31 = 0
No
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
No
bit 31 Another "Optional Features" field to follow
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
(P+9)h
1
2
113:
--01
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bit 0 = 1
Yes
(P+A)h
(P+B)h
114:
115:
--03
--00
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Dow n Bit Status active
bit 4 EFA Block Lock-Bit Status register active
bit 5 EFA Block Lock-Dow n Bit Status active
bit 0 = 1
Yes
Yes
No
bit 1 = 1
bit 4 = 0
bit 5 = 0
No
(P+C)h
(P+D)h
1
1
V
V
CC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
116:
--18
1.8V
PP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
117:
--90
9.0V
Address
112:
Discrete
512-Mbit
–B
–T
–-
–B
–T
–-
die 1 (B)
--40
die 2 (T)
--00
die 1 (T)
--40
die 2 (B)
--00
--00
--00
Datasheet
65
Mar 2010
OrderNumber:320003-09
P33-65nm
Table 35: OTP Register Information
Offset(1) Length
Description
Hex
P = 10Ah
(P+E)h
(Optional flash features and commands)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Add. Code Value
1
4
118: --02
2
(P+F)h
(P+10)h
(P+11)h
(P+12)h
Protection Field 1: Protection Description
119: --80
11A: --00
80h
00h
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed
w ith device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The follow ing bytes are factory
pre-programmed and user-programmable.
11B: --03 8 byte
11C: --03 8 byte
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
(P+18)h
(P+19)h
(P+1A)h
(P+1B)h
(P+1C)h
10
Protection Field 2: Protection Description
Bits 0–31 point to the Protection register physical Lock-w ord
address in the Jedec-plane.
11D: --89
11E: --00
11F: --00
120: --00
121: --00
122: --00
123: --00
124: --10
125: --00
89h
00h
00h
00h
0
Follow ing bytes are factory or user-programmable.
bits 32–39 = “n” such that n = factory pgm'd groups (low byte)
bits 40–47 = “n” such that n = factory pgm'd groups (high byte)
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n” such that n = user pgm'd groups (low byte)
0
0
16
0
16
bits 64–71 = “n” such that n = user pgm'd groups (high byte)
bits 72–79 = “n” such that 2n = user programmable bytes/group
126:
--04
Datasheet
66
Mar 2010
Order Number: 320003-09
P33-65nm
Figure 30: Burst Read Information
Offset(1) Length
P = 10Ah
Description
(Optional flash features and commands)
Page Mode Read capability
Hex
Add. Code Value
(P+1D)h
1
127:
--05 32 byte
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device w ord w idth to
determine page-mode data output w idth. 00h indicates no
read page buffer.
(P+1E)h
(P+1F)h
1
1
Number of synchronous mode read configuration fields that follow . 00h
indicates no burst capability.
128:
129:
--04
--01
4
4
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
Bits 0–2 “n” such that 2n+1 HEX value represents the maximum number of
continuous synchronous reads w hen the device is configured for its maximum
w ord w idth. A value of 07h indicates that the device is capable of continuous
linear bursts that w ill output data until the internal burst counter reaches the end
of the device’s burstable address space. This field’s 3-bit value can be w ritten
directly to the Read Configuration Register bits 0–2 if the device is configured
for its maximum w ord w idth. See offset 28h for w ord w idth to determine the
burst data output w idth.
(P+20)h
(P+21)h
(P+22)h
1
1
1
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
12A:
12B:
12C:
--02
--03
--07
8
16
Cont
Table 36: Partition and Erase Block Region Information
Offset(1)
P = 10Ah
Bottom Top
See table below
Address
Description
(Optional flash features and commands)
Bot
Top
Len
Number of device hardw are-partition regions w ithin the device.
x = 0: a single hardw are partition device (no fields follow ).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
1
12D:
12D:
(P+23)h (P+23)h
Datasheet
67
Mar 2010
OrderNumber:320003-09
P33-65nm
Table 37: Partition Region 1 Information (Sheet 1 of 2)
Offset(1)
See table below
Address
P = 10Ah
Bottom Top
Description
(Optional flash features and commands)
Bot
Top
12E
12F
130:
131:
132:
Len
(P+24)h (P+24)h Data size of this Parition Region Information field
(P+25)h (P+25)h (# addressable locations, including this field)
(P+26)h (P+26)h Number of identical partitions w ithin the partition region
(P+27)h (P+27)h
2
12E:
12F
130:
131:
132:
2
1
(P+28)h (P+28)h Number of programor erase operations allow ed in a partition
bits 0–3 = number of simultaneous Programoperations
bits 4–7 = number of simultaneous Erase operations
(P+29)h (P+29)h Simultaneous programor erase operations allow ed in other partitions w hile a
partition in this region is in Program mode
1
1
1
133:
134:
135:
133:
134:
135:
bits 0–3 = number of simultaneous Programoperations
bits 4–7 = number of simultaneous Erase operations
(P+2A)h (P+2A)h Simultaneous programor erase operations allow ed in other partitions w hile a
partition in this region is in Erase mode
bits 0–3 = number of simultaneous Programoperations
bits 4–7 = number of simultaneous Erase operations
(P+2B)h (P+2B)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w / contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Datasheet
68
Mar 2010
Order Number: 320003-09
P33-65nm
Table 38: Partition Region 1 Information (Sheet 2 of 2)
Offset(1)
See table below
Address
P = 10Ah
Bottom Top
Description
(Optional flash features and commands)
Bot
Top
136:
137:
138:
139:
13A:
13B:
13C:
Len
(P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information
4
136:
137:
138:
139:
13A:
13B:
13C:
(P+2D)h (P+2D)h
(P+2E)h (P+2E)h
(P+2F)h (P+2F)h
(P+30)h (P+30)h Partition 1 (Erase Block Type 1)
(P+31)h (P+31)h Block erase cycles x 1000
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2
1
(P+32)h (P+32)h Partition 1 (erase block Type 1) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+33)h (P+33)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities
defined in Table 10.
1
6
13D:
13D:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition Region 1 (Erase Block Type 1) Programming Region Information
(P+34)h (P+34)h
(P+35)h (P+35)h
(P+36)h (P+36)h
(P+37)h (P+37)h
(P+38)h (P+38)h
(P+39)h (P+39)h
bits 0–7 = x, 2^x = Programming Region aligned size (
)
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
bytes
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode
bits 24-31 = Reserved
size in bytes
valid
bits 32-39 = z = Control Mode
size in bytes
invalid
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
(P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information
4
(P+3B)h (P+3B)h
(P+3C)h (P+3C)h
(P+3D)h (P+3D)h
(P+3E)h (P+3E)h Partition 1 (Erase Block Type 2)
(P+3F)h (P+3F)h Block erase cycles x 1000
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2
1
(P+40)h (P+40)h Partition 1 (erase block Type 2) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+41)h (P+41)h Partition 1 (erase block Type 2) page mode and synchronous mode capabilities
defined in Table 10.
1
6
14B:
14B:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
Partition Region 1 (Erase Block Type 2) Programming Region Information
(P+42)h (P+42)h
(P+43)h (P+43)h
(P+44)h (P+44)h
(P+45)h (P+45)h
(P+46)h (P+46)h
(P+47)h (P+47)h
bits 0–7 = x, 2^x = Programming Region aligned size (
)
14C:
14D:
14E:
14F:
150:
151:
bytes
14C:
14D:
14E:
14F:
150:
151:
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode
bits 24-31 = Reserved
size in bytes
valid
bits 32-39 = z = Control Mode
size in bytes
invalid
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
Datasheet
69
Mar 2010
OrderNumber:320003-09
P33-65nm
Table 39: Partition and Erase Block Region Information
Address 256-Mbit
12D:
–B
–T
--01
--24
--00
--01
--00
--11
--00
--00
--02
--03
--00
--80
--00
--64
--00
--02
--03
--00
--80
--00
--00
--00
--80
--FE
--00
--00
--02
--64
--00
--02
--03
--00
--80
--00
--00
--00
--80
--01
--24
--00
--01
--00
--11
--00
--00
--02
--FE
--00
--00
--02
--64
--00
--02
--03
--00
--80
--00
--00
--00
--80
--03
--00
--80
--00
--64
--00
--02
--03
--00
--80
--00
--00
--00
--80
12E:
12F:
130:
131:
132:
133:
134:
135:
136:
137:
138:
139:
13A
13B:
13C:
13D:
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A
14B:
14C:
14D:
14E:
14F:
150:
151:
Datasheet
70
Mar 2010
Order Number: 320003-09
P33-65nm
Table 40: CFI Link Information
Length
Description
(Optional flash features and commands)
CFI Link Field bit definitions
Hex
Code
Add.
152:
153:
154:
155:
Value
4
Bits 0–9 = Address offset (w ithin 32Mbit segment) of referenced CFI table
Bits 10–27 = nth 32Mbit segment of referenced CFI table
Bits 28–30 = Memory Type
See table below
See table below
Bit 31 = Another CFI Link field immediately follow s
CFI Link Field Quantity Subfield definitions
Bits 0–3 = Quantity field (n such that n+1 equals quantity)
Bit 4 = Table & Die relative location
1
156:
Bit 5 = Link Field & Table relative location
Bits 6–7 = Reserved
Address
Discrete
512-Mbit
–B
–-
–T
–-
–B
die 1 (B) die 2 (T)
–T
die 1 (T)
--10
--20
--00
--00
die 2 (B)
--FF
--FF
--FF
--FF
152:
153:
154:
155:
156:
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--10
--20
--00
--00
--10
--FF
--FF
--FF
--FF
--FF
--10
--FF
Datasheet
71
Mar 2010
OrderNumber:320003-09
P33-65nm
A.2
Flowcharts
Figure 31: Word Program Flowchart
Start
Command Cycle
- Issue Program Command
- Address = location to program
- Data = 0x40
Data Cycle
- Address = location to program
- Data = Data to program
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal D7
No
No
Program Suspend
See Suspend/
Resume Flowchart
No
D7 = '1'
?
Suspend
?
Errors
?
Yes
Yes
Yes
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
Error-Handler
User Defined Routine
End
Datasheet
72
Mar 2010
Order Number: 320003-09
P33-65nm
Figure 32: Program Suspend/Resume Flowchart
PROGRAM SUSPEND/ RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Read Status
Read
Data= 70h
Write
Write
Status Addr= Block to suspend (BA)
Write70h
Any Address
Program Data= B0h
Suspend Addr= X
Program Suspend
Write B0h
Any Address
Status register data
Initiate a read cycle to update Status
register
Read
Read Status
Register
Addr= Suspended block (BA)
Check SR.7
Standby
Standby
1= WSM ready
0= WSM busy
0
0
SR.7=
1
Check SR.2
1= Program suspended
0= Program completed
Program
Completed
SR.2 =
1
Read
Array
Data= FFh
Addr= Block address to read(BA)
Write
Read
Write
Read Array
Write FFh
Any Address
Read array data from block other than
the one being programmed
Read Array
Data
Program Data= D0h
Resume Addr= Suspended block (BA)
Done
No
Reading
Yes
Program Resume
Read Array
Write FFh
Write D0h
Any Address
Program
Resumed
Read Array
Data
Read Status
Write70h
Any Address
PGM_SUS. WMF
Datasheet
73
Mar 2010
OrderNumber:320003-09
P33-65nm
Figure 33: Buffer Program Flowchart
Bus
Operation
Command
Comments
Data =E8H
Write to
Buffer
Write
Addr = Block Address
Start
SR. 7 = Valid
Addr = Block Address
Read
(Note 7)
Device
Supports Buffer
Writes?
Check SR.7
1 = Device WSM is Busy
0 = Device WSM is Ready
Use Single Word
Programming
No
Standby
Yes
Data =N-1 = Word Count
N = 0 corresponds to count=1
Addr = Block Address
Write
( Notes1, 2)
Set Timeout or
Loop Counter
Write
( Notes3, 4)
Data = Write Buffer Data
Addr = Start Address
Get Next
Target Address
Write
( Notes5, 6)
Data = Write Buffer Data
Addr = Block Address
Issue Write to Buffer
Command E8h and
Block Address
Program
Confirm
Data =D0H
Addr = Block Address
Write
Read
Status register Data
CE # and OE# low updates SR
Addr = Block Address
Read Status Register
Block Address
(note 7)
Check SR.7
1 = WSM Ready
0 = WSM Busy
No
Standby
Timeout
or Count
Expired?
0 = No
Is WSM Ready?
SR. 7=
Notes:
Yes
.
1. Word count values on DQ0-DQ15 are loaded into the Count
register. Count ranges for this device are N=0000h to 00FFh.
1 = Yes
2. The device outputs the status register when read.
Write Word Count
Block Address
3. Write Buffer contents will be programmed at the device start
address or destination flash address.
Write Buffer Data
Start Address
X = X + 1
4. Align the start address on a Write Buffer boundary for maximum
programming performance (i.e., A8-A1 of the start address =0).
.
Write Buffer Data
Block Address
5. The device aborts the Buffered Program command if the
X =0
current address is outside the original block address .
No
.
6. The Status register indicates an “improper command
Sequence” if the Buffered Program command is aborted. Follow
this with a Clear Status Register command .
No
Abort Bufferred
Program?
X =N?
Yes
7. The device default state is to output SR data after the Buffered
Programming Setup Command (E8h).CE# and OE low drive the
device to update Status Register . It is not allowed to issue 70h to
read SR data after E8h command otherwise 70h would be
counted as Word count.
Yes
Write Confirm D0h
and Block Address
Write to another
Block Address
Buffered Program
Aborted
8. Full status check can be done after all erase and write
sequences complete . Write FFh after the last operation to reset
the device to read array mode.
Read Status Register
No
Suspend
Program
Loop
Yes
Suspend
Program
0
SR. 7=?
1
Full Status
Check if Desired
Yes
Another Buffered
Programming?
No
Program Complete
Datasheet
74
Mar 2010
Order Number: 320003-09
P33-65nm
Figure 34: BEFP Flowchart
Setup Phase
Start
Program/Verify Phase
Exit Phase
Read Status
Register
Read Status
Register
A
B
Issue BEFP Setup Cmd
(Data = 0x80)
No (SR.0=1)
Buffer Ready ?
No (SR.7=0)
BEFP Exited ?
Issue BEFP Confirm Cmd
(Data = 00D0h)
Yes (SR.0=0)
Write Data Word to Buffer
Yes (SR.7=1)
BEFP
Setup
Delay
Full Status
Register check for
errors
No
Buffer Full ?
Yes
Read Status
Register
Finish
Read Status
Register
Yes (SR.7=0)
BEFP Setup
Done ?
A
No (SR.0=1)
No (SR.7=1)
Program
Done ?
SR Error Handler
(User-Defined)
Yes (SR.0=0)
Exit
Program
Yes
More Data ?
No
Write 0xFFFFh outside Block
B
Datasheet
75
Mar 2010
OrderNumber:320003-09
P33-65nm
Figure 35: Block Erase Flowchart
Start
Command Cycle
- Issue Erase command
- Address = Block to be erased
- Data = 0x20
Confirm Cycle
- Issue Confirm command
- Address = Block to be erased
- Data = Erase confirm (0xD0)
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal SR.7
No
No
Erase Suspend
See Suspend/
Resume Flowchart
Yes
No
SR.7 = '1'
?
Suspend
?
Errors
?
Yes
Yes
Error-Handler
User Defined Routine
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
End
Datasheet
76
Mar 2010
Order Number: 320003-09
P33-65nm
Figure 36: Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Bus
Operation
Start
Command
Comments
Lock Setup
Write 60h
Block Address
Lock
Setup
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Write
Write
Lock,
Unlock, or
Lockdown
Data = 01h (Lock block)
D0h (Unlock block)
Lock Confirm
Write 01,D0,2Fh
Block Address
2Fh (Lockdown block)
Confirm Addr = Block to lock/unlock/lock-down (BA)
Read ID Plane
Write 90h
Write
(Optional)
Read ID Data = 90h
Plane
Addr = Block address offset+2 (BA+2)
Read
(Optional)
Block Lock Block Lock status data
Status Addr = Block address offset+2 (BA+2)
Read Block Lock
Status
Confirm locking change on DQ , DQ0.
(See Block Locking State Transitions Table
for valid combinations.)
1
Standby
(Optional)
Locking
No
Change?
Yes
Read
Array
Data = FFh
Addr = Block address (BA)
Write
Read Array
Write FFh
Any Address
Lock Change
Complete
LOCK_OP.WMF
Datasheet
77
Mar 2010
OrderNumber:320003-09
P33-65nm
Figure 37: Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Read Status
Write 70h
Any Address
Read
Data = 70h
Write
Write
Status Addr = Any device address
Data = B0h
Addr = Same partition address as
Erase
Suspend
above
Erase Suspend
Write B0h
Any Address
Status register data. Toggle CE# or
OE# to update Status register
Addr =X
Read
Read Status
Register
Check SR.7
Standby
1 = WSM ready
0 = WSM busy
0
0
SR.7 =
1
Check SR.6
1 = Erase suspended
0 = Erase completed
Standby
Write
Erase
Completed
SR.6 =
1
Read Array Data = FFh or 40h
or Program Addr = Block to program or read
Read or
Write
Read array or program data from/to
block other than the one being erased
Read
Program
Read or
Program?
Read Array
Data
Program
Loop
Program Data = D0h
Resume Addr = Any address
No
Write
Done?
Yes
Erase Resume
Read Array
Write D0h
Write FFh
Any Address
Any Addres
Erase
Resumed
Read Array
Data
Read Status
Write 70h
Any Address
ERAS_SUS.WMF
Datasheet
78
Mar 2010
Order Number: 320003-09
P33-65nm
Figure 38: OTP Register Programming Flowchart
Start
OTP Program Setup
- Write 0xC0
- OTP Address
Confirm Data
- Write OTP Address and Data
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal SR.7
No
SR.7 = '1'
?
Yes
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
End
Datasheet
79
Mar 2010
OrderNumber:320003-09
P33-65nm
Figure 39: Status Register Flowchart
Start
Command Cycle
- Issue Status Register Command
- Address = any device address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
No
SR7 = '1'
Yes
Yes
- Set/Reset
by WSM
Erase Suspend
See Suspend/Resume Flowchart
SR6 = '1'
No
Yes
Program Suspend
See Suspend/Resume Flowchart
SR2 = '1'
No
Error
Command Sequence
Yes
Yes
SR5 = '1'
SR4 = '1'
No
No
Error
Erase Failure
Yes
Error
Program Failure
SR4 = '1'
No
- Set by WSM
- Reset by user
- See Clear Status
Register Command
Yes
Error
< VPENLK/PPLK
SR3 = '1'
VPEN/PP
No
Yes
Error
Block Locked
SR1 = '1'
No
End
Datasheet
80
Mar 2010
Order Number: 320003-09
P33-65nm
A.3
Write State Machine
Show here are the command state transitions (Next State Table) based on incoming
commands. Only one partition can be actively programming or erasing at a time. Each
partition stays in its last read state (Read Array, Read Device ID, Read CFI or Read
Status Register) until a new command changes it. The next WSM state does not depend
on the partition’s output state.
Note:
IS refers to Illegal State in the Next State Tables.
Table 41: Next State Table for P3x-65nm (Sheet 1 of 3)
(1)
Command Input and Resulting Chip Next State
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
N/A
N/A
N/A
Ready
Ready
Ready
Ready
(Lock
Error
[Botc
h])
Ready
Ready
(Lock
Block
)
(Lock Ready
Ready (Lock
Error [Botch])
Ready (Lock Error
[Botch])
down (Set N/A
Lock/RCR/ECR Setup
Ready (Lock Error [Botch])
Block CR)
)
Setup
OTP Busy
IS in
OTP Busy
N/A
OTP Busy
OTP Busy
N/A
Ready
N/A
OTP
IS in OTP
Busy
Illegal State in OTP
Busy
Busy
OTP
OTP Busy
OTP Busy
OTP Busy
N/A
OTP
Busy
Busy
OTP Busy
IS in OTP Busy
Setup
OTP Busy
Word Program Busy
N/A
N/A
Pgm Busy
Pgm Busy
IS in
Pgm
Busy
IS in Pgm
Busy
Pgm Pgm
IS in Word Pgm
Busy
Busy
Pgm
Pgm Busy
Word Pgm Busy
Word Pgm Busy
Busy Susp
Ready
Busy
IS in Pgm Busy
Word Pgm Busy
Pgm
Word
Program
IS in
Pgm
Susp
Susp Word
Pgm
Susp
Pgm
Suspend
IS in Pgm
Susp
Pgm
Busy
Illegal State in Pgm
Suspend
Word Program
Suspend
Suspend
Pgm Susp
(Er
Pgm
N/A
Word Pgm Susp
bits Susp
clear)
N/A
N/A
IS in Pgm
Suspend
EFI Setup
Sub-function
Setup
Sub-op-code
Load 1
Word Program Suspend
Sub-function Setup
Sub-op-code Load 1
Sub-function Load 2 if word count >0, else Sub-function confirm
Sub-function
Load 2
Sub-function
Confirm
Sub-function Confirm if data load in program buffer is complete, ELSE Sub-function Load 2
S-fn
Ready (Error [Botch])
Ready (Error [Botch])
Busy
EFI
IS in
S-fn
Busy
Sub-function
S-fn
Illegal State S-fn S-fn
in S-fn Busy Busy Susp
S-fn Busy
S-fn Busy
IS in S-fn Busy
S-fn Busy
S-fn Busy
S-fn Susp
Busy
Busy
Ready
N/A
IS in Sub-
function Busy
Sub-function Busy
S-fn
IS in
Susp
Sub-function
Susp
S-fn
Susp
Illegal State S-fn
in S-fn Busy Busy
S-fn
Suspend
S-fn
Susp
S-fn Sub-function
Susp
(Er
bits
IS in S-fn Susp
S-fn Suspend
N/A
clear)
IS in S-fn Susp
Sub-function Suspend
Datasheet
81
Mar 2010
OrderNumber:320003-09
P33-65nm
Table 41: Next State Table for P3x-65nm (Sheet 2 of 3)
(1)
Command Input and Resulting Chip Next State
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
Setup
BP Load 1 (8)
BP Load 1
BP Load 2 if word count >0, else BP confirm
BP Confirm if data
load in program
buffer is
complete, else BP
load 2
Ready
(Error
[Botc
h])
N/A
BP Load 2 (8)
BP Confirm if data load in program buffer is complete, ELSE BP load 2
BP
BP Confirm
Ready (Error [Botch])
Ready (Error [Botch])
Buffer
Busy
Pgm
IS in
BP
Busy
BP
Busy
Illegal State
BP
BP
BP Busy
BP Busy
BP Busy
BP Busy
IS in BP Busy
BP Busy
BP Busy
BP Susp
(BP)
in BP Busy Busy Susp
Ready
N/A
IS in BP Busy
BP Susp
BP
Susp
(Er
IS in
BP
Susp
BP
Susp
Illegal State
in BP Busy Busy
BP
BP
Susp
BP Suspend
BP Suspend
IS in BP Susp
BP Suspend
N/A
bits
clear)
IS in BP Susp
Setup
BP Suspend
Erase
Ready (Err
Botch0])
Ready (Error [Botch])
Ready (Error [Botch])
N/A
N/A
Busy
N/A
IS in
Erase Erase Busy
Busy
Erase
Busy
IS in Erase Erase Erase
Busy Busy Susp
Busy
Erase Busy
IS in Erase Busy
Erase Busy
Ers Busy
IS in Erase Busy
Erase Busy
Ready
Lock/
RCR/
ECR
Erase
Word
Pgm
EFI
Setup
in
BP
Setup
in
Erase
Susp
IS in
Erase
Susp
Erase Setup
IS in Erase Erase
Erase
Erase
Susp
Erase
Susp
Suspend
(Er
bits
Setup
in
Erase Suspend
N/A
N/A
Erase Susp
Susp
in
Erase
Susp
Erase
Susp
Suspend
Busy
Suspend
N/A
N/A
Erase
Susp
clear)
Erase
Susp
Erase Suspend
IS in Erase Susp
Setup
Word Pgm busy in Erase Suspend
Word
Pgm
busy
in
Erase
Susp
Word
Word
Pgm
Pgm
IS in
Pgm
busy
Word Pgm
busy in
IS in Word
Pgm busy in
Ers Susp
busy
in
Word Pgm busy in
Erase Susp
IS in Word Pgm
busy in Ers Susp
Word Pgm busy in
Erase Susp
Erase
Susp
Busy
Susp
in Ers
Susp
in Ers Erase Susp
Susp
Erase
Susp
Illegal state(IS)
IS in
Ers
Susp
Word Pgm Busy in
Ers Suspend
in Pgm busy in
Word Pgm busy in Erase Suspend
Word
Erase Suspend
Pgm in
Erase
Suspend
Suspend
Word
Word
Pgm
Susp
in Ers
Susp
(Er
Word iS in
Pgm pgm
Word Word
Pgm Pgm
susp susp
in Ers in Ers
susp susp
Word
Pgm
susp
in Ers
susp
Pgm
busy
in
Word Pgm
iS in pgm
susp in Ers
Susp
iS in Word Pgm
susp in Ers Susp
Word Pgm susp in
Ers susp
susp susp susp in Ers
N/A
in Ers in Ers
susp Susp
susp
Erase
Susp
N/A
bits
clear)
Illegal State in
Word Program
Suspend in Erase
Suspend
Word Pgm busy in Erase Suspend
Setup
BP Load 1 (8)
BP Load 1 in Erase Suspend
BP Load 2 in Erase Suspend if word count >0, else BP confirm
Ers
Susp
(Error
[Botc
h])
BP Confirm in
Erase Suspend
when count=0,
ELSE BP load 2
N/A
BP Load 2 (8)
BP Confirm
BP Confirming Erase Suspend if data load in program buffer is complete, ELSE BP load 2 in Erase Suspend
Erase Suspend (Error [BotchBP])
IS in
Erase Susp (Error [Botch BP])
IS in BP Busy in
BP Busy in Ers Susp N/A
BP
BP
BP
Busy
in Ers
Susp
BP
Illegal State
in BP Busy in
Ers Susp
Busy
in Ers
Susp
BP Busy in
Erase Susp
Susp
in Ers
Susp
BP Busy in Ers
Susp
Erase
Susp
BP in
Erase
BP Busy
Busy
in Ers
Susp
BP Busy in Ers Susp
Erase Suspend
Suspend
IS in
Ers
IS in BP Busy
BP Busy in Erase Suspend
BP
Susp
IS in
BP
Susp
in Ers
Susp
Susp
BP
BP
BP
BP Suspend Illegal State
in Ers
Susp
in Ers
Susp
Busy BP Susp in
Susp
in Ers
Susp
IS in BP Busy in
Erase Suspend
BP Susp in Ers
Susp
BP Susp
in Erase
Suspend
in BP Busy in
Ers Susp
Susp
(Er
BP Susp in Ers Susp N/A
in Ers
Susp
Ers Susp
N/A
bits
clear)
IS in BP Suspend
BP Suspend in Erase Suspend
Datasheet
82
Mar 2010
Order Number: 320003-09
P33-65nm
Table 41: Next State Table for P3x-65nm (Sheet 3 of 3)
(1)
Command Input and Resulting Chip Next State
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
EFI Setup
Sub-function
Setup
Sub-function Setup in Erase Suspend
Sub-op-code Load 1 in Erase Suspend
Sub-op-code
Load 1
Sub-function Load 2 in Erase Suspend if word count >0, else Sub-function confirm in Erase Suspend
Sub-function
Ers
Confirm if data
N/A
Susp load in program
Sub-function
Load 2
Sub-function Confirm in Erase Suspend if data load in program buffer is complete, ELSE Sub-function Load 2
(Error
buffer is
[Botc complete, ELSE
h])
Sub-function
Load 2
Sub-function
Erase Suspend (Error [Botch])
IS in
Erase Suspend (Error [Botch])
Confirm
EFI in
S-fn
Busy
in Ers
Susp
S-fn
Busy
in Ers
Susp
S-fn
Susp
in Ers
Susp
Erase
Suspend
S-fn
Busy
in Ers
Susp
Illegal State
Sub-function
S-fn Busy in
Ers Suspend
S-fn Busy in Ers
Susp
IS in S-fn Busy in
Ers Susp
S-fn Busy in Ers
S-fn Busy in Ers Erase
in S-fn Busy
in Ers Susp
N/A
Busy
Susp
Susp
Susp
IS in
Ers
IS in Sub-
Sub-function Busy in Ers Susp
S-fn
function Busy
Susp
IS in
S-fn
Susp
S-fn
in Ers
Susp IS in S-fn Susp in S-fn Suspend in Ers
S-fn
Susp
in Ers
Susp
S-fn
Busy
in Ers
Susp
S-fn
Illegal State
S-fn
Sub-function
Susp
S-fn Susp in Ers
Susp
Susp Suspend in in S-fn Busy
Suspend in Susp
N/A
in Ers
Susp
Ers Susp
Susp
in Ers
Susp
Ers Susp
in Ers Susp
Ers Susp
(Er
bits
N/A
clear)
IS in Phase-1
Susp
Sub-Function Suspend in Erase Suspend
Ers
Susp
(Un-
lock
Block
)
Ers
Ers
Susp
Blk
Ers
Susp
Blk
Ers
Susp
CR
Lock/RCR/ECR/Lock
EFA Block Setup in
Erase Suspend
Susp
(Error
[Botc
h])
Erase Suspend (Lock Error
[Botch])
Ers Susp (Error
[Botch])
Ers Susp (Lock Error [Botch])
N/A
N/A
N/A
Lk-
Lock
Set
Down
BC
Busy
Ready (Error
[Botch])
Setup
Ready (Error [Botch])
IS in BC Busy
N/A
Ready (Error [Botch])
IS in
Blank
BC
IS in BC
Busy
Blank Check Busy
Check
BC
BC Busy
Blank Check Busy
BP Busy
BC Busy
Busy
Busy
BC Busy
Ready
IS in Blank Check
Busy
BEFP
Load
Data
Setup
Ready (Error [Botch])
Ready (Error [Botch])
N/A
BEFP
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands
treated as data. (7)
BEFP Busy
Ready
BEFP Busy
Ready
Datasheet
83
Mar 2010
OrderNumber:320003-09
P33-65nm
Table 42: Output Next State Table for P3x-65nm
(1)
Command Input to Chip and Resulting Output MUX Next State
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
BEFPSetup,
BEFP Pgm & Verify Busy,
Erase Setup,
OTP Setup,
BP Setup, Load 1, Load 2
BP Setup, Load1, Load 2 - in
Erase Susp.
BP Confirm
EFI Sub-function Confirm
Status Read
WordPgmSetup,
Word Pgm Setup in Erase
Susp,
BP Confirm in Erase Suspend,
EFI S-fn Confirm in Ers Susp,
Blank Check Setup,
Blank Check Busy
Lock/RCR/ECR Setup,
Lock/RCR/ECR Setup in Erase
Susp
Status Read
EFI S-fn Setup, Ld 1, Ld 2
EFI S-fn Setup, Ld1, Ld 2 - in
Erase Susp.
Output MUX will not change
BP Busy
BP Busy in Erase Suspend
EFI Sub-function Busy
EFI Sub-fn Busy in Ers Susp
Word Program Busy,
Word Pgm Busy in Erase
Suspend,
OTP Busy
Erase Busy
Status
Read
Status
Read
Output MUX does
not Change
Status Read
Ready,
Word Pgm Suspend,
BP Suspend,
Phase-1 BP Suspend,
Erase Suspend,
BP Suspend in Erase Suspend
Phase-1 BP Susp in Ers Susp
Notes:
1.
2.
3.
4.
IS refers to Illegal State in the Next State Table.
“Illegal commands” include commands outside of the allowed command set.
The device defaults to "Read Array" on powerup.
If a “Read Array” is attempted when the device is busy, the result will be “garbage” data (we should not tell the user that
it will actually be Status Register data). The key point is that the output mux will be pointing to the “array”, but garbage
data will be output. “Read ID” and "Read Query" commands do the exact same thing in the device. The ID and Query data
are located at different locations in the address map.
The Clear Status command only clears the error bits in the status register if the device is not in the following modes:1.
WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes) 2. Suspend states (Erase
Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend).
5.
6.
7.
BEFP writes are only allowed when the status register bit #0 = 0 or else the data is ignored.
Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register and Blank Check) perform the
operation and then move to the Ready State.
8.
9.
Buffered programming will botch when a different block address (as compared to the address given on the first data write
cycle) is written during the BP Load1 and BP Load2 states.
All two cycle commands will be considered as a contiguous whole during device suspend states. Individual commands will
not be parsed separately. (I.e. If an erase set-up command is issued followed by a D0h command, the D0h command will
not resume the program operation. Issuing the erase set-up places the CUI in an “illegal state”. A subsequent command
will clear the “illegal state”, but the command will be otherwise ignored.
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Appendix B Conventions - Additional Documentation
B.1
Acronyms
BEFP:
CUI :
MLC :
OTP :
PLR :
PR :
Buffered Enhanced Factory Programming
Command User Interface
Multi-Level Cell
One-Time Programmable
one-time programmable Lock Register
one-time programmable Register
Read Configuration Register
Reserved for Future Use
Status Register
RCR :
RFU :
SR :
SRD
Status Register Data
WSM
Write State Machine
B.2
Definitions and Terms
VCC :
Signal or voltage connection
V
:
Signal or voltage level
CC
h :
Hexadecimal number suffix
0b :
0x :
Binary number prefix
hexadecimal number prefix
SR.4 :
Denotes an individual register bit.
Denotes a group of similarly named signals, such as address or data bus.
A[15:0] :
Denotes one element of a signal group membership, such as an individual address
bit.
A5 :
Bit :
Single Binary unit
Eight bits
Byte :
Word :
Kbit :
KByte :
KWord :
Mbit :
MByte :
MWord :
K
Two bytes, or sixteen bits
1024 bits
1024 bytes
1024 words
1,048,576 bits
1,048,576 bytes
1,048,576 words
1,000
M
1,000,000
3.0 V :
9.0 V :
V
(core) and V
(I/O) voltage range of 2.3 V – 3.6 V
CC
CCQ
VPP voltage range of 8.5 V – 9.5 V
A group of bits, bytes, or words within the flash memory array that erase
simultaneously. The P33-65nm has two block sizes: 32 KByte and 128 KByte.
Block :
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P33-65nm
An array block that is usually used to store code and/or data. Main blocks are larger
than parameter blocks.
Main block :
An array block that may be used to store frequently changing data or small system
parameters that traditionally would be stored in EEPROM.
Parameter block :
A device with its parameter blocks located at the highest physical address of its
memory map.
Top parameter device :
Bottom parameter device :
A device with its parameter blocks located at the lowest physical address of its
memory map.
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Appendix C Revision History
Date
Revision Description
Program performance update in front page, Section 25, “Program and Erase
Specifications” and CFI.
specification comments, Table 24, “AC Write Specifications” on page 54.
t
DVWH
Erase/program suspend latency specification update, Table 25, “Program and Erase
Specifications” on page 58.
Leaded TSOP part EOL.
Mar 2010
09
Burst latency update and 40MHz spec update, Table 12, “LC and Frequency Support”
on page 36.
Clarify the capacitance, Table 22, “Capacitance” on page 49.
Ordering Information update.
Update the Block lock Operations, Program Suspend/Resume, Erase Suspend/Resume flowcharts in
Figure 36, Figure 37, Figure 37, backward compatible with 130nm.
Align the sequence error description in Table 11.
Add TSOP 40Mhz Burst Spec, f
, t
, t
, t
, Table 23, “AC Read Specifications -”
CLK CLK CHQV CHTV
Aug 2009
08
on page 49.
Add note 7 in buffer program flowchart Figure 33.
Update V undershoot and overshoot of Note 2 in Table 20.
IL
Update CFI 0x2A data in Section A.1, “Common Flash Interface” .
Add 512 Mbit (256/256) memory map in Figure 1, “P33-65nm Memory Map” on
page 7
Correct RCR.4, RCR.5, RCR.7 and RCR.9 definitions in Table 11, “Read Configuration
Register Description” on page 34
Apr 2009
Dec 2008
07
06
Correct A to A signal naming and remove invalid x8 information in Table 29, “Example of
0
1
Query Structure Output of x16 Devices” on page 62
Correct Page buffer address bits to Four on Section 7.1, “Asynchronous Page-Mode
Read” on page 21.
Correct VHH to V
on Table 19, “DC Current Characteristics” on page 46 note.
PPH
Update the Buffer program flowchart to reflect the read status register;
minor wording modification;
Return to StrataFlash;
Nov 2008
05
Update the buffer program comments for cross 512-Word boundary;
Remove 128M related contents from this document;
Correct A24 to A25 for virtual CE description in section 1.3;
Remove Numonyx Confidential;
TM
Updated Axcell
trademark;
Sep 2008
July 2008
04
03
Remove 64M related content;
Added W28 AC specification;
Fixed Buffered Program Command error in figure 38;
Updated block locking state diagram;
Updated Address range in Memory Map figure;
Changed LSB Address from A0 to A1 in figure7 under dual die configurations section;
Changed LSB Address in ballout and pinout description from A0 back to A1 to match P33 130nm.
June 2008
May 2008
02
01
Corrected SCSP order information
Initial release
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Datasheet
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Mar 2010
Order Number: 320003-09
相关型号：
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