ISD14B20 [NUVOTON]
SINGLE-CHIP, MULTIPLE-MESSAGE VOICE RECORD/PLAYBACK DEVICE;
| 型号： | ISD14B20 |
| 厂家： | 
NUVOTON |
| 描述： | SINGLE-CHIP, MULTIPLE-MESSAGE VOICE RECORD/PLAYBACK DEVICE |
| 文件： | 总27页 (文件大小：993K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISD14B00
ISD14B00
SINGLE-CHIP, MULTIPLE-MESSAGE
VOICE RECORD/PLAYBACK DEVICE
Publication Release Date: Jan 19, 2009
Revision 0.30
ISD14B00
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ...............................................................................................................................3
2. FEATURES.......................................................................................................................................................3
3. BLOCK DIAGRAM............................................................................................................................................5
4. PIN DESCRIPTION ..........................................................................................................................................6
5. FUNCTIONAL DESCRIPTION .........................................................................................................................9
5.1
5.1.1.
5.1.2.
Address Mode........................................................................................................................................... 9
Record (¯R¯E¯C¯) Operation................................................................................................................. 10
Edge-triggered Playback (¯P¯la¯y¯E¯) Operation ................................................................................... 12
Level-triggered Playback (¯P¯la¯y¯L¯) Operation................................................................................... 12
Playback (Supersedes Record) Operation ...................................................................................... 13
XCLK Feature.................................................................................................................................. 14
5.1.3.
5.1.4.
5.1.5.
5.2. Direct Mode............................................................................................................................................. 14
5.3. Other Operations .................................................................................................................................... 17
5.3.1.
Rosc Operation................................................................................................................................ 17
5.3.2.
5.3.3.
5.3.4.
5.3.5.
5.3.6.
LED Operation ................................................................................................................................ 18
Feed-Through mode Operation....................................................................................................... 18
Power-On Playback Operation ........................................................................................................ 18
Automatic Single Message Playback............................................................................................... 18
Power is interrupted Abruptly........................................................................................................... 18
6. ABSOLUTE MAXIMUM RATINGS [1]..............................................................................................................19
6.1. Operating Conditions .............................................................................................................................. 19
7. ELECTRICAL CHARACTERISTICS...............................................................................................................20
7.1. DC Parameters ....................................................................................................................................... 20
7.2. AC Parameters ....................................................................................................................................... 21
8. TYPICAL APPLICATION CIRCUIT.................................................................................................................22
9. PACKAGING...................................................................................................................................................24
9.1. Die Information........................................................................................................................................ 24
10. ORDERING INFORMATION ..........................................................................................................................25
11. VERSION HISTORY.......................................................................................................................................26
Publication Release Date: Jan 19, 2009
Revision 0.30
ISD14B00
1. GENERAL DESCRIPTION
Nuvoton’s ISD14B00 ChipCorder® Series is a single-chip multiple-message record/playback series with dual operating
modes with wide operating voltage ranging from 2.4V to 5.5V. The sampling frequency can be selected from 4 to 12 kHz
via an external resistor, which also determines the duration. The device is designed for mostly standalone applications, and
of course, it can be manipulated by a microcontroller, if necessary.
The two operating modes are Address Mode and Direct Mode. While in Address Mode, both record and playback
operations are manipulated according to the start address and end address specified through the start address and end
address pins. In Direct Mode, the device can configure the memory up to as many as eight similar duration messages,
pending upon the fixed message configuration settings. With the record or playback feature being pre-selected, each
message can be randomly accessed via its message control pin.
The device has a selectable differential microphone input with AGC feature or single-ended analog input, AnaIn,
under feed-through mode. The audio output is either a differential Class-D PWM direct-drive or a single-ended
voltage output (AUX out), depending on the derivative selected.
2. FEATURES
The ISD14B00 is a multiple messages record/playback device with two operational modes: Address Mode and
Direct Mode.
Supply voltage: 2.4V to 5.5V.
External resistor, Rosc, selects sampling frequency and duration.
Sampling Frequency
Rosc
12 kHz
53.3 KΩ
10.6 sec
21.3 sec
42.6 sec
8 kHz
80 KΩ
16 sec
32 sec
64 sec
6.4 kHz
100 KΩ
20 sec
40 sec
80 sec
5.3 kHz
120 KΩ
24 sec
48 sec
96 sec
4 kHz
160 KΩ
32 sec
64 sec
128 sec
ISD14B20
ISD14B40
ISD14B80
Mic+/Mic-: differential microphone inputs.
AGC: automatic gain control for microphone preamp circuit.
F¯T¯: feed-through the AnaIn signal to the speaker outputs while AnaIn is converted from MIC+.
When both F¯T¯ and recording are active, device will record AnaIn signal into memory with AnaIn signal output
to speaker simultaneously.
SP+/SP-: Class-D PWM differential speaker drivers or single-ended voltage output, depending on the
derivative selected.
¯L¯E¯D¯: LED is on during recording.
Automatically power down after each operation cycle.
Playback takes precedence over the recording operationTemperature option: 0C to +50C (die)
Packaging: die only
2.1. Address Mode
While in Address Mode, flexible message duration is defined by start address and end address.
Utilize four start address pins (S0, S1, S2 & S3) and four end address pins (E0, E1, E2 & E3) to specify
the message duration.
Publication Release Date: Jan 19, 2009
Revision 0.30
ISD14B00
¯R¯E¯C¯: Level-hold or Edge-trigger (toggle on-off) recording from start to end addresses.
¯P¯la¯y¯E¯: Edge-trigger playback from start to end address and stops at EOM marker, if EOM is prior to end
address. Toggle on-off.
¯P¯la¯y¯L¯: Level-hold playback from start to end address. Also, if constantly Low, device will loop playback
from start to end address.
2.2. Direct Mode
While Direct Mode is active, utilizing the configuration pins, FMC1, FMC2 & FMC3, to define up to eight
similar duration messages for random access.
The control pins are: M¯¯1 ~ M¯¯8 (message activation) and ¯R¯/P (record or playback selection).
The record or playback operation is pre-defined by the ¯R¯/P pin.
Each message can be randomly accessed via its message control pin (M¯¯1 ~ M¯¯8) and the desired
operation is facilitated accordingly.
Publication Release Date: Jan 19, 2009
Revision 0.30
ISD14B00
3. BLOCK DIAGRAM
Rosc
Clock Control
MIC+_
AnaIn
SP +
Non-Volatile
Multi Level Storage
Array
Antialiasing
Filter
Smoothing
Filter
Pre-
Amp
Amp
Amp
MIC-
SP -
Automatic
Gain Control
(AGC)
Switch
AGC
Power Conditioning
Device & Address Control
VCCA
VCCA
VSSA
VCCD VSSD VCCp VSSP1
VSSP2
Address Trigger: Addr
Direct Trigger:
LED FT
PlayE PlayL
XCLK
S0 S1 S2 S3 E0 E1 E2 E3
REC
M4
FMC1 R/P M1 M2 M3
M5 M6 M7 M8
Drct LED FT FMC3 FMC2
Publication Release Date: Jan 19, 2009
Revision 0.30
ISD14B00
4. PIN DESCRIPTION
PIN NAME
VSSD
S0/M¯¯1
PIN # I / O
FUNCTION
Digital Ground: Ground path for digital circuits.
1
2
I
I
S0[1] : In Address Mode, Start Address Bit 0.
M¯¯1: When Direct Mode is active, low active operation on 1st Message.
Internal pull-up & debounce existed.
S1/M¯¯2
S2/M¯¯3
3
4
5
6
I
I
I
I
S1[1] : In Address Mode, Start Address Bit 1.
M¯¯2: When Direct Mode is active, low active operation on 2nd Message.
Internal pull-up & debounce existed.
S2[1] : In Address Mode, Start Address Bit 2.
M¯¯3: When Direct Mode is active, low active operation on 3rd Message.
Internal pull-up & debounce existed.
S3/M¯¯4
S3[1] : In Address Mode, Start Address Bit 3.
M¯¯4: When Direct Mode is active, low active operation on 4th Message.
Internal pull-up & debounce existed.
¯P¯la¯y¯L¯/FMC1
¯P¯la¯y¯L¯: In Address Mode, low active input, Level-hold playback start to end
addresses, debounce & internal pull-up existed. Holding ¯P¯la¯y¯L¯ Low
constantly will perform looping playback function from start to end
addresses with insignificant dead time between messages regardless of
sampling frequencies.
FMC1: When Direct Mode is active, FMC1, together with FMC2 & FMC3,
setup various fixed-message configurations.
E0/M¯¯5
7
I
E0[1] : In Address Mode, End Address Bit 0.
M¯¯5: When Direct Mode is active, low active operation on 5th Message.
Internal pull-up & debounce existed.
VSSA
E1/M¯¯6
8
9
I
I
Analog Ground: Ground path for analog circuits.
E1[1] : In Address Mode, End Address Bit 1.
M¯¯6: When Direct Mode is active, low active operation on 6th Message.
Internal pull-up & debounce existed.
E2/M¯¯7
10
I
E2[1] : In Address Mode, End Address Bit 2.
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Revision 0.30
ISD14B00
PIN NAME
PIN # I / O
FUNCTION
M¯¯7: When Direct Mode is active, low active operation on 7th Message.
Internal pull-up & debounce existed.
E3/M¯¯8
11
I
E3[1] : In Address Mode, End Address Bit 3.
M¯¯8: When Direct Mode is active, low active operation on 8th Message.
Internal pull-up & debounce existed.
VSSP2
SP-
12
13
I
O
Ground: Ground for negative PWM speaker driver.
SP-: Negative signal of the differential Class-D PWM speaker outputs. This
output, together with the SP+, is used to drive an 8Ω speaker directly.
Speaker Power Supply: Power supply for PWM speaker drivers.
Depending on the derivative selected, it could be:
SP+: Positive signal of the differential Class-D PWM speaker outputs. This
output, together with the SP-, is used to drive an 8Ω speaker directly.
Or,
VCCP
SP+
14
15
I
O
AUX out: single-ended voltage output.
VSSP1
AGC
16
17
I
I
Ground: Ground for positive PWM speaker driver.
Automatic Gain Control (AGC): The AGC adjusts the gain of the
preamplifier dynamically to compensate for the wide range of microphone
input levels. The AGC allows the full range of signals to be recorded with
minimal distortion. The AGC is designed to operate with a nominal capacitor
of 4.7 µF connected to this pin.
Connecting this pin to ground (VSSA) provides maximum gain to the
preamplifier circuitry. Conversely, connecting this pin to the power supply
(VCCA) provides minimum gain to the preamplifier circuitry.
MIC+ / AnaIn
18
I
MIC+: Non-inverting input of the differential microphone signal.
AnaIn: When F¯T¯ is selected, the MIC+ input is configured to a single-
ended input with 1Vp-p maximum input amplitude and feed-through to the
speaker outputs.
MIC- / NC
Rosc
19
20
I
I
MIC-: Inverting input of the differential microphone signal. While F¯T¯ is
enabled, MIC- pin is disabled and must be floated.
Oscillator Resistor: Connect an external resistor from this pin to VSSA to
select the internal sampling frequency.
VCCA
¯L¯E¯D¯
21
22
I
O
Analog Power Supply: Power supply for analog circuits.
LED output: During recording, this output is Low. Also, ¯L¯E¯D¯ pulses Low
momentarily at the end of playback.
¯P¯la¯y¯E¯/FMC2
23
I
¯P¯la¯y¯E¯: In Address Mode, low active input, edge-trigger playback from start
to end addresses & toggle on-off. Debounce & internal pull-up existed.
FMC2: When Direct Mode is active, FMC2, together with FMC1 & FMC3,
setup various fixed-message configurations.
¯R¯E¯C¯/¯R¯/P
24
I
¯R¯E¯C¯: In Address Mode, level-hold (after 1 sec holding) or edge-trigger
(toggle on-off), low active, recording from start to end addresses. Debounce
& internal pull-up existed.
Publication Release Date: Jan 19, 2009
- 7 -
Revision 0.30
ISD14B00
PIN NAME
PIN # I / O
FUNCTION
¯R¯/P ( When Direct Mode is active):
When ¯R¯/P is set to Low, level-hold record operation is selected.
When ¯R¯/P is set to High, edge-trigger & toggle on-off playback operation is
selected.
¯X¯C¯L¯K¯/FMC3
25
I
External Clock: In Address Mode, low active and level-hold input. As ¯X¯C¯L¯K¯
activated, Rosc pin accepts external clock input signal, provided resistor at
Rosc must be removed. Connecting this pin to High enables device running
on internal clock via Rosc resistor. If not used, ¯X¯C¯L¯K¯ must be at high level.
When Direct Mode is active, FMC3, together with FMC1 & FMC2, setup
various fixed-message configurations.
F¯T¯
26
27
I
I
Feed-Through: Low active input, Level-hold, debounce & Internal pull-up
required. When F¯T¯ is selected, the MIC+ input is configured to a single-
ended input with 1Vp-p maximum input amplitude and feed-through to the
speaker outputs.
Addr/¯D¯r¯c¯t
Level-hold input.
Addr: When set to High, the device operates under Address Mode.
Level-hold input.
¯D¯r¯c¯t : When set to Low, the device operates under Direct Mode. The
device reconfigures its pin definitions to fit various fixed-message
configurations utilizing FMC1 , FMC2 & FMC3 pins as below table.
FMC3
FMC2
FMC1
# of fixed messages
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
VCCD
28
I
Digital Power Supply: Power supply for digital circuits.
Notes: [1] : Address bits S0, S1, S2, S3, E0, E1, E2 & E3 are used to access the memory location.
Publication Release Date: Jan 19, 2009
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Revision 0.30
ISD14B00
5. FUNCTIONAL DESCRIPTION
There are two operational modes: Address Mode and Direct Mode. After a new condition is selected
on Addr/¯D¯r¯c¯t , the power must be cycled to enable it.
5.1 ADDRESS MODE
The start address pins (S0, S1, S2 & S3) and end address pins (E0, E1, E2 & E3) are used to
access the memory location and they can divide the memory into a maximum of 16 slots. They
are defined as follows, under 8K sampling frequency:
S3
E3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
E2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
E1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
E0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Row #
I14B20
Duration [s]
0
(
)
(
)
(
)
(
)
0
8
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
16
24
32
40
48
56
64
72
80
88
96
104
112
120
9.0
10.0
11.0
12.0
13.0
14.0
15.0
S3
E3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
E2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
E1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
E0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Row #
I14B40
Duration [s]
0
(
)
(
)
(
)
(
)
0
16
32
48
64
80
96
112
128
144
160
176
192
208
232
240
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
Publication Release Date: Jan 19, 2009
Revision 0.30
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ISD14B00
S3
E3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
E2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
E1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
E0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Row #
I14B80
Duration [s]
0
(
)
(
)
(
)
(
)
0
32
64
96
4.0
8.0
12.0
16.0
20.0
24.0
28.0
32.0
36.0
40.0
44.0
48.0
52.0
56.0
60.0
128
160
192
224
256
288
320
352
384
416
464
480
Below is an example:
Given sampling rate set to 6.4 kHz, using the ISD14B20 to record four messages: three messages of
2.5 seconds and one message of 12.5 seconds, then the memory can be assigned as follows:
S3, S2, S1, S0
E3, E2, E1, E0
Message 1 (2.5 seconds)
Message 2 (2.5 seconds)
Message 3 (2.5 seconds)
Message 4 (12.5 seconds)
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
1
1
1
1
1
5.1.1. Record (¯R¯E¯C¯) Operation
Low active input:
o
o
level-hold for level-trigger or
falling edge for edge-trigger with debounce required.
For 8kHz sampling frequency, if ¯R¯E¯C¯ is held at Low for a period equal to 1 sec or more, then
level recording is activated. However, if ¯R¯E¯C¯ is pulsed Low for less than 1 sec, then edge-
trigger recording is initiated.
For 6.4kHz sampling frequency, if ¯R¯E¯C¯ is held at Low for a period equal to 1.25 sec or more,
then level recording is activated. However, if ¯R¯E¯C¯ is pulsed Low for less than 1.25 sec, then
edge-trigger recording is initiated.
Recording begins from the start address to end address and ¯L¯E¯D¯ is on.
Recording ceases whenever:
.
¯R¯E¯C¯ returns to High in level-hold mode or
Publication Release Date: Jan 19, 2009
Revision 0.30
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ISD14B00
.
.
a subsequent low-pulse appears while in edge-trigger mode or
when end address is reached.
o
o
Then an EOM marker is written at the end of message. And ¯L¯E¯D¯ is off.
Then the device will automatically power down.
This pin has an internal pull-up device.
Once ¯R¯E¯C¯ is active, input on F¯T¯, Addr/¯D¯r¯c¯t , S0, S1, S2, S3, E0, E1, E2 or E3 is illegal.
Addr/Drct
<S3:S0>
<E3:E0>
TASet
TAHold
REC
LED
TDeb
TStop1
TErs
Mic+/-
or AnaIn
End Address
Figure 5-1 Record–Level (¯R¯E¯C¯) function till end address
Addr/Drct
<S3:S0>
<E3:E0>
TAHold
TASet
TASet
TAHold
Start
REC
LED
Start
TDeb
Stop
TSettle1
TDeb
TDeb
TStop1
TErs
TErs
Mic+/-
or AnaIn
End Address
Figure 5-2 Record–Level (¯R¯E¯C¯) function with start and stop actions
Publication Release Date: Jan 19, 2009
Revision 0.30
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ISD14B00
Addr/Drct
<S3:S0>
<E3:E0>
TAHold
Start
TAHold
Start
TASet
Stop
TASet
REC
LED
TDeb
TSettle1
TDeb
TDeb
TStop1
TErs
TErs
Mic+/-
or AnaIn
End Address
Figure 5-3 Record–Edge (¯R¯E¯C¯) function with on-off
5.1.2. Edge-triggered Playback (¯P¯la¯y¯E¯) Operation
Low active input, edge-trigger, toggle on-off, debounce required.
Playback begins from the start address to end address or EOM, whichever occurrs first.
At the end of message, ¯L¯E¯D¯ pulses Low momentarily.
o
Then device will automatically power down.
During playback, a subsequent trigger terminates the playback operation. If EOM marker is not
encountered, then ¯L¯E¯D¯ will not pulses Low momentarily.
This pin has an internal pull-up device.
Once ¯P¯la¯y¯E¯ is active, input on ¯P¯la¯y¯L¯, ¯R¯E¯C¯, F¯T¯, Addr/¯D¯r¯c¯t , S0, S1, S2, S3, E0, E1, E2 or
E3 is banned.
Addr/Drct
<S3:S0>
<E3:E0>
TAHold
Start
TASet
Stop
TAHold
Start
TASet
PlayE
LED
TEOM
TDeb
TDeb
TSettle2
TDeb
End of
Message
Sp+
Sp-
Figure 5-4 Playback–Edge (¯P¯la¯y¯E¯) function
5.1.3. Level-triggered Playback (¯P¯la¯y¯L¯) Operation
Low active input, Level-hold, debounce required.
Once active, playback begins from the start address and stops whenever ¯P¯la¯y¯L¯ returns to
High. When an EOM is encountered, ¯L¯E¯D¯ pulses Low momentarily.
Publication Release Date: Jan 19, 2009
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Revision 0.30
ISD14B00
o
Then device will automatically power down.
This pin has an internal pull-up device.
Once ¯P¯la¯y¯L¯ is active, input on ¯P¯la¯y¯E¯, ¯R¯E¯C¯, F¯T¯, Addr/¯D¯r¯c¯t , S0, S1, S2, S3, E0, E1, E2 or
E3 is prohibited.
Addr/Drct
<S3:S0>
<E3:E0>
TASet
TAHold
Start
TDeb
TASet
TAHold
Start
PlayL
LED
Stop
TSettle2
TEOM
TDeb
TDeb
Part of
Message
End of
Message
Sp+
Sp-
Figure 5-5 Playback–Level (¯P¯la¯y¯L¯) function
Holding ¯P¯la¯y¯L¯ Low constantly will perform looping playback function, without power down, from
start address to end address.
Addr/Drct
<S3:S0>
<E3:E0>
TASet
TAHold
PlayL
TDeb
TEOM
TEOM
LED
Sp+
Sp-
Figure 5-6 Looping playback function via ¯P¯la¯y¯L¯
5.1.4. Playback (Supersedes Record) Operation
Playback takes precedence over the Recording operation.
If either ¯P¯la¯y¯E¯ or ¯P¯la¯y¯L¯ is activated during a recording cycle, the recording immediately ceases
with an EOM marker attached, and without power down, playback of the just-recorded message
performs accordingly. Then device powers down.
Publication Release Date: Jan 19, 2009
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Revision 0.30
ISD14B00
Addr/Drct
<S3:S0>
<E3:E0>
TAHold
TASet
REC
LED
TEOM
TDeb
TErs
Mic+/-
or AnaIn
TSettle1 TSettle3
PlayE
TDeb
SP+
SP-
Figure 5-7 An example of Playback supersedes Record
5.1.5. XCLK Feature
When precision sampling frequency is required, external clock mode can be activated by setting
¯X¯C¯L¯K¯ to Low. Under such condition, the resistor at Rosc pin must be removed and the external
clock signal must be applied to the Rosc pin. These conditions must be satisfied prior to any
operations.
However, when internal clock is used, ¯X¯C¯L¯K¯ must be linked to High.
The external clock frequencies required for various sampling frequencies are listed in below table.
Sampling Freq [kHz]
¯X¯C¯L¯K¯ [MHz]
12
3.072
8
6.4
1.638
5.3
1.356
4
2.048
1.024
5.2.
DIRECT MODE
The Direct Mode is selected by the ¯D¯r¯c¯t pin. Once chosen, the supply voltage must be reset to
allow the device to construct itself to the appropriate configuration by re-defining the function on
the related control pins. Also, the mode change is only allowed while the device is in power down
state and is inhibited when an operation is in progress.
Once Direct Mode is activated, FMC1, FMC2 & FMC3 are utilized to select various (1 to 8) fixed
[1]
message configurations
.
Pending upon the arrangement on FMC1, FMC2 & FMC3, each
divided message has approximate equal length of duration, which is related to the number of rows
assigned as in tables below.
The record or playback operation is pre-defined by the ¯R¯/P pin. Setting this pin to Low allows
record operation while setting it to High enables playback operation.
Each message can be randomly accessed via its message control pin (M¯¯1 ~ M¯¯8) and the desired
operations are facilitated accordingly. Non-configured pins are automatically disabled and must
be floated.
Publication Release Date: Jan 19, 2009
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Revision 0.30
ISD14B00
Notes: [1] : Number of fixed message arrangement with respect to FMC1, FMC2 & FMC3.
# of fixed messages [1]
FMC2
FMC1
FMC3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
[2]
: Number of memory row arrangement with respect to different number of fixed
messages for ISD14B20 (128 Rows). The non-configured Message control pins
(Mx) will be disabled.
# of
Msg
1
2
3
4
5
6
7
8
M1
128
64
44
32
26
23
20
16
M2
M3
M4
M5
M6
M7
M8
64
42
32
26
21
18
16
42
32
26
21
18
16
32
26
21
18
16
24
21
18
16
21
18
16
18
16
16
for ISD14b40 (256 Rows)
# of
Msg
1
2
3
4
5
6
7
8
M1
256
128
86
64
52
43
37
32
M2
M3
M4
M5
M6
M7
M8
128
85
64
51
43
37
32
85
64
51
43
37
32
64
51
43
37
32
51
42
36
32
42
36
32
36
32
32
for ISD14B80 (512 Rows)
# of
Msg
M1
512
256
172
128
103
M2
M3
M4
M5
M6
M7
M8
1
2
3
4
5
256
170
128
103
170
128
102
128
102
102
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Revision 0.30
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ISD14B00
6
7
8
86
74
64
86
73
64
85
73
64
85
73
64
85
73
64
85
73
64
73
64
64
[3] : The durations for various fixed message configurations on I14B20 device at
8 kHz sampling frequency are shown in below table.
# of
Msg
1
M1
16
M2
M3
M4
M5
M6
M7
M8
2
8
8
3
4
5
5.5
4.0
3.25
5.25
4.0
3.25
5.25
4.0
3.25
4.0
3.25
3.0
6
2.875 2.625 2.625 2.625 2.625 2.625
7
8
2.50
2.0
2.25
2.0
2.25
2.0
2.25
2.0
2.25
2.0
2.25
2.0
2.25
2.0
2.0
for ISD14B40 (256 Rows)
# of
Msg
1
2
M1
32
16
10.75 10.625 10.625
M2
M3
M4
M5
M6
M7
M8
16
3
4
5
6
7
8.0
6.5
8.0
6.375
8.0
8.0
6.375
5.375
4.625
4.0
6.375 6.375
5.375 5.25
4.625 4.5
5.375 5.375
4.625 4.625
4.0
5.25
4.5
4.0
4.5
4.0
8
4.0
4.0
4.0
4.0
for ISD14B80 (512 Rows)
# of
Msg
1
2
M1
64
32
M2
32
M3
M4
M5
M6
M7
M8
3
4
21.5
16.0
21.25
16.0
21.25
16.0
16.0
5
12.875 12.875 12.75
12.75
12.75
6
7
8
10.75
9.25
8.0
10.75
9.125
8.0
10.625 10.625 10.625 10.625
9.125
8.0
9.125
8.0
9.125
8.0
9.125
8.0
9.125
8.0
8.0
Publication Release Date: Jan 19, 2009
Revision 0.30
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ISD14B00
Example of four Fixed-Message Configuration:
Addr/Drct
FM3
FM2
FM1
TFSet
R / P
Stop
TSettle1
Start
M1 ~ M4
Start
TDeb
TDeb
TDeb
LED
TStop1
End of Duration
TErs
TErs
Mic+/-
or AnaIn
Figure 5-8 Record Operation under FMC mode
Addr/Drct
FM3
FM2
FM1
TFSet
R / P
Start
Stop
Start
M1 ~ M4
TEOM
LED
TSettle2
TDeb
TDeb
TDeb
End of Message
Sp+
Sp-
Figure 5-9 Playback Operation under FMC mode
5.3.
OTHER OPERATIONS
5.3.1. Rosc Operation
When the ROSC varies from 53.3 KΩ to 160 KΩ, the sampling frequency changes from 12 to 4
kHz accordingly.
When ROSC resistor value is changed during playback, the tone of a recorded message will
alter either faster or slower.
Publication Release Date: Jan 19, 2009
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Revision 0.30
ISD14B00
If the ground side of ROSC resistor is floated or tied to VCC, then the current operation will be
freezed.
The operation will resume when the resistor is connected back to ground.
5.3.2. LED Operation
¯L¯E¯D¯ turns on during recording. Also, ¯L¯E¯D¯ pulses Low at the end of message. The Low
period must be sufficiently greater than debounce time.
5.3.3. Feed-Through mode Operation
As F¯T¯ is held Low, the Mic+ pin will be reconfigured as AnaIn input, and the AnaIn signal will
be transmitted to the speaker outputs. Under this mode, Mic- pin is not used (must be floated).
After F¯T¯ is enabled, If ¯R¯E¯C¯ is triggered, then AnaIn signal will be recorded into memory
while the Feed-Through path remains on.
If F¯T¯ is already enabled, activating either ¯P¯la¯y¯E¯ or ¯P¯la¯y¯L¯ will first disable the FT path and
then play the recorded message. Once playback completes, FT path will be resumed.
During an operation, activating the F¯T¯ pin is not allowed.
5.3.4. Power-On Playback Operation
If ¯P¯la¯y¯E¯ is kept at Low during power turns on, the device plays message once, then powers
down.
If ¯P¯la¯y¯L¯ is held at Low during power turns on and constantly maintained at Low, the device
will play the message repeatedly, with insignificant dead time between messages regardless of
sampling frequencies. This status will sustain unless power is turned off or ¯P¯la¯y¯L¯ somehow
returns to High.
5.3.5. Automatic Single Message Playback
If ¯L¯E¯D¯ is connected to ¯P¯la¯y¯E¯ , once ¯P¯la¯y¯E¯ is triggered, the device plays message
repeatedly without power down between the looping playback. However, if ¯P¯la¯y¯E¯ is triggered
again during playback, then playback will stop
5.3.6. Power is interrupted Abruptly
During the device is in operation, it is strongly recommended that the supply power cannot be
interrupted. Otherwise, it may cause the device to become malfunctioning.
Publication Release Date: Jan 19, 2009
Revision 0.30
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ISD14B00
6. ABSOLUTE MAXIMUM RATINGS [1]
ABSOLUTE MAXIMUM RATINGS
CONDITION
VALUE
Junction temperature
150°C
-65°C to +150°C
Storage temperature range
Voltage applied to any pins
(VSS – 0.3V) to (VCC + 0.3V)
(VSS – 1.0V) to (VCC + 1.0V)
(VSS – 1.0V) to (VCC + 1.0V)
-0.3V to +7.0V
Voltage applied to Input pins (current limited to +/-20 mA)
Voltage applied to output pins (current limited to +/-20 mA)
VCC – VSS
[1] Stresses above those listed may cause permanent damage to the device. Exposure to the
absolute maximum ratings may affect device reliability and performance. Functional operation is
not implied at these conditions.
6.1.
OPERATING CONDITIONS
OPERATING CONDITIONS
CONDITION
VALUE
0°C to +50°C
+2.4V to +5.5V
0V
Operating temperature range
Operating voltage (VCC) [1]
Ground voltage (VSS) [2]
[1]
V
= VCCA = VCCD
= VSSA = VSSD
CC
[2]
V
SS
Publication Release Date: Jan 19, 2009
Revision 0.30
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ISD14B00
7. ELECTRICAL CHARACTERISTICS
7.1.
DC PARAMETERS
PARAMETER
Input Low Voltage
SYMBOL MIN[2]
VIL
TYP[1]
MAX[2] UNITS
CONDITIONS
0.3xVcc
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Standby Current
Record Current
Playback Current
Pull-up device for ¯R¯E¯C¯, ¯P¯la¯y¯E¯, RPU1
¯P¯la¯y¯L¯, F¯T¯ & M¯¯1 ~ M¯¯8 pins
VIH
0.7xVcc
0.7xVcc
VOL
VOH
ISTBY
IREC
IPLAY
0.3xVcc
V
IOL = 4.0 mA[3]
V
IOH = -1.6 mA[3]
[4] [5]
1
20
20
600
10
30
30
µA
mA
mA
k
VCC = 5.5V [4] [5]
VCC = 5.5V, no load [4] [5]
MIC+ Input Resistance
MIC- Input Resistance
AnaIn Input Resistance
MIC Differential Input
AnaIn Input
RMICP
RMICN
RANAIN
VIN1
VIN2
AMSP
18
18
42
KΩ
KΩ
KΩ
mV
V
15
6
300
1
40
Peak-to-peak
Peak-to-peak
VIN = 15~300 mVp-p,
AGC = 4.7 µF,
Gain from MIC to SP+/-
dB
VCC = 2.4V~5.5V
VCC = 2.4V~5.5V
Gain from AnaIn to SP+/-
Output Load Impedance
Speaker Output Power
AASP
RSPK
Pout
0
dB
Ω
mW
mW
mW
mW
8
Speaker load
VDD = 5.5 V 1Vp-p,
670
313
117
49
1 kHz sine
wave at
AnaIn. RSPK
= 8 Ω
VDD = 4.4 V
VDD= 3 V
VDD= 2.4 V
Speaker Output Voltage
Total Harmonic Distortion
VOUT1
THD
VDD
V
RSPK = 8Ω Speaker,
Typical buzzer
15 mV p-p 1 kHz sine
wave, Cmessage
weighted
1
%
Notes: [1] Typical values @ VCC = 5.5V, TA = 25° and sampling frequency (Fs) at 8 kHz, unless stated.
[2]
Not all specifications are 100 percent tested. All Min/Max limits are guaranteed by Nuvoton via design,
electrical testing and/or characterization.
LED output during recording.
VCCA, VCCD and VCCP are connected together. Also, VSSA, VSSD, VSSP1 and VSSP2 are linked together.
All required control pins must be at appropriate status. External components are biased under a separated
[3]
[4]
[5]
power supply.
Publication Release Date: Jan 19, 2009
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Revision 0.30
ISD14B00
7.2.
AC PARAMETERS
CHARACTERISTIC [1]
Sampling Frequency
Record Duration
SYMBOL MIN[2]
TYP
MAX[2] UNITS
CONDITIONS
[3]
[3]
[3]
Fs
4
10.6
10.6
225k/Fs
30
225k/Fs
30
12
32
32
kHz
sec
sec
TREC
TPLAY
TDeb
TASet
TAHold
TFSet
TSettle1
TSettle2
Playback Duration
Debounce Time
Address Setup Time
Address Hold Time
FMC Setup Time
Record Settle Time
Play Settle Time
Delay from Record to Play TSettle3
[3] [4]
msec
nsec
msec
nsec
msec
msec
msec
nsec
msec
[3] [4]
[3] [4]
[3] [4]
[3] [4]
32k/Fs
256k/Fs
128k/Fs
Record Stop Time
LED Pulse Low Time
TStop1
TEOM
30
[3] [4]
256k/Fs
Notes:
[1]
Conditions are VCC = 5.5V, TA = 25°C and sampling frequency (FS) at 8kHz, unless specified.
[2]
[3]
[4]
Not all specifications are 100 percent tested. All Min/Max limits are guaranteed by Nuvoton via design,
electrical testing and/or characterization.
When different FS is applied, the value will change accordingly. Also, stability of internal oscillator may
vary as much as +10% over the operating temperature and voltage ranges.
k = 1000.
Publication Release Date: Jan 19, 2009
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Revision 0.30
ISD14B00
8. TYPICAL APPLICATION CIRCUIT
The following typical application examples on ISD14B00 series are for references only. They make
no representation or warranty that such applications shall be suitable for the use specified. It’s
customer’s obligation to verify the design in its own system for the functionalities, voice quality,
current consumption, and etc.
In addition, the below notes apply to the following application examples:
The suggested values are for references only. Depending on system requirements, they can be
adjusted for functionalities, voice quality and degree of performance.
It is important to have a separate path for each ground and power back to the related terminals to
minimize the noise. Besides, the power supplies should be decoupled as close to the device as
possible.
Also, it is crucial to follow good audio design practices in layout and power supply decoupling. See
recommendations in Application Notes from our websites.
Example #1: Operations via start and end address under Address Mode.
REC
ADDR
D1
1 K
PLAYE
Vcc
Gnd
LED
PLAYL
XCLK
VCCA
VCCD
VCCP
S3
S2
S1
S0
VCCD
VCCD
VSSD
VCCA
VSSA
0.1 F
10 F*
To switches or
address I/Os
VCC
VCCA
E3
E2
E1
E0
ISD14B00
0.1 F
10 F*
4.7 k
VCCP
4.7 F*
VCCP
0.1 F
4.7 k
FT
10 F*
VSSP1
10 F*
0.1 F*
0.1 F
Mic+_AnaIn
Mic-
VSSP2
0.1 F*
4.7 F*
AGC
Rosc
SP+
SP-
Speaker
4.7 k
Rosc*
Publication Release Date: Jan 19, 2009
Revision 0.30
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ISD14B00
Example #2: Fixed Message Configuration Operations under Direct Mode.
VCC
D1
1 k
Vcc
Gnd
R/P
M1
M2
M3
M4
M5
M6
M7
M8
LED
VCCA
VCCD
VCCP
DRCT
FMC3
FMC2
FMC1
VCCD
VCCD
10 F*
0.1 F
VSSD
VCCA
VCC
VCCA
ISD14B00
4.7 k
10 F
0.1 F
4.7 F*
VSSA
VCCP
4.7 k
VCCP
FT
0.1 F*
0.1 F
10 F*
Mic+_AnaIn
Mic-
VSSP1
VSSP2
10 F*
0.1 F*
0.1 F
4.7 F*
4.7 k
AGC
Rosc
Rosc*
SP+
SP-
Speaker
Good Audio Design Practices
Nuvoton’s ChipCorder are very high-quality single-chip voice recording and playback devices. To
ensure the highest quality voice reproduction, it is important that good audio design practices on
layout and power supply decoupling are followed. See Application Information links below for details.
Good Audio Design Practices
http://www.nuvoton-usa.com/products/isd_products/chipcorder/applicationinfo/apin11.pdf
Single-Chip Board Layout Diagrams
http://www.nuvoton-usa.com/products/isd_products/chipcorder/applicationinfo/apin12.pdf
It is strongly recommended that before any design or layout project starts, the designer should contact
Nuvoton Sales Rep for the most update technical information and layout advice.
Publication Release Date: Jan 19, 2009
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Revision 0.30
ISD14B00
9. PACKAGING
9.1.
DIE INFORMATION
Addr/Drct
VSSD VCCD
S0 / M1
S1 / M2
S2 / M3
FT XCLK / FMC3
REC / R/P
S3 / M4
PLAYE / FMC2
LED
PLAYL / FMC1
E0 / M5
14B00
VCCA
VSSA
E1 / M6
E2 / M7
Rosc
VCCA
Mic-
E3 / M8
Mic+_AnaIn
VSSP2
VCCP
VSSP1
SP-
SP+
AGC
Contact Nuvoton Sales Representatives for other information.
Publication Release Date: Jan 19, 2009
Revision 0.30
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ISD14B00
10.ORDERING INFORMATION
Product Number Descriptor Key
I14Bxxxx
Product Name:
I = ISD
Product Series:
14B = 14B00
Duration:
20 : 10.6 – 32 secs
40 : 21.3 – 64 secs
80 : 42.6 – 128 secs
Temperature:
Blank = Commercial
Die (0C to +50C)
Package Type:
Die
X
=
When ordering ISD14B00 devices, please refer to the above ordering scheme. Contact the local Nuvoton
Sales Representatives for any questions and the availability.
For the latest product information, please contact the Nuvoton Sales/Rep or access
Nuvoton’s worldwide web site at http://www.nuvoton-usa.com
Publication Release Date: Jan 19, 2009
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Revision 0.30
ISD14B00
11.VERSION HISTORY
VERSION
DATE
DESCRIPTION
0
Sep 21, 2007
Oct 10, 2007
Oct 16, 2007
Nov 07,2008
Initial revision
0.1
0.2
0.21
Update block diagram
Update description
Change to Nuvoton logo
Update Application Circuit
0.30
Jan 19, 2009
Rename Norm/M¯¯o¯d¯e to Addr/¯D¯r¯c¯t .
Publication Release Date: Jan 19, 2009
Revision 0.30
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ISD14B00
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment
intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could
result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Nuvoton for any damages resulting from such improper use or sales.
The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no
representation or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice.
No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this
publication. Except as set forth in Nuvoton's Standard Terms and Conditions of Sale, Nuvoton assumes no liability
whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or
infringement of any Intellectual property.
The contents of this document are provided “AS IS”, and Nuvoton assumes no liability whatsoever and disclaims any
express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual
property. In no event, shall Nuvoton be liable for any damages whatsoever (including, without limitation, damages for loss
of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this
documents, even if Nuvoton has been advised of the possibility of such damages.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only
and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the
Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton. This product incorporates
SuperFlash®.
Information contained in this ISD® ChipCorder® datasheet supersedes all data for the ISD ChipCorder products published
by ISD® prior to August, 1998.
This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD® ChipCorder® product
specifications. In the event any inconsistencies exist between the information in this and other product documentation,
or in the event that other product documentation contains information in addition to the information in this, the information
contained herein supersedes and governs such other information in its entirety. This datasheet is subject to change
without notice.
Copyright© 2005, Nuvoton Electronics Corporation. All rights reserved. ChipCorder® and ISD® are trademarks of
Nuvoton Electronics Corporation. SuperFlash® is the trademark of Silicon Storage Technology, Inc. All other trademarks
are properties of their respective owners.
Headquarters
Nuvoton Technology Corporation America
Technology Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
27F, 299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62356998
TEL: 886-3-5770066
FAX: 1-408-5441797
FAX: 886-3-5665577
http://www.Nuvoton-usa.com/
http://www.Nuvoton.com.tw/
Taipei Office
Nuvoton Technology Corporation Japan
Nuvoton Technology (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District
Taipei, 114 Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
7F Daini-ueno BLDG. 3-7-18
Shinyokohama Kohokuku,
Yokohama, 222-0033
TEL: 81-45-4781881
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
FAX: 81-45-4781800
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
Publication Release Date: Jan 19, 2009
Revision 0.30
- 27 -
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