ISD5008PYI [NUVOTON]
3V, SINGLE-CHIP VOICE RECORD/PLAYBACK DEVICE 4- TO 8-MINUTES DURATION;
| 型号： | ISD5008PYI |
| 厂家： | 
NUVOTON |
| 描述： | 3V, SINGLE-CHIP VOICE RECORD/PLAYBACK DEVICE 4- TO 8-MINUTES DURATION |
| 文件： | 总54页 (文件大小：1510K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISD5008
ISD5008
3V, SINGLE-CHIP
VOICE RECORD/PLAYBACK DEVICE
4- TO 8-MINUTES DURATION
Publication Release Date: Oct 31 2008
Revision 1.2
- 1 -
ISD5008
Table of Contents
1
2
3
4
5
6
GENERAL DESCRIPTION............................................................................................................... 3
FEATURES ...................................................................................................................................... 4
BLOCK DIAGRAM............................................................................................................................ 5
PIN CONFIGURATION .................................................................................................................... 6
PIN DESCRIPTION.......................................................................................................................... 7
FUNCTIONAL DESCRIPTION....................................................................................................... 10
6.1
DETAILED DESCRIPTION .........................................................................................................................10
Speech/Sound Quality....................................................................................................................10
Duration.........................................................................................................................................10
Flash Storage.................................................................................................................................10
Microcontroller Interface ..............................................................................................................10
Memory Architecture .....................................................................................................................11
Programming.................................................................................................................................11
ANALOG FUNCTIONAL PINS ....................................................................................................................12
Mic+, Mic-.....................................................................................................................................12
ANA IN (Analog Input) ..................................................................................................................12
AUX IN (Auxillary Input)...............................................................................................................13
ACAP (AGC Capacitor).................................................................................................................14
INTERNAL FUNCTIONAL BLOCKS ............................................................................................................15
SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION ..............................................................................19
Message Cuing...............................................................................................................................19
Opcodes .........................................................................................................................................20
Power-Up Sequence.......................................................................................................................21
SPI Port .........................................................................................................................................22
SPI Control Register......................................................................................................................22
OPERATIONAL MODES DESCRIPTION ......................................................................................................29
Feed Through Mode.......................................................................................................................29
Call Record....................................................................................................................................32
Memo Record.................................................................................................................................33
Memo and Call Playback...............................................................................................................33
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.5.1
6.5.2
6.5.3
6.5.4
7
TIMING DIAGRAMS....................................................................................................................... 36
8
ABSOLUTE MAXIMUM RATINGS [1] ............................................................................................. 38
8.1
OPERATING CONDITIONS ........................................................................................................................39
9
ELECTRICAL CHARACTERISTICS .............................................................................................. 40
9.1
9.2
GENERAL PARAMETERS..........................................................................................................................40
TIMING PARAMETERS .............................................................................................................................41
ANALOG PARAMETERS ...........................................................................................................................42
SPI AC PARAMETERS (1) .........................................................................................................................47
TYPICAL APPLICATION CIRCUIT ............................................................................................ 48
9.3
9.4
10
11
PACKAGE DRAWING AND DIMENSIONS ............................................................................... 49
11.1 28-LEAD LEAD 8X13.4MM PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE 1...........................49
11.2 28-LEAD 600 MIL PLASTIC DUAL INLINE PACKAGE (PDIP) ....................................................................50
11.3 28-LEAD 300 MIL PLASTIC SMALL OUTLINE IC (SOIC) .........................................................................51
12
13
ORDERING INFORMATION ...................................................................................................... 52
VERSION HISTORY................................................................................................................... 53
Publication Release Date: Oct 31 2008
- 2 -
Revision 1.2
ISD5008
1
GENERAL DESCRIPTION
The ISD5008 ChipCorder product is a 3V fully-integrated, single-chip solution which provides seamless
integration of enhanced voice record and playback features for digital cellular phones (GSM, CDMA,
TDMA, PDC, and PHS), automotive communications, GPS/navigation systems, and portable
communication products. This low-power, 3-volt device enables customers to quickly and easily
integrate 4 to 8 minutes of voice storage features such as one-way or two-way (full duplex) call record,
voice memo record, and call screening/answering machine functionality.
Like other ChipCorder products, the ISD5008 integrates the sampling clock, anti-aliasing and
smoothing filters, and the Multi-Level Storage (MLS) array into a single chip. For enhanced voice
features, the ISD5008 eliminates external circuitry mostly by also integrating automatic gain control
(AGC), a power amplifier/speaker driver, volume control, summing amplifiers, analog switches, and a
car kit interface. Input level adjustable amplifiers are also implemented, providing a flexible interface for
multiple applications.
Duration/sample rate selection is accomplished via software, allowing customers to optimize quality
and duration for various features within the same end product.
The ISD5008 device is designed for use in a microprocessor- or microcontroller-based system.
Address, control, and duration selection are accomplished through a Serial Peripheral Interface (SPI)
or Microwire Serial Interface to minimize pin count.
Recordings are stored into on-chip non-volatile memory cells, providing zero-power message storage.
This unique, single-chip solution is made possible through Nuvoton’s patented MLS technology. Voice
and audio signals are stored directly into solid-state memory in their natural, uncompressed form,
providing superior quality voice and music reproduction.
Publication Release Date: Oct 31 2008
- 3 -
Revision 1.2
ISD5008
2
FEATURES
Fully-Integrated Solution
Single-chip voice record/playback solution
Integrated sampling clock, anti-aliasing and smoothing filters, and MLS array
Integrated analog features such as automatic gain control (AGC), audio gating switches, speaker
driver, summing amplifiers, volume control, and AUX IN/AUX OUT interface (e.g., for car kits)
Low-Power Consumption
Single +3 volt supply
Operating current:
o
o
o
ICC_Play = 15 mA (typical)
ICC_Rec = 25 mA (typical)
ICC_Feedthru = 12 mA (typical)
Standby current:
o
ISB = 1 µA (typical)
Power consumption controlled by SPI or Microwire control register
Most stages can be individually powered down for minimum power consumption
Enhanced Voice Features
One or two-way (full duplex) conversation record (record signal summation)
One- or two-way (full duplex) message playback (while on a call)
Voice memo record and playback
Private call screening
Answering machine
Personalized outgoing message (given caller ID information from host chip set)
Private call announce while on call (given CIDCW information from host chip set)
Easy-to-Use and Control
No compression algorithm development required
User-selectable sampling rates of 8.0 kHz, 6.4 kHz, 5.3 kHz, or 4.0 kHz
Microcontroller SPI or Microwire™ Serial Interface
Fully addressable to handle multiple messages
High Quality Solution
High quality voice and music reproduction
Standard 100-year message retention (typical)
100,000 record cycles (typical)
Options
Available in die, PDIP, SOIC, TSOP, and chip scale packaging (CSP)
Compact µBGA chip scale package available for portable applications
Temperature : Commercial, Extended and Industrial
Publication Release Date: Oct 31 2008
Revision 1.2
- 4 -
ISD5008
3
BLOCK DIAGRAM
FTHRU
6dB
CHIP SET
ANA OUT+
INP
FILTO
SUM1
ANA
OUT
AMP
SUM1
Summing
AMP
MICROPHONE
ANA OUT-
INP
SUM2
Summing
AMP
MIC+
MIC IN
VOL
FILTO
AGC
1
SUM1 MUX
Low Pass
Filter
SUM2
SUM1
ARRAY
(AOPD)
MIC -
1
ANA IN
(AGPD)
2
1
3
AGCCAP
S1M0
S1M1
1
(FLPD)
(
)
2
AOS0
(FLS0)
FILTO
ANA IN
ARRAY
AUX IN
S2M0
S2M1
AOS1
( )
(
)
AOS2
CAR KIT
AUX IN
1
(INS0)
AUX IN
AMP
1
Internal
Clock
Multilevel
Storage Array
(AXPD)
CAR KIT
AUX OUT
2
AUX
OUT
AMP
AXG0
S1S0
S1S1
(
)
(
)
FILTO
VOL
2
AXG1
2
FLD0
(
)
FLD1
XCLK
SPEAKER
SP+
SUM2
CHIP SET
ANA IN
Spkr.
AMP
ANA IN
ANA IN
AMP
SP-
1
2
SUM1
INP
(AIPD)
2
OPS0
OPS1
Volume
Control
(
)
OPA0
OPA1
(
)
ANA IN
SUM2
2
AIG0
AIG1
3
1
(
)
(VLPD)
VOL0
VOL1
( )
2
VOL2
VLS0
VLS1
(
)
Power Conditioning
Device Control
SCLK SS MOSI MISO INT RAC
VCCA VSSA VSSA VSSA VSSD VSSD VCCD VCCD
Publication Release Date: Oct 31 2008
Revision 1.2
- 5 -
ISD5008
4
PIN CONFIGURATION
SCLK
SS
1
2
3
4
28
27
26
25
VCCD
VCCD
XCLK
INT
MOSI
MISO
VSSD
VSSD
NC
5
6
7
24
23
22
RAC
VSSA
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
VSSA
RAC
INT
XCLK
VCCD
VCCD
SCLK
SS
MOSI
MISO
VSSD
VSSD
NC
NC
2
AUX OUT
AUX IN
ANA IN
VCCA
SP+
VSSA
3
4
MIC+
VSSA
MIC-
8
9
21
20
19
NC
5
AUX OUT
AUX IN
6
7
10
8
SP-
ANA OUT+
ANA OUT-
11
12
18
17
ANA IN
VCCA
9
ACAP
ANA OUT-
ANA OUT+
MIC-
MIC+
VSSA
10
11
12
13
14
ACAP
SP-
13
14
16
15
SP+
VSSA
TSOP
PDIP/SOIC
Publication Release Date: Oct 31 2008
Revision 1.2
- 6 -
ISD5008
5
PIN DESCRIPTION
PIN NAME PDIP/SOIC TSOP
FUNCTION
SCLK
1
8
Serial Clock: The SCLK is the clock input to the ISD5008.
Generated by the master microcontroller, the SCLK
synchronizes data transfers in and out of the device through the
MISO and MOSI lines.
2
3
9
Slave Select: This input, when LOW, selects the device.
SS
MOSI
10
Master Out Slave In: MOSI is the serial data input to the
ISD5008 device. The master microcontroller places data to be
clocked into the ISD5008 device on the MOSI line one-half
cycle before the rising edge of SCLK. Data is clocked into the
device with LSB (Least Significant Bit) first.
MISO
4
11
Master In Slave Out: MISO is the serial data output of the
ISD5008. Data is clocked out on the falling edge of SCLK. This
output goes into a high-impedance state when the device is not
selected. Data is clocked out of the device with LSB first.
VSSD / VSSA
5, 6 /
12, 13 /
Ground: The ISD5008 utilizes separate analog and digital
ground busses. The analog ground (VSSA) pins should be tied
together as close to the package as possible and connected
through a low-impedance path to power supply ground. The
digital ground (VSSD) pin should be connected through a
separate low-impedance path to power supply ground. These
ground paths should be large enough to ensure that the
impedance between the VSSA pins and the VSSD pins is less than
3 Ω. The backside of the die is connected to VSSD through the
substrate resistance. In a chip-on-board design, the die attach
9, 15, 23
2, 15,
22
area must be connected to VSSD
.
MIC+ / MIC-
8 / 10
16 / 17
Microphone +/–: The microphone inputs transfer the voice
signal to the on-chip AGC preamplifier or directly to the ANA
OUT MUX, depending on the selected path. The AGC circuit
has a range of 45dB in order to deliver a nominal 694 mVp-p
into the storage array from a typical electret microphone output
of 2 to 20 mVp-p. The direct path to the ANA OUT MUX has a
gain of 6dB so a 208 mVp-p signal across the differential
microphone inputs would give 416 mVp-p across the ANA OUT
pins. The input impedance is typically 10 kΩ.
ANAOUT+ /
ANAOUT-
11 / 12
18 / 19
Analog Outputs: These differential outputs are designed to
match to the microphone input of the telephone chip set. It is
designed to drive a minimum of 5 kΩ between the ―+‖ and ―–‖
pins to a nominal voltage level of 700 mVp-p. Both pins have
DC bias of approximately 1.2 VDC. The AC signal is
superimposed upon this analog ground voltage. These pins can
be used single-ended, getting only half the voltage. Do NOT
ground the unused pin.
Publication Release Date: Oct 31 2008
- 7 -
Revision 1.2
ISD5008
PIN NAME PDIP/SOIC TSOP
FUNCTION
ACAP
13
20
AGC Capacitor: This pin provides the capacitor connection for
setting the parameters of the microphone AGC circuit. It should
have a 4.7 µF capacitor connected to ground. It cannot be
floating. This is because the capacitor is also used in the
playback mode for the AutoMute circuit. This circuit reduces the
amount of noise present in the output during quiet pauses.
Tying this pin to ground gives maximum gain, or to VCCA gives
minimum gain for the AGC amplifier but will cancel the
AutoMute function.
SP- / SP+
14 / 16
21 / 23
Speaker Outputs: This differential speaker output is designed
to drive an 8Ω speaker up to a maximum power of 23.5 mW.
This stage has two selectable gains, 1.32 and 1.6, which can be
chosen through the configuration registers. These pins are
biased to approximately 1.2 VDC and, if used single-ended,
must be capacitively coupled to their load. Do NOT ground the
unused pin.
VCCA / VCCD
17 /
24 /
6, 7
Power Supplies: To minimize noise, the analog and digital
circuits in the ISD5008 device uses separate power busses.
These +3V busses lead to separate pins. Tie the VCCD pins
together as close as possible and decouple both supplies as
near to the package as possible
27, 28
ANA IN
18
25
Analog Input: The ANA IN pin is the analog input from the
telephone chip set. It can be switched (by the SPI bus) to the
speaker output, the array input or to various paths. This pin is
designed to accept a nominal 1.11 Vp-p when at its minimum
gain (6dB) setting. See Table 4. There is additional gain
available in 3dB steps controlled from the SPI bus, if required,
up to 15dB.
AUX IN
19
20
26
27
Auxiliary Input: The AUX IN is an additional audio input to the
ISD5008, such as from the microphone circuit in a mobile
phone ―car kit.‖ This input has a nominal 700 mVp-p level at its
minimum gain setting (0dB). See Table 5. Additional gain is
available in 3 dB steps (controlled by the SPI bus) up to 9dB.
AUX OUT
Auxiliary Output: The AUXOUT is an additional audio output
pin, to be used, for example, to drive the speaker circuit in a
―car kit.‖ It drives a minimum load of 5 kΩ and up to a maximum
of 1 Vp-p. The AC signal is superimposed on approximately 1.2
VDC bias and must be capacitively coupled to the load.
Publication Release Date: Oct 31 2008
- 8 -
Revision 1.2
ISD5008
PIN NAME PDIP/SOIC TSOP
FUNCTION
RAC
24
3
Row Address Clock: RAC is an open drain output pin that
marks the end of a row. At the 8 kHz sampling frequency, the
duration of this period is 200 ms. There are 1,200 rows of
memory in the ISD5008 devices. RAC stays HIGH for 175 ms
and stays LOW for the remaining 25 ms before it reaches the
end of the row.
At the 8 kHz sampling frequency, the RAC pin remains HIGH
for 109.38 µsec and stays LOW for 15.63 µsec under the
Message Cueing mode. See Table 15 Timing Parameters for
RAC timing information at other sample rates. When a record
command is first initiated, the RAC pin remains HIGH for an
extra TRACLO period, to load sample and hold circuits internal to
the device. The RAC pin can be used for message
management techniques.
A pull-up resistor is required to connect this pin to other device.
25
4
INT
Interrupt: INT is an open drain output pin. The ISD5008
interrupt pin goes LOW and stays LOW when an Overflow
(OVF), or End of Message (EOM) marker or Message Cueing is
detected. The interrupt is cleared the next time an SPI cycle is
completed. The interrupt status can be read by a RINT
instruction that will give one of the two flags out the MISO line.
A pull-up resistor is required to connect this pin to other device.
OVF Flag. The overflow flag indicates that the end of the
ISD5008’s analog memory has been reached during a record or
playback operation.
EOM Flag. The end of message flag is set only during
playback, when an EOM is found. There are eight possible
EOM markers per row.
XCLK
26
5
External Clock: The external clock input has an internal pull-
down device. Normally, the ISD5008 is operated at one of four
internal rates selected for its internal oscillator by the Sample
Rate Select bits. If greater precision is required, the device can
be clocked through the XCLK pin as described in Table 2.
Because the anti-alising and smoothing filters track the Sample
Rate Select bits, one must, for optimum performance, change
the external clock AND the Sample Rate Configuration bits to
one of the four values properly to set the filters to the correct
cutoff frequency as described in Table 1. The duty cycle on the
input clock is not critical, as the clock is immediately divided by
two internally. If the XCLK is not used, this input should be
connected to VSSD
.
Publication Release Date: Oct 31 2008
Revision 1.2
- 9 -
ISD5008
6
FUNCTIONAL DESCRIPTION
6.1 DETAILED DESCRIPTION
6.1.1 Speech/Sound Quality
The ISD5008 ChipCorder product can be configured via software to operate at 4.0, 5.3, 6.4, or 8.0 kHz
sampling frequency, allowing the user a choice of speech quality options. Increasing the duration
decreases the sampling frequency and bandwidth, which affects sound quality. Table 1 shows the
relationship between sampling frequency, duration and filter pass band.
The speech samples are stored directly into on-chip non-volatile memory without the digitization and
compression associated with other solutions. Direct analog storage provides a natural sounding
reproduction of voice, music, tones, and sound effects not available with most solid-state solutions.
6.1.2 Duration
To meet end system requirements, the ISD5008 device is a single-chip solution which provides from 4
to 8 minutes of voice record and playback, depending on the sample rates defined by customer
software.
TABLE 1: SAMPLING RATE / DURATION / FILTER EDGE
Sample Rate
(kHz)
Duration
(Minutes)
4.0
Filter Pass Band*
(kHz)
8
3.4
2.7
2.3
1.7
6.4
5.3
4
5.0
6.0
8.0
*
-3dB point
6.1.3 Flash Storage
One of the benefits of Nuvoton’s ChipCorder technology is the use of on-chip nonvolatile memory,
which provides zero- power message storage. The message is retained for up to 100 years (typically)
without power. In addition, the device can be re-recorded over 100,000 times (typically).
6.1.4 Microcontroller Interface
A four-wire (SCLK, MOSI, MISO, SS) SPI interface is provided for ISD5008 control, addressing
functions, and sample rate selection. The ISD5008 is configured to operate as a peripheral slave
device with a microcontroller-based SPI bus interface. Read/Write access to all the internal registers
occurs through this SPI interface. An interrupt signal (INT) and internal read-only Status Register are
provided for handshake purposes.
Publication Release Date: Oct 31 2008
- 10 -
Revision 1.2
ISD5008
6.1.5 Memory Architecture
The ISD5008 device contains a total of 1,920K Flash memory cells, which is organized as 1,200 rows
of 1,600 cells each. The duration is counted according to the number of rows, while the row number is
represented by the related 16 address bits of MOSI as described in the SPI section.
6.1.6 Programming
The ISD5008 device is also ideal for playback-only applications, where single- or multiple-message
playback is controlled through the SPI port. Once the desired message configuration is created,
duplicates can easily be generated via a third-party programmer. For more information on available
application tools and programmers, please see the Nuvoton website at www.Nuvoton-usa.com.
TABLE 2: EXTERNAL CLOCK INPUT
Duration
(Minutes)
Sample Rate
(kHz)
Required Clock
(kHz)
4
5
6
8
8.0
6.4
5.3
4.0
1024
819.2
682.7
512
TABLE 3: INTERNAL SAMPLING RATE / FILTER EDGE
FLD1 FLD0
Sample
Rate (kHz)
Filter Pass Band
(kHz)
0
0
1
1
0
1
0
1
8
3.4
2.7
2.3
1.7
6.4
5.3
4
Publication Release Date: Oct 31 2008
Revision 1.2
- 11 -
ISD5008
6.2 ANALOG FUNCTIONAL PINS
6.2.1 Mic+, Mic-
VCC
1.5 k
+
220
F
Internal to the device
MIC+
1.5 k
Ra = 10 k
CCOUP = 0.1
F
Electret
Microphone
WM-54B
Panasonic
10 k
0.1
F
1.5 k
MIC
1
NOTE: fCUTOFF=
2RaCCOUP
FIGURE 1: MICROPHONE INPUT
6.2.2 ANA IN (Analog Input)
Internal to the device
Rb
Gain
Setting
Resistor Ratio
(Rb/Ra) k/k
Gain Gain 2
(dB)
CCOUP = 0.1
F
Ra
ANA IN
Input
00
01
63.9/102
77.9/88.1
92.3/73.8
106/60
0.625
0.88
1.25
1.77
-4.1
-1.1
1.9
10
ANA IN
Input Apmlifier
11
4.9
1
NOTE: fCUTOFF=
2RaCCOUP
Publication Release Date: Oct 31 2008
Revision 1.2
- 12 -
ISD5008
FIGURE 2: ANA IN INPUT MODES
TABLE 4: ANA IN AMPLIFIER GAIN SETTINGS
Setting (1) 0TLP Input
CFG0
Gain (2)
Array In/Out
VPP
Speaker Out
(3)
(4)
VPP
VPP
AIG1
AIG0
6 dB
9 dB
.694
.694
.694
.694
1.11
.785
.555
.393
0
0
1
1
0
1
0
1
.625
.883
2.22
2.22
2.22
2.22
12 dB
15 dB
1.250
1.767
NOTES:
1. Gain from ANA IN to SP+ / _
2. Gain from ANA In to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB
below clipping.
4.
Speaker Out gain set to 1.6 (High). (Differential)
6.2.3 AUX IN (Auxillary Input)
Internal to the device
Rb
Gain
Setting
Resistor Ratio
(Rb/Ra) k/k
Gain Gain 2
(dB)
CCOUP = 0.1
F
Ra
AUX IN
Input
00
01
10
11
40.1/40.1
47.0/33.2
53.5/26.7
58.2/21.0
1
1.414
2
0
3
6
9
AUX IN
Input Apmlifier
2.82
1
NOTE: fCUTOFF=
2RaCCOUP
FIGURE 3: AUX IN INPUT MODES
Publication Release Date: Oct 31 2008
Revision 1.2
- 13 -
ISD5008
TABLE 5: AUXIN AMPLIFIER GAIN SETTINGS
Setting (1) 0TLP Input
CFG0
Gain (2)
Array In/Out
VPP
ANA OUT
VPP
(3)
(4)
VPP
AXG1
AXG0
0 dB
3 dB
6 dB
9 dB
.694
.694
.694
.694
.694
.694
.694
.694
.694
.491
.347
.245
0
0
1
1
0
1
0
1
1.00
1.41
2.00
2.82
NOTES:
1. Gain from AUX IN to ANA OUT
2. Gain from AUX IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB
below clipping.
4. Differential
6.2.4 ACAP (AGC Capacitor)
This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It
should have a 4.7 F capacitor connected to ground. It cannot be left floating. This is because the
capacitor is also used for the AutoMute circuit. This circuit reduces the amount of noises present in the
output during quiet pauses. Tying this pin to ground gives maximum gain; to VCCA gives minimum gain
for the AGC amplifier but will cancel the AutoMute function.
Publication Release Date: Oct 31 2008
- 14 -
Revision 1.2
ISD5008
6.3 INTERNAL FUNCTIONAL BLOCKS
FIGURE 7: MICROPHONE AMPLIFIER
FIGURE 7: ANA IN and AUX IN
Publication Release Date: Oct 31 2008
Revision 1.2
- 15 -
ISD5008
FIGURE 7: ISD5008 CORE (LEFT HALF)
FIGURE 8: ISD5008 CORE (RIGHT HALF)
Publication Release Date: Oct 31 2008
Revision 1.2
- 16 -
ISD5008
FIGURE 9: VOLUME CONTROL
VLPD
Power Up
0
1
Power Down
ANA IN
SUM 2
VOL
MUX
VOL1
VOL0 Attenuation
VOL2
0 dB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-4 dB
-8 dB
-12 dB
-16 dB
-20 dB
-24 dB
-28 dB
SUM 1
INP
Volume
Control
VOL
VLS1 VLS0 SOURCE
ANA IN
SUM 2
0
0
1
1
0
1
0
1
VOL0
3
1(VLPD)
VOL1
( )
2
VLS0
VOL2
SUM 1
INP
(VLS1)
15 14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
CFG0
CFG1
15 14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
FIGURE 10: SPEAKER and AUX OUT
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FIGURE 11: ANA OUT Output
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6.4 SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION
The ISD5008 product operates from a SPI serial interface, which operates with the following protocol:
The data transfer protocol assumes that the microcontroller’s SPI shift registers are clocked on the
falling edge of the SCLK. However, for the ISD5008, data is clocked into the MOSI pin at the rising
clock edge, while data is clocked out onto the MISO pin at the falling clock edge.
1. All serial data transfers begin with the falling edge of SS pin.
2. SS is held LOW during all serial communications and held HIGH between instructions.
3. Data is clocked in on the rising clock edge and data is clocked out on the falling clock edge.
4. Play and Record operations are initiated by enabling the device by asserting the SS pin LOW,
shifting in an opcode and an address field to the ISD5008 device (refer to the Opcode
Summary of Table 6).
5. The opcodes and address fields are as follows: <8 control bits> and <16 address bits>.
6. Each operation that ends in an EOM or Overflow will generate an interrupt, including the
Message Cueing cycles. The Interrupt will be cleared the next time an SPI cycle is completed.
7. As Interrupt data is shifted out of the ISD5008 MISO pin, control and address data is
simultaneously being shifted into the MOSI pin. Care should be taken such that the data
shifted in is compatible with current system operation. It is possible to read interrupt data and
start a new operation within the same SPI cycle.
8. A record or playback operation begins with the RUN bit set and the operation ends with the
RUN bit reset.
9. All operations begin with the rising edge of SS.
6.4.1 Message Cuing
Message cueing allows the user to skip through messages, without knowing the actual physical
location of the message. This operation is used during playback. In this mode, the messages are
skipped 1600 times faster than in normal playback mode. It will stop when an EOM marker is reached.
Then, the internal address counter will point to the next message.
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6.4.2 Opcodes
Instruction
TABLE 6: OPCODE SUMMARY
Opcode <8 bits> [1]
Operational Summary
Address <16 bits>
Power-Up: Power-Up the device
POWERUP
LOADCFG0 [2]
LOADCFG1
SETPLAY
PLAY
0110 0000
01X0 0010 <D15-D0>
01X0 0100 <D15-D0>
1110 0000 <A15-A0>
1111 0000
Loads a 16-bit value into Configuration Register 0
Loads a 16-bit value into Configuration Register 1
Initiates Playback from address <A15-A0>
Playback from current address (until EOM or OVF)
Initiates Record at address <A15-A0>
SETREC
REC
1010 0000 <A15-A0>
1011 0000
Records from current address until OVF is reached
Initiates Message Cueing (MC) from address <A15-A0>
SETMC
1110 1000 <A15-A0>
1111 1000
MC
Performs a Message Cue. Proceeds to the end of the
current message (EOM) or enters OVF condition if it
reaches the end of the array.
STOP
0111 0000
0101 0000
Stops current operation
STOPWRDN
Stops current operation and enters stand-by (power-
down) mode.
RINT
0111 0000
Read interrupt status bits: OVF and EOM.
NOTES:
[1]
X = Don’t Care.
[2]
Changes in CFG0 are not recognized until CFG1 is loaded. The changes will occur at the rising edge of
SS during the cycle that CFG1 is loaded.
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6.4.3 Power-Up Sequence
The ISD5008 will be ready for an operation after TPUD (25 ms approximately for 8 kHz sample rate).
The user needs to wait TPUD before issuing an instruction. Below are suggested playback and record
examples for references.
6.4.3.1 Record Mode
1. Send POWERUP command.
2. Wait TPUD (power-up delay).
3. Send POWERUP command.
4. Wait 2 x TPUD (power-up delay).
5. Load CFG0 and CFG1 for desired operation.
6. Wait TPUD.
7. Send SETREC command with address xx, or send REC command.
8. Send STOP to halt the record operation or when the end of memory (OVF) is reached, then
record stops automatically.
9. Wait TStop/Pause.
.
6.4.3.2 Playback Mode
1.
2.
3.
4.
5.
6.
Send POWERUP command.
Wait TPUD (power-up delay).
Load CFG0 and CFG1 for desired operation.
Wait TPUD.
Send SETPLAY command with address xx, or send PLAY command.
Send STOP to halt the playback operation or wait until an EOM is reached, then playback
stops automatically.
7.
Wait TStop/Pause..
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6.4.4 SPI Port
The following diagram describes the SPI port and the control bits associated with it.
Byte 1
Byte 2
Byte 3
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C0 C1 C2 C3 C4 C5 C6 C7
MOSI
Reserved
Load CFG0 (LC0)
Load CFG1 (LC1)
Message Cueing
Ignore Address Bit
PowerUp
Play/Record
Run
6.4.5 SPI Control Register
The SPI control register provides control of individual device functions such as Play, Record, Message
Cueing, Power-Up and Power-Down, Start and Stop operations, Ignore Address Pointers and Load
Configuration Registers.
TABLE 7: SPI CONTROL REGISTER
Control
Control
Bit
Device Function
Bit
Device Function
Master power control
Register
Register
RUN
Enable or Disable an operation
PU
=
1
Start
=
1
Power-Up
=
0
Stop
=
0
Power-Down
Selects Play or Record operation
IAB
Ignore address control bit
P/
R
=
=
1
0
Ignore input address register (A15-
A0)
1
0
Play
=
=
Record
Use the input address register
contents for an operation (A15-A0)
MC
Enable or Disable Message
Cueing
A15-A0
D15-D0
Output of the row pointer register
Input control and address register
=
=
Enable Message Cueing
Disable Message Cueing
1
0
LC0
LC1
=
=
1
0
Load Configuration Reg 0
No Load
=
=
1
0
Load Configuration Reg 1
No Load
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TABLE 8: CONFIGURATION REGISTER 0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CFGO
AIG1
AIG0
AIPD
AXG1
AXG0
AXPD
INS0
AOS2
AOS1
AOS0
AOPD
OPS1
OPS0
OPA1
OPA0
VLPD
NOTE: See details on following pages
TABLE 9: CONFIGURATION REGISTER 1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CFG1
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLSO
FLD1
FLD0
FLPD
AGPD
NOTE: See details on following pages
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Detail of Configuration Register 0
Volume Control Power Bit
Bit 0
0
= Power ON
(VLPD)
1
= Power OFF
SPEAKER and AUX OUT
Control Bits
Bits 2,1
00 = Power down SPKR and AUX
(OPA1, OPA0)
01 = SPKR ON, HIGH GAIN, AUX Power down
10 = SPKR ON, LOW GAIN, AUX Power down
11 = SPKR Powered down, AUX ON
OUTPUT MUX Con trol Bits
Bits 4,3
00 = Source is VOL CONTROL (VOL)
(OPS1, OPS0)
01 = Source is ANA IN Input (ANA IN AMP)
10 = Source is LOW PASS FILTER (FILT0)
11 = Source is SUM2 SUMMING AMP (SUM2)
ANA OUT Power Bit
Bit 5
0
1
= Power ON
= Power OFF
(AOPD)
ANA OUT MUX Con trol Bits Bits 8,7,6
(AOS2, AOS1,
000 = Source is MICROPHONE AMP (FTHRU)
001 = Source is INPUT MUX (INP)
010 = Source is VOLUME CONTROL (VOL)
011 = Source is LOW PASS FILTER (FILT0)
100 = Source is SUM1 SUMMING AMP (SUM1)
101 = Source is SUM2 SUMMING AMP (SUM2)
110 = Unused
AOS0)
111 = Unused
INPUT SOURCE MUX
Control Bit
Bit 9
0
= Source is Microphone AGC AMP (AGC)
= Source is AUX IN Input (AUX IN AMP)
= Power ON
(INS0)
1
AUX IN AMP Power Bit
Bit 10
0
(AXPD)
Bits 12,11
(AXG1, AXG0)
1
= Power OFF
AUX IN AMP Control Bits
00
01
10
11
0
= Input Gain = 1, OTLP input Level = 0.694
= Input Gain = 1.414, OTLP input Level = 0.491
= Input Gain = 2, OTLP input Level = 0.347
= Input Gain = 2.828, OTLP input Level = 0.245
= Power ON
ANA IN AMP Power Bit
ANA IN AMP Control Bits
Bit 13
(AIPD)
1
= Power OFF
Bits 15,14
(AIG1, AIG0)
00
01
10
11
= Input Gain = 0.625, OTLP input Level = 1.11
= Input Gain = 0.883, OTLP input Level = 0.7l85
= Input Gain = 1.250, OTLP input Level = 0.555
= Input Gain = 1.767, OTLP input Level = 0.393
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Detail of Configuration Register 1
AGC Power Control Bit
Bit 0
0
1
0
1
= Power ON
= Power OFF
= Power ON
= Power OFF
(AGPD)
Bit 1
LOW PASS FILTER Power
Control Bit
(FLPD)
SAMPLE RATE and LOW PASSBits 3,2
FILTER Control Bits
00 = Sample Rate = 8 KHz, FPB = 3.4 KHz
01 = Sample Rate = 6.4 KHz, FPB = 2.7 KHz
10 = Sample Rate = 5.3 KHz, FPB = 2.3 KHz
11 = Sample Rate = 4 KHz, FPB = 1.7 KHz
(FLD1, FLD0)
FILTER MUX Control bits
Bit 4
(FLS0)
0
1
= Source is SUM1 SUMMING AMP (SUM1)
= Source is Analog Memory Array (ARRAY)
SUM 2 SUMMING AMP Control Bits 6,5
Bits
00 = Source is both ANA IN AMP and FILT0
01 = Source is ANA IN Input (ANA IN AMP) ONLY
10 = Source is LOW PASS FILTER (FILT0) ONLY
11 = Power Down SUM2 SUMMING AMP
00 = Source is both SUM1 and INP
(S2M1, S2M0)
SUM1 SUMMING AMP Control Bit 8,7
Bits
(S1M1, S1M0)
01 = Source is SUM1 SUMMING AMP (SUM1) ONLY
10 = Source is INPUT MUX (INP) ONLY
11 = Power Down SUM1 SUMMING AMP
00 = Source is ANA IN Input (ANA IN AMP)
01 = Source is Analog Memory Array (ARRAY)
10 = Source is LOW PASS FILTER (FILT0)
11 = UNUSED
SUM1MUX Control Bits
Bit 10,9
(S1S1, S1S0)
VOLUME CONTROL Control
Bits
Bits 13,12,11
000 = Attenuation = 0 dB
(VOL2, VOL1, VOL0) 001 = Attenuation = 4 dB
010 = Attenuation = 8 dB
011 = Attenuation = 12 dB
100 = Attenuation = 16 dB
101 = Attenuation = 20 dB
110 = Attenuation = 24 dB
111 = Attenuation = 28 dB
VOL MUX Control Bits
Bit 15,14 (VLS1, VLS0) 00 = Source is ANA IN Input (ANA IN AMP)
01 = Source is SUM2 SUMMING AMP (SUM2)
10 = Source is SUM1 SUMMING AMP (SUM1)
11 = Source is INPUT MUX (INP)
Configuration Register Notes
1. Important: All changes to the internal settings of the ISD5008 are synchronized with the load of
Configuration Register 1. A command to load Configuration Register 1 immediately transfers the
input data to the internal settings of the device and the changes take place immediately at the end
of the command when SS goes HIGH. A load to Configuration Register 0 sends the new data to
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a temporary register in the ISD5008 and does not affect the internal settings of the device. The
next time Configuration Register 1 is loaded, data will also transfer from the temporary register to
the Configuration Register 0 and effect the desire changes. See Figure & Table 13.
2. Configuration Registers may be loaded with data at any time, including when the chip is powered
down using the PU bit in the SPI Control Resgister. The PU bit in the SPI Control Word will have to
be set to a ―1‖ before the changes in configurarion will be seen.
FIGURE 13: Configuration Register Programming Sequence
Temporary Register
Configuration Register 0
Configuration Register 1
Command =
Load Configuration Register 0
Command =
Load Configuration Register 1
LSB
A0
C
0
C
7
A15
Input Shift Register
MOSI
FIGURE 14: SPI Interface Simplified Block Diagram
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D0
D0
D15
D15
CFG1
CFG0
Configuration
Registers
LSB
A0
A15
C
0
C
7
Input Shift Register
MOSI
(Loaded to Row Counter
only if IAB = 0)
A0-A15
Select Logic
Row Counter
P0-P15
LSB
OVF EOM P0 ...
MISO
Output Shift Register
P15
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FIGURE 15: TypicalDigital Cellular Phone Integration
Baseband Section
MIC+
MIC-
MIC IN+
MIC IN-
ANA OUT+
ANA OUT-
RF
Section
VB
Codec
BB
Codec
DSP
ISD5008
SP OUT-
SP OUT+
ANA IN
SP+
SP-
Earpiece
SPI
AUX IN AUX OUT
(INT, RAC)
Microcontroller
Car Kit
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6.5 OPERATIONAL MODES DESCRIPTION
The ISD5008 can operate in many different modes. It’s flexibility allows the user to configure the chip
such that almost any input can mixed with any other input and then be directed to any output. The
variable settings for the ANA and AUX input amplifiers plus the microphone AGC and speaker volume
controls make it possible to use the device with most existing cell phone or cordless phone chip sets
with no external level adjustment. Several modes will be found in most applications, however, please
refer to the ISD5008 block diagram to better understand the following modes. In all cases, we are
assuming that the chip has been powered up with the PU bit in the SPI control register and that a time
period of TPUD has elapsed after that bit was set.
6.5.1 Feed Through Mode
This mode enables the ISD5008 to connect to a base band cell phone or cordless phone chip set
without affecting the audio source or destination. There are two paths involved, the transmit path and
the receive path. The transmit path connects the ISD chip’s microphone source through to the
microphone input on the base band chip set. The receive path connects the base band chip set’s
speaker output through to the speaker driver on the ISD chip. This allows the ISD chip to substitute for
those functions and incidentally gain access to the audio to and from the base band chip set. Figure 15
shows one possible connection to such a chip set.
Figure 16 shows the part of the ISD5008 block diagram that is used in Feed Through Mode. The rest
of the chip will be powered down to conserve power. The bold lines highlight the audio paths. Note that
the Microphone to ANA OUT +/– path is differential
FIGURE 16: BASIC FEED THRU MODE
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To select this mode, the following control bits must be configured in the ISD5008 configuration
registers. To set up the transmit path:
1.
Select the FTHRU path through the ANA OUT MUX—Bits AOS0, AOS1 and AOS2 control
the state of the ANAOUT MUX. These are the D6, D7 and D8 bits respectively of
Configura tion Register 0 (CFG0) and they should all be ZERO to select the FTHRU path.
2.
Power up the ANA OUT amplifier—Bit AOPD controls the power up state of ANA OUT.
This is bit D5 of CFG0 and it should be a ZERO to power up the amplifier.
To set up the receive path:
1. Set up the ANA IN amplifier for the correct gain—Bits AIG0 and AIG1 control the gain settings
of this amplifier. These are bits D14 and D15 respectively of CFG0. The input level at this pin
determines the setting of this gain stage. Table 4 will help determine this setting. In this
example we will assume that the peak signal never goes above 1 volt p-p single ended. That
would enable us to use the 9dB attenuation setting, or where D14 is ONE and D15 is ZERO.
2. Power up the ANA IN amplifier—Bit AIPD controls the power up state of ANA IN. This is bit
D13 of CFG0 and should be a ZERO to power up the amplifier.
3. Select the ANA IN path through the OUTPUT MUX—Bits OPS0 and OPS1 control the state of
the OUTPUT MUX. These are bits D3 and D4 respectively of CFG0 and they should be set to
the state where D3 is ONE and D4 is ZERO to select the ANA IN path.
4. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker and
AUX amplifiers. These are bits D1 and D2 respectively of CFG0. They should be set to the
state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and configures
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it for it’s higher gain setting for use with a piezo speaker element and also powers down the
AUX output stage.
The status of the rest of the functions in the ISD5008 chip must be defined before the configuration
registers settings are updated:
1. Power down the Volume Control Element—Bit VLPD controls the power up state of the
Volume Control. This is bit D0 fo CFG0 and it should be set to a ONE to power down the
statge.
2. Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN input
amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down the stage.
3. Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the SUM
mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1
and bits D5 and D6 in CFG1 respectively. All 4 bits should be set to a ONE to power down the
stage.
4. Power down the FILTER stage—Bit FLPD controls the power up state of the FILTER stage in
the device. This is bit D0 in CFG1 and should be set to a ONE to power down the stage.
5. Power down the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier.
This is bit D0 in CFG1 and should be set to a ONE to power down the stage.
6. Don’t Care bits—The following stages are not used in Feed Through Mode. Their bits may be
set to either level. In this example we will set all the following bits to ZERO.
a. Bit INS0, bit D9 of CFG0 controls the Input Source Mux.
b. Bits AXG0 and AXG1 are bits D11 and D12 respectively in CFG0. They control the
AUX IN amplifier gain setting.
c. Bits FLD0 and FLD1 are bits D2 and D3 respectively in CFG1. They control the
sample rate and filter band pass setting.
d. Bit FLS0 is bit D4 in CFG1. It controls the FILTER MUX.
e. Bits S1S0 and S1S1 are bits D9 and D10 of CFG1. They control the SUM1 MUX.
f. Bits VOL0, VOL1 and VOL2 are bits D11, D12 and D13 of CFG1. They control the
setting of the Volume Control.
g. Bits VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control
Mux.
The end result of the above set up is:
CFG0 = 0100 0100 0000 1011 (hex 4408)
and
CFG1 = 0000 0001 1110 0011 (hex 01E3)
Since both registers are being loaded, CFG0 is loaded followed by the loading of CFG1. These two
registers must be loaded in this order. The internal set up for both registers will take effect
synchronously with the rising edge of SS
.
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6.5.2 Call Record
The call record mode adds the ability to record the incoming phone call. In most applications, the
ISD5008 would first be set up for Feed Through Mode as described above. When the user wishes to
record the incoming call, the set up of the chip is modified to add that ability. For the purpose of this
explanation, we will use the 6.4 kHz sample rate during recording.
The block diagram of the ISD5008 shows that the Multilevel Storage array is always driven from the
SUM2 SUMMING amplifier. The path traces back from there through the LOW PASS Filter, THE
FILTER MUX, THE SUM1 SUMMING amplifier, the SUM1 MUX, then from the ANA in amplifier. Feed
Through Mode has already powered up the ANA IN amp so we only need to power up and enable the
path to the Multilevel Storage array from that point:
1.
2.
Select the ANA IN path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of
the SUM1 MUX. These are bits D9 and D10 respectively of CFG1 and they should be set
to the state where both D9 and D10 are ZERO to select the ANA IN path.
Select the SUM1 MUX input (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively
of CFG1 and they should be set to the state where D7 is ONE and D8 is ZERO to select
the SUM1 MUX (only) path.
3.
4.
5.
6.
Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls
the state of the FILTER MUX. This is bit D4 of CFG1 and it should be set to ZERO to
select the SUM1 SUMMING amplifier path.
Power up the LOWPASS FILTER—Bit FLPD controls the power up state of the LOWPASS
FILTER stage. This is bit D1 of CFG1 and it should be set to ZERO to power up the LOW
PASS FILTER STAGE.
Select the 6.4 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1.
To enable the 6.4 kHz sample rate, D2 should be set to ONE and D3 to ZERO.
Select the LOW PASS FILTER input (only) to the SUM2 SUMMING amplifier—Bits S2M0
and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is
ONE to select the LOW PASS FILTER (only) path.
In this mode, the elements of the original PASS THROUGH mode do not change. The sections of the
chip not required to add the record path remain powered down. In fact, CFG0 does not change and
remains
CFG0=0100 0100 0000 1011 (hex 440B).
CFG1 changes to
CFG1=0000 0000 1100 0101 (hex 00C5).
Since CFG0 is not changed, it is only necessary to load CFG1. Note that if only CFG0 was changed, it
would be necessary to load both registers.
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6.5.3 Memo Record
The Memo Record mode sets the chip up to record from the local microphone into the chip’s Multilevel
Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down
and is not active in this mode. The path to be used is microphone input to AGC amplifier, then through
the INPUT SOURCE MUX to the SUM1 SUMMING amplifier. From there the path goes through the
FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL
STORAGE ARRAY. In this instance, we will select the 5.3 kHz sample rate. The rest of the chip may
be powered down.
1.
2.
Power up the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier.
This is bit D0 of CFG1 and should be set to ZERO to power up the stage.
Select the AGC amplifier through the INPUT SOURCE MUX—Bit INS0 controls the state
of the INPUT SOURCE MUX. This is bit D9 of CFG0 and should be set to a ZERO to
select the AGC amplifier.
3.
Select the INPUT SOURCE MUX (only) to the SUM1 SUMMING amplifier—Bits S1M0 and
S1M1 control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8
respectively of CFG1 and they should be set to the state where D7 is ZERO and D8 is
ONE to select the INPUT SOURCE MUX (only) path.
4.
5.
6.
7.
Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls
the state of the FILTER MUX. This is bit D4 of CFG1 and it should be set to ZERO to
select the SUM1 SUMMING amplifier path.
Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW
PASS FILTER stage. This is bit D1 of CFG1 and it should be set to ZERO to power up the
LOW PASS FILTER stage.
Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1.
To enable the 5.3 kHz sample rate, D2 should be set to ZERO and D3 set to ONE.
Select the LOW PASS FILTER input (only) to the SUM2 SUMMING amplifier—Bits S2M0
and S2M1 control the state of the SUM2 SUMMING amplifier. These bits are D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is
ONE to select the LOW PASS FILTER (only) path.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0001 (hex 2421).
CFG1=0000 0001 0100 1000 (hex 0148).
Only those portions necessary for this mode are powered up.
6.5.4 Memo and Call Playback
This mode sets the chip up for local playback of messages recorded earlier. The playback path is from
the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage.
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From there the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through
the VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a
pizeo speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages will be
powered down.
1.
2.
3.
4.
Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX—Bit FLS0
controls the state of the FILTER MUX. This is bit D4 of CFG1 and should be set to ONE to
select the MULTILEVEL STORAGE ARRAY.
Power up the LOW PASS FILTER—Bit FLPD controls the power up of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it should be set to ZERO to power up the LOW
PASS FILTER stage.
Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1.
To enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO.
Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0 and
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is
ONE to select the LOW PASS FILTER (only) path.
5.
Select the SUM2 SUMMING amplifier path through the VOLUME MUX—Bits VLS0 and
VLS1 control the state VOLUME MUX. These bits are D14 and D15, respectively of CFG1.
They should be set to the state where D14 is ONE and D15 is ZERO to select the SUM2
SUMMING amplifier.
6.
7.
Power up the VOLUME CONTROL LEVEL—Bit VLPD controls the power up state of the
VOLUME CONTROL attenuator. This is bit D0 of CFG0. This bit should be set a ZERO to
power up the VOLUME CONTROL.
Select a VOLUME CONTROL LEVEL—Bits VOL0, VOL1 and VOL2 control the state fo
the VOLUME CONTROL LEVEL. Theses are bits D11, D12 and D13, repectively of CFG1.
A binary count of 000 through 111 controls the amount of attenuation throught that state. In
most cases, the software will select an attenuation level according to the desires of the
current users of the product. In this example, we will assume the user wants an
attenuation of –12 dB. For that setting, D11 should be set to ONE, D12 should be set to
ONE, and D13 shoulde be set to ZERO.
8.
9.
Select the VOLUME CONTROL path through the OUTPUT MUX—Bits OPS0 and OPS1
control the state of the OUTPUT MUX. These are bits D3 and D4, respectively of CFG0.
They should be set to the state where D3 and D4 are ZERO to select the VOLUME
CONTROL.
Power up the SPEAKER amplifier and select the HIGH GAIN mode—Bits OPA0 and
OPA1 control the state of the speaker (SP+ and SP-) and AUX OUT outputs. These are
bits D1 and D2 of CFG0. They should be set to the state where D1 is ONE and D2 is
ZERO to power up the speaker outputs in the HIGH GAIN mode and to power down the
AUX OUT.
To set up the chip for Memo or Call Playback, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0010 (hex 2422).
Publication Release Date: Oct 31 2008
- 34 -
Revision 1.2
ISD5008
CFG1=0101 1001 1101 0001 (hex 59D1).
Only those portions necessary for this mode are powered up.
Publication Release Date: Oct 31 2008
Revision 1.2
- 35 -
ISD5008
7
TIMING DIAGRAMS
SS
BYTE 1
BYTE 2
BYTE 3
SCLK
LSB
C0
C4 C5 C6 C7
C1 C2
C3
MOSI
MISO
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
LSB
OVFEOMA0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
X
X
X
X
X
X
FIGURE 17: 24-BIT SPI COMMAND FORMAT
TSSH
SS
TSSmin
TSCKhi
TSSS
SCLK
MOSI
TDIH
TSCKlow
TDIS
TPD
TPD
TDF
(TRISTATE)
LSB
MISO
FIGURE 18: SPI TIMING DIAGRAM
Publication Release Date: Oct 31 2008
Revision 1.2
- 36 -
ISD5008
SS
SCLK
MOSI
Stop
Play/Record
Data
Data
MISO
TSTOP/PAUSE
(Rec)
ANA IN
TSTOP/PAUSE
(Play)
ANA OUT
FIGURE 19: PLAYBACK/RECORD AND STOP CYCLE
SS
SCLK
MOSI
LSB
A8
A9
A10
C0
C1
C2
C3
C4
LSB
OVF
EOM
P0
P1
P2
P3
P4
P5
MISO
FIGURE 20: 8-Bit SPI Command Format
Publication Release Date: Oct 31 2008
Revision 1.2
- 37 -
ISD5008
8
ABSOLUTE MAXIMUM RATINGS [1]
TABLE 10: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)
CONDITIONS VALUES
Junction temperature
150ºC
-65ºC to +150ºC
Storage temperature range
Voltage applied to any pin
(VSS – 0.3V) to (VCC + 0.3V)
(VSS – 1.0V) to 5.5V
Voltage applied to MOSI, SCLK, INT , RAC and SS pins
(Input current limited to ±20mA)
Lead temperature (Soldering – 10sec)
VCC – VSS
300ºC
-0.3V to +7.0V
TABLE 11: ABSOLUTE MAXIMUM RATINGS (DIE)
CONDITIONS
VALUES
150ºC
Junction temperature
Storage temperature range
-65ºC to +150ºC
(VSS – 0.3V) to 5.5V
Voltage applied to MOSI, SCLK, INT , RAC and SS pins
(Input current limited to ±20mA)
VCC – VSS
-0.3V to +7.0V
[1]
Note:
Stresses above those listed may cause permanent damage to the device. Exposure to the
absolute maximum ratings may affect device reliability and performance. Functional operation is
not implied at these conditions.
Publication Release Date: Oct 31 2008
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Revision 1.2
ISD5008
8.1 OPERATING CONDITIONS
TABLE 12: OPERATING CONDITIONS (PACKAGED PARTS)
CONDITION
Commercial operating temperature range (Case temperature)
Extended operating temperature (Case temperature)
Industrial operating temperature (Case temperature)
Supply voltage (VCC) [1]
VALUE
0ºC to +70ºC
-20ºC to +70ºC
-40ºC to +85ºC
+2.7V to 3.3V
Ground voltage (VSS) [2]
TABLE 13: OPERATING CONDITIONS (DIE)
CONDITION
Commercial operating temperature range
Supply voltage (VCC) [1]
VALUE
0ºC to +50ºC
+2.7V to +3.3V
0V
Ground voltage (VSS) [2]
[1]
V
V
= VCCA = VCCD
= VSSA = VSSD
CC
[2]
SS
Publication Release Date: Oct 31 2008
Revision 1.2
- 39 -
ISD5008
9
ELECTRICAL CHARACTERISTICS
9.1 GENERAL PARAMETERS
TABLE 14: GENERAL PARAMETERS
PARAMETERS
Input Low Voltage
Input High Voltage
Output Low Voltage
SYMBOLS
MIN(2)
TYP(1)
MAX(2)
UNITS
CONDITIONS
VIL
VCC x 0.2
V
V
V
V
VIH
VCC x 0.8
VOL
VOL1
0.4
0.4
IOL = 10 µA
IOL = 1 mA
RAC, INT Output Low
Voltage
Output High Voltage
Operating Current :
- Playback
VOH
ICC
VCC - 0.4
V
IOH = -10 µA
15
25
12
1
mA
mA
mA
µA
No load (3)
No load (3)
No load (3)
- Record
- Feedthru
(3) (4)
Standby Current
Input Leakage Current
MISO Tristate Current
ISB
IIL
10
1
10
µA
IHZ
30
1
µA
1. Typical values @ TA = 25º and 3.0V.
2. All Min/Max limits are guaranteed by Nuvoton via electronical testing or characterization. Not all
specifications are 100 percent tested.
3. VCCA and VCCD summed together.
4.
SS = VCCA = VCCD, XCLK = MOSI = VSSA = VSSD and all other pins floating.
Publication Release Date: Oct 31 2008
Revision 1.2
- 40 -
ISD5008
9.2 TIMING PARAMETERS
TABLE 15: TIMING PARAMETERS
CHARACTERISTICS
SYMBOLS
FS
MIN(2)
TYP(1)
MAX(2) UNITS
CONDITIONS
(4)
Sampling Frequency
8.0
kHz
kHz
kHz
kHz
(4)
(4)
(4)
6.4
5.3
4.0
3-dB Roll-Off
Point(3)(7)
Filter Pass Band
FCF
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
Record Duration
3.4
2.7
2.3
1.7
kHz
kHz
kHz
kHz
TREC
(6)
(6)
(6)
(6)
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
Playback Duration
4
5
6
8
min
min
min
min
TPLAY
(6)
(6)
(6)
(6)
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
Power-Up Delay
4
5
6
8
min
min
min
min
TPUD
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
Stop or Pause
25
31.25
37.5
50
msec
msec
msec
msec
TSTOP or PAUSE
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
50
62.5
75
msec
msec
msec
msec
100
Publication Release Date: Oct 31 2008
Revision 1.2
- 41 -
ISD5008
RAC Clock Period
TRAC
(9)
(9)
(9)
(9)
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
RAC Clock Low Time
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
200
250
300
400
msec
msec
msec
msec
TRACLO
25
31.25
37.5
50
msec
msec
msec
msec
RAC Clock Periond in
Messge Cueing Mode
TRACM
125
156.3
187.5
250
µsec
µsec
µsec
µsec
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
RAC Clock Low Time in
Message Cueing Mode
TRACML
15.63
19.53
23.44
31.25
µsec
µsec
µsec
µsec
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
Total Harmonic Distortion THD
1
2
%
@ 1 kHz at
0TLP, sample
rate = 5.3 kHz
ANA IN to ARRAY,
ARRAY to SPKR
9.3 ANALOG PARAMETERS
TABLE 16: ANALOG PARAMETERS
CHARACTERISTICS
MICROPHONE INPUT (14)
MIC+/- Input Voltage
SYMBOL
MIN (2)
TYP (1)
MAX (2)
UNITS
CONDITIONS
VMIC+/-
3
mV
mV
Peak-to-Peak (4)(8)
Peak-to-Peak (4)(10)
300
MIX+/- input reference VMIC (0TLP)
transmission level point
(0TLP)
208
6.0
(4)
Gain from MIC+/- input to AMIC
ANA OUT
5.5
6.5
dB
1kHz at VMIC (0TLP)
Publication Release Date: Oct 31 2008
Revision 1.2
- 42 -
ISD5008
MIC+/- Gain Tracking
AMIC (GT)
input RMIC
AGC AAGC
±0.1
10
dB
Ω
1kHz, +3 to 40 dB 0TLP
Input
Microphone
resistance
5
6
15
40
MIC- and MIC+ pins
Microphone
Amplifier Range
dB
Over 3-300 mV Input
Range
ANA IN (9)
ANA IN Input Voltage
VANA IN
1.6
V
V
Peak-to-Peak (6dB gain
setting)
ANA IN (0TLP) Input VANA
Voltage
1.11
Peak-to-Peak (6dB gain
setting) (10)
IN
(0TLP)
Gain from ANA IN to AANA IN (SP)
SP+/-
6 to 15
-4 to +5
dB
dB
4 Steps of 3 dB
Gain from ANA IN to AUX AANA IN (AUX
4 Steps of 3 dB
OUT
OUT)
(11)
ANA IN Gain Accuracy
ANA IN Gain Tracking
AANA IN (GA)
AANA IN (GT)
-0.5
+0.5
dB
dB
±0.1
1000 Hz, +3 to -40dB
0TLP Input, 6dB setting
ANA IN Input Resistance
RANA IN
60 to
102
kΩ
See Ra in Figure 2
AUX IN (9)
AUX IN Iput Voltage
VAUX IN
1.0
V
Peak-to-Peak (0dB gain
setting)
AUX IN (0TLP) Input VAUX
694.2
0 to 9
mV
dB
Peak-to-Peak (0dB gain
setting) (10)
IN
Voltage
(0TLP)
Gain from AUX IN to ANA AAUX IN (ANA
4 Steps of 3dB
OUT
OUT)
(11)
AUX IN Gain Accuracy
AUX IN Gain Tracking
AAUX IN (GA)
AAUX IN (GT)
-0.5
+0.5
dB
dB
±0.1
1000 Hz, +3 to -40dB
0TLP Input, 0dB setting
AUX IN Input Resistance
RAUX IN
21 to
40
kΩ
See Ra in Figure 3
SPEAKER OUTPUTS (9)
SP+/- Output Voltage VSPHG
(High Gain setting)
3.6
V
Peak-to-Peak, differential
load = 150 Ω; OPA1,
OPA0 = 01
SP+/- Output Load Imp. RSPLG
(Low Gain)
8
Ω
Ω
OPA1, OPA0 = 10
SP+/- Output Load Imp. RSPHG
(High Gain)
70
OPA1, OPA0 = 01
SP+/- Output Load Cap.
CSP
100
pF
SP+/- Output Bias Voltage VSPAG
(analog ground)
1.2
VDC
Publication Release Date: Oct 31 2008
Revision 1.2
- 43 -
ISD5008
Speaker Output DC Offset VSPDCO
ANA IN to SP+/- Idle ICNANA
-100
100
mVDC
With ANA IN to Speaker,
ANA IN AC coupled to
VSSA
-65
-65
dB
dB
Speaker load = 150 Ω
(12)(13)
Channel Noise
IN/(SP+/-)
SP+/- to ANA OUT Cross CRT(SP+/-)
1kHz 0TLP input to ANA
IN, with MIC+/ and AUX
Talk
ANA OUT
IN AC coupled to VSSA
,
and measured at ANA
OUT feedthrough mode
(12)
Power Supply Rejection PSRR
Ratio
-50
dB
dB
Measured
with
a
1kHz,100 mVpp sine
wave input at VCCA and
VCCD pins
Frequency
Response FR
-0.25
23.5
62.5
+0.25
With 0TLP input to ANA
IN, 6dB setting (12)
(300-3400 Hz)
Power Output (Low Gain POUTLG
Setting)
mW
RMS
Differential load at 8 Ω
SINAD ANA IN to SP+/-
SINAD
dB
0TLP ANA IN input
minimum gain, 150
Ω
load (12)(13)
ANA OUT (9)
SINAD MIC IN to ANA SINAD
Out+/-
62.5
62.5
dB
dB
dB
dB
dB
Load = 5 kΩ (12)(13)
Load = 5 kΩ (12)(13)
Load = 5 kΩ (12)(13)
Load = 5 kΩ (12)(13)
SINAD AUX IN to ANA SINAD
OUT+/-
Idle Channel Noise
Microphone
–
ICNMIC/ANA
OUT
-65
-65
Idle Channel Noise – AUX ICNAUX
IN
IN (0 to 9 dB)
/NA OUT
Power Supply Rejection PSRR(ANA
-50
1.2
Measured with a 1kHz,
100mVpp sine wave to
VCCA, VCCD pins
Ratio
OUT)
ANA OUT+ and ANA VBIAS
OUT-
VDC
mVDC
kΩ
Inputs AC coupled to
VSSA
ANA OUT+ and ANA VOFFSET
OUT-
-100
5
+100
Inputs AC coupled to
VSSA
Minimum
Load RL
Differential Load
Impedence
Frequency
(300-3400 Hz)
Response FR
-0.25
+0.25
dB
0TLP input to MIC+/- in
feedthrough mode.
0TLP input to AUX IN in
feedthrough mode (12)
Publication Release Date: Oct 31 2008
Revision 1.2
- 44 -
ISD5008
ANA OUT to SP+/- Cross CRTANA
-65
-65
dB
dB
1kHz 0TLP output from
ANA OUT, with ANA IN
AC coupled to VSSA, and
measured at SP+/- (12)
Talk
OUT/(SP+/-)
ANA OUT to AUX OUT CRTANA
1kHz 0TLP output from
ANA OUT, with ANA IN
AC coupled to VSSA, and
Cross Talk
OUT/AUX OUT
measured at AUX OUT
(12)
AUX OUT (9)
AUX OUT
Output Swing
–
Maximum VAUX OUT
Load RL
1.0
Vpp
kΩ
5 kΩ Load
Minimum
5
Impedence
Maximum
Load CL
100
pF
Capacitance
AUX OUT
VBIAS
1.2
VDC
dB
SINAD – ANA IN to AUX SINAD
62.5
0TLP ANA IN input,
OUT
minimum gain, 5k load
(12)(13)
Idle Channel Noise – ANA ICN(AUX
-65
-65
dB
dB
Load = 5 kΩ (12)(13)
IN to AUX OUT
OUT)
AUX OUT to ANA OUT CRTAUX
Cross Talk
1 kHz 0TLP input to ANA
IN, with MIC +/- and AUX
OUT/ANA OUT
IN AC coupled to VSSA
,
and measured at SP+/-,
load = 5 kΩ. Referenced
to nominal 0TLP
output
@
VOLUME CONTROL (9)
Output Gain
AOUT
-28 to 0
dB
dB
8
Steps of
4
dB,
referenced to output
Gain Accuracy
-0.5
0.5
ANA IN = 1 kHz 0TLP,
6dB Gain setting
Notes:
1. Typical values: TA = 25°C and Vcc = 3.0V.
2. All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications
are 100 percent tested.
3. Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions).
4. Differential input mode. Nominal differential input is 208 mVp-p. (0 dBm0)
5. Sampling frequency can vary as much as –6/+4 percent over the industrial temperature and voltage
ranges. For greater stability, an external clock can be utilized (see Pin Descriptions). Sampling
frequency will be accurate within ±1% for 5.3kHz, and ±5% for 4.0, 6.4 and 8.0 kHz sampling rates at
room temperature.
Publication Release Date: Oct 31 2008
- 45 -
Revision 1.2
ISD5008
6. Playback and Record Duration can vary as much as –6/+4 percent over the industrial temperature and
voltage ranges. For greater stability, an external clock can be utilized (See Pin Descriptions). Playback
and record durations are accurate within ±1% for 5.3kHz, and ±5% for 4.0, 6.4 and 8.0kHz sampling
rates at room temperature.
7. Filter specification applies to the low pass filter. Therefore, from input to output, expect a 6 dB drop by
nature of passing through the filter twice.
8. For optimal signal quality, this maximum limit is recommended.
9. When a record command is sent, TRAC = TRAC + TRACLO on the first row addressed.
10. The maximum signal level at any input is defined as 3.17dB higher than the reference transmission
level point. (0TLP) This is the point where signal clipping may begin.
11. Measured at 0TLP point for each gain setting. See Table 4 and Table 5.
12. 0TLP is the reference test level through inputs and outputs. See Table 4 and Table 5.
13. Referenced to 0TLP input at 1kHz, measured over 300 to 3,400 Hz bandwidth.
14. For die, only typical values from Analog Parameters are applicable.
Publication Release Date: Oct 31 2008
- 46 -
Revision 1.2
ISD5008
9.4
SPI AC PARAMETERS (1)
TABLE 17: SPI AC PARAMETERS
CHARACTERISTIC
SYMBOL
TSSS
MIN
MAX
UNITS
CONDITIONS
500
nsec
SS Setup Time
TSSH
500
nsec
SS Hold Time
Data in Setup Time
Data in Hold Time
Output Delay
TDIS
TDIH
TPD
200
200
nsec
nsec
nsec
nsec
µsec
500
500
(2)
Output Delay to hiZ
TDF
TSSmin
1
SS HIGH
SCLK High Time
SCLK Low Time
CLK Frequency
Notes:
TSCKhi
TSCKlow
F0
400
400
nsec
nsec
kHz
1,000
1. Typical values @ TA = 25º and VCC = 3.0V. Timing measured at 50 percent of the VCC level.
2. Tristate test condition.
VCC
6.32K
MISO
10.91K
50pF (Includes scope and fixture capacitance)
Publication Release Date: Oct 31 2008
Revision 1.2
- 47 -
ISD5008
10 TYPICAL APPLICATION CIRCUIT
1
To μC I/O
for message
management
(optional)
SClk
24
25
μ
To C
RAC
INT
2
3
4
SS
SPI Interface
& Address
Setting
MOSI
MISO
VCC
27
28
17
VCC
VCCD
VCCD
VCCA
0.1 F
μ
Ω
1.5K
0.1 F
μ
Ω
1.5K
8
MIC+
0.1μF
5
6
VSSD
VSSD
VSSA
VSSA
VSSA
220
F
μ
Electret
ISD5008
0.1 F
μ
9
microphone
10
13
MIC-
15
23
Ω
1.5K
4.7 F
μ
20
11
ACAP
Aux Out
AnaOut+
12
AnaOut-
18
19
Ana In
Aux In
16
14
SP+
SP-
SOIC / PDIP
FIGURE 21: Recording via Microphone
Publication Release Date: Oct 31 2008
Revision 1.2
- 48 -
ISD5008
11 PACKAGE DRAWING AND DIMENSIONS
11.1 28-LEAD LEAD 8X13.4MM PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE 1
A
B
G
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
F
C
9
10
18
17
16
15
11
12
13
14
E
J
H
INCHES
Nom
MILLIMETERS
Nom
Min
Max
0.711
0.104
0.299
0.0115
0.016
Min
Max
A
0.701
0.097
0.292
0.005
0.014
0.706
0.101
0.296
0.009
0.016
0.050
0.406
0.032
17.81
2.46
17.93
2.56
18.06
2.64
7.59
0.29
0.48
0
B
C
D
E
F
7.42
7.52
0.127
0.35
0.22
0.41
1.27
G
H
0.400
0.024
0.410
0.040
10.16
0.61
10.31
0.81
10.41
1.02
Note: Lead coplanarity to be within 0.004 inches.
Publication Release Date: Oct 31 2008
Revision 1.2
- 49 -
ISD5008
11.2 28-LEAD 600 MIL PLASTIC DUAL INLINE PACKAGE (PDIP)
INCHES
Nom
MILLIMETERS
Min
Max
Min
Nom
36.83
3.81
Max
A
B1
B2
C1
C2
D
1.445
1.450
0.150
0.070
1.455
36.70
36.96
0.065
0.600
0.530
0.075
0.625
0.550
0.19
1.65
15.24
13.46
1.78
1.91
15.88
13.97
4.83
0.540
13.72
D1
E
0.015
0.125
0.015
0.055
0.38
3.18
0.38
1.40
0.135
0.022
0.065
3.43
0.56
1.62
F
0.018
0.060
0.100
0.010
0.075
0.46
1.52
2.54
0.25
1.91
G
H
J
0.008
0.070
0°
0.012
0.080
15°
0.20
1.78
0°
0.30
2.03
15°
S
θ
Publication Release Date: Oct 31 2008
Revision 1.2
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ISD5008
11.3 28-LEAD 300 MIL PLASTIC SMALL OUTLINE IC (SOIC)
28
26 25
23 22 21 20 19 18 17
15
16
27
24
1
2
3
4
5
6 7
9 10 11 12 13 14
8
A
G
C
B
D
F
E
H
INCHES
Nom
MILLIMETERS
Nom
Min
Max
0.711
0.104
0.299
0.0115
0.019
Min
17.81
2.46
Max
18.06
2.64
7.59
0.29
0.48
A
B
C
D
E
F
0.701
0.097
0.292
0.005
0.014
0.706
0.101
0.296
0.009
0.016
0.050
0.406
0.032
17.93
2.56
7.42
7.52
0.127
0.35
0.22
0.41
1.27
G
H
0.400
0.024
0.410
0.040
10.16
0.61
10.31
0.81
10.41
1.02
Note: Lead coplanarity to be within 0.004 inches.
Publication Release Date: Oct 31 2008
Revision 1.2
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ISD5008
12 ORDERING INFORMATION
ISD5008xxx
Product Series :
ISD5008 Series
Temperature :
Industrial (-40C to +85C)
I
=
(4 to 8 minutes duration)
Blank = Commerical (0C to +70C)
Package Option :
Y
= Lead-free
Package Type :
P
S
E
=
=
=
Plastic Dual Inline Package (PDIP) Package
Small Outline Integrated Circuit (SOIC) Package
Thin Small Outline Package (TSOP) Package
When ordering, please refer to the above valid part number scheme that are supported in volume for
this product series. Contact the local Nuvoton Sales Representative or Distributor for availability
information.
For the latest product information, access Nuvoton’s worldwide website at
http://www.Nuvoton-usa.com
Publication Release Date: Oct 31 2008
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Revision 1.2
ISD5008
13 VERSION HISTORY
VERSION
DATE
DESCRIPTION
0
Before 2004
April, 2004
Initial issue
1.0
Reformat the document.
Add application diagram.
Revise die info.
Revise ordering information.
1.1
Feb, 2008
Update Opcode
Update power-up sequence.
Update pin description of RAC and INT.
Publication Release Date: Oct 31 2008
Revision 1.2
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ISD5008
The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton
makes no representation or warranties with respect to the accuracy or completeness of the contents of this
publication and reserves the right to discontinue or make changes to specifications and product descriptions at
any time without notice. No license, whether express or implied, to any intellectual property or other right of
Nuvoton or others is granted by this publication. Except as set forth in Nuvoton's Standard Terms and
Conditions of Sale, Nuvoton assumes no liability whatsoever and disclaims any express or implied warranty of
merchantability, fitness for a particular purpose or infringement of any Intellectual property.
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or
equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other
applications intended to support or sustain life. Further more, Nuvoton products are not intended for
applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death
or severe property or environmental injury could occur.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration
only and Nuvoton makes no representation or warranty that such applications shall be suitable for the use
specified.
ISD® and ChipCorder® are treademarks of Nuvoton Electronics Corporation. SuperFlash® is the trademark of
Silicon Storage Technology, Inc.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as
published in the Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton.
Information contained in this ISD® ChipCorder® data sheet supersedes all data for the ISD ChipCorder products
published by ISD® prior to August, 1998.
This data sheet and any future addendum to this data sheet is(are) the complete and controlling ISD®
ChipCorder® product specifications. In the event any inconsistencies exist between the information in this and
other product documentation, or in the event that other product documentation contains information in addition to
the information in this, the information contained herein supersedes and governs such other information in its
entirety.
Copyright© 2003, Nuvoton Technology Corporation. All rights reserved. ISD® is a registered trademark of
Nuvoton. ChipCorder® is a treademark of Nuvoton. All other trademarks are properties of their respective
owners.
Headquarters
Nuvoton Technology Corporation America
Nuvoton Technology (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
27F, 299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62356998
TEL: 886-3-5770066
FAX: 1-408-5441797
FAX: 886-3-5665577
http://www.Nuvoton-usa.com/
http://www.Nuvoton.com.tw/
Taipei Office
Nuvoton Technology Corporation Japan
Nuvoton Technology (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District
Taipei, 114 Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
7F Daini-ueno BLDG. 3-7-18
Shinyokohama Kohokuku,
Yokohama, 222-0033
TEL: 81-45-4781881
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
FAX: 81-45-4781800
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
This product incorporates SuperFlash® technology licensed From SST.
Publication Release Date: Oct 31 2008
Revision 1.2
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