M0519LE3AE [NUVOTON]
ARM® Cortex®-M0 32-bit Microcontroller;
| 型号： | M0519LE3AE |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortex®-M0 32-bit Microcontroller 微控制器 |
| 文件： | 总69页 (文件大小：1522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M0519
ARM® Cortex® -M0
32-bit Microcontroller
NuMicro® Family
M0519 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Nov. 02, 2016
Page 1 of 69
Rev 1.02
M0519
Table of Contents
1
2
3
4
GENERAL DESCRIPTION .......................................................................6
FEATURES .........................................................................................7
ABBREVIATIONS................................................................................10
PARTS INFORMATION LIST AND PIN CONFIGURATION ..............................12
NuMicro® M0519 Selection Guide..................................................................12
Pin Configuration......................................................................................13
Pin Description ........................................................................................16
BLOCK DIAGRAM ...............................................................................23
FUNCTIONAL DESCRIPTION.................................................................24
ARM® Cortex® -M0 Core..............................................................................24
System Manager......................................................................................26
Clock Controller .......................................................................................35
Flash Memory Controller (FMC)....................................................................38
General Purpose I/O (GPIO)........................................................................39
Timer Controller (TIMER)............................................................................40
Basic PWM Generator and Capture Timer (BPWM) ............................................41
Enhanced PWM Generator (EPWM) ..............................................................42
Enhanced Input Capture Timer (ECAP)...........................................................43
4.1
4.2
4.3
5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
Watchdog Timer (WDT)..............................................................................44
Window Watchdog Timer (WWDT) ................................................................45
Universal Asynchronous Receiver Transmitter (UART) ........................................46
I2C Serial Interface Controller (I²C) ................................................................47
Serial Peripheral Interface (SPI)....................................................................48
Hardware Divider (HDIV) ............................................................................49
Enhanced Analog-to-Digital Converter (EADC)..................................................50
Analog Comparator (ACMP) ........................................................................51
OP Amplifier (OPA)...................................................................................52
7
ELECTRICAL CHARACTERISTICS ..........................................................53
Absolute Maximum Ratings .........................................................................53
DC Electrical Characteristics........................................................................54
AC Electrical Characteristics........................................................................58
Analog Characteristics ...............................................................................60
7.1
7.2
7.3
7.4
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7.5
Flash DC Electrical Characteristics ................................................................64
PACKAGE DIMENSIONS ......................................................................65
LQFP 100V (14x14x1.4 mm footprint 2.0mm) ...................................................65
LQFP 64S (7x7x1.4 mm footprint 2.0 mm) .......................................................66
LQFP 48L (7x7x1.4mm footprint 2.0mm) .........................................................67
REVISION HISTORY............................................................................68
8
9
8.1
8.2
8.3
Nov. 02, 2016
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List of Figures
Figure 4-1 NuMicro® M0519 Selection Code........................................................................ 12
Figure 4-2 NuMicro® M0519VxxAE Series LQFP-100 Pin Diagram ..................................... 13
Figure 4-3 NuMicro® M0519SxxAE Series LQFP-64 Pin Diagram ....................................... 14
Figure 4-4 NuMicro® M0519LxxAE Series LQFP-48 Pin Diagram........................................ 15
Figure 5-1 NuMicro® M0519 Series Block Diagram.............................................................. 23
Figure 6-1 Functional Controller Diagram ............................................................................ 24
Figure 6-2 NuMicro® M0519 Series Power Distribution Diagram.......................................... 27
Figure 6-3 Clock Generator Block Diagram ......................................................................... 36
Figure 6-4 Clock Generator Global View Diagram ............................................................... 37
Figure 7–1 Typical Crystal Application Circuit...................................................................... 58
Nov. 02, 2016
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List of Tables
Table 6-1 Address Space Assignments for On-Chip Controllers.......................................... 29
Table 6-2 Exception Model .................................................................................................. 32
Table 6-3 System Interrupt Map Vector Table...................................................................... 33
Table 6-4 Vector Table ........................................................................................................ 34
Table 6-5 Clock Stable Count Value Table .......................................................................... 35
Nov. 02, 2016
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1
GENERAL DESCRIPTION
The NuMicro® M0519 Series 32-bit microcontroller is embedded with the newest ARM® Cortex® -
M0 core at a cost equivalent to traditional 8-bit microcontroller for industrial control and
applications which need high performance.
The NuMicro® M0519 Series embedded with the Cortex® -M0 core runs up to 72 MHz and
supports a variety of industrial control and applications which need high CPU performance. The
NuMicro® M0519 Series provides 128K/64K bytes embedded flash, 4 Kbytes data flash, 8 Kbytes
flash for the ISP, and 16K bytes embedded SRAM. This MCU includes advanced PWM function
and input capture timer which are specially designed for motor driving application. It is also
equipped with plenty of peripheral devices, such as Timers, Watchdog Timer, UART, SPI, I2C,
PWM Timer, GPIO, 12-bit ADC, Low Voltage Detector and Brown-out detector. These useful
functions make the NuMicro® M0519 Series powerful for a wide range of applications.
In addition, the NuMicro® M0519 Series is equipped with ISP (In-System Programming), ICP (In-
Circuit Programming) functions and IAP (In-Application Programming) which allow user to update
the program memory without removing the chip from the actual end product.
Nov. 02, 2016
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2
FEATURES
Core
–
–
–
–
–
ARM® Cortex® -M0 core running up to 72 MHz
One 24-bit system timer
Supports Low Power Sleep mode by WFI instructions
Single-cycle 32-bit hardware multiplier
Supports programmable 4 level priorities of Nested Vectored Interrupt Controller
(NVIC)
–
Supports Serial Wire Debug (SWD) support with two watchpoints and four breakpoints
Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V
Memory
–
–
–
–
128K/64K bytes Flash for program memory (APROM)
4KB Flash for data memory (Data Flash)
8KB Flash for loader (LDROM)
Supports In-system program (ISP) and In-application program (IAP) application code
update
–
–
–
Supports 2-wired ICP update through SWD/ICE interface
Supports fast parallel programming mode by external programmer
16K bytes embedded SRAM
Clock Control
–
Built-in 22.1184 MHz internal high speed RC oscillator (HIRC) for system operation
(variation < 2% at -40˚C ~ +105˚C)
–
–
–
–
Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-
up operation
Built-in 4~24 MHz external high speed crystal oscillator (HXT) for precise timing
operation
Supports one PLL up to 72 MHz for high performance system operation, sourced from
HIRC and HXT
Supports clock output
Hardware divider
–
Supports signed 32-bit dividend, 16-bit divisor operation
GPIO port
–
–
–
–
–
–
–
Four I/O modes:
TTL/Schmitt trigger input selectable
Bit control available
I/O pin configured as interrupt source with edge/level trigger setting
Supports high driver and high sink current I/O (up to 16 mA at 5V)
INT0 and INT1 pins with individual interrupt vectors
Supports up to 82/51/38 GPIOs for LQFP100/64/48 respectively
Timers
–
–
–
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
Provides One-shot, Periodic, Toggle and Continuous Counting operation modes
Supports event counting function to count the event from external pin
Watchdog Timer
–
–
–
–
–
Supports multiple clock sources from LIRC(default selection) and HCLK/2048
8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source)
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Time-out reset delay period time can be selected
Window Watchdog Timer
Nov. 02, 2016
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M0519
–
–
–
Supports multiple clock sources from HCLK/2048 (default selection) and LIRC
Window set by 6-bit counter with 11-bit prescale
Able to wake up from Power-down or Idle mode
Basic PWM
–
–
1 unit of 16-bit basic PWM, up to 2ch output
Alternative function as input capture timer
Enhanced PWM
–
2 units of 16-bit enhanced PWM, up to 6ch output with dead-zone control, brake and
polarity control for motor drive
–
Default tri-state during any reset
Enhanced Input Capture
–
–
Up to 2 units of 24-bit input capture
Each unit has 3 inputs: ECAPx_IC0, ECAPx_IC1 and ECAPx_IC2
UART
–
–
–
–
–
–
Up to two 16550 compatible UART devices
Programmable baud-rate generator
Buffered receiving and transmitting, each with 16 bytes FIFO
Supports flow control (TX, RX, CTS and RTS)
Supports IrDA(SIR) function
Supports RS-485
SPI
–
–
–
–
–
–
–
Up to three sets of SPI device
Supports SPI master/slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Supports Byte Suspend mode in 32-bit transmission
I2C
–
–
–
–
–
–
Master/Slave up to 1 Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters
Programmable clocks allow versatile rate control
Multiple address recognition (four slave address with mask option)
ADC
–
–
–
–
–
Two A/D converters
Each ADC with up to 8 channel, 12-bit resolution with 10-bit accuracy
16 result registers
Sampling rate up to 800ksps
Two operating modes:
Single Sampling mode: Only one specified channel can be sampled at one time.
Simultaneous Sampling mode: Allowing two ADC channels to be sampled
simultaneously.
–
–
Two converting result digital comparators
Conversion start by software, external pins, or linked with Timer 0~3 or PWM module
Up to three Analog Comparators
Up to two OPA (operational amplifier)
Nov. 02, 2016
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M0519
Brown-out detector
–
–
4 levels: 4.4V/3.7V/2.7V/2.2V
Optional brown-out interrupt or reset
Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V
Low Voltage Reset
96-bit unique ID
Operating Temperature: -40℃~105℃
Develop tools: parallel writer or In-Circuit Programming (ICP) writer
Packages:
–
–
All Green package (RoHS)
LQFP 100/64/48-pin
Nov. 02, 2016
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3
ABBREVIATIONS
Acronym
Description
ACMP
ADC
AES
APB
AHB
BOD
CAN
DAP
DES
EBI
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
Advanced High-Performance Bus
Brown-out Detection
Controller Area Network
Debug Access Port
Data Encryption Standard
External Bus Interface
EPWM
FIFO
FMC
FPU
GPIO
HCLK
HIRC
HXT
IAP
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital Input/Output
Serial Peripheral Interface
SDIO
SPI
Nov. 02, 2016
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M0519
SPS
Samples per Second
TDES
TMR
Triple Data Encryption Standard
Timer Controller
UART
UCID
USB
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Nov. 02, 2016
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4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® M0519 Selection Guide
4.1.1 NuMicro® M0519 Selection Guide
Connectivity
x2,
M0519LD3AE
M0519LE3AE
M0519SD3AE
M0519SE3AE
M0519VE3AE
64
128
64
16
16
16
16
16
4
8
8
8
8
8
38
38
51
51
82
4
4
4
4
4
2
2
2
2
2
1
1
2
2
3
1
1
1
1
1
2
2
2
2
2
-
-
6
2
2
2
2
2
2
2
2
2
3
v
v
v
v
v
LQFP48
LQFP48
LQFP64
LQFP64
LQFP100
16-ch
x2,
Config.
4
6
16-ch
x2,
-
10
10
14
16-ch
x2,
128
128
Config.
Config.
-
16-ch
x2,
6
16-ch
4.1.2 NuMicro® M0519 Naming Rule
- X X
M0519
X E
X
CPU core
ARM Cortex M0
Temperature
E: - 40℃ ~ +105℃
Package Type
Version
A: Version
L: LQFP 48 (7x7)
S: LQFP 64 (7x7)
V: LQFP 100 (14x14)
SRAM Size
Flash ROM
3: 16KB SRAM
D: 64 KB Flash ROM
E: 128 KB Flash ROM
Figure 4-1 NuMicro® M0519 Selection Code
Nov. 02, 2016
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Rev 1.02
M0519
4.2 Pin Configuration
4.2.1 LQFP 100-pin
ADC1_CH7/P7.7
ADC1_CH6/P7.6
ACMP2_P/ADC1_CH5/P7.5
ACMP2_N/ADC1_CH4/P7.4
ADC1_CH3/P7.3
ADC1_CH2/P7.2
ADC1_CH1/P7.1
ADC1_CH0/P7.0
ACMP0_P/P8.4
ACMP0_N/P8.3
OP1_O/P9.0
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P5.2/SPI2_MISO/ACMP1_O
P2.0/SPI2_MOSI/ACMP2_O
P2.1/ECAP0_IC2
P2.2/ECAP0_IC1
P2.3/ECAP0_IC0
P0.4/EPWM0_CH4
P0.5/EPWM0_CH5
P0.6/EPWM0_BRAKE1
P0.7/STADC
P2.4
P2.5
OP1_N/P9.1
P2.6/SPI0_SS/UART1_nCTS
P2.7/SPI0_CLK/UART1_nRTS
P5.1/SPI0_MISO/UART0_nCTS/I2C_SDA
P5.0/SPI0_MOSI/UART0_nRTS/I2C_SCL
VSS
M0519VxxAE
LQFP 100-pin
OP1_P/P9.2
VDD
VSS
P8.5
EPWM1_BRAKE1/P9.3
nRESET
VDD
P4.7/TM3
XT1_OUT
P3.1/UART0_TXD/ACMP0_O
P3.0/UART0_RXD/CLKO
P1.0/EPWM1_CH0
P1.1/EPWM1_CH1
P4.6/TM2
XT1_IN
ICE_DAT
ICE_CLK
SPI1_CLK/P9.4
SPI1_MISO/P9.5
SPI1_MOSI/P9.6
P3.3/INT1
P4.3
Figure 4-2 NuMicro® M0519VxxAE Series LQFP-100 Pin Diagram
Nov. 02, 2016
Page 13 of 69
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4.2.2 LQFP 64-pin
ADC1_CH7/P7.7
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P5.2/SPI2_MISO/ACMP1_O
P2.0/SPI2_MOSI/ACMP2_O
P0.4/EPWM0_CH4
P0.5/EPWM0_CH5
P2.4
ADC1_CH6/P7.6
ACMP2_P/ADC1_CH5/P7.5
ACMP2_N/ADC1_CH4/P7.4
ADC1_CH3/P7.3
ADC1_CH2/P7.2
ADC1_CH1/P7.1
ADC1_CH0/P7.0
OP1_O/P9.0
P2.5
P2.6/SPI0_SS/UART1_nCTS
P2.7/SPI0_CLK/UART1_nRTS
M0519SxxAE
LQFP 64-pin
P5.1/SPI0_MISO/UART0_nCTS/I2C_SDA
P5.0/SPI0_MOSI/UART0_nRTS/I2C_SCL
VSS
OP1_N/P9.1
OP1_P/P9.2
nRESET
VDD
XT1_OUT
P3.1/UART0_TXD
XT1_IN
P3.0/UART0_RXD/CLKO
P1.0/EPWM1_CH0
ICE_DAT
ICE_CLK
P1.1/EPWM1_CH1
Figure 4-3 NuMicro® M0519SxxAE Series LQFP-64 Pin Diagram
Nov. 02, 2016
Page 14 of 69
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M0519
4.2.3 LQFP 48-pin
ADC1_CH7/P7.7
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
P6.7/ADC0_CH7
ADC1_CH6/P7.6
ACMP2_P/ADC1_CH5/P7.5
ACMP2_N/ADC1_CH4/P7.4
ADC1_CH3/P7.3
ADC1_CH2/P7.2
ADC1_CH1/P7.1
ADC1_CH0/P7.0
OP1_O/P9.0
P0.7/STADC
P2.6/SPI0_SS/UART1_nCTS
P2.7/SPI0_CLK/UART1_nRTS
P5.1/SPI0_MISO/UART0_nCTS/I2C_SDA
P5.0/SPI0_MOSI/UART0_nRTS/I2C_SCL
P3.1/UART0_TXD/ACMP0_O
P3.0/UART0_RXD/CLKO
P1.5/EPWM1_CH5
M0519LxxAE
LQFP 48-pin
OP1_N/P9.1
P1.4/EPWM1_CH4
OP1_P/P9.2
P1.3/EPWM1_CH3
nRESET
P1.2/EPWM1_CH2
Figure 4-4 NuMicro® M0519LxxAE Series LQFP-48 Pin Diagram
Nov. 02, 2016
Page 15 of 69
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4.3 Pin Description
Pin Number
Pin
Pin Name
Description
Type[1]
100- pin 64-pin 48-pin
10
6
34
7
VDD
P
P
POWER SUPPLY: Supply voltage Digital VDD for operation.
61
89
11
35
60
90
21
7
8
6
VSS
GROUND: Digital Ground potential.
22
5
LDO: LDO output pin
9
LDO_CAP
P
P
Note: It needs to be connected with a 1uF capacitor.
1
-
-
PVSS
AVDD
AVSS
PLL GROUND: PLL Ground potential.
74
73
47
46
36
35
AP Power supply for internal analog circuit
AP Ground Pin for analog circuit
Voltage reference input for ADC
75
48
-
VREF
AP
Note: It needs to be connected with a 1uF capacitor.
RESET: nRESET pin is a Schmitt trigger input pin for hardware device
reset. A “Low” on this pin for 768 clock counter of Internal RC 22.1184
MHz while the system clock is running will reset the device. nRESET
pin has an internal pull-up resistor allowing power-on reset by simply
I
93
60
48
nRESET
(ST)
connecting an external capacitor to GND.
CRYSTAL OUT: This is the output pin from the internal inverting
amplifier. It emits the inverted signal of XT1_IN.
94
95
61
62
4
3
XT1_OUT
XT1_IN
O
CRYSTAL IN: This is the input pin to the internal inverting amplifier.
The system clock is from external crystal or resonator when FOSC[1:0]
(CONFIG3[1:0]) are both logic 1 by default.
I
(ST)
96
97
63
64
2
1
ICE_DAT
ICE_CLK
P0.0
I/O Serial Wired Debugger Data pin
I
Serial Wired Debugger Clock pin
I/O General purpose digital I/O pin
57
-
-
PWM0_CH0
ECAP1_IC0
P0.1
O
I
PWM0 output of PWM Unit 0
Input 0 of Enhanced Input Capture Unit 1
I/O General purpose digital I/O pin
56
55
-
-
-
-
PWM0_CH1
ECAP1_IC1
P0.2
O
I
PWM1 output of PWM Unit 0
Input 1 of Enhanced Input Capture Unit 1
I/O General purpose digital I/O pin
PWM0_CH2
O
PWM2 output of PWM Unit 0
Nov. 02, 2016
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Pin Number
Pin
Pin Name
Description
Type[1]
100- pin 64-pin 48-pin
ECAP1_IC2
P0.3
I
Input 2 of Enhanced Input Capture Unit 1
I/O General purpose digital I/O pin
54
45
-
-
-
PWM0_CH3
STADC
O
I
PWM3 output of PWM Unit 0
ADC external trigger input
P0.4
I/O General purpose digital I/O pin
PWM4 output of PWM Unit 0
I/O General purpose digital I/O pin
PWM5 output of PWM Unit 0
I/O General purpose digital I/O pin
Brake input pin 1 of PWM Unit 0
I/O General purpose digital I/O pin
ADC external trigger input
I/O General purpose digital I/O pin
PWM0 output of PWM Unit 1
I/O General purpose digital I/O pin
PWM1 output of PWM Unit 1
I/O General purpose digital I/O pin
PWM2 output of PWM Unit 1
I/O General purpose digital I/O pin
PWM3 output of PWM Unit 1
I/O General purpose digital I/O pin
PWM4 output of PWM Unit 1
I/O General purpose digital I/O pin
PWM5 output of PWM Unit 1
I/O General purpose digital I/O pin
Brake input pin 0 of PWM Unit 0
I/O General purpose digital I/O pin
Brake input pin0 of PWM Unit 1
30
PWM0_CH4
P0.5
O
44
43
42
30
29
20
19
18
17
16
8
29
-
-
-
PWM0_CH5
P0.6
O
PWM0_BRAKE1
P0.7
I
-
23
-
STADC
I
P1.0
18
17
16
15
14
13
12
4
PWM1_CH0
P1.1
O
-
PWM1_CH1
P1.2
O
13
14
15
16
-
PWM1_CH2
P1.3
O
PWM1_CH3
P1.4
O
PWM1_CH4
P1.5
O
PWM1_CH5
P1.6
O
PWM0_BRAKE0
P1.7
I
5
PWM1_BRAKE0
P2.0
I
I/O General purpose digital I/O pin
I/O SPI2 MOSI (Master Out, Slave In) pin
AO Analog comparator 2 output pin
I/O General purpose digital I/O pin
49
48
31
-
-
-
SPI2_MOSI
ACMP2_O
P2.1
ECAP0_IC2
I
Input 2 of Enhanced Input Capture Unit 0
Nov. 02, 2016
Page 17 of 69
Rev 1.02
M0519
Pin Number
Pin
Pin Name
Description
Type[1]
100- pin 64-pin 48-pin
P2.2
I/O General purpose digital I/O pin
47
46
-
-
-
-
ECAP0_IC1
P2.3
I
Input 1 of Enhanced Input Capture Unit 0
I/O General purpose digital I/O pin
Input 0 of Enhanced Input Capture Unit 0
ECAP0_IC0
P2.4
I
41
40
28
27
-
-
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O SPI0 slave select pin
P2.5
P2.6
39
26
22
SPI0_SS
UART1_nCTS
P2.7
I
UART1 CTS pin
I/O General purpose digital I/O pin
I/O SPI0 serial clock pin
38
31
25
19
21
17
SPI0_CLK
UART1_nRTS
P3.0
O
UART1 RTS pin
I/O General purpose digital I/O pin
Data Receiver input pin for UART0
I/O General purpose digital I/O pin
Data transmitter output pin for UART0
UART0_RXD
I
P3.1
32
20
18
UART0_TXD
ACMP0_O
P3.2
O
AO Analog comparator 0 output
I/O General purpose digital I/O pin
7
3
-
-
-
INT0
I
External Interrupt 0 input pin
I/O General purpose digital I/O pin
External Interrupt 1 input pin
P3.3
27
INT1
I
P3.4
I/O General purpose digital I/O pin
I/O Timer0 external clock
6
5
2
1
-
-
TM0
I2C0_SDA
P3.5
I/O I2C0 data input/output pin
I/O General purpose digital I/O pin
I/O Timer1 external clock
TM1
I2C0_SCL
P3.6
I/O I2C0 clock output pin
4
3
-
-
-
-
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
P3.7
P4.0
23
24
-
-
-
-
ECAP1_IC0
P4.1
I
Input 0 of Enhanced Input Capture Unit 1
I/O General purpose digital I/O pin
ECAP1_IC1
I
Input 1 of Enhanced Input Capture Unit 1
Nov. 02, 2016
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Pin Number
Pin
Pin Name
Description
Type[1]
100- pin 64-pin 48-pin
P4.2
I/O General purpose digital I/O pin
25
-
-
ECAP1_IC2
P4.3
I
Input 2 of Enhanced Input Capture Unit 1
26
21
22
-
-
-
-
-
-
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O Timer2 external clock
P4.4
P4.5
P4.6
28
33
-
-
-
-
TM2
P4.7
I/O General purpose digital I/O pin
I/O Timer3 external clock
TM3
P5.0
I/O General purpose digital I/O pin
I/O SPI0 MOSI (Master Out, Slave In) pin
36
37
23
24
19
20
SPI0_MOSI
UART0_nRTS
P5.1
O
UART0 RTS pin
I/O General purpose digital I/O pin
SPI0_MISO
UART0_nCTS
I/O SPI0 MISO (Master In, Slave Out) pin
I
UART0 CTS pin
P5.2
I/O General purpose digital I/O pin
50
32
-
SPI2_MISO
ACMP1_O
P5.3
I/O SPI2 MISO (Master In, Slave Out) pin
AO Analog comparator 1 output pin
I/O General purpose digital I/O pin
I/O SPI2 serial clock pin
51
52
33
34
-
-
SPI2_CLK
P5.4
I/O General purpose digital I/O pin
SPI2_SS
P5.5
I/O SPI2 slave select pin
I/O General purpose digital I/O pin
53
15
14
69
-
-
CLKO
O
Frequency Divider output pin
P5.6
I/O General purpose digital I/O pin
I/O PWM0 output of PWM unit 2
11
10
42
12
11
31
PWM2_CH0
P5.7
I/O General purpose digital I/O pin
I/O PWM1 output of PWM unit 2
PWM2_CH1
P6.0
I/O General purpose digital I/O pin
AI ADC analog input 0 for sample-and-hold A
I/O General purpose digital I/O pin
AI ADC analog input 1 for sample-and-hold A
I/O General purpose digital I/O pin
ADC0_CH0
P6.1
68
67
41
40
30
29
ADC0_CH1
P6.2
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Pin Number
Pin
Pin Name
Description
Type[1]
100- pin 64-pin 48-pin
ADC0_CH2
P6.3
AI ADC analog input 2 for sample-and-hold A
I/O General purpose digital I/O pin
66
65
39
38
28
27
ADC0_CH3
P6.4
AI ADC analog input 3 for sample-and-hold A
I/O General purpose digital I/O pin
ADC0_CH4
ACMP1_N
P6.5
AI ADC analog input 4 for sample-and-hold A
AI Analog comparator 1 negative input
I/O General purpose digital I/O pin
64
37
26
ADC0_CH5
ACMP1_P
P6.6
AI ADC analog input 5 for sample-and-hold A
AI Analog comparator 1 positive input
I/O General purpose digital I/O pin
63
62
83
82
81
80
36
35
56
55
54
53
25
24
44
43
42
41
ADC0_CH6
P6.7
AI ADC analog input 6 for sample-and-hold A
I/O General purpose digital I/O pin
ADC0_CH7
P7.0
AI ADC analog input 7 for sample-and-hold A
I/O General purpose digital I/O pin
ADC1_CH0
P7.1
AI ADC analog input 0 for sample-and-hold B
I/O General purpose digital I/O pin
ADC1_CH1
P7.2
AI ADC analog input 1 for sample-and-hold B
I/O General purpose digital I/O pin
ADC1_CH2
P7.3
AI ADC analog input 2 for sample-and-hold B
I/O General purpose digital I/O pin
ADC1_CH3
P7.4
AI ADC analog input 3 for sample-and-hold B
I/O General purpose digital I/O pin
79
78
52
51
40
39
ADC1_CH4
ACMP2_N
P7.5
AI ADC analog input 4 for sample-and-hold B
AI Analog comparator 2 negative input
I/O General purpose digital I/O pin
ADC1_CH5
ACMP2_P
P7.6
AI ADC analog input 5 for sample-and-hold B
AI Analog comparator 2 positive input
I/O General purpose digital I/O pin
77
76
72
50
49
45
38
37
34
ADC1_CH6
P7.7
AI ADC analog input 6 for sample-and-hold B
I/O General purpose digital I/O pin
ADC1_CH7
P8.0
AI ADC analog input 7 for sample-and-hold B
I/O General purpose digital I/O pin
OP0_P
AI OP Amplifier 0 positive input
Nov. 02, 2016
Page 20 of 69
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Pin Number
Pin
Pin Name
Description
Type[1]
100- pin 64-pin 48-pin
P8.1
I/O General purpose digital I/O pin
71
70
85
84
44
43
-
33
32
-
OP0_N
P8.2
AI OP Amplifier 0 negative input
I/O General purpose digital I/O pin
AO OP Amplifier 0 output
OP0_O
P8.3
I/O General purpose digital I/O pin
AI Analog comparator negative input pin
I/O General purpose digital I/O pin
AI Analog comparator positive input pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
ACMP0_N
P8.4
-
-
ACMP0_P
P8.5
91
59
-
-
-
-
P8.6
P8.7
58
86
87
88
92
98
99
100
2
-
57
58
59
-
-
45
46
47
-
ACMP0_O
P9.0
O
Analog comparator output pin
I/O General purpose digital I/O pin
AO OP Amplifier 1 output
OP1_O
P9.1
I/O General purpose digital I/O pin
AI OP Amplifier 1 negative input
I/O General purpose digital I/O pin
AI OP Amplifier 1 positive input
I/O General purpose digital I/O pin
OP1_N
P9.2
OP1_P
P9.3
PWM1_BRAKE1
P9.4
I
Brake input pin 1 of PWM Unit 1
I/O General purpose digital I/O pin
I/O SPI1 serial clock pin
-
-
SPI1_CLK
P9.5
I/O General purpose digital I/O pin
I/O SPI1 MISO (Master In, Slave Out) pin
I/O General purpose digital I/O pin
I/O SPI1 MOSI (Master Out, Slave In) pin
I/O General purpose digital I/O pin
I/O SPI1 slave select pin
-
-
SPI1_MISO
P9.6
-
-
SPI1_MOSI
P9.7
-
-
SPI1_SS
PA.0
I/O General purpose digital I/O pin
13
12
9
8
10
9
UART1_TXD
I2C0_SDA
PA.1
O
Data transmitter output pin for UART1
I/O I2C0 data input/output pin
I/O General purpose digital I/O pin
UART1_RXD
I
Data Receiver input pin for UART1
Nov. 02, 2016
Page 21 of 69
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M0519
Pin Number
Pin
Pin Name
Description
Type[1]
100- pin 64-pin 48-pin
I2C0_SCL
I/O I2C0 clock output pin
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power
Nov. 02, 2016
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M0519
5
BLOCK DIAGRAM
Timer / PWM
Analog Interface
Memory
32-bit
Timer x 4
EPWM
Timer x 12
2 sets of 12-bit
ADC x 8
APROM 128/64 KB
LDROM 8 KB
ARM®
Cortex® -M0
72 MHz
Watchdog
Timers
ICAP
Timer x 2
Operating Amp. x 2
Comparators x 3
Data Flash 4 KB
SRAM 16 KB
BPWM Timer x 2
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
GPIO
Connectivity
LDO
PLL
General Purpose I/O
UART x 2
Power-on Reset
LVR
HS Osc.
22.1184 MHz
HS Ext. Crystal
Osc. 4~24 MHz
Reset Pin
SPI x 3
I²C
LS Osc.
10 kHz
External Interrupt
Brown-out Detection
Figure 5-1 NuMicro® M0519 Series Block Diagram
Nov. 02, 2016
Page 23 of 69
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M0519
6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6-1 shows the functional controller of processor.
CortexTM-M0 Components
CortexTM-M0 processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
CortexTM-M0
Processor
Core
Debug
Access
Port
Wakeup
Interrupt
Controller
(WIC)
Debugger
Interface
Bus Matrix
(DAP)
AHB-Lite
Interface
Serial Wire or
JTAG Debug Port
Figure 6-1 Functional Controller Diagram
The implemented device provides the following components and features:
A low gate count processor:
-
-
-
-
-
-
-
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
-
-
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
NVIC:
Nov. 02, 2016
Page 24 of 69
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M0519
-
-
-
-
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support
-
-
-
-
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
-
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
-
Single 32-bit slave port that supports the DAP (Debug Access Port)
Nov. 02, 2016
Page 25 of 69
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M0519
6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Resets
System Power Distribution
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Hardware Reset
Power-on Reset (POR)
Low level on the Reset pin (nRESET)
Watchdog Time-out Reset (WDT)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD)
Software Reset
SYS Reset - SYSRESETREQ (AIRCR[2])
Cortex® -M0 Core One-shot Reset - CPU_RST (IPRSTC1[1])
Chip One-shot Reset - CHIP_RST (IPRSTC1[0])
Power-on Reset or CHIP_RST (IPRST1[0]) reset the whole chip including all peripherals,
external crystal circuit and BS (ISPCON[1]) bit.
SYSRESETREQ (AIRCR[2]) reset the whole chip including all peripherals, but does not reset
external crystal circuit and BS (ISPCON[1]) bit.
Nov. 02, 2016
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6.2.3 System Power Distribution
In this chip, the power distribution is divided into two segments.
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the I/O pins and internal
regulator which provides a fixed 1.8V power for digital operation.
The output of internal voltage regulators, LDO_CAP, requires an external capacitor which should
be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level
of the digital power (VDD).
AVDD
Brown-
out
Detector
Low
Voltage
Reset
12-bit
SAR-ADC
Analog
Comparator
OPA
AVSS
Internal
22.1184 MHz & 10 kHz
Oscillator
Temperature
Seneor
FLASH
Digital Logic
LDO_CAP
1uF
1.8V
POR18
POR50
XT1_IN
4~24MHz
Crystal
PLL
LDO
IO cell
GPIO
XT1_OUT
Figure 6-2 NuMicro® M0519 Series Power Distribution Diagram
Nov. 02, 2016
Page 27 of 69
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M0519
6.2.4 System Memory Map
The NuMicro® M0519 Series provides 4G-byte addressing space. The memory locations assigned
to each on-chip controllers are shown in Table 6-1. The detailed register definition, memory
space, and programming detailed will be described in the following sections for each on-chip
peripheral. The NuMicro® M0519 Series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF
0x2000_0000 – 0x2000_3FFF
FLASH_BA
SRAM_BA
FLASH Memory Space (128 KB)
SRAM Memory Space (16 KB)
AHB Controllers Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_C000 – 0x5000_FFFF
0x5001_4000 – 0x5001_7FFF
GCR_BA
CLK_BA
INT_BA
System Global Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
FMC_BA
HDIV_BA
Flash Memory Control Registers
Hardware Divider Register
APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4000_4100 – 0x4000_7FFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4003_4000 – 0x4003_7FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_3FFF
0x400F_0000 – 0x400F_3FFF
WDT_BA
Watchdog Timer Control Registers
WWDT_BA
TMR01_BA
I2C0_BA
Window Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
I2C0 Interface Control Registers
SPI0_BA
SPI0 with master/slave function Control Registers
SPI1 with master/slave function Control Registers
Basic PWM0 Control Registers
SPI1_BA
BPWM0_BA
UART0_BA
ACMP_BA
EADC_BA
OPA_BA
UART0 Control Registers
Analog Comparator Control Registers
Enhanced Analog-Digital-Converter (EADC) Control Registers
Operation Amplifier Control Registers
APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF)
0x4011_0000 – 0x4011_3FFF
0x4013_0000 – 0x4013_3FFF
0x4015_0000 – 0x4015_3FFF
Reserved
TMR23_BA
SPI2_BA
Timer2/Timer3 Control Registers
SPI2 with master/slave function Control Registers
UART1 Control Registers
UART1_BA
Reserved
Reserved
0x4019_0000 – 0x4019_3FFF
0x4019_4000 – 0x4019_7FFF
EPWM0_BA
EPWM1_BA
Enhanced PWM0 Control Registers
Enhanced PWM1 Control Registers
Nov. 02, 2016
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Address Space
0x401B_0000 – 0x401B_3FFF
0x401B_4000 – 0x401B_7FFF
Reserved
Token
Controllers
ECAP0_BA
ECAP1_BA
Reserved
Reserved
Reserved
Enhanced Input Capture 0 Control Registers
Enhanced Input Capture 1 Control Registers
Reserved
Reserved
Reserved
Reserved
Reserved
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E01F
0xE000_E100 – 0xE000_E4EF
0xE000_ED00 – 0xE000_ED3F
SYST_BA
NVIC_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6-1 Address Space Assignments for On-Chip Controllers
Nov. 02, 2016
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6.2.5 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
Nov. 02, 2016
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6.2.6 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core
and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
Nov. 02, 2016
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6.2.6.1
Exception Model and System Interrupt Map
Table 6-2 lists the exception model supported by the NuMicro® M0519 Series. Software can set
four levels of priority on some of these exceptions as well as on all interrupts. The highest user-
configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority
of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on
the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Reset
Vector Number
Priority
-3
1
NMI
2
-2
Hard Fault
Reserved
3
-1
4 ~ 10
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
11
Reserved
12 ~ 13
PendSV
14
SysTick
15
16 ~ 47
Interrupt (IRQ0 ~ IRQ31)
Table 6-2 Exception Model
Interrupt Number
(Bit In Interrupt
Registers)
Power
Down
Wake-Up
Exception Vector
Interrupt
Name
Source
Module
Exception Description
Number
1 ~ 15
16
Address
-
-
-
System exceptions
-
Brown-out low voltage detected
interrupt
0x40
0
BOD_INT
Brown-out
Yes
17
18
19
0x44
0x48
0x4C
1
2
3
WDT_INT
EINT0_INT
EINT1_INT
WDT
P3.2
P3.3
Watchdog Timer interrupt
Yes
Yes
Yes
External signal interrupt from P3.2 pin
External signal interrupt from P3.3 pin
P0~P4 except External interrupt from GPIO group 0
P3.2 and P3.3 (P0~P4) except P3.2 and P3.3
20
21
0x50
0x54
4
5
GPG0_INT
GPG1_INT
Yes
Yes
External interrupt from GPIO group 1
P5~PA
(P5~PA)
22
23
24
25
26
27
28
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
6
7
BPWM0_INT
EADC0_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART0_INT
BPWM0
EADC0
TMR0
Basic PWM0 interrupt
EADC0 interrupt
Timer 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
UART0 interrupt
No
No
No
No
No
No
Yes
8
9
TMR1
10
11
12
TMR2
TMR3
UART0
Nov. 02, 2016
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Interrupt Number
(Bit In Interrupt
Registers)
Power
Down
Wake-Up
Exception Vector
Interrupt
Name
Source
Module
Exception Description
Number
Address
29
30
31
32
33
33
34
35
36
36
37
38
39
40
0x74
0x78
0x7C
0x80
0x84
0x84
0x88
0x8C
0x90
0x90
0x94
0x98
0x9C
0xA0
13
14
15
16
17
17
18
19
20
20
21
22
23
24
UART1_INT
SPI0_INT
UART1
SPI0
UART1 interrupt
Yes
No
No
No
-
SPI0 interrupt
SPI1 interrupt
SPI2 interrupt
SPI1_INT
SPI1
SPI2_INT
SPI2
Reserved
Reserved
I2C0_INT
Reserved Reserved
Reserved Reserved
No
Yes
No
-
I2C0 interrupt
CKD interrupt
I2C0
CKD_INT
CKD
Reserved
Reserved
EPWM0_INT
EPWM1_INT
ECAP0_INT
ECAP1_INT
Reserved Reserved
Reserved Reserved
-
EPWM0
EPWM1
ECAP0
ECAP1
Enhanced PWM0 interrupt
No
No
No
No
Enhanced PWM1 interrupt
Enhanced input capture 0 interrupt
Enhanced input capture 1 interrupt
Yes (only
by analog
comparator)
Analog Comparator 0 or 1, or OP
Amplifier digital output interrupt
41
0xA4
25
ACMP_INT
ACMP
42
43
42
43
0xA8
0xAC
0xA8
0xAC
26
27
26
27
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
-
-
-
-
Clock controller interrupt for chip wake
up from power-down state
44
0xB0
28
PWRWU_INT
CLKC
-
45
46
47
0xB4
0xB8
0xBC
29
30
31
EADC1_INT
EADC2_INT
EADC3_INT
EADC1
EADC2
EADC3
EADC1 interrupt
No
No
No
EADC2 interrupt
EADC3 interrupt
Table 6-3 System Interrupt Map Vector Table
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6.2.6.2
Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset (Bytes)
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Table 6-4 Vector Table
Vector Number
6.2.6.3
Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex® -M0 core executes the WFI instruction only if the SLEEPDEEP
(SCR[2]) bit is set to 1. After that, chip enters Power-down mode and wait for wake-up interrupt
source triggered to leave Power-down mode. In the Power-down mode, the clock controller turns
off the 4~24 MHz external high speed crystal oscillator and 22.1184 MHz internal high speed RC
oscillator to reduce the overall system power consumption. Figure 6-3 shows the clock generator
and the overview of the clock source control.
The clock generator consists of 4 clock sources as listed below:
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLL_FOUT), PLL source can be selected
from 4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz internal
high speed RC oscillator (HIRC)
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
Each of these clock sources has certain stable time to wait for clock operating at stable
frequency. When clock source is enabled, a stable counter start counting and correlated clock
stable
index
(OSC22M_STB(CLKSTATUS[4]),
OSC10K_STB(CLKSTATUS[3]),
PLL_STB(CLKSTATUS[2]) and XTL12M_STB(CLKSTATUS[0])) are set to 1 after stable counter
value reach a define value as Table 6-5. System and peripheral can use these clock as its
operating clock only when correlate clock stable index is set to 1. The clock stable index will auto
clear
when
user
disables
the
clock
source
(OSC10K_EN(PWRCON[3]),
OSC22M_EN(PWRCON[2]), XTL12M_EN(PWRCON[0]) and PD(PLLCON[16])). Besides, the
clock stable index of HXT, HIRC and PLL will auto clear when chip enter power-down and clock
stable counter will re-counting after chip wake-up if correlate clock is enabled.
Clock Source
Clock Stable Count Value
HXT
PLL
4096 HXT clock
6144 PLL source
(PLL source is HXT if PLL_SRC(PLLCON[19]) = 0, or HIRC if PLL_SRC(PLLCON[19]) = 1)
HIRC
LIRC
256 HIRC clock
1 LIRC
Table 6-5 Clock Stable Count Value Table
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XTL12M_EN (PWRCON[0])
HXT
XT1_OUT
XT1_IN
4~24 MHz
HXT
PLL_SRC (PLLCON[19])
PLL
0
1
PLL FOUT
OSC22M_EN (PWRCON[2])
22.1184 MHz
HIRC
HIRC
LIRC
OSC10K_EN (PWRCON[3])
10 kHz
LIRC
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6-3 Clock Generator Block Diagram
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22.1184
MHz
22.1184 MHz
10 kHz
111
011
010
001
000
CPUCLK
HCLK
CPU
4~12
MHz
PLLFOUT
Reserved
4~24 MHz
ACMP
I2C
1/(HCLK_N+1)
TMR0
TMR1
TMR2
TMR3
BPWM0
EPWM0
EPWM1
ECAP0
ECAP1
OPA
10 kHz
PCLK
CLKSEL0[2:0]
22.1184 MHz
4~24 MHz
1
PLLFOUT
0
PLLCON[19]
QEI0
QEI1
22.1184 MHz
HCLK
MDU
11
10
01
00
FRQDIV
SysTick
Reserved
4~24 MHz
CPUCLK
22.1184 MHz
HCLK
1
0
CLKSEL2[3:2]
1/2
1/2
1/2
111
011
010
001
000
SYST_CSR[2]
4~24 MHz
Reserved
4~24 MHz
CLKSEL2[17:16]
10 kHz
11
10
WWDT
CLKSEL0[5:3]
10 kHz
11
10
01
00
HCLK
HCLK
HCLK
1/2048
1/512
1/128
WDT
BOD
FMC
10 kHz
22.1184 MHz
22.1184 MHz
11
01
00
CLKSEL1[1:0]
HCLK
PLLFOUT
4~24 MHz
1
0
SPI0
SPI1
SPI2
PLLFOUT
CLKSEL1[4]
CLKSEL1[5]
CLKSEL1[6]
CLKSEL1[25:24]
1/(UART_N+1)
1/(EADC_N+1)
UART0-1
EADC
PCLK
Note: Before clock switching, both the pre-selected and newly selected clock sources must
be turned on and stable.
Figure 6-4 Clock Generator Global View Diagram
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The NuMicro® M0519 Series is equipped with 128/64 KB on-chip embedded flash for application
program memory (APROM) and data flash, and with 8K bytes for ISP loader program memory
(LDROM) that could be programmed boot loader to update APROM and data flash through In
System Programming (ISP) procedure. ISP function enables user to update embedded flash
when chip is soldered on PCB. After chip is powered on, Cortex® -M0 CPU fetches code from
APROM or LDROM decided by boot select CBS (Config0[7:6]). By the way, the NuMicro® M0519
Series also provides data flash for user to store some application dependent data before chip
power off. For 128 KB APROM device, the data flash is shared with original 128 KB program
memory and its start address is configurable in Config1. For 64 KB APROM device, the data flash
is fixed at 4K bytes.
6.4.2 Features
Runs up to 72 MHz and optional up to 50 MHz with zero wait state for continuous address
read access
Supports 512 bytes page erase for all embedded flash
Supports 128/64 Kbytes application program ROM (APROM)
Supports 8 KB loader ROM (LDROM)
Supports 4KB data flash for 64 Kbytes APROM device
Supports configurable data flash size for 128KB APROM device
Supports 8 bytes User Configuration block to control system initiation
Support In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded flash memory
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
The NuMicro® M0519 Series has up to 82 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 82 pins are arranged in 10 ports named
as P0, P1, P2, P3, P4, P5, P6, P7, P8, P9 and PA. The P0/1/2/3/4/5/6/7/8/9 port has the
maximum of 8 pins and PA port has the maximum of 2 pins. Each of the 82 pins is independent
and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, open-
drain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are stay at input mode. In
Quasi-bidirectional mode, I/O pin has a very weak individual pull-up resistor which is about
110~300 K for VDD is from 5.0 V to 2.5 V.
6.5.2 Features
Four I/O modes:
Quasi-bidirectional
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable by Px_TYPE[7:0] in Px_MFP[23:16]
I/O pin configured as interrupt source with edge/level setting
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling pin interrupt function will also enable the pin wake-up function
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6.6 Timer Controller (TIMER)
6.6.1 Overview
The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.6.2 Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through TDR (TDR[23:0])
Supports event counting function
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
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6.7 Basic PWM Generator and Capture Timer (BPWM)
6.7.1 Overview
The NuMicro® M0519 series has 1 set of BPWM group (BPWM0), supporting 1 set of BPWM
generators that can be configured as 2 independent BPWM outputs, BPWM0_CH0 and
BPWM0_CH1, or as 1 complementary BPWM pairs, (BPWM0_CH0, BPWM0_CH1) with
programmable dead-zone generator.
The BPWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two BPWM Timers including two clock selectors, two 16-bit BPWM down-counters
for BPWM period control, two 16-bit comparators for BPWM duty control and one dead-zone
generator. The BPWM generator provides two independent BPWM interrupt flags which are set
by hardware when the corresponding BPWM period down counter reaches zero.
Each BPWM interrupt source with its corresponding enable bit can cause CPU to request BPWM
interrupt. The BPWM generators can be configured as one-shot mode to produce only one
BPWM cycle signal or auto-reload mode to output BPWM waveform continuously. BPWM can be
used to trigger EADC when operation in center-aligned mode.
6.7.2 Features
6.7.2.1
BPWM Function:
Up to 1 BPWM group to support 2 BPWM channels or 1 BPWM paired channels.
Supports 8-bit prescaler from 1 to 255
Up to 16-bit resolution BPWM timer
PWM timer supports edge-aligned and center-aligned operation type
One-shot or Auto-reload mode BPWM
PWM Interrupt request synchronized with BPWM period or duty
Supports dead-zone generator with 8-bit resolution for BPWM paired channels
Supports trigger EADC
6.7.2.2
Capture Function:
Supports 2 Capture input channels shared with 2 BPWM output channels
Supports rising or falling capture condition
Supports rising or falling capture interrupt
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6.8 Enhanced PWM Generator (EPWM)
6.8.1 Overview
This device has two built-in PWM units with the same architecture whose function is specially
designed for driving motor control applications.
6.8.2 Features
Each unit supports the features below:
Three independent 16-bit PWM duty control units with maximum 6 port pins:
3 independent PWM output:
EPWM0_CH0, EPWM0_CH2 and EPWM0_CH4 for Unit 0
EPWM1_CH0, EPWM1_CH2 and EPWM1_CH4 for Unit 1
3 complementary PWM pairs, with each pin in a pair mutually complement to each
other and capable of programmable dead-time insertion:
(EPWMx_CH0, EPWMx_CH1), (PWMx_CH2, EPWMx_CH3) and (EPWMx_CH4,
EPWMx_CH5) where x=0~1.
3 synchronous PWM pairs, with each pin in a pair in-phase:
(EPWMx_CH0, EPWMx_CH1), (EPWMx_CH2, EPWMx_CH3) and (EPWMx_CH4,
EPWMx_CH5) where x=0~1
Group control bits:
EPWMx_CH2 and EPWMx_CH4 are synchronized with EPWMx_CH0
Supports Edge aligned mode and Center aligned mode
Programmable dead-time insertion between complementary paired PWMs
Each pin of EPWMx_CH0 to EPWMx_CH5 has independent polarity setting control
Mask output control for Electrically Commutated Motor operation
Tri-state output at reset and brake state
Hardware brake protection
Two Interrupt Sources:
Interrupt is synchronously requested at PWM frequency when up/down counter
comparison matched (edge and center aligned modes) or underflow (center aligned
mode).
Interrupt is requested when external brake pins asserted
PWM signals before polarity control stage are defined in the view of positive logic. The PWM
ports is active high or active low are controlled by polarity control register.
High Source/Sink current.
Supports trigger EADC
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6.9 Enhanced Input Capture Timer (ECAP)
6.9.1 Overview
This device provides up to two units of Input Capture Timer/Counter which capture function can detect
the digital edge changed signal at channel inputs. Each unit has three input capture channels. The
timer/counter is equipped with up counting, reload and compare-match capabilities.
6.9.2 Features
Up to two Input Capture Timer/Counter Units, Input Capture 0 and Input Capture 1.
Each unit has own interrupt vector
24-bit Input Capture up-counting timer/counter
With noise filter in front end of input ports
Edge detector with three options
Rising edge detection
Falling edge detection
Both edge detection
Each input channel is supported with one capture counter hold register
Captured event reset/reload capture counter option
Supports the compare-match function
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6.10 Watchdog Timer (WDT)
6.10.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 218) and the time-out interval is 1.6 ms ~ 26.214 s if
WDT_CLK = 10 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset
delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN in
Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as 10 kHz
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6.11 Window Watchdog Timer (WWDT)
6.11.1 Overview
The Window Watchdog Timer is used to perform a system reset within a specified window period to
prevent software from running to uncontrollable state by any unpredictable condition usually generated
by external interferences or unexpected logical conditions.
When the window function is used to trim the watchdog behavior to match the application perfectly,
software must refresh the counter before time-out.
6.11.2 Features
6-bit down counter value WWDTCVAL (WWDTCVR[5:0]) and 6-bit compare value WINCMP
(WWDTCR[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value PERIODSEL (WWDTCR[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
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6.12 Universal Asynchronous Receiver Transmitter (UART)
6.12.1 Overview
The NuMicro® M0519 series provides two channels of Universal Asynchronous
Receiver/Transmitters (UART). UART Controller performs Normal Speed UART and supports
flow control function. The UART Controller performs a serial-to-parallel conversion on data
received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU.
Each UART Controller channel supports seven types of interrupts. The UART controller also
supports IrDA SIR, RS-485 and LIN.
6.12.2 Features
Full duplex, asynchronous communications
Separates receive / transmit 16 bytes entry FIFO for data payloads
Supports hardware auto-flow control/flow control function (nCTS, nRTS) and programmable
nRTS flow control trigger level
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports nCTS wake-up function
Supports 8-bit receiver buffer time out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UA_TOR [15:8]) register
Supports break error, frame error, parity error and receive / transmit buffer overflow detect
function
Fully programmable serial-interface characteristics
Programmable data bit length, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit length, 1, 1.5, or 2 stop bit generation
IrDA SIR function mode
Supports 3-/16-bit duration for normal mode
LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software direct enable control provided by nRTS pin
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6.13 I2C Serial Interface Controller (I²C)
6.13.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. I2C controller supports Power-down wake-up function.
6.13.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus are:
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allows devices with different bit rates to communicate via one
serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
A built-in a 14-bit time out counter requested the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
External pull-up resistors are needed for high output
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
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6.14 Serial Peripheral Interface (SPI)
6.14.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NuMicro® M0519 series contains up to three sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller
can be configured as a master or a slave device.
6.14.2 Features
Up to three sets of SPI controllers
Supports Master or Slave mode operation
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 8-layer depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports the Byte Reorder function
Supports 3-wire, no slave select signal, bi-direction interface
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6.15 Hardware Divider (HDIV)
6.15.1 Overview
The hardware divider is useful to the high performance application. The hardware divider is a
signed, integer divider with quotient and remainder outputs.
6.15.2 Features
Supports Signed (two’s complement) integer calculation.
Supports 32-bit dividend with 16-bit divisor calculation capacity.
Supports 32-bit quotient and 16-bit remainder outputs.
Supports divided by 0 warning flag.
7 HCLK clocks taken for one cycle calculation.
Software triggered with finish flag.
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6.16 Enhanced Analog-to-Digital Converter (EADC)
6.16.1 Overview
The NuMicro® M0519 Series contains two 12-bit successive approximation analog-to-digital converters
(SAR A/D converter) with 16 input channels. The two A/D converters ADCA and ADCB can be
sampled with Simultaneous or Single Sampling mode. The A/D converters can be started by software,
PWM triggers, timer0~3 overflow pulse triggers, ADINT0, ADINT1 interrupt EOC pulse trigger and
external STADC pin input signal.
Note: The analog input port pins must be configured as input type before the EADC function is
enabled.
6.16.2 Features
Analog input voltage range: 0~VREF(Max to 5.0V).
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 16 single-end analog input channels.
Two SAR ADC converters.
Four EADC interrupts with individual interrupt vector addresses.
Maximum EADC clock frequency: 16MHz.
Up to 1.6M SPS conversion rate, each of ADC converter conversion time less than 1.25μs.
Two operating modes
Single sampling mode: two ADC converters run at normal operation.
Simultaneous sampling mode: Allow two ADC converters can be sampled
simultaneously.
An A/D conversion can be started by:
Writing 1 to ADST(ADSSTR[n]) bit ( n = 0~15) through software
External pin STADC
Timer0~3 overflow pulse triggers
ADINT0, ADINT1 interrupt EOC pulse triggers
PWM triggers
Conversion results are held in 16 data registers with valid and overrun indicators.
SAMPLEA0~7 ADC control logic modules, each of them is configurable for ADCA converter
channel AINA0~7 and trigger source.
SAMPLEB0~7 ADC control logic modules, each of them is configurable for ADCB converter
channel AINB0~7 and trigger source.
Channel AINA0 supports 2 input sources: external analog voltage and internal OP0 Amplifier
output voltage.
Channel AINB0 supports 2 input sources: external analog voltage and internal OP1 Amplifier
output voltage.
Channel AINA7 supports 4 input sources: external analog voltage, internal fixed band-gap
voltage, internal temperature sensor output, and analog ground.
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6.17 Analog Comparator (ACMP)
6.17.1 Overview
The NuMicro® M0519 Series contains three comparators. The comparator output is logic 1 when
positive input voltage is greater than negative input voltage; otherwise the output is logic 0. Each
comparator can be configured to cause an interrupt when the comparator output value changes.
The block diagram is shown in 錯誤! 找不到參照來源。.
6.17.2 Features
Analog input voltage range: 0~ AVDD
Supports hysteresis function
Supports wake-up function
Supports comparator output inverse function
Supports the comparator output can be the brake source for EPWM function
ACMP0 supports
2 positive sources: ACMP0_P and OP0_O
2 negative sources: ACMP0_N and Internal band-gap voltage (VBG
)
)
)
ACMP1 supports
2 positive sources: ACMP1_P and OP1_O
2 negative sources: ACMP1_N and Internal band-gap voltage (VBG
ACMP2 supports
1 positive sources: ACMP2_P
2 negative sources: ACMP2_N and Internal band-gap voltage (VBG
Shares one ACMP interrupt vector for all comparators
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6.18 OP Amplifier (OPA)
6.18.1 Overview
This device integrated two operational amplifiers. It can be enabled through OP0_EN (OPACR[0]) and
OP1_EN (OPACR[1]) bit. User can measure the output of the OP amplifier through the integrated A/D
converter.
6.18.2 Features
Analog input voltage range: 0~AVDD
Supports two analog OP amplifiers
Supports OP output voltage measurement by A/D converter
Supports Schmitt trigger buffer outputs and generate interrupt
OP amplifier 0 output can be an optional input source of integrated comparator 0 positive
input
OP amplifier 1 output can be an optional input source of integrated comparator 1 positive
input
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7
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
VDDVSS
VIN
MIN
-0.3
VSS-0.3
4
MAX
+6.3
VDD+0.3
24
UNIT
V
DC Power Supply
Input Voltage
V
Oscillator Frequency
1/tCLCL
TA
MHz
C
Operating Temperature
-40
105
Storage Temperature
TST
-55
+150
120
C
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
-
mA
mA
mA
mA
mA
mA
120
35
35
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and
reliability of the device.
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7.2 DC Electrical Characteristics
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Operation voltage
VDD
2.5
-
5.5
-
V
VDD =2.5V ~ 5.5V
VSS
/
Power Ground
-0.3
-
V
AVSS
VLDO
AVDD
VREF
LDO Output Voltage
1.62
2.5
1.8
1.98
VDD
V
V
V
VDD >= 2.5V
Analog Operating Voltage
Analog Reference Voltage
-
-
1.2
AVDD
All digital
module
VDD HXT HIRC PLL
Operating Current
Normal Run Mode
At 72MHz
38.7
IDD1
mA
Χ
Χ
Χ
Χ
Χ
5.5V 12MHz
Χ
17.9
37.2
16.4
32.9
15.5
IDD2
IDD3
IDD4
IDD5
mA 5.5V 12MHz
mA 3.3V 12MHz
mA 3.3V 12MHz
mA 5.5V 12MHz
while(1){} executed
from flash
VLDO =1.8V
Χ
Operating Current
Normal Run Mode
At 60MHz
Χ
Χ
Χ
IDD6
mA 5.5V 12MHz
mA 3.3V 12MHz
31.4
14.0
while(1){} executed
from flash
IDD7
VLDO =1.8V
Χ
Χ
IDD8
mA 3.3V 12MHz
29.1
14.5
Χ
Χ
IDD9
mA 5.5V 12MHz
mA 5.5V 12MHz
Operating Current
Normal Run Mode
At 50MHz
Χ
IDD10
while(1){} executed
from flash
27.6
Χ
IDD11
mA 3.3V 12MHz
VLDO =1.8V
13.0
28.1
14.0
Χ
Χ
Χ
Χ
IDD12
IDD13
IDD14
mA 3.3V 12MHz
mA 5.5V 12MHz
mA 5.5V 12MHz
Operating Current
Normal Run Mode
At 48MHz
Χ
while(1){} executed
from flash
26.6
Χ
IDD15
mA 3.3V 12MHz
12.5
19.9
10.4
18.4
Χ
Χ
Χ
Χ
IDD16
IDD17
IDD18
mA 3.3V 12MHz
mA 5.5V 12MHz
mA 5.5V 12MHz
VLDO =1.8V
Operating Current
Normal Run Mode
At 32MHz
Χ
while(1){} executed
from flash
Χ
Χ
IDD19
mA 3.3V 12MHz
mA 3.3V 12MHz
VLDO =1.8V
8.9
Χ
IDD20
Nov. 02, 2016
Page 54 of 69
Rev 1.02
M0519
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
11.7
Operating Current
Χ
Χ
Χ
IDD21
IDD22
IDD23
mA 5.5V
mA 5.5V
Normal Run Mode
At 22.1184MHz
while(1){} executed
from flash
5.3
Χ
Χ
Χ
11.6
Χ
Χ
mA 3.3V
mA 3.3V
VLDO =1.8V
5.2
Χ
Χ
IDD24
8.6
4.9
Operating Current
Normal Run Mode
At 12MHz
Χ
Χ
Χ
Χ
IDD25
IDD26
IDD27
mA 5.5V 12MHz
mA 5.5V 12MHz
Χ
while(1){} executed
from flash
7.2
3.4
Χ
Χ
Χ
Χ
mA 3.3V 12MHz
mA 3.3V 12MHz
VLDO =1.8V
Χ
IDD28
HXT/
VDD
All digital
module
Operating Current
Normal Run Mode
At 10kHz
LIRC
PLL
LXT
0.13
IDD29
mA
Χ
Χ
Χ
Χ
Χ
Χ
Χ
Χ
5.5V
mA 5.5V
mA 3.3V
mA 3.3V
10KHz
10KHz
10KHz
10KHz
Χ
while(1){} executed
from flash
0.12
0.11
0.11
IDD30
IDD31
IDD32
VLDO =1.8V
Χ
All digital
module
VDD HXT HIRC PLL
Operating Current
Idle Mode
30.1
IIDLE1
mA
Χ
Χ
Χ
Χ
Χ
Χ
5.5V 12MHz
At 72MHz
9.2
28.6
7.7
Χ
IIDLE2
IIDLE3
IIDLE4
IIDLE5
IIDLE6
mA 5.5V 12MHz
mA 3.3V 12MHz
mA 3.3V 12MHz
mA 5.5V 12MHz
mA 5.5V 12MHz
while(1){} executed
from flash
Χ
VLDO =1.8V
25.7
8.2
Operating Current
Idle Mode
Χ
At 60MHz
24.2
6.7
while(1){} executed
from flash
Χ
Χ
IIDLE7
mA 3.3V 12MHz
mA 3.3V 12MHz
VLDO =1.8V
Χ
IIDLE8
23.0
8.4
Operating Current
Idle Mode
Χ
Χ
IIDLE9
mA 5.5V 12MHz
mA 5.5V 12MHz
Χ
IIDLE10
At 50MHz
while(1){} executed
from flash
21.5
6.9
Χ
Χ
IIDLE11
mA 3.3V 12MHz
mA 3.3V 12MHz
VLDO =1.8V
Χ
IIDLE12
Nov. 02, 2016
Page 55 of 69
Rev 1.02
M0519
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
22.3
Χ
Χ
IIDLE13
IIDLE14
mA 5.5V 12MHz
Operating Current
Idle Mode
8.1
Χ
mA 5.5V 12MHz
mA 3.3V 12MHz
At 48MHz
while(1){} executed
from flash
20.8
Χ
IIDLE15
VLDO =1.8V
6.7
Χ
Χ
Χ
IIDLE16
IIDLE17
IIDLE18
IIDLE19
IIDLE20
IIDLE21
IIDLE22
mA 3.3V 12MHz
mA 5.5V 12MHz
16.0
Operating Current
Idle Mode
6.4
Χ
Χ
Χ
mA 5.5V 12MHz
At 32MHz
while(1){} executed
from flash
14.5
mA 3.3V 12MHz
mA 3.3V 12MHz
4.9
8.6
VLDO =1.8V
Χ
Χ
Χ
Χ
Χ
mA 5.5V
mA 5.5V
Operating Current
Idle Mode
2.2
8.6
Χ
Χ
Χ
At 22.1184MHz
while(1){} executed
from flash
Χ
Χ
IIDLE23
IIDLE24
IIDLE25
mA 3.3V
mA 3.3V
VLDO =1.8V
2.2
7.2
Χ
Χ
Χ
Χ
mA 5.5V 12MHz
mA 5.5V 12MHz
Operating Current
Idle Mode
3.4
Χ
Χ
Χ
IIDLE26
At 12MHz
while(1){} executed
from flash
5.7
1.9
Χ
Χ
Χ
Χ
IIDLE27
IIDLE28
mA 3.3V 12MHz
mA 3.3V 12MHz
VLDO =1.8V
Χ
HXT/
VDD
All digital
module
LIRC
PLL
LXT
Operating Current
Idle Mode
0.13
IIDLE29
mA
Χ
Χ
Χ
Χ
5.5V
10KHz
10KHz
At 10kHz
0.12
Χ
IIDLE30
IIDLE31
IIDLE32
mA 5.5V
while(1){} executed
from flash
0.11
0.11
Χ
Χ
Χ
Χ
mA 3.3V
mA 3.3V
10KHz
10KHz
VLDO =1.8V
Χ
All digital
module
VDD HXT HIRC LIRC
IPWD1
-
A
Χ
Χ
Χ
Χ
Χ
Χ
Χ
Χ
5.5V
5.5V
5.5V
3.3V
3.3V
Χ
Χ
Standby Current
IPWD2
IPWD3
IPWD4
IPWD5
-
-
-
-
A
A
A
A
Power-down Mode
Χ
Χ
Χ
Χ
Χ
Nov. 02, 2016
Page 56 of 69
Rev 1.02
M0519
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Χ
Χ
Χ
IPWD6
IIL
-
3.3V
A
Logic 0 Input Current (Quasi-
bidirectional mode)
-
-
-
-
-75
2
A
A
Input Leakage Current (input
only)
ILK
Logic 1 to 0 Transition
Current (Quasi-bidirectional
mode)
[3]
ITL
-
-
-660
VDD = 5.5V, VIN<2.0V
A
Internal Pull-High Resistor of
/RESET[1]
RRST
15
-0.3
-
-
-
kΩ
V
Input Low Voltage (TTL
input)
VIL
0.2VDD-0.1
0.3VDD
0.15VDD
VDD +0.3
VDD +0.3
-
Input Low Voltage (Schmitt
input)
VIL1
VIL2
VIH
-0.3
V
Input Low Voltage (/RESET,
XTAL in)
-0.3
V
Input High Voltage (TTL
input)
0.2VDD+0.9
0.7VDD
-
-
V
Input High Voltage (Schmitt
input, /RESET, XTAL in)
VIH1
VHY
-
V
Hysteresis voltage of
(Schmitt input)
0.2VDD
V
-360
-60
-50
-25
-4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD = 4.5V, VS = 2.4V
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
A
A
A
Source Current (Quasi-
bidirectional Mode)
IOH
IOH1
IOL
mA VDD = 4.5V, VS = 2.4V
mA VDD = 2.7V, VS = 2.2V
mA VDD = 2.5V, VS = 2.0V
mA VDD = 4.5V, VS = 0.45V
mA VDD = 2.7V, VS = 0.45V
mA VDD = 2.5V, VS = 0.45V
Source Current (Push-pull
Mode)
-3
16
10
9
Sink Current (Quasi-
bidirectional and Push-pull
Mode)
Note:
1. /RESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. I/O pin can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V,
5he transition current reaches its maximum value when VIN approximates to 2V.
Nov. 02, 2016
Page 57 of 69
Rev 1.02
M0519
7.3 AC Electrical Characteristics
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
SYMBOL
tCHCX
PARAMETER
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
CONDITION
MIN.
TYP.
MAX.
UNIT
nS
10
10
2
-
-
-
-
-
tCLCX
-
nS
tCLCH
15
15
nS
tCHCL
2
nS
7.3.1 External 4~24MHz Crystal
PARAMETER
Operation Voltage VDD
Temperature
CONDITION
MIN.
TYP..
MAX.
5.5
85
UNIT
V
-
2.5
-40
-
-
-
-
℃
Operating Current
12 MHz at VDD = 5V
External crystal
1
-
mA
MHz
Clock Frequency
4
24
7.3.1.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R
4 MHz ~ 24 MHz
10~20 pF
10~20 pF
without
C1
XTAL1
XTAL2
R
C2
Figure 7–1 Typical Crystal Application Circuit
Nov. 02, 2016
Page 58 of 69
Rev 1.02
M0519
7.3.2 Internal 22.1184 MHz Oscillator
PARAMETER
CONDITION
MIN.
2.5
-
TYP.
MAX.
5.5
-
UNIT
V
Supply voltage
-
-
-
22.1184
-
MHz
%
-1
+1
Frequency
+25C; VDD = 5V
(After calibration)
-40 to +105C;
-2
-
-
+2
-
%
VDD = 2.5V~5.5V
Operation Current
VDD =5V
500
uA
7.3.3 Internal 10 kHz Oscillator
PARAMETER
Supply voltage
CONDITION
MIN.
2.5
-
TYP.
MAX.
5.5
-
UNIT
V
-
-
10
-
Center Frequency
-
kHz
%
+25℃; VDD =5 V
-30
+30
Calibrated Internal Oscillator Frequency
-40℃~+85℃;
-50
-
+50
%
VDD=2.5 V~5.5 V
Nov. 02, 2016
Page 59 of 69
Rev 1.02
M0519
7.4 Analog Characteristics
7.4.1 12-bit SARADC
PARAMETER
Resolution
SYMBOL
CONDITON
MIN.
TYP.
MAX.
12
UNIT
Bit
-
-
-
-
-
-
-
Differential nonlinearity error
Integral nonlinearity error
Offset error
DNL
INL
EO
EG
-
-1~2
-1~4
±4
LSB
LSB
LSB
LSB
±2
±1
10
Full scale error
1
1.005
Monotonic
Guaranteed
AVDD = 5V
AVDD = 3V
AVDD = 5V
AVDD = 3V
-
-
-
16
ADC clock frequency
Sample rate
FADC
MHz
ksps
-
8
-
-
800
FS
-
-
400
Sample time
Conversion time
Supply voltage
VREF voltage
TS
TADC
AVDD
VREF
IDDA
-
-
8
12
-
-
Clock
Clock
V
-
2.5
2.0
-
5.5
AVDD
Supply current
Reference current
Input voltage
1.5
1
-
mA
mA
V
IREF
-
-
VREF
-
VIN
CIN
0
-
Capacitance
-
5
pF
7.4.2 LDO
PARAMETER
Input Voltage VDD
MIN.
TYP.
MAX.
5.5
UNIT
NOTE
2.5
V
V
VDD input voltage
VDD > 2.5 V
Output Voltage
1.62
1.8
1.98
Operating Temperature
-40
-
25
1
105
-
℃
Cbp
RESR = 1 Ω
F
Note:
1. It is recommended that a 10 uF or higher capacitor and a 100 nF bypass capacitor are connected between VDD and the
closest VSS pin of the device.
2. To ensure power stability, a 1 F or higher capacitor must be connected between LDO_CAP pin and the closest VSS
pin of the device.
Nov. 02, 2016
Page 60 of 69
Rev 1.02
M0519
7.4.3 Low Voltage Reset
PARAMETER
Operation Voltage
CONDITION
MIN.
0
TYP.
MAX.
5.5
5
UNIT
V
-
-
1
Quiescent Current
AVDD=5.5 V
-
-
A
℃
Operation Temperature
-40
25
105
Threshold Voltage
Hysteresis
-
-
1.6
0
2.0
0
2.4
0
V
V
7.4.4 Brown-out Detector
PARAMETER
Operation Voltage
CONDITION
MIN.
0
TYP.
-
MAX.
5.5
UNIT
V
-
Temperature
-
-40
-
25
-
105
125
4.6
℃
μA
V
Quiescent Current
AVDD=5.5 V
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
-
4.2
3.5
2.6
2.1
30
4.4
3.7
2.7
2.2
-
3.9
V
Brown-out Voltage
2.8
V
2.3
V
Hysteresis
150
mV
7.4.5 Power-On Reset (5V)
PARAMETER
Operation Temperature
Reset Voltage
CONDITION
MIN.
TYP.
25
2
MAX.
UNIT
℃
-
V+
-40
105
-
-
-
-
V
Quiescent Current
Vin > reset voltage
1
nA
Nov. 02, 2016
Page 61 of 69
Rev 1.02
M0519
7.4.6 Temperature Sensor
PARAMETER
Operation Voltage[1]
Operation Temperature
Current Consumption
Gain
CONDITIONS
MIN.
2.5
TYP.
MAX.
5.5
UNIT
V
-
-
-40
105
℃
6.4
-
10.5
μA
-1.76
720
mV/℃
mV
Offset Voltage
Temp=0 ℃
7.4.7 Comparator
PARAMETER
Operation Voltage AVDD
Operation Temperature
Operation Current
CONDITION
MIN.
2.5
-40
-
TYP.
MAX.
UNIT
V
-
5.5
-
25
20
5
85
℃
VDD=3.0 V
40
μA
mV
V
Input Offset Voltage
Output Swing
-
-
15
-
0.1
0.1
-
-
VDD-0.1
Input Common Mode Range
DC Gain
-
-
VDD-1.2
V
-
70
200
-
-
dB
ns
Propagation Delay
VCM=1.2 V and VDIFF=0.1 V
-
20 mV at VCM=1 V
50 mV at VCM=0.1 V
50 mV at VCM=VDD-1.2
10 mV for non-hysteresis
Comparison Voltage
10
20
-
mV
Hysteresis
VCM=0.4 V ~ VDD-1.2 V
-
-
±10
-
-
mV
CINP=1.3 V
CINN=1.2 V
Wake-up Time
2
μs
Nov. 02, 2016
Page 62 of 69
Rev 1.02
M0519
7.4.8 OP Amplifier
PARAMETER
AVDD
CONDITION
MIN.
TYP.
3.3
2
MAX.
UNIT
V
-
-
3.0
5.5
Input offset voltage
Input offset average drift
Output swing
-
5
mV
uV/℃
V
-
-
1
-
0.1
-
VDD-0.1
Input common mode range
DC gain
-
0.1
-
VDD-1.2
V
-
-
-
-
-
-
80
-
-
5
-
dB
MHz
°
Unity gain freq.
Phase margin
PSRR+
AVDD=5V
50°
90
90
AVDD=5V
AVDD=5V
-
dB
dB
CMRR
-
AVDD=5V, RLOAD=33K,
CLOAD=50p
Slew rate
6.0
-
-
V/us
Wake up time
-
-
-
-
1
2
us
Quiescent current
mA
Nov. 02, 2016
Page 63 of 69
Rev 1.02
M0519
7.5 Flash DC Electrical Characteristics
SYMBOL
PARAMETER
Supply Voltage
Endurance
CONDITIONS
MIN.
1.62
TYP.
MAX.
UNIT
V[2]
VDD
1.8
1.98
NENDUR
TRET
TERASE
TMER
TPROG
IDD1
10000
100
cycles[1]
year
At 25℃
Data Retention
Page Erase Time
Mass Erase Time
Program Time
20
40
ms
ms
μs
40
Read Current
-
0.15
0.5
7
mA/MHz
mA
IDD2
Program/Erase Current
Note : This table is guaranteed by design, not test in production.
[1] Number of program/erase cycles.
[2] VDD is source from chip LDO output voltage.
Nov. 02, 2016
Page 64 of 69
Rev 1.02
M0519
8
PACKAGE DIMENSIONS
8.1 LQFP 100V (14x14x1.4 mm footprint 2.0mm)
H
D
D
A
A2
7
A1
51
7
50
H
E E
100
26
L1
L
1
25
c
e
b
Y
Controlling Dimension : Millimeters
Dimension in inch
Dimension in mm
Symbol
A
Min Nom
Max
Min Nom
Max
1.60
0.063
A1
A
0.002
0.05
1.45
0.27
0.053 0.055 0.057
1.35
0.17
0.10
1.40
0.22
b
0.011
0.008
0.009
0.006
0.007
0.004
0.547
0.547
c
0.15
0.20
D
E
14.00
0.551
0.551
0.020
14.10
13.90
13.90
0.556
0.556
14.00 14.10
0.50
e
H D
16.00
16.20
16.20
16.00
15.80
15.80
0.45
0.622
0.638
0.638
0.030
0.630
H E
L
0.622 0.630
0.60
1.00
0.75
0.024
0.039
0.018
L1
y
0.10
7
0.004
7
0
0
Nov. 02, 2016
Page 65 of 69
Rev 1.02
M0519
8.2 LQFP 64S (7x7x1.4 mm footprint 2.0 mm)
Nov. 02, 2016
Page 66 of 69
Rev 1.02
M0519
8.3 LQFP 48L (7x7x1.4mm footprint 2.0mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension : Millimeters
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Max
Min
Max Min
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.45
0.25
0.20
7.10
7.10
0.65
9.10
1.40
0.20
A
0.006
0.004
0.272
0.272
0.014
0.350
0.350
0.018
0.15
0.008 0.010
b
c
D
0.006
0.276
0.276
0.020
0.10 0.15
0.008
0.280
0.280
0.026
0.358
7.00
7.00
6.90
6.90
0.35
8.90
E
0.50
9.00
e
H
D
0.354
0.358
0.030
8.90
0.45
9.00
0.60
1.00
9.10
0.75
0.354
0.024
E
H
L
L
Y
0.039
1
0.004
7
0.10
7
0
0
0
Nov. 02, 2016
Page 67 of 69
Rev 1.02
M0519
9
REVISION HISTORY
Date
Revision
Description
2015.06.11
2016.07.31
2016.11.02
1.00
1.
1.
1.
Preliminary version.
1.01
Added “Flash DC Electrical Characteristics” in section 7.5.
Updated OPA and ADC item in 4.1.1 selection guide.
1.02
Nov. 02, 2016
Page 68 of 69
Rev 1.02
M0519
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Nov. 02, 2016
Page 69 of 69
Rev 1.02
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