M2354LJFAE [NUVOTON]
NuMicro® Family Based on Arm® Cortex®-M23;
| 型号： | M2354LJFAE |
| 厂家： | 
NUVOTON |
| 描述： | NuMicro® Family Based on Arm® Cortex®-M23 |
| 文件： | 总233页 (文件大小：4314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NuMicro® Family
Based on Arm® Cortex® -M23
M2354 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Dec. 25, 2020
Page 1 of 233
Rev. 1.00
TABLE OF CONTENTS
1 GENERAL DESCRIPTION.............................................................................12
2 FEATURES.....................................................................................................14
3 PARTS INFORMATION .................................................................................27
3.1 Package Type...............................................................................................................27
3.2 M2354 Series Selection Guide ..................................................................................28
3.3 M2354 Series Selection Code ...................................................................................29
4 PIN CONFIGURATION...................................................................................30
4.1 Pin Configuration..........................................................................................................30
4.1.1 M2354 Pin Diagram....................................................................................................... 30
4.1.2 M2354 Multi-Function Pin Diagram............................................................................. 33
4.2 M2354 Pin Mapping.....................................................................................................46
4.3 M2354 Pin Functional Description.............................................................................50
5 BLOCK DIAGRAM.........................................................................................76
6 FUNCTIONAL DESCRIPTION .......................................................................77
6.1 Arm® Cortex®-M23 Core .............................................................................................77
6.2 System Manager..........................................................................................................79
6.2.1 Overview ......................................................................................................................... 79
6.2.2 Reset................................................................................................................................ 79
6.2.3 Power Modes and Wake-up Sources.......................................................................... 85
6.2.4 System Power Distribution ........................................................................................... 90
6.2.5 Bus Matrix ....................................................................................................................... 92
6.2.6 System Memory Map..................................................................................................... 92
6.2.7 Implementation Defined Attribution Unit (IDAU)........................................................ 96
6.2.8 SRAM Memory Organization........................................................................................ 98
6.2.9 Auto Trim....................................................................................................................... 101
6.2.10Register Lock Control.................................................................................................. 102
6.2.11System Timer (SysTick) .............................................................................................. 105
6.2.12Nested Vectored Interrupt Controller (NVIC) ........................................................... 105
6.2.13Security Attribution Unit (SAU)................................................................................... 106
6.3 Clock Controller..........................................................................................................107
6.3.1 Overview ....................................................................................................................... 107
6.3.2 Clock Generator........................................................................................................... 110
6.3.3 System Clock and SysTick Clock .............................................................................. 112
6.3.4 Peripherals Clock......................................................................................................... 114
6.3.5 Power-down Mode Clock............................................................................................ 115
6.3.6 Clock Output................................................................................................................. 115
Dec. 25, 2020
Page 2 of 233
Rev. 1.00
6.3.7 Share Registers............................................................................................................ 116
6.4 Security Configuration Unit (SCU)...........................................................................117
6.4.1 Overview ....................................................................................................................... 117
6.4.2 Features ........................................................................................................................ 117
6.5 Arm® TrustZone® ........................................................................................................118
6.5.1 Address Space Partition ............................................................................................. 119
6.5.2 Security Attribute Configuration ................................................................................. 121
6.5.3 System Address Map and Access Scheme ............................................................. 122
6.6 Flash Memory Controller (FMC)..............................................................................125
6.6.1 Overview ....................................................................................................................... 125
6.6.2 Features ........................................................................................................................ 125
6.7 General Purpose I/O (GPIO)....................................................................................126
6.7.1 Overview ....................................................................................................................... 126
6.7.2 Features ........................................................................................................................ 126
6.8 PDMA Controller (PDMA).........................................................................................127
6.8.1 Overview ....................................................................................................................... 127
6.8.2 Features ........................................................................................................................ 127
6.9 Timer Controller (TMR) .............................................................................................128
6.9.1 Overview ....................................................................................................................... 128
6.9.2 Features ........................................................................................................................ 128
6.10 Watchdog Timer (WDT).......................................................................................130
6.10.1Overview ....................................................................................................................... 130
6.10.2Features ........................................................................................................................ 130
6.11 Extra Watchdog Timer (EWDT) .........................................................................131
6.11.1Overview ....................................................................................................................... 131
6.11.2Features ........................................................................................................................ 131
6.12 Window Watchdog Timer (WWDT) ...................................................................132
6.12.1Overview ....................................................................................................................... 132
6.12.2Features ........................................................................................................................ 132
6.13 Extra Window Watchdog Timer (EWWDT) ......................................................133
6.13.1Overview ....................................................................................................................... 133
6.13.2Features ........................................................................................................................ 133
6.14 Real Time Clock (RTC) .......................................................................................134
6.14.1Overview ....................................................................................................................... 134
6.14.2Features ........................................................................................................................ 134
6.15 EPWM Generator and Capture Timer (EPWM)...............................................135
6.15.1Overview ....................................................................................................................... 135
6.15.2Features ........................................................................................................................ 135
Dec. 25, 2020
Page 3 of 233
Rev. 1.00
6.16 Basic PWM Generator and Capture Timer (BPWM) ......................................137
6.16.1Overview ....................................................................................................................... 137
6.16.2Features ........................................................................................................................ 137
6.17 Quadrature Encoder Interface (QEI).................................................................138
6.17.1Overview ....................................................................................................................... 138
6.17.2Features ........................................................................................................................ 138
6.18 Enhanced Input Capture Timer (ECAP) ...........................................................139
6.18.1Overview ....................................................................................................................... 139
6.18.2Features ........................................................................................................................ 139
6.19 UART Interface Controller (UART)....................................................................140
6.19.1Overview ....................................................................................................................... 140
6.19.2Features ........................................................................................................................ 140
6.20 Smart Card Host Interface (SC).........................................................................142
6.20.1Overview ....................................................................................................................... 142
6.20.2Features ........................................................................................................................ 142
6.21 I2S Controller (I2S)...............................................................................................143
6.21.1Overview ....................................................................................................................... 143
6.21.2Features ........................................................................................................................ 143
6.22 Serial Peripheral Interface (SPI)........................................................................144
6.22.1Overview ....................................................................................................................... 144
6.22.2Features ........................................................................................................................ 144
6.23 Quad Serial Peripheral Interface (QSPI)..........................................................145
6.23.1Overview ....................................................................................................................... 145
6.23.2Features ........................................................................................................................ 145
6.24 USCI - Universal Serial Control Interface Controller (USCI).........................146
6.24.1Overview ....................................................................................................................... 146
6.24.2Features ........................................................................................................................ 146
6.25 I2C Serial Interface Controller (I2C) ...................................................................147
6.25.1Overview ....................................................................................................................... 147
6.25.2Features ........................................................................................................................ 147
6.26 USCI – UART Mode.............................................................................................148
6.26.1Overview ....................................................................................................................... 148
6.26.2Features ........................................................................................................................ 148
6.27 USCI - SPI Mode..................................................................................................149
6.27.1Overview ....................................................................................................................... 149
6.27.2Features ........................................................................................................................ 149
6.28 USCI - I2C Mode...................................................................................................151
6.28.1Overview ....................................................................................................................... 151
Dec. 25, 2020
Page 4 of 233
Rev. 1.00
6.28.2Features ........................................................................................................................ 151
6.29 Controller Area Network (CAN)..........................................................................152
6.29.1Overview ....................................................................................................................... 152
6.29.2Features ........................................................................................................................ 152
6.30 Secure Digital Host Controller (SDH)................................................................153
6.30.1Overview ....................................................................................................................... 153
6.30.2Features ........................................................................................................................ 153
6.31 External Bus Interface (EBI)...............................................................................154
6.31.1Overview ....................................................................................................................... 154
6.31.2Features ........................................................................................................................ 154
6.32 USB 1.1 Device Controller (USBD)...................................................................155
6.32.1Overview ....................................................................................................................... 155
6.32.2Features ........................................................................................................................ 155
6.33 USB 1.1 Host Controller (USBH).......................................................................156
6.33.1Overview ....................................................................................................................... 156
6.33.2Features ........................................................................................................................ 156
6.34 USB On-The-Go (OTG) ......................................................................................157
6.34.1Overview ....................................................................................................................... 157
6.34.2Features ........................................................................................................................ 157
6.35 CRC Controller (CRC).........................................................................................158
6.35.1Overview ....................................................................................................................... 158
6.35.2Features ........................................................................................................................ 158
6.36 Cryptographic Accelerator (CRYPTO)..............................................................159
6.36.1Overview ....................................................................................................................... 159
6.36.2Features ........................................................................................................................ 159
6.37 Enhanced 12-bit Analog-to-Digital Converter (EADC) ...................................161
6.37.1Overview ....................................................................................................................... 161
6.37.2Features ........................................................................................................................ 161
6.38 True Random Number Generator (TRNG).......................................................163
6.38.1Overview ....................................................................................................................... 163
6.38.2Features ........................................................................................................................ 163
6.39 Key Store (KS)......................................................................................................164
6.39.1Overview ....................................................................................................................... 164
6.39.2Features ........................................................................................................................ 164
6.40 LCD Controller......................................................................................................165
6.40.1Overview ....................................................................................................................... 165
6.40.2Features ........................................................................................................................ 165
6.41 Tamper Controller (TC)........................................................................................167
Dec. 25, 2020
Page 5 of 233
Rev. 1.00
6.41.1Overview ....................................................................................................................... 167
6.41.2Features ........................................................................................................................ 167
6.42 Digital to Analog Converter (DAC).....................................................................168
6.42.1Overview ....................................................................................................................... 168
6.42.2Features ........................................................................................................................ 168
6.43 Analog Comparator Controller (ACMP)............................................................169
6.43.1Overview ....................................................................................................................... 169
6.43.2Features ........................................................................................................................ 169
6.44 Peripherals Interconnection................................................................................170
6.44.1Overview ....................................................................................................................... 170
7 APPLICATION CIRCUIT..............................................................................171
7.1 Power Supply Scheme with External VREF .............................................................171
7.2 Peripheral Application scheme.................................................................................172
8 ELECTRICAL CHARACTERISTIC ..............................................................173
8.1 Absolute Maximum Ratings......................................................................................173
8.1.1 Voltage Characteristics ............................................................................................... 173
8.1.2 Current Characteristics ............................................................................................... 173
8.1.3 Thermal Characteristics.............................................................................................. 174
8.1.4 EMC Characteristics.................................................................................................... 174
8.1.4.1Electrostatic
discharge
(ESD)
174
8.1.5 Package Moisture Sensitivity(MSL) .......................................................................... 175
8.1.6 Soldering Profile........................................................................................................... 176
8.2 General Operating Conditions .................................................................................177
8.3 DC Electrical Characteristics....................................................................................178
8.3.1 Supply Current Characteristics .................................................................................. 178
8.3.2 On-Chip Peripheral Current Consumption ............................................................... 190
8.3.3 Wakeup Timefrom Low-Power Modes...................................................................... 192
8.3.4 I/O DC Characteristics................................................................................................. 193
8.4 AC Electrical Characteristics....................................................................................196
8.4.1 12MHz Internal High Speed RC Oscillator (HIRC) ................................................. 196
8.4.2 48MHz Internal High Speed RC Oscillator (HIRC48)............................................. 196
8.4.3 32 kHz Internal Low Speed RC Oscillator (LIRC) ................................................... 197
8.4.4 32kHz Internal Low Speed RC Oscillator in VBAT domain (LIRC) ......................... 197
8.4.5 4MHz internal medium speed RC oscillator (MIRC)............................................... 197
8.4.6 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
198
8.4.7 External 4~24 MHz High Speed Clock Input Signal Characteristics.................... 200
Dec. 25, 2020
Page 6 of 233
Rev. 1.00
8.4.8 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
201
8.4.9 External 32.768 kHz Low Speed Clock Input Signal Characteristics................... 202
8.4.10PLL Characteristics...................................................................................................... 203
8.4.11I/O AC Characteristics................................................................................................. 203
8.5 Analog Characteristics ..............................................................................................205
8.5.1 LDO................................................................................................................................ 205
8.5.2 DC-DC ........................................................................................................................... 205
8.5.3 Low-Voltage Reset....................................................................................................... 206
8.5.4 12-bit SAR Analog To Digital Converter (ADC)........................................................ 208
8.5.5 Digital to Analog Converter (DAC)............................................................................. 212
8.5.6 Analog Comparator Controller (ACMP) .................................................................... 213
8.5.7 Temperature Sensor.................................................................................................... 214
8.5.8 LCD controller............................................................................................................... 215
8.6 Commucications Characteristics.............................................................................217
8.6.1 SPI Dynamic Characteristics...................................................................................... 217
8.6.2 SPI - I2S Dynamic Characteristics............................................................................. 219
8.6.3 I2C Dynamic Characteristics....................................................................................... 221
8.6.4 USCI - SPI Dynamic Characteristics......................................................................... 222
8.6.5 USCI - I2C Dynamic Characteristics.......................................................................... 222
8.6.6 USB Characteristics .................................................................................................... 223
8.6.7 SDIO Characteristics................................................................................................... 224
8.7 Flash DC Eletrical Charateristics.............................................................................227
9 PACKAGE DIMENSIONS ............................................................................228
9.1 LQFP 48 (7x7x1.4 mm3 Footprint 2.0 mm)............................................................228
9.2 LQFP 64 (7x7x1.4 mm3 Footprint 2.0 mm)............................................................229
9.3 LQFP 128 (14x14x1.4 mm3 Footprint 2.0 mm) .....................................................230
10ABBREVIATIONS ........................................................................................231
10.1 Abbreviations........................................................................................................231
11REVISION HISTORY....................................................................................233
Dec. 25, 2020
Page 7 of 233
Rev. 1.00
LIST OF FIGURES
Figure 4.1-1 M2354 LQFP 48-pin Diagram ....................................................................................30
Figure 4.1-2 M2354 LQFP 64-pin Diagram ....................................................................................31
Figure 4.1-3 M2354 LQFP 128-pin Diagram ..................................................................................32
Figure 4.1-4 M2354LJFAE Multi-function Pin Diagram..................................................................33
Figure 4.1-5 M2354SJFAE Multi-function Pin Diagram..................................................................36
Figure 4.1-6 M2354KJFAE Multi-function Pin Diagram..................................................................40
Figure 5-1 M2354 Block Diagram...................................................................................................76
Figure 6.1-1 Cortex® -M23 Block Diagram ......................................................................................77
Figure 6.2-1 System Reset Sources...............................................................................................80
Figure 6.2-2 nRESET Reset Waveform .........................................................................................82
Figure 6.2-3 Power-on Reset (POR) Waveform.............................................................................83
Figure 6.2-4 Low Voltage Reset (LVR) Waveform .........................................................................83
Figure 6.2-5 Brown-out Detector (BOD) Waveform .......................................................................84
Figure 6.2-6 Power Mode State Machine.......................................................................................87
Figure 6.2-7 Power Distribution Diagram .......................................................................................91
Figure 6.2-8 IDAU Memory Map.....................................................................................................97
Figure 6.2-9 IDAU Block Diagram ..................................................................................................98
Figure 6.2-10 SRAM Block Diagram ..............................................................................................99
Figure 6.2-11 SRAM Memory Organization ...................................................................................99
Figure 6.2-12 SRAM Marco Organization ....................................................................................100
Figure 6.3-1 Clock Generator Global View Diagram (1/3)............................................................108
Figure 6.3-2 Clock Generator Global View Diagram (2/3)............................................................109
Figure 6.3-3 Clock Generator Global View Diagram (3/3)............................................................110
Figure 6.3-4 Clock Generator Block Diagram...............................................................................111
Figure 6.3-5 System Clock Block Diagram...................................................................................113
Figure 6.3-6 HXT Stop Protect Procedure....................................................................................114
Figure 6.3-7 SysTick Clock Control Block Diagram .....................................................................114
Figure 6.3-8 Clock Output Block Diagram....................................................................................116
Figure 6.5-1 Secure World View and Non-secure World View on a Chip....................................118
Figure 6.5-2 The 4 GB Memory Map Divided Into Secure and Non-secure Regions by IDAU....120
Figure 6.5-3 Typical Setting of SAU .............................................................................................121
Figure 6.5-4 Example of SRAM Divided Into Secure Block and Non-secure Block.....................123
Figure 6.5-5 Checking Point of Accesses.....................................................................................124
Figure 6.27-1 SPI Master Mode Application Block Diagram ........................................................149
Figure 6.27-2 SPI Slave Mode Application Block Diagram ..........................................................149
Dec. 25, 2020
Page 8 of 233
Rev. 1.00
Figure 6.28-1 I2C Bus Timing .......................................................................................................151
Figure 8.1-1 Soldering profile from J-STD-020C..........................................................................176
Figure 8.4-1 Typical Crystal Application Circuit............................................................................200
Figure 8.4-2 Typical 32.768 kHz Crystal Application Circuit ........................................................202
Figure 8.5-1 Power Ramp Up/Down Condition ............................................................................208
Figure 8.6-1 SPI Master Mode Timing Diagram...........................................................................217
Figure 8.6-2 SPI Slave Mode Timing Diagram.............................................................................218
Figure 8.6-3 I2S Master Mode Timing Diagram ...........................................................................219
Figure 8.6-4 I2S Slave Mode Timing Diagram..............................................................................220
Figure 8.6-5 I2C Timing Diagram..................................................................................................221
Figure 8.6-6 USCI-SPI Master Mode Timing Diagram .................................................................222
Figure 8.6-8 USCI-I2C Timing Diagram ........................................................................................223
Figure 8.6-9 SDIO Default Mode..................................................................................................225
Figure 8.6-10 SDIO High-speed Mode.........................................................................................226
Dec. 25, 2020
Page 9 of 233
Rev. 1.00
List of Tables
Table 3-1 M2354 Series Selection Guide.......................................................................................28
Table 3-2 M2354 Series Selection Code........................................................................................29
Table 4.1-1 M2354LJFAE Multi-function Pin Table........................................................................35
Table 4.1-3 M2354KJFAE Multi-function Pin Table .......................................................................45
Table 6.2-1 Reset Value of Registers.............................................................................................82
Table 6.2-2 Power Mode Table ......................................................................................................86
Table 6.2-3 Power Mode Entry Setting Table.................................................................................86
Table 6.2-4 Power Mode Difference Table.....................................................................................86
Table 6.2-5 Clocks in Power Modes...............................................................................................88
Table 6.2-6 Condition of Entering Power-down Mode Again .........................................................90
Table 6.2-7 Address Space Assignments for On-Chip Controllers ................................................94
Table 6.2-8 SRAM Power Mode Behavior....................................................................................101
Table 6.2-9 List of Registers with Write Protection ......................................................................104
Table 6.3-1 Each Clock Source Enable Bit and Corresponding Stable Flag Table .....................112
Table 6.3-2 Clock Controller Share Register list ..........................................................................116
Table 6.5-1 Peripherals and Regions that are Always Secure.....................................................122
Table 6.19-1 NuMicro® M2354 Series UART Features................................................................141
Table 8.1-1 Voltage characteristics ..............................................................................................173
Table 8.1-2 Current characteristics ..............................................................................................174
Table 8.1-3 Thermal characteristics .............................................................................................174
Table 8.1-4 EMC characteristics ..................................................................................................175
Table 8.1-5 Package Moisture Sensitivity(MSL) ..........................................................................175
Table 8.1-6 Soldering Profile ........................................................................................................176
Table 8.2-1 General operating conditions ....................................................................................177
Table 8.3-1 Current consumption in LDO Normal Run mode ......................................................179
Table 8.3-2 Current consumption in DC-DC Normal Run mode ..................................................179
Table 8.3-3 Current consumption in Idle mode ............................................................................180
Table 8.3-4 Current consumption in DC-DC mode ......................................................................181
Table 8.3-5 Chip Current Consumption in LDO Power-down mode ............................................185
Table 8.3-6 Chip Current Consumption in DC-DC Power-down mode........................................188
Table 8.3-7 Chip Current Consumption for RTC..........................................................................190
Table 8.3-8 Peripheral Current Consumption...............................................................................192
Table 8.3-9 Low-power mode wakeup timings.............................................................................193
Table 8.3-10 I/O input characteristics...........................................................................................194
Table 8.3-11 I/O output characteristics.........................................................................................194
Dec. 25, 2020
Page 10 of 233
Rev. 1.00
Table 8.3-12 nRESET Input Characteristics.................................................................................195
Table 8.4-1 12 MHz Internal High Speed RC Oscillator(HIRC) characteristics ...........................196
Table 8.4-2 48 MHz Internal High Speed RC Oscillator(HIRC) characteristics ...........................196
Table 8.4-3 32 kHz Internal Low Speed RC Oscillator(LIRC) characteristics ..............................197
Table 8.4-4 32 kHz Internal Low Speed RC Oscillator(LIRC_VBAT) characteristics ..................197
Table 8.4-5 4MHz internal medium speed RC oscillator (MIRC) characteristics .........................198
Table 8.4-6 External 4~24 MHz High Speed Crystal (HXT) Oscillator.........................................199
Table 8.4-7 External 4~24 MHz High Speed Clock Input Signal..................................................201
Table 8.4-8 External 32.768 kHz Low Speed Crystal (LXT) Oscillator ........................................201
Table 8.4-9 External 32.768 kHz Low Speed Clock Input Signal.................................................202
Table 8.4-10 PLL characteristics..................................................................................................203
Table 8.4-11 I/O AC characteristics..............................................................................................204
Table 8.5-1 LDO characteristics...................................................................................................205
Table 8.5-2 LDO characteristics...................................................................................................206
Table 8.5-3 LVR characteristics ...................................................................................................207
Table 8.5-5 12-bit SAR Analog To Digital Converter....................................................................209
Table 8.5-6 12-bit SAR Analog To Digital Converter-low speed ..................................................210
Table 8.5-7 Digital to Analog Converter .......................................................................................213
Table 8.5-8 Analog Comparator Controller...................................................................................214
Table 8.5-9 Temprature Sensor ...................................................................................................215
Table 8.5-10 LCD controller .........................................................................................................216
Table 8.6-1 SPI Master Mode Characteristics..............................................................................217
Table 8.6-2 SPI Slave Mode Characteristics................................................................................218
Table 8.6-3 I2S Characteristics ....................................................................................................219
Table 8.6-4 I2C characteristics......................................................................................................221
Table 8.6-5 USCI-SPI Master Mode Characteristics....................................................................222
Table 8.6-7 USCI-I2C characteristics............................................................................................223
Table 8.6-8 USB Full-Speed Characteristics................................................................................224
Table 8.6-9 USB Full-Speed PHY Characteristics .......................................................................224
Table 8.6-10 SDIO Characteristics...............................................................................................224
Table 8.6-11 SDIO Dynamic Characteristics................................................................................225
Table 8.7-1 Flash DC Eletrical Characteristics.............................................................................227
Table 10.1-1 List of Abbreviations................................................................................................232
Dec. 25, 2020
Page 11 of 233
Rev. 1.00
1
GENERAL DESCRIPTION
The NuMicro® M2354 Series is a TrustZone® for Armv8-M architecture empowered microcontroller
series focusing on IoT Security based on Arm® Cortex® -M23 CPU core technology. It runs up to 96
MHz with 1024 Kbytes embedded Flash memory and 256 Kbytes SRAM, supporting Flash in dual-
bank mode, secure firmware OTA (Over-The-Air) update, ultra-low power consumption in normal run
with 89.3 uA/MHz in LDO mode, 39.6 uA/MHz in DC-DC mode and an 8x40 COM/SEG LCD driver
inside. Besides the fundamental microcontroller security features, it further enhances the chip-level
security in covering side-channel attacks mitigation to crypto hardware engine, fault injection mitigation
for operating voltage and clock as well as active shield to cryptographic key storage. The series
supports power supply voltage from 1.7V ~ 3.6V in operating temperature range from -40°C to
+105°C, and is equipped with both LDO and DC-DC power supply functionalities. The M2354 Series is
quite competitive for those devices that need more secure, fast computing and low power in the IoT
market.
The one of major challenges for IoT devices that are connected to cloud services or other devices by
network communication is security, so the IoT devices must meet some security requirements to
protect firmware, software and secure assets from being stolen or modified by an attacker.
“Execution”, “Storage”, and “Connectivity” are the three important security targets for IoT devices.
The TrustZone® technology based on Armv8-M architecture is a System-on-Chip (SoC) and CPU
system-wide approach to microcontroller security. The whole system isolates secure and normal
worlds to avoid the trusted assets being accessed by a non-secure process. In addition to the
firmware-level security, the M2354 series is also equipped with rich functions to improve system
security. The Secure Bootloader supports trusted system-boot feature which can protect certificated
firmware from being replaced with malware possibly in the upgrade processing and taking control of
system resource finally. The hardware crypto accelerators, including AES, ECC and RSA, support
encryption and decryption operations to offload the main processor’s computing power and ensure
data transmission in secure.
The M2354 series also enhances firmware update security requirement with monotonic version
counter. The firmware cannot be rollback to older one which has lower security protection.
Furthermore, there is a secure crypto keys storage protected by the chip-level active shield function to
physical intrusion. The series addresses the physical attack protection and system security certification
for Arm® PSA CertifiedTM Level 2 even for PSA CertifiedTM Level 3.
Other than security, low power is also vital for IoT applications. The M2354 series supports 4 core
power levels with both LDO and DC-DC power supply mechanism. Except normal run mode, the
series also provides idle run mode with power consumption 31.5 μA/MHz in LDO mode and 14.3
μA/MHz in DC-DC mode. The current consumption of Deep Power-Down mode without VBAT is less
than 0.1 μA.
The M2354 series is equipped with plenty of peripherals such as Timers, Watchdog Timers, RTC,
PDMA, UART, Universal Serial Control Interface (USCI), SPI/ I²S, I2C, GPIOs, makes it highly suitable
for connecting comprehensive external modules. The M2354 integrates high performance analog
front-end circuit blocks, such as 16 channels of 12-bit 6 MSPS ADC, temperature sensor, low voltage
reset (LVR) and brown-out detector (BOD) to enhance product performance, reduce external
components and form factor simultaneously. Moreover, it supports up to 8x40 COM/SEG for segment
LCD display needed such as metering devices.
The M2354 series provides LQFP48 (7mm x 7mm), LQFP64 (7mm x 7mm) and LQFP128 (14mm x
14mm).
The NuMicro® M2354 is suitable for a wide range of applications such as:
IoT Devices with Secure Connection
Collaborative Secure Software Development Business Model
Dec. 25, 2020
Page 12 of 233
Rev. 1.00
Secure Fingerprint Lock
Smart Home Appliance
Smart City Facilities
Wireless Sensor Node Device (WSND)
Secure Wireless Connectivity Module (SWCM)
Auto Meter Reading (AMR)
Digital Currency Authentication
Trusted Execution Environment (TEE) with Trusted Applications (TAs)
Dec. 25, 2020
Page 13 of 233
Rev. 1.00
2
FEATURES
Core And System
Arm® Cortex® -M23 processor, running up to 96 MHz
96 MHz at 1.8V-3.63V; 84 MHz at 1.7V
Supports Arm® TrustZone® Technology
Built-in PMSAv8 Memory Protection Unit (MPU)
Built-in Security Attribution Unit (SAU)
Built-in Nested Vectored Interrupt Controller (NVIC)
Built-in Embedded Trace Macrocell (ETM)
Arm® Cortex® -M23
32-bit Single-cycle hardware multiplier and 32-bit 17-cycle
hardware divider
24-bit system tick timer
Supports Programmable and maskable interrupt
Supports Low Power Sleep mode by WFI and WFE
instructions
Supports single cycle I/O access
Configure SRAM’s security and privilege attribution block by
block
Configure GPIOs’ security and privilege attribution port by
port
Configure peripherals’ security and privilege attribution
Generates secure and privilege violation interrupt
Equipped with a 24-bit timer as a non-secure state monitor
Monotonic firmware version counter
Secure Configuration Unit
(SCU)
Debug protection mechanism
Product life-cycle management
Eight-level BOD with brown-out interrupt and reset option
(3.0V/2.8V/2.6V/2.4V/2.2V/2.0V/1.8V/1.6V)
Brown-out Detector (BOD)
LVR with 1.5V threshold voltage level
Low Voltage Reset (LVR)
Power Manager
Dual voltage regulator is available for DC-DC converter or
LDO
Supports 1.26V, 1.2V, 1.1V and 0.9V core voltage while
operating
Supports Power-down mode
Supports Standby Power -down mode
Supports Low Leakage Power-down mode
Supports Ultra-low Leakage Power-down mode
Supports Fast Wake-up Power-down mode
Supports Deep Power-down mode
Dec. 25, 2020
Page 14 of 233
Rev. 1.00
128-bit Unique ID (UID)
128-bit Unique Customer ID (UCID)
Security
One built-in temperature sensor with 1°C resolution
Memories
Factory pre-loaded 16 KB mask ROM for secure boot
procedure
Uses SHA-256 and ECC-256 to validate data in APROM,
LDROM and external SPI Flash
Boot Loader
Nuvoton ISP (In-System-Programming) tool for firmware
upgrade via UART and high speed USB device
ISP/IAP libraries
Dual bank 1024/512KB on-chip Application ROM (APROM)
for Over-The-Air (OTA) upgrade
16 KB on-chip Flash for user-defined loader (LDROM)
Excute Only Memory (XOM) for intelectual property
protection
All on-chip Flash support 2 KB page erase
Fast Flash programming verification with CRC
Flash
On-chip Flash programming with In-Chip Programming
(ICP), In-System Programming (ISP) and In-Application
Programming (IAP) capabilities
Always boot from boot loader
2-wired ICP Flash updating through SWD interface
32-bit/64-bit and multi-word Flash programming function
Up to 256 KB on-chip SRAM includes:
32 KB SRAM located in bank 0 that supports hardware parity
check; Exception (NMI) generated upon a parity check error
SRAM
128/128 KB SRAM located in bank 1 and bank2
Byte-, half-word- and word-access
PDMA operation
Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32
polynomials
Programmable initial value and seed value
Programmable order reverse setting and one’s complement
setting for input data and CRC checksum
Cyclic Redundancy
Calculation (CRC)
8-bit, 16-bit, and 32-bit data width
8-bit write mode with 1-AHB clock cycle operation
16-bit write mode with 2-AHB clock cycle operation
32-bit write mode with 4-AHB clock cycle operation
Uses DMA to write data with performing CRC operation
Dec. 25, 2020
Page 15 of 233
Rev. 1.00
16 independent and configurable channels for automatic
data transfer between memories and peripherals
8 channels of PDMA1 can be configured as secure or non-
secure channels
Supports time-out function when transfer time-out
Basic and Scatter-Gather transfer modes
Each channel supports circular buffer management using
Scatter-Gather Transfer mode
Peripheral DMA (PDMA)
Stride function for rectangle image data movement
Fixed-priority and Round-robin priorities modes
Single and burst transfer types
Byte-, half-word- and word tranfer unit with count up to
65536
Incremental or fixed source and destination address
Clocks
4~24 MHz High-speed external crystal oscillator (HXT) for
precise timing operation
32.768 kHz Low-speed external crystal oscillator (extLXT) for
RTC function and low-power system operation
External Clock Source
Supports clock failure detection for external crystal oscillators
and exception generation (NMI)
12 MHz High-speed Internal RC oscillator (HIRC) trimmed to
0.25% accuracy that can optionally be used as a system
clock
48 MHz High-speed Internal RC oscillator (HIRC48) trimmed
to 0.25% accuracy that can optionally be used as a system
clock
Internal Clock Source
32 kHz Low-speed Internal RC oscillator (LIRC32) for RTC
function
Up to 200 MHz on-chip PLL, sourced from HIRC or HXT,
allows CPU operation up to the maximum CPU frequency
without the need for a high-frequency crystal
Real-Time Clock with a separate power domain
The RTC clock source includes Low-speed external crystal
oscillator (extLXT) and 32 kHz Low-speed Internal RC
oscillator (LIRC32)
The RTC block includes 80 bytes of battery-powered backup
registers, which can be cleared by tamper pins
Real-Time Clock (RTC)
Supports 6 static and dynamic tamper pins
Able to wake up CPU from any reduced power mode
Supports Alarm registers (second, minute, hour, day, month,
year)
Supports RTC Time Tick and Alarm Match interrupt
Automatic leap year recognition
Dec. 25, 2020
Page 16 of 233
Rev. 1.00
Supports 1 Hz clock output for calibration
Frequency of RTC clock source compensated by
RTC_FRWQADJ register
Timers
TIMER
Four sets of 32-bit timers with 24-bit up counter and one 8-bit
pre-scale counter from independent clock source
One-shot, Periodic, Toggle and Continuous Counting
operation modes
Supports event counting function to count the event from
external pins
Supports external capture pin for interval measurement and
resetting 24-bit up counter
Supports chip wake-up function, if a timer interrupt signal is
generated
32-bit Timer
PWM
Eight 16-bit PWM counters with 12-bit clock prescale with up
to 64 MHz
Supports 12-bit deadband (dead time)
Up, down or up-down PWM counter type
Supports brake function
Supports mask function and tri-state output for each PWM
channel
Twelve 16-bit counters with 12-bit clock prescale for twelve
36 MHz PWM output channels
Up to 12 independent input capture channels with 16-bit
resolution counter
Supports dead time with maximum divided 12-bit prescale
Up, down or up-down PWM counter type
Supports complementary mode for 3 complementary paired
PWM output channels
Enhanced PWM (EPWM)
Synchronous function for phase control
Counter synchronous start function
Brake function with auto recovery mechanism
Mask function and tri-state output for each PWM channel
Able to trigger EADC or DAC to start conversion
Two 16-bit counters with 12-bit clock prescale for twelve 36
MHz PWM output channels
Up to 6 independent input capture channels with 16-bit
resolution counter
Basic PWM (BPWM)
Up, down or up-down PWM counter type
Counter synchronous start function
Complementary mode for 3 complementary paired PWM
Dec. 25, 2020
Page 17 of 233
Rev. 1.00
output channels
Mask function and tri-state output for each PWM channel
Able to trigger EADC to start conversion
18-bit free running up counter for WDT time-out interval
Supports multiple clock sources from LIRC (default
selection), HCLK/2048 and LXT with 8 selectable time-out
period
Able to wake up system from Power-down or Idle mode
Time-out event to trigger interrupt or reset system
Watchdog
Supports four WDT reset delay periods, including 1026, 130,
18 or 3 WDT_CLK reset delay period
Configured to force WDT enabled on chip power-on or reset
Clock sourced from HCLK/2048 or LIRC; the window set by
6-bit down counter with 11-bit prescale
Window Watchdog
Suspended in Idle/Power-down mode
Analog Interfaces
One 12-bit, 19-ch SAR EADC with up to 16 single-ended
input channels or 8 differential input pairs; 10-bit accuracy is
guaranteed
Three internal channels for VBAT, band-gap VBG input and
Temperature sensor input
Supports external VREF pin
Two power saving modes: Power-down mode and Standby
mode.
Enhanced Analog-to-Digital
Converter (EADC)
Supports calibration capability
Analog-to-Digital conversion can be triggered by software
enable, external pin, Timer 0~3 overflow pulse trigger or
EPWM trigger
Configurable EADC sampling time
Up to 19 sample modules
Double data buffers for sample module 0~3
PDMA operation
Two 12-bit, 1 MSPS voltage type DAC with 8-bit mode and
8μs rail-to-rail settle time
Maximum output voltage AVDD -0.2V at buffer mode
Digital-to-Analog conversion triggered by Timer0~3, EPWM0,
EPWM1, external trigger pin to start DAC conversion or
software
Digital-to-Analog Converter
(DAC)
Supports group mode for synchronized data update of two
DACs.
PDMA operation
Two rail-to-rail Analog Comparators
Analog Comparator
Dec. 25, 2020
Page 18 of 233
Rev. 1.00
Supports four multiplexed I/O pins at positive input
(ACMP)
Supports I/O pins, band-gap, DAC output, and 16-level
Voltage divider from AVDD or VREF at negative input
Supports four programmable propagation speeds for power
saving.
Supports wake up from Power-down by interrput
Supports triggers for brake events and cycle-by-cycle control
for PWM
Supports window compare mode and window latch mode
Supports programmable hysteresis window: 0mV, 10mV,
20mV and 30mV
Supports the following COM/SEG configurations:
– 320 dots (8-COM x 40-SEG)
– 252 dots (6-COM x 42-SEG)
– 176 dots (4-COM x 44-SEG)
– 104 dots (8-COM x 13-SEG) for M2354SIFAE
Supports maximum 8 COM driving pins, multiplexed with
GPIO pins
Supports maximum 44 SEG driving pins, multiplexed with
GPIO pins
Supports 3 bias voltage levels 1/2, 1/3, and 1/4
LCD
Supports 8 duty ratios 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, and 1/8
Supports clock frequency divider from 2, 4, 6… 2048 to
configure the LCD operating frequency
Configurable frame counting event interrupt period
Supports LCD blinking display controlled by frame counting
event.
Supports LCD frame end interrupt
LCD keeps display or blinking even if in Power-down mode
when LCD clock source is selected as LIRC or LXT
Supports both type A and type B driving waveforms
Communication Interfaces
Auto-Baud Rate measurement and baud rate compensation
function
Supports low power UART (LPUART): baud rate clock from
LXT(32.768 kHz) with 9600bps in Power-down mode even
system clock is stopped
16-byte FIFOs with programmable level trigger
Auto flow control ( nCTS and nRTS)
Low-power UART
Supports IrDA (SIR) function
Supports LIN function on UART0 and UART1
Supports RS-485 9-bit mode and direction control
Supports nCTS, incoming data, Received Data FIFO
Dec. 25, 2020
Page 19 of 233
Rev. 1.00
reached threshold and RS-485 Address Match (AAD mode)
wake-up function in idle mode
Supports hardware or software enables to program nRTS pin
to control RS-485 transmission direction
Supports wake-up function
8-bit receiver FIFO time-out detection function
Supports break error, frame error, parity error and
receive/transmit FIFO overflow detection function
PDMA operation
Three sets of ISO-7816-3 which are compliant with ISO-
7816-3 T=0, T=1
Supports full duplex UART function
4-byte FIFOs with programmable level trigger
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8 bit time-out counters for Answer to
Request (ATR) and waiting times processing
Smart Card Interface
Auto inverse convention function
Stop clock level and clock stop (clock keep) function
Transmitter and receiver error retry function
Supports hardware activation, deactivation and warm reset
sequence process
Supports hardware auto deactivation sequence after card
removal
Three sets of I2C devices with Master/Slave mode
Supports Standard mode (100 kbps), Fast mode (400 kbps)
and Fast mode plus (1 Mbps)
Supports 10 bits mode
Programmable clocks allowing for versatile rate control
I2C
Supports multiple address recognition (four slave address
with mask option)
Supports SMBus and PMBus
Supports multi-address power-down wake-up function
PDMA operation
Up to four sets of SPI/I2S controllers with Master/Slave mode
SPI/ I2S provides separate 4-level of 32-bit (or 8-level of 16-
bit) transmit and receive FIFO buffers
SPI
SPI/I2S
Configurable bit length of a transfer word from 8 to 32-bit
MSB first or LSB first transfer sequence
Byte reorder function
Supports Byte or Word Suspend mode
Supports one data channel half-duplex transfer
Dec. 25, 2020
Page 20 of 233
Rev. 1.00
Supports receive-only mode
PDMA operation
I2S
Supports mono and stereo audio data with 8-, 16-, 24- and
32-bit audio data sizes
Supports PCM mode A, PCM mode B, I2S and MSB justified
data format
PDMA operation
One set of SPI Quad controller with Master/Slave mode
2-bit Transfer mode
Dual and Quad I/O Transfer mode
QSPI provides separate 8-level of 32-bit transmit and receive
FIFO buffers
Configurable bit length of a transfer word from 8 to 32-bit
MSB first or LSB first transfer sequence
Byte reorder function
QSPI
Supports Byte or Word Suspend mode
3-wired, no slave select signal, bi-direction interface
Supports one data channel half-duplex transfer
Supports receive-only mode
PDMA operation
One set of I2S interface with Master/Slave mode
Supports mono and stereo audio data with 8-, 16-, 24- and
32-bit word sizes
Two 16-level FIFO data buffers, one for transmitting and the
other for receiving
Supports I2S protocols: Philips standard, MSB-justified, and
LSB-justified data format
I2S
Supports PCM protocols: PCM standard, MSB-justified, and
LSB-justified data format
PCM protocol supports TDM multi-channel transmission in
one audio sample; the number of data channel can be set as
2, 4, 6 or 8
PDMA operation
Two sets of USCI, configured as UART, SPI or I2C function
Supports single byte TX and RX buffer mode
UART
Universal Serial Control
Interface (USCI)
Supports one transmit buffer and two receive buffers for data
payload
Supports hardware auto flow control function and
programmable flow control trigger level
9-bit Data Transfer
Dec. 25, 2020
Page 21 of 233
Rev. 1.00
Baud rate detection by built-in capture event of baud rate
generator
Supports wake-up function
PDMA operation
SPI
Supports Master or Slave mode operation
Supports one transmit buffer and two receive buffer for data
payload
Configurable bit length of a transfer word from 4 to 16-bit
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in slave
mode
Supports one data channel half-duplex transfer
PDMA operation
I2C
Supports master and slave device capability
Supports one transmit buffer and two receive buffer for data
payload
Communication in standard mode (100 kbps), fast mode (up
to 400 kbps), and Fast mode plus (1 Mbps)
Supports 10-bit mode
Supports 10-bit bus time out capability
Supports bus monitor mode
Supports power-down wake-up by data toggle or address
match
Supports multiple address recognition
Supports device address flag
Programmable setup/hold time
Two sets of CAN 2.0B controllers
Each supports 32 Message Objects; each Message Object
has its own identifier mask
Controller Area Network
(CAN)
Programmable FIFO mode (concatenation of Message
Object)
Disabled Automatic Re-transmission mode for Time
Triggered CAN applications
Supports power-down wake-up function
One sets of Secure Digital Host Controllers, compliant with
SD Memory Card Specification Version 2.0
Secure Digital Host
Controller (SDHC)
Supports 36 MHz to achieve 192 Mbps at 3.3V operation
Supports dedicated DMA master with Scatter-Gather
function to accelerate the data transfer between system
Dec. 25, 2020
Page 22 of 233
Rev. 1.00
memory and SD/SDHC/SDIO card
Supports up to three memory banks with individual
adjustment of timing parameter
Each bank supports dedicated external chip select pin with
polarity control and up to 1 MB addressing space
8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports variable external bus base clock (MCLK) which
based on HCLK
External Bus Interface
(EBI)
Configurable idle cycle for different access condition: Idle of
Write command finish (W2X) and Idle of Read-to-Read
(R2R)
Supports Address/Data multiplexed mode
Supports address bus and data bus separate mode
Supports LCD interface i80 mode
PDMA operation
Supports four I/O modes: Quasi bi-direction, Push-Pull
output, Open-Drain output and Input only with high
impendence mode
Selectable TTL/Schmitt trigger input
Configured as interrupt source with edge/level trigger setting
Supports independent pull-up/pull-down control
Supports high driver and high sink current I/O
Supports software selectable slew rate control
Supports 5V-tolerance function except analog I/O.
Improve access efficiency by using single cycle I/O bus
GPIO
Control Interfaces
Two QEI phase inputs (QEI_A, QEI_B) and one Index input
(QEI_INDEX)
Quadrature Encoder
Interface (QEI)
Supports 2/4 times free-counting mode and 2/4 compare-
counting mode
Supports encoder pulse width measurement mode with
ECAP
Input Capture Timer/Counter
Supports three input channels with independent capture
counter hold register
24-bit Input Capture up-counting timer/counter supports
captured events reset and/or reload capture counter
Enhanced Capture (ECAP)
Supports rising edge, falling edge and both edge detector
options with noise filter in front of input ports
Supports compare-match function
Advanced Connectivity
Dec. 25, 2020
Page 23 of 233
Rev. 1.00
USB 2.0 Full Speed OTG (On-The-Go)
On-chip USB 2.0 full speed OTG transceiver
Compliant with USB OTG Supplement 2.0
Configurable as host-only, device-only, ID-dependent or
OTG device
USB 1.1 Host Controller
Compliant with USB Revision 1.1 Specification
Compatible with OHCI (Open Host Controller Interface)
Revision 1.0
Supports full-speed (12Mbps) and low-speed (1.5Mbps) USB
devices
Supports Control, Bulk, Interrupt, Isochronous and Split
transfers
USB 2.0 Full Speed with
on-chip transceiver
Integrated a port routing logic to route full/low speed device
to OHCI controller
Supports an integrated Root Hub
Supports port power control and port overcurrent detection
Built-in DMA
USB 2.0 Full Speed Device Controller
Compliant with USB Revision 2.0 Specification
Supports suspend function when no bus activity existing for 3
ms
12 configurable endpoints for configurable Isochronous,
Bulk, Interrupt and Control transfer types
1024 bytes configurable RAM for endpoint buffer
Remote wake-up capability
Cryptography Accelerator
Hardware ECC accelerator
Supports both prime field GF(p) and binary field GF(2m)
Supports NIST P-192, P-224, P-256, P-384 and P-521 curve
sizes
Supports NIST B-163, B-233, B-283, B-409 and B-571 curve
sizes
Supports NIST K-163, K-233, K-283, K-409 and K-571 curve
sizes
Elliptic Curve
Cryptography (ECC)
Supports Curve25519
Supports point multiplication, addition and doubling
operations in GF(p) and GF(2m)
Supports modulus division, multiplication, addition and
subtraction operations in GF(p)
Supports three techniques to improve side-channel attack
protection ability
Supports Public Key Cryptographic Algorithm SM2 Based on
Dec. 25, 2020
Page 24 of 233
Rev. 1.00
Elliptic Curves
Hardware AES accelerator
Supports 128-bit, 192-bit and 256-bit key length and key
expander, and is compliant with FIPS 197
Advanced Encryption
Standard (AES)
Supports ECB, CBC, CFB, OFB, CTR, CBC-CS1, CBC-CS2
and CBC-CS3 block cipher modes
Compliant with NIST SP800-38A and addendum
Supports SM4 cipher block alogrithm
Hardware SHA accelerator
Supports SHA-160, SHA-224, SHA-256, SHA-384, and SHA-
512
Secure Hash Algorithm
(SHA)
Compliant with FIPS 180/180-2
Supprots SM3 Cryptographic Hash Alogrithm
Hardware RSA accelerator
Supports both encryption and decryption with 1024, 2048,
3072 and 4096 bits
Rivest, Shamir and
Adleman Cryptography
(RSA)
Supports Chinese Remainder Theorem (CRT) decryption
with 2048, 3072 and 4096 bits
Supports three techniques to improve side-channel attack
protection ability
Supports 128, 163, 192, 224, 233, 255, 256, 283, 384, 409,
512, 521 and 571 bits random number generation (283~571
bits only generate for Key Store)
Pseudo Random Number
Generator (PRNG)
Able to take the true random number seed from TRNG
Up to 800 random bits per second
True Randon Number
Generator (TRNG)
Provide the true random number seed for PRNG
Key Store
Supports programming interface for key management
Supports multiple key size from 128 bits to 4096 bits
Supports 4 Kbytes SRAM, 2 Kbytes Flash and 544bytes
OTP for key storage
Supports 32 keys for SRAM, 32 keys for Flash and 8 keys for
OTP at most
Supports crypto engine access or store key in key store
directly
Key Store
Supports ECDH operation with ECC and PRNG engine
Supports to store middle data for RSA CRT and SCAP mode
Supports revoke operation for each key
Supports erase key in SRAM/Flash and revoke key in OTP
while tamper detected
Supports integrity checking
Dec. 25, 2020
Page 25 of 233
Rev. 1.00
Supports data scrambling at SRAM, Flash and OTP
Supports data remanence prevention at SRAM
Supports silent access for side-channel protection at SRAM,
Flash and OTP
Attack Detection
Includes voltage, clock and I/O tamper detectors:
– Voltage,
HV detector detects if VDD ﹥4.0V
LV detector detects if LDO_CAP ﹥± 20%
– Clock detector:
detects if external clock (LXT) is failed or stopped
– I/O tamper detector:
detects GPF6~11 pins
Attack Detection (TAMPER)
Provides event response after an attack detected:
– Clear key or data content in SRAM and Flash of Key
Store, and revoke the OTP in Key Store
– Clear RTC spare register
– Reset Crypto
– Chip reset
– Interrupt
– Wake up the system
Not supported in DPD mode.
Dec. 25, 2020
Page 26 of 233
Rev. 1.00
3
PARTS INFORMATION
3.1 Package Type
Part No.
LQFP48
LQFP64
LQFP128
M2354
M2354LJFAE
M2354SJFAE
M2354KJFAE
Dec. 25, 2020
Page 27 of 233
Rev. 1.00
3.2 M2354 Series Selection Guide
M2354
PART NUMBER
LJFAE
SJFAE
KJFAE
1024
256
Flash (KB)
SRAM (KB)
ISP Loader ROM (KB)
I/O
1024
256
1024
256
16
50
4
40
1
106
6
32-bit Timer
Tamper I/O
RTC
1
√
LPUART
6
ISO-7816
3
Quad SPI SPI/I2S
I2S
1
3
1
4
1
4
1
3
I2C
USCI (UART/I2C/
SPI)
2
CAN
LIN
1
2
SDHC
1
1
1
TRNG
√
AES
√
ECC
√
SHA/HMAC
RSA
√
√
FVC
√
DPM
√
PLM
√
Key Store
√
Power Glitch Detector
LCD (COMXSEG)
16-bit Enhanced PWM
16-bit Basic PWM
QEI
√
-
8 X 13
8 X 40
12
12
2
1
2
2
1
ECAP
1
USB 2.0 FS OTG
12-bit ADC
12-bit DAC
Analog Comparator
External Bus Interface
Package
√
11
16
16
2
2
√
2
√
2
√
LQFP48
LQFP 64
LQFP 128
Table 3-1 M2354 Series Selection Guide
Dec. 25, 2020
Page 28 of 233
Rev. 1.00
3.3 M2354 Series Selection Code
M23
54
K
J
F
A
E
Secure Core
Line
Package
Flash
SRAM
Rev.
Temperature
Cortex® -M23
54: Ultra Line
(Segment LCD)
L: LQFP48
(7x7 mm)
J: 1024 KB
F: 256 kB
E: -40°C~105°C
S: LQFP64
(7x7 mm)
K: LQFP128
(14x14 mm)
Table 3-2 M2354 Series Selection Code
Dec. 25, 2020
Page 29 of 233
Rev. 1.00
4 PIN CONFIGURATION
Users can find pin configuration information in the M2354 Multi-function Pin diagram sections or by
using NuTool - PinConfigure. The NuTool - PinConfigure contains all NuMicro® Family chip series with
all part number, and helps users configure GPIO multi-function correctly and handily.
4.1 Pin Configuration
4.1.1
M2354 Pin Diagram
4.1.1.1 M2354 LQFP 48-Pin Diagram
Corresponding Part Number: M2354LJFAE
37
24
23
22
21
20
19
18
17
16
15
14
13
PA.15
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
PF.4
38
VSS
39
Vsw
40
VDD
41
LDO_CAP
42
PB.15
LQFP48
43
PB.14
44
PB.13
45
PB.12
46
AVDD
47
AVSS
48
PB.7
VDDIO power domain
Figure 4.1-1 M2354 LQFP 48-pin Diagram
Dec. 25, 2020
Page 30 of 233
Rev. 1.00
4.1.1.2 M2354 LQFP 64-Pin Diagram
Corresponding Part Number: M2354SJFAE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
Vsw
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
LDO_CAP
VDD
VDD
LDO_CAP
PB.15
PB.14
PB.13
PB.12
AVDD
LQFP64
VREF
AVSS
VSS
PB.11
PB.10
PB.9
PA.6
PA.7
PC.6
PC.7
PF.2
PB.8
PB.7
VDDIO power domain
VBAT power domain
Figure 4.1-2 M2354 LQFP 64-pin Diagram
Dec. 25, 2020
Page 31 of 233
Rev. 1.00
4.1.1.3 M2354 LQFP 128-Pin Diagram
Corresponding Part Number: M2354KJFAE
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PE.7
PE.6
nRESET
PE.15
PE.14
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
LDO_CAP
VDD
98
99
PE.5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PE.4
PE.3
PE.2
VSS
VDD
PE.1
PE.0
PH.8
PH.9
PH.10
PH.11
PD.14
VSS
VSS
PA.6
PA.7
PC.6
PC.7
PC.8
PE.13
PE.12
PE.11
PE.10
PE.9
PE.8
VDD
LQFP128
Vsw
VDD
LDO_CAP
PB.15
PB.14
PB.13
PB.12
AVDD
VREF
AVSS
PB.11
PB.10
PB.9
VSS
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
PB.8
PB.7
PB.6
VDDIO power domain
VBAT power domain
Figure 4.1-3 M2354 LQFP 128-pin Diagram
Dec. 25, 2020
Page 32 of 233
Rev. 1.00
4.1.2
M2354 Multi-Function Pin Diagram
4.1.2.1
M2354 LQFP 48-Pin Multi-function Pin Diagram
Corresponding Part Number: M2354LJFAE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
USB_OTG_ID
/
EPWM0_SYNC_IN
/
BPWM1_CH5
/
SC2_CLK
/
I2C2_SDA
/
SPI2_MOSI
/
UART0_RXD
/
I2S0_DO
/
PA.15
VSS
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
PF.4
/
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
I2C2_SDA
I2C2_SCL
/
BPWM0_CH0
BPWM0_CH1
/
EPWM0_CH5 DAC0_ST
/
Vsw
VDD
/
/
EPWM0_CH4 / DAC1_ST
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
/
SC0_RST
/
UART4_RXD
/
UART1_RXD
/
I2C1_SDA
I2C0_SMBAL
I2C0_SDA CAN0_RXD
I2C0_SCL CAN0_TXD
BPWM1_CH3 ACMP1_WLAT
BPWM1_CH2 ACMP0_WLAT
/
I2C0_SMBSUS
BPWM0_CH3
UART0_RXD
UART0_TXD
/
BPWM0_CH2
EPWM0_CH2
BPWM0_CH4
BPWM0_CH5
TM3 INT0
TM2 INT1
/
EPWM0_CH3
LDO_CAP
/
SPI0_SS SC0_PWR
/
/
UART4_TXD
/
UART1_TXD
/
I2C1_SCL
/
/
/
/
QEI0_B
/
EPWM1_BRAKE1
EPWM0_CH1 QEI0_A
EPWM0_CH0 QEI0_INDEX
USB_VBUS_EN
TM1_EXT EPWM1_CH1
EPWM1_CH2 I2C2_SCL
EPWM1_CH3 SD0_nCD I2C2_SDA
/
TM0_EXT
/
EPWM1_CH0
/
I2C2_SMBAL
I2C2_SMBSUS
USCI0_DAT0
USCI0_CLK
/
UART3_TXD
/
UART0_nCTS
/
USCI0_CTL1
/
SPI0_SS
/
SC1_PWR
SC1_RST
/
/
EBI_AD12
EBI_AD13
/
/
/
/
EADC0_CH15
EADC0_CH14
EADC0_CH13
EADC0_CH12
/
/
/
/
PB.15
PB.14
PB.13
PB.12
AVDD
QSPI0_MOSI1
QSPI0_MISO1
/
/
SPI0_I2SMCLK
SPI1_I2SMCLK
/
/
SC0_nCD
SC2_nCD
/
/
UART0_nRTS
UART0_nCTS
/
/
UART5_RXD
UART5_TXD
/
/
/
/
/
/
LQFP48
USB_VBUS_ST
TM4_EXT TM2_EXT
TM3_EXT
/
CLKO
/
/
/
EPWM0_BRAKE1
/
/
UART3_RXD
/
UART0_nRTS
/
USCI0_DAT1
/
SPI0_CLK
/
/
/
/
/
/
/
/
/
/
/
UART3_nRTS
/
UART0_TXD
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
SC1_DAT
SC1_CLK
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
DAC1_OUT
DAC0_OUT
EBI_AD6
EBI_AD7
/
/
SPI1_SS
/
SC2_CLK
/
UART0_RXD
/
I2C1_SDA
I2C1_SCL
QSPI0_CLK XT1_OUT
XT1_IN BPWM1_CH0
BPWM0_CH5 X32_OUT
/
TM5
TM4
BPWM1_CH1
/
EPWM1_CH5
/
/
/
/
TM5_EXT
/
/
/
/
/
UART3_nCTS
/
UART0_RXD
/
SPI1_CLK
/
SC2_DAT
/
UART0_TXD
/
/
/
EPWM1_CH4
/
/
/
/
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
/
/
AVSS
/
/
/
ACMP0_O
/
USB_VBUS_ST
/
INT5
/
EPWM1_CH4
/
EPWM1_BRAKE0
/
BPWM1_CH4
/
EBI_nCS0
/
UART1_TXD
/
USCI1_DAT0
/
EBI_nWRL
/
EADC0_CH7
/
PB.7
UART2_TXD
/
UART2_nRTS
/
EPWM0_CH1
/
/
Figure 4.1-4 M2354LJFAE Multi-function Pin Diagram
Pin M2354LJFAE Pin Function
PB.5 / EADC0_CH5 / ACMP1_N / EBI_ADR0 / SD0_DAT3 / SPI1_MISO / I2C0_SCL / UART5_TXD / USCI1_CTL0 /
SC0_CLK / I2S0_BCLK / EPWM0_CH0 / UART2_TXD / TM0 / INT0
1
2
3
4
PB.4 / EADC0_CH4 / ACMP1_P1 / EBI_ADR1 / SD0_DAT2 / SPI1_MOSI / I2C0_SDA / UART5_RXD / USCI1_CTL1 /
SC0_DAT / I2S0_MCLK / EPWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / EADC0_CH3 / ACMP0_N / EBI_ADR2 / SD0_DAT1 / SPI1_CLK / UART1_TXD / UART5_nRTS / USCI1_DAT1
/ SC0_RST / I2S0_DI / EPWM0_CH2 / I2C1_SCL / TM4 / TM2 / INT2
PB.2 / EADC0_CH2 / ACMP0_P1 / EBI_ADR3 / SD0_DAT0 / SPI1_SS / UART1_RXD / UART5_nCTS / USCI1_DAT0
/ SC0_PWR / I2S0_DO / EPWM0_CH3 / I2C1_SDA / TM5 / TM3 / INT3
Dec. 25, 2020
Page 33 of 233
Rev. 1.00
Pin M2354LJFAE Pin Function
PB.1 / EADC0_CH1 / EBI_ADR8 / SD0_CLK / SPI1_I2SMCLK / UART2_TXD / USCI1_CLK / I2C1_SCL / I2S0_LRCK /
EPWM0_CH4 / EPWM1_CH4 / EPWM0_BRAKE0 / QSPI0_MISO1
5
6
PB.0 / EADC0_CH0 / EBI_ADR9 / SD0_CMD / SPI2_I2SMCLK / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA /
EPWM0_CH5 / EPWM1_CH5 / EPWM0_BRAKE1 / QSPI0_MOSI1
PA.11
/ ACMP0_P0 / EBI_nRD / SC2_PWR / SPI2_SS / USCI0_CLK / I2C2_SCL / BPWM0_CH0 /
7
EPWM0_SYNC_OUT / TM0_EXT / DAC1_ST
PA.10 / ACMP1_P0 / EBI_nWR / SC2_RST / SPI2_CLK / USCI0_DAT0 / I2C2_SDA / BPWM0_CH1 / QEI1_INDEX /
ECAP0_IC0 / TM1_EXT / DAC0_ST
8
PA.9 / EBI_MCLK / SC2_DAT / SPI2_MISO / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / QEI1_A / ECAP0_IC1 /
TM4_EXT / TM2_EXT
9
PA.8 / EBI_ALE / SC2_CLK / SPI2_MOSI / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / QEI1_B / ECAP0_IC2 /
TM5_EXT / TM3_EXT / INT4
10
11 PF.6 / EBI_ADR19 / SC0_CLK / I2S0_LRCK / SPI0_MOSI / UART4_RXD / EBI_nCS0 / TAMPER0
12 PF.5 / UART2_RXD / UART2_nCTS / EPWM0_CH0 / BPWM0_CH4 / EPWM0_SYNC_OUT / X32_IN / EADC0_ST
13 PF.4 / UART2_TXD / UART2_nRTS / EPWM0_CH1 / BPWM0_CH5 / X32_OUT
14 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
15 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
PA.7 / EBI_AD7 / SPI1_CLK / SC2_DAT / UART0_TXD / I2C1_SCL / TM4 / EPWM1_CH4 / BPWM1_CH2 /
ACMP0_WLAT / TM2 / INT1
16
PA.6 / EBI_AD6 / SPI1_SS / SC2_CLK / UART0_RXD / I2C1_SDA / TM5 / EPWM1_CH5 / BPWM1_CH3 /
ACMP1_WLAT / TM3 / INT0
17
PA.5 / QSPI0_MISO1 / SPI1_I2SMCLK / SC2_nCD / UART0_nCTS / UART5_TXD / I2C0_SCL / CAN0_TXD /
UART0_TXD / BPWM0_CH5 / EPWM0_CH0 / QEI0_INDEX
18
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART5_RXD / I2C0_SDA / CAN0_RXD /
UART0_RXD / BPWM0_CH4 / EPWM0_CH1 / QEI0_A
19
PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / UART4_TXD / UART1_TXD / I2C1_SCL / I2C0_SMBAL / BPWM0_CH3 /
EPWM0_CH2 / QEI0_B / EPWM1_BRAKE1
20
PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / UART4_RXD / UART1_RXD / I2C1_SDA / I2C0_SMBSUS /
BPWM0_CH2 / EPWM0_CH3
21
PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / I2C2_SCL / BPWM0_CH1 /
EPWM0_CH4 / DAC1_ST
22
PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / I2C2_SDA / BPWM0_CH0 /
EPWM0_CH5 / DAC0_ST
23
24 VDDIO
25 nRESET
26 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
27 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
28 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / CAN0_TXD / UART4_TXD / EPWM1_CH0
PC.4 / EBI_AD4 / QSPI0_MOSI1 / SC1_nCD / I2S0_BCLK / SPI1_I2SMCLK / UART2_RXD / I2C1_SDA / CAN0_RXD
/ UART4_RXD / EPWM1_CH1
29
30 PC.3 / EBI_AD3 / QSPI0_SS / SC1_PWR / I2S0_MCLK / SPI1_MISO / UART2_nRTS / I2C0_SMBAL / UART3_TXD /
Dec. 25, 2020
Page 34 of 233
Rev. 1.00
Pin M2354LJFAE Pin Function
EPWM1_CH2
PC.2 / EBI_AD2 / QSPI0_CLK / SC1_RST / I2S0_DI / SPI1_MOSI / UART2_nCTS / I2C0_SMBSUS / UART3_RXD /
EPWM1_CH3
31
32
33
34
35
PC.1 / EBI_AD1 / QSPI0_MISO0 / SC1_DAT / I2S0_DO / SPI1_CLK / UART2_TXD / I2C0_SCL / EPWM1_CH4 /
ACMP0_O / EADC0_ST
PC.0 / EBI_AD0 / QSPI0_MOSI0 / SC1_CLK / I2S0_LRCK / SPI1_SS / UART2_RXD / I2C0_SDA / EPWM1_CH5 /
ACMP1_O
PA.12 / I2S0_BCLK / UART4_TXD / I2C1_SCL / SPI2_SS / CAN0_TXD / SC2_PWR / BPWM1_CH2 / QEI1_INDEX /
USB_VBUS
PA.13 / I2S0_MCLK / UART4_RXD / I2C1_SDA / SPI2_CLK / CAN0_RXD / SC2_RST / BPWM1_CH3 / QEI1_A /
USB_D-
36 PA.14 / I2S0_DI / UART0_TXD / SPI2_MISO / I2C2_SCL / SC2_DAT / BPWM1_CH4 / QEI1_B / USB_D+
PA.15 / I2S0_DO / UART0_RXD / SPI2_MOSI / I2C2_SDA / SC2_CLK / BPWM1_CH5 / EPWM0_SYNC_IN /
USB_OTG_ID
37
38 VSS
39 Vsw
40 VDD
41 LDO_CAP
PB.15 / EADC0_CH15 / EBI_AD12 / SC1_PWR / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD /
I2C2_SMBAL / EPWM1_CH0 / TM0_EXT / USB_VBUS_EN
42
PB.14 / EADC0_CH14 / EBI_AD13 / SC1_RST / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD /
I2C2_SMBSUS / EPWM0_BRAKE1 / EPWM1_CH1 / TM1_EXT / CLKO / USB_VBUS_ST
43
PB.13 / EADC0_CH13 / DAC1_OUT / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SC1_DAT / SPI0_MISO / USCI0_DAT0 /
UART0_TXD / UART3_nRTS / I2C2_SCL / EPWM1_CH2 / TM2_EXT / TM4_EXT
44
PB.12 / EADC0_CH12 / DAC0_OUT / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SC1_CLK / SPI0_MOSI / USCI0_CLK /
UART0_RXD / UART3_nCTS / I2C2_SDA / SD0_nCD / EPWM1_CH3 / TM3_EXT / TM5_EXT
45
46 AVDD
47 AVSS
PB.7 / EADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / EPWM1_BRAKE0 /
EPWM1_CH4 / INT5 / USB_VBUS_ST / ACMP0_O
48
Table 4.1-1 M2354LJFAE Multi-function Pin Table
Dec. 25, 2020
Page 35 of 233
Rev. 1.00
M2354 LQFP 64-Pin Multi-function Pin Diagram
Corresponding Part Number: M2354SJFAE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
Vsw
nRESET
VDDIO
VDD
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
LCD_COM6/SEG14
LCD_COM7/SEG13
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
I2C2_SDA
I2C2_SCL
/
BPWM0_CH0
BPWM0_CH1
/
EPWM0_CH5 DAC0_ST
/
LDO_CAP
/
/
EPWM0_CH4 / DAC1_ST
USB_VBUS_EN
TM1_EXT EPWM1_CH1
EPWM1_CH2 I2C2_SCL UART3_nRTS
H3 SD0_nCD I2C2_SDA UART3_nCTS
/
TM0_EXT
EPWM0_BRAKE1
UART0_TXD
UART0_RXD
/
EPWM1_CH0
I2C2_SMBSUS
USCI0_DAT0
USCI0_CLK
/
I2C2_SMBAL
/
UART3_TXD
/
UART0_nCTS
/
USCI0_CTL1
/
SPI0_SS
/
SC1_PWR
SC1_RST
/
/
EBI_AD12
EBI_AD13
/
/
/
/
EADC0_CH15
EADC0_CH14
EADC0_CH13
EADC0_CH12
/
/
/
/
PB.15
PB.14
PB.13
PB.12
AVDD
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS LCD_SEG4
/
LCD_SEG3
/
SC0_RST
/
UART4_RXD
UART4_TXD
/
UART1_RXD
/
I2C1_SDA
I2C0_SMBAL
/
I2C0_SMBSUS
BPWM0_CH3
CAN0_RXD UART0_RXD
CAN0_TXD UART0_TXD
/
BPWM0_CH2
EPWM0_CH2 EPWM1_BR
BPWM0_CH4 EPWM0_CH1
BPWM0_CH5 / EPWM0_CH0
/
EPWM0_CH3
KO
/
/
/
/
/
UART3_RXD
/
UART0_nRTS
/
USCI0_DAT1
/
SPI0_CLK
/
/
/
/
SC0_PWR
/
/
UART1_TXD I2C1_SCL
/
/
/
/
/
QEI0_B
/
/
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
SC1_DAT
SC1_CLK
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
DAC1_OUT
DAC0_OUT
QSPI0_MOSI1
QSPI0_MISO1
/
/
SPI0_I2SMCLK
SPI1_I2SMCLK
/
/
LCD_SEG5
LCD_SEG6
/
/
SC0_nCD
SC2_nCD
/
/
UART0_nRTS
UART0_nCTS
/
/
UART5_RXD
UART5_TXD
/
I2C0_SDA
I2C0_SCL
/
/
/
/
/
/
/
/
/
/
/
/
/
LQFP64
LDO_CAP
VDD
VREF
AVSS
VSS
SPI3_CLK
SPI3_SS
SPI3_MISO
SPI3_MOSI
USB_VBUS_ST INT5 EPWM1_CH4
/
BPWM1_CH0
BPWM1_CH1
BPWM1_CH2
BPWM1_CH3
EPWM1_BRAKE0
/
SPI0_I2SMCLK
CAN0_RXD I2C1_SDA
I2C0_SCL I2C1_SMBAL
I2C0_SDA I2C1_SMBSUS
BPWM1_CH4
/
CAN0_TXD
UART4_RXD
UART1_nCTS
UART1_nRTS
EBI_nCS0
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART0_TXD
/
UART0_nCTS
/
/
EBI_ADR16
EBI_ADR17
/
/
EADC0_CH11
EADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
SPI1_SS
/
SC2_CLK
/
UART0_RXD
/
I2C1_SDA
I2C1_SCL
UART0_nRTS
UART0_nCTS
XT1_OUT BPWM1_CH1
/
LCD_SEG7
LCD_SEG8
I2C1_SMBSUS
I2C1_SMBAL
/
TM5
/
EPWM1_CH5
EPWM1_CH4
EPWM1_CH3
EPWM1_CH2
/
BPWM1_CH3
BPWM1_CH2
BPWM1_CH1
BPWM1_CH0
/
ACMP1_WLAT
ACMP0_WLAT
LCD_SEG9
LCD_SEG10 /
/ TM3 / INT0
/
/
/
/
/
/
USCI1_CTL0
SPI1_CLK
/
SC2_DAT
/
UART0_TXD
/
/
/
TM4
/
/
/
/
TM2
TM1
TM0
/
INT1
INT2
INT3
INT7
INT6
/
/
/
/
/
/
/
USCI1_CTL1
USCI1_CLK
/
/
EBI_ADR18
EBI_ADR19
/
/
/
EADC0_CH9
/
/
/
PB.9
PB.8
PB.7
SPI1_MOSI
SPI1_MISO
/
/
UART4_RXD
UART4_TXD
I2C0_SDA
/
SC2_RST
SC2_PWR
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
UART0_RXD
UART1_TXD
/
EADC0_CH8
EADC0_CH7
/
/
/
/
/
/
ACMP0_O
/
/
/
/
/
/
/
USCI1_DAT0
/
EBI_nWRL
EBI_nCS1
/
UART0_RXD
/
/
QSPI0_CLK
/
/
Figure 4.1-5 M2354SJFAE Multi-function Pin Diagram
Pin M2354SJFAE Pin Function
PB.6 / EADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / EPWM1_BRAKE1 /
EPWM1_CH5 / INT4 / USB_VBUS_EN / ACMP1_O
1
2
PB.5 / EADC0_CH5 / ACMP1_N / EBI_ADR0 / SD0_DAT3 / SPI1_MISO / I2C0_SCL / UART5_TXD / USCI1_CTL0 /
SC0_CLK / I2S0_BCLK / EPWM0_CH0 / UART2_TXD / TM0 / INT0
Dec. 25, 2020
Page 36 of 233
Rev. 1.00
Pin M2354SJFAE Pin Function
PB.4 / EADC0_CH4 / ACMP1_P1 / EBI_ADR1 / SD0_DAT2 / SPI1_MOSI / I2C0_SDA / UART5_RXD / USCI1_CTL1 /
SC0_DAT / I2S0_MCLK / EPWM0_CH1 / UART2_RXD / TM1 / INT1
3
4
PB.3 / EADC0_CH3 / ACMP0_N / EBI_ADR2 / SD0_DAT1 / SPI1_CLK / UART1_TXD / UART5_nRTS / USCI1_DAT1
/ SC0_RST / I2S0_DI / EPWM0_CH2 / I2C1_SCL / TM4 / TM2 / INT2
PB.2 / EADC0_CH2 / ACMP0_P1 / EBI_ADR3 / SD0_DAT0 / SPI1_SS / UART1_RXD / UART5_nCTS / USCI1_DAT0
/ SC0_PWR / I2S0_DO / EPWM0_CH3 / I2C1_SDA / TM5 / TM3 / INT3
5
PB.1 / EADC0_CH1 / EBI_ADR8 / SD0_CLK / SPI1_I2SMCLK / SPI3_I2SMCLK / UART2_TXD / USCI1_CLK /
I2C1_SCL / I2S0_LRCK / EPWM0_CH4 / EPWM1_CH4 / EPWM0_BRAKE0 / QSPI0_MISO1
6
PB.0 / EADC0_CH0 / EBI_ADR9 / SD0_CMD / SPI2_I2SMCLK / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA /
EPWM0_CH5 / EPWM1_CH5 / EPWM0_BRAKE1 / QSPI0_MOSI1
7
PA.11
/ ACMP0_P0 / EBI_nRD / SC2_PWR / SPI2_SS / USCI0_CLK / I2C2_SCL / BPWM0_CH0 /
8
EPWM0_SYNC_OUT / TM0_EXT / DAC1_ST
PA.10 / ACMP1_P0 / EBI_nWR / SC2_RST / SPI2_CLK / USCI0_DAT0 / I2C2_SDA / BPWM0_CH1 / QEI1_INDEX /
ECAP0_IC0 / TM1_EXT / DAC0_ST
9
PA.9 / EBI_MCLK / SC2_DAT / SPI2_MISO / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / QEI1_A / ECAP0_IC1 /
TM4_EXT / TM2_EXT / LCD_SEG12
10
11
PA.8 / EBI_ALE / SC2_CLK / SPI2_MOSI / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / QEI1_B / ECAP0_IC2 /
TM5_EXT / TM3_EXT / LCD_SEG11 / INT4
12 PF.6 / EBI_ADR19 / SC0_CLK / I2S0_LRCK / SPI0_MOSI / UART4_RXD / EBI_nCS0 / SPI3_I2SMCLK / TAMPER0
13 VBAT
14 PF.5 / UART2_RXD / UART2_nCTS / EPWM0_CH0 / BPWM0_CH4 / EPWM0_SYNC_OUT / X32_IN / EADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / EPWM0_CH1 / BPWM0_CH5 / X32_OUT
16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
PC.7 / EBI_AD9 / SPI1_MISO / UART4_TXD / SC2_PWR / UART0_nCTS / I2C1_SMBAL / EPWM1_CH2 /
BPWM1_CH0 / LCD_SEG10 / TM0 / INT3
18
PC.6 / EBI_AD8 / SPI1_MOSI / UART4_RXD / SC2_RST / UART0_nRTS / I2C1_SMBSUS / EPWM1_CH3 /
BPWM1_CH1 / LCD_SEG9 / TM1 / INT2
19
PA.7 / EBI_AD7 / SPI1_CLK / SC2_DAT / UART0_TXD / I2C1_SCL / LCD_SEG8 / TM4 / EPWM1_CH4 /
BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
20
PA.6 / EBI_AD6 / SPI1_SS / SC2_CLK / UART0_RXD / I2C1_SDA / LCD_SEG7 / TM5 / EPWM1_CH5 / BPWM1_CH3
/ ACMP1_WLAT / TM3 / INT0
21
22 VSS
23 VDD
24 LDO_CAP
PA.5 / QSPI0_MISO1 / SPI1_I2SMCLK / LCD_SEG6 / SC2_nCD / UART0_nCTS / UART5_TXD / I2C0_SCL /
CAN0_TXD / UART0_TXD / BPWM0_CH5 / EPWM0_CH0 / QEI0_INDEX
25
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / LCD_SEG5 / SC0_nCD / UART0_nRTS / UART5_RXD / I2C0_SDA /
CAN0_RXD / UART0_RXD / BPWM0_CH4 / EPWM0_CH1 / QEI0_A
26
PA.3 / QSPI0_SS / SPI0_SS / LCD_SEG4 / SC0_PWR / UART4_TXD / UART1_TXD / I2C1_SCL / I2C0_SMBAL /
BPWM0_CH3 / EPWM0_CH2 / QEI0_B / EPWM1_BRAKE1
27
Dec. 25, 2020
Page 37 of 233
Rev. 1.00
Pin M2354SJFAE Pin Function
PA.2 / QSPI0_CLK / SPI0_CLK / LCD_SEG3 / SC0_RST / UART4_RXD / UART1_RXD / I2C1_SDA / I2C0_SMBSUS /
BPWM0_CH2 / EPWM0_CH3
28
29
30
PA.1 / QSPI0_MISO0 / SPI0_MISO / LCD_COM7/SEG13 / SC0_DAT / UART0_TXD / UART1_nCTS / I2C2_SCL /
BPWM0_CH1 / EPWM0_CH4 / DAC1_ST
PA.0 / QSPI0_MOSI0 / SPI0_MOSI / LCD_COM6/SEG14 / SC0_CLK / UART0_RXD / UART1_nRTS / I2C2_SDA /
BPWM0_CH0 / EPWM0_CH5 / DAC0_ST
31 VDDIO
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / CAN0_TXD / UART4_TXD / EPWM1_CH0 /
LCD_SEG15 / LCD_COM5
35
PC.4 / EBI_AD4 / QSPI0_MOSI1 / SC1_nCD / I2S0_BCLK / SPI1_I2SMCLK / UART2_RXD / I2C1_SDA / CAN0_RXD
/ UART4_RXD / EPWM1_CH1 / LCD_SEG16 / LCD_COM4
36
PC.3 / EBI_AD3 / QSPI0_SS / SC1_PWR / I2S0_MCLK / SPI1_MISO / UART2_nRTS / I2C0_SMBAL / UART3_TXD /
EPWM1_CH2 / LCD_COM3
37
PC.2 / EBI_AD2 / QSPI0_CLK / SC1_RST / I2S0_DI / SPI1_MOSI / UART2_nCTS / I2C0_SMBSUS / UART3_RXD /
EPWM1_CH3 / LCD_COM2
38
PC.1 / EBI_AD1 / QSPI0_MISO0 / SC1_DAT / I2S0_DO / SPI1_CLK / UART2_TXD / I2C0_SCL / EPWM1_CH4 /
LCD_COM1 / ACMP0_O / EADC0_ST
39
PC.0 / EBI_AD0 / QSPI0_MOSI0 / SC1_CLK / I2S0_LRCK / SPI1_SS / UART2_RXD / I2C0_SDA / EPWM1_CH5 /
LCD_COM0 / ACMP1_O
40
PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / SC2_PWR / SC1_nCD / UART0_TXD /
LCD_SEG2
41
42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / SC2_RST / UART0_RXD / LCD_SEG1
43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD / I2C2_SCL / SC2_DAT / LCD_SEG0
44 VLCD
PA.12 / I2S0_BCLK / UART4_TXD / I2C1_SCL / SPI2_SS / CAN0_TXD / SC2_PWR / BPWM1_CH2 / QEI1_INDEX /
USB_VBUS
45
PA.13 / I2S0_MCLK / UART4_RXD / I2C1_SDA / SPI2_CLK / CAN0_RXD / SC2_RST / BPWM1_CH3 / QEI1_A /
USB_D-
46
47 PA.14 / I2S0_DI / UART0_TXD / SPI2_MISO / I2C2_SCL / SC2_DAT / BPWM1_CH4 / QEI1_B / USB_D+
PA.15 / I2S0_DO / UART0_RXD / SPI2_MOSI / I2C2_SDA / SC2_CLK / BPWM1_CH5 / EPWM0_SYNC_IN /
USB_OTG_ID
48
49 VSS
50 Vsw
51 VDD
52 LDO_CAP
PB.15 / EADC0_CH15 / EBI_AD12 / SC1_PWR / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD /
I2C2_SMBAL / EPWM1_CH0 / TM0_EXT / USB_VBUS_EN
53
Dec. 25, 2020
Page 38 of 233
Rev. 1.00
Pin M2354SJFAE Pin Function
PB.14 / EADC0_CH14 / EBI_AD13 / SC1_RST / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD /
I2C2_SMBSUS / EPWM0_BRAKE1 / EPWM1_CH1 / TM1_EXT / CLKO / USB_VBUS_ST
54
55
56
PB.13 / EADC0_CH13 / DAC1_OUT / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SC1_DAT / SPI0_MISO / USCI0_DAT0 /
UART0_TXD / UART3_nRTS / I2C2_SCL / EPWM1_CH2 / TM2_EXT / TM4_EXT
PB.12 / EADC0_CH12 / DAC0_OUT / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SC1_CLK / SPI0_MOSI / USCI0_CLK /
UART0_RXD / UART3_nCTS / I2C2_SDA / SD0_nCD / EPWM1_CH3 / TM3_EXT / TM5_EXT
57 AVDD
58 VREF
59 AVSS
PB.11 / EADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / CAN0_TXD / SPI0_I2SMCLK /
BPWM1_CH0 / SPI3_CLK
60
61
62
63
64
PB.10 / EADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / CAN0_RXD /
BPWM1_CH1 / SPI3_SS
PB.9 / EADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / I2C1_SMBAL / I2C0_SCL /
BPWM1_CH2 / SPI3_MISO / INT7
PB.8 / EADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / I2C1_SMBSUS / I2C0_SDA /
BPWM1_CH3 / SPI3_MOSI / INT6
PB.7 / EADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / EPWM1_BRAKE0 /
EPWM1_CH4 / INT5 / USB_VBUS_ST / ACMP0_O
Dec. 25, 2020
Page 39 of 233
Rev. 1.00
M2354 LQFP 128-Pin Multi-function Pin Diagram
Corresponding Part Number: M2354KJFAE
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PE.7
PE.6
nRESET
PE.15
PE.14
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
LDO_CAP
VDD
98
99
PE.5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PE.4
PE.3
PE.2
VSS
VDD
PE.1
PE.0
PH.8
PH.9
PH.10
PH.11
PD.14
VSS
VSS
PA.6
PA.7
PC.6
PC.7
PC.8
PE.13
PE.12
PE.11
PE.10
PE.9
PE.8
VDD
LQFP128
Vsw
VDD
LDO_CAP
PB.15
PB.14
PB.13
PB.12
AVDD
VREF
AVSS
PB.11
PB.10
PB.9
VSS
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
PB.8
PB.7
PB.6
VDDIO power domain
VBAT power domain
Figure 4.1-6 M2354KJFAE Multi-function Pin Diagram
Pin M2354KJFAE Pin Function
PB.5 / EADC0_CH5 / ACMP1_N / EBI_ADR0 / SD0_DAT3 / SPI1_MISO / I2C0_SCL / UART5_TXD / USCI1_CTL0 /
SC0_CLK / I2S0_BCLK / EPWM0_CH0 / UART2_TXD / TM0 / INT0
1
2
3
PB.4 / EADC0_CH4 / ACMP1_P1 / EBI_ADR1 / SD0_DAT2 / SPI1_MOSI / I2C0_SDA / UART5_RXD / USCI1_CTL1 /
SC0_DAT / I2S0_MCLK / EPWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / EADC0_CH3 / ACMP0_N / EBI_ADR2 / SD0_DAT1 / SPI1_CLK / UART1_TXD / UART5_nRTS / USCI1_DAT1
/ SC0_RST / I2S0_DI / EPWM0_CH2 / I2C1_SCL / TM4 / TM2 / INT2
PB.2 / EADC0_CH2 / ACMP0_P1 / EBI_ADR3 / SD0_DAT0 / SPI1_SS / UART1_RXD / UART5_nCTS / USCI1_DAT0
/ SC0_PWR / I2S0_DO / EPWM0_CH3 / I2C1_SDA / TM5 / TM3 / INT3
4
5
PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / SPI3_MISO / SC0_nCD / ECAP1_IC2 / EPWM1_CH0 / ACMP0_O
Dec. 25, 2020
Page 40 of 233
Rev. 1.00
Pin M2354KJFAE Pin Function
6
7
8
PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / SPI3_MOSI / ECAP1_IC1 / EPWM1_CH1 / ACMP1_O
PC.10 / EBI_ADR6 / SPI3_CLK / UART3_TXD / ECAP1_IC0 / EPWM1_CH2
PC.9 / EBI_ADR7 / SPI3_SS / UART3_RXD / EPWM1_CH3
PB.1 / EADC0_CH1 / EBI_ADR8 / SD0_CLK / SPI1_I2SMCLK / SPI3_I2SMCLK / UART2_TXD / USCI1_CLK /
I2C1_SCL / I2S0_LRCK / EPWM0_CH4 / EPWM1_CH4 / EPWM0_BRAKE0 / QSPI0_MISO1
9
PB.0 / EADC0_CH0 / EBI_ADR9 / SD0_CMD / SPI2_I2SMCLK / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA /
EPWM0_CH5 / EPWM1_CH5 / EPWM0_BRAKE1 / QSPI0_MOSI1
10
11 VSS
12 VDD
PA.11
/ ACMP0_P0 / EBI_nRD / SC2_PWR / SPI2_SS / USCI0_CLK / I2C2_SCL / BPWM0_CH0 /
13
14
15
16
EPWM0_SYNC_OUT / TM0_EXT / DAC1_ST
PA.10 / ACMP1_P0 / EBI_nWR / SC2_RST / SPI2_CLK / USCI0_DAT0 / I2C2_SDA / BPWM0_CH1 / QEI1_INDEX /
ECAP0_IC0 / TM1_EXT / DAC0_ST
PA.9 / EBI_MCLK / SC2_DAT / SPI2_MISO / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / QEI1_A / ECAP0_IC1 /
TM4_EXT / TM2_EXT
PA.8 / EBI_ALE / SC2_CLK / SPI2_MOSI / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / QEI1_B / ECAP0_IC2 /
TM5_EXT / TM3_EXT / INT4
17 PC.13 / EBI_ADR10 / SC2_nCD / SPI2_I2SMCLK / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / EADC0_ST
18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / QEI0_INDEX / CLKO / EADC0_ST / INT5
19 PD.11 / EBI_nCS1 / UART1_TXD / CAN0_TXD / QEI0_A / INT6
20 PD.10 / EBI_nCS2 / UART1_RXD / CAN0_RXD / QEI0_B / INT7
21 PG.2 / EBI_ADR11 / SPI2_SS / I2C0_SMBAL / I2C1_SCL / TM0 / LCD_SEG39
22 PG.3 / EBI_ADR12 / SPI2_CLK / I2C0_SMBSUS / I2C1_SDA / TM1 / LCD_SEG38
23 PG.4 / EBI_ADR13 / SPI2_MISO / TM4 / TM2 / LCD_SEG37
24 PF.11 / EBI_ADR14 / SPI2_MOSI / UART5_TXD / TAMPER5 / TM5 / TM3
25 PF.10 / EBI_ADR15 / SC0_nCD / I2S0_BCLK / SPI0_I2SMCLK / UART5_RXD / TAMPER4
26 PF.9 / EBI_ADR16 / SC0_PWR / I2S0_MCLK / SPI0_SS / UART5_nRTS / TAMPER3
27 PF.8 / EBI_ADR17 / SC0_RST / I2S0_DI / SPI0_CLK / UART5_nCTS / TAMPER2
28 PF.7 / EBI_ADR18 / SC0_DAT / I2S0_DO / SPI0_MISO / UART4_TXD / TAMPER1
29 PF.6 / EBI_ADR19 / SC0_CLK / I2S0_LRCK / SPI0_MOSI / UART4_RXD / EBI_nCS0 / SPI3_I2SMCLK / TAMPER0
30 VBAT
31 PF.5 / UART2_RXD / UART2_nCTS / EPWM0_CH0 / BPWM0_CH4 / EPWM0_SYNC_OUT / X32_IN / EADC0_ST
32 PF.4 / UART2_TXD / UART2_nRTS / EPWM0_CH1 / BPWM0_CH5 / X32_OUT
33 PH.4 / EBI_ADR3 / SPI1_MISO / LCD_SEG36
34 PH.5 / EBI_ADR2 / SPI1_MOSI / LCD_SEG35
35 PH.6 / EBI_ADR1 / SPI1_CLK / LCD_SEG34
Dec. 25, 2020
Page 41 of 233
Rev. 1.00
Pin M2354KJFAE Pin Function
36 PH.7 / EBI_ADR0 / SPI1_SS / LCD_SEG33
37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
39 VSS
40 VDD
PE.8 / EBI_ADR10 / I2S0_BCLK / SPI2_CLK / USCI1_CTL1 / UART2_TXD / EPWM0_CH0 / EPWM0_BRAKE0 /
ECAP0_IC0 / TRACE_DATA3 / LCD_SEG32
41
42
43
44
45
46
PE.9 / EBI_ADR11 / I2S0_MCLK / SPI2_MISO / USCI1_CTL0 / UART2_RXD / EPWM0_CH1 / EPWM0_BRAKE1 /
ECAP0_IC1 / TRACE_DATA2 / LCD_SEG31
PE.10 / EBI_ADR12 / I2S0_DI / SPI2_MOSI / USCI1_DAT0 / UART3_TXD / EPWM0_CH2 / EPWM1_BRAKE0 /
ECAP0_IC2 / TRACE_DATA1 / LCD_SEG30
PE.11 / EBI_ADR13 / I2S0_DO / SPI2_SS / USCI1_DAT1 / UART3_RXD / UART1_nCTS / EPWM0_CH3 /
EPWM1_BRAKE1 / ECAP1_IC2 / TRACE_DATA0
PE.12 / EBI_ADR14 / I2S0_LRCK / SPI2_I2SMCLK / USCI1_CLK / UART1_nRTS / EPWM0_CH4 / ECAP1_IC1 /
TRACE_CLK
PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / EPWM0_CH5 / EPWM1_CH0 / BPWM1_CH5 /
ECAP1_IC0
47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / EPWM1_CH1 / BPWM1_CH4
PC.7 / EBI_AD9 / SPI1_MISO / UART4_TXD / SC2_PWR / UART0_nCTS / I2C1_SMBAL / EPWM1_CH2 /
BPWM1_CH0 / TM0 / INT3
48
PC.6 / EBI_AD8 / SPI1_MOSI / UART4_RXD / SC2_RST / UART0_nRTS / I2C1_SMBSUS / EPWM1_CH3 /
BPWM1_CH1 / TM1 / INT2
49
PA.7 / EBI_AD7 / SPI1_CLK / SC2_DAT / UART0_TXD / I2C1_SCL / TM4 / EPWM1_CH4 / BPWM1_CH2 /
ACMP0_WLAT / TM2 / INT1
50
PA.6 / EBI_AD6 / SPI1_SS / SC2_CLK / UART0_RXD / I2C1_SDA / TM5 / EPWM1_CH5 / BPWM1_CH3 /
ACMP1_WLAT / TM3 / INT0
51
52 VSS
53 VDD
54 LDO_CAP
PA.5 / QSPI0_MISO1 / SPI1_I2SMCLK / SC2_nCD / UART0_nCTS / UART5_TXD / I2C0_SCL / CAN0_TXD /
UART0_TXD / BPWM0_CH5 / EPWM0_CH0 / QEI0_INDEX / LCD_SEG29
55
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART5_RXD / I2C0_SDA / CAN0_RXD /
UART0_RXD / BPWM0_CH4 / EPWM0_CH1 / QEI0_A / LCD_SEG28
56
PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / UART4_TXD / UART1_TXD / I2C1_SCL / I2C0_SMBAL / LCD_SEG27 /
BPWM0_CH3 / EPWM0_CH2 / QEI0_B / EPWM1_BRAKE1
57
PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / UART4_RXD / UART1_RXD / I2C1_SDA / I2C0_SMBSUS / LCD_SEG26
/ BPWM0_CH2 / EPWM0_CH3
58
PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / I2C2_SCL / LCD_SEG25 /
BPWM0_CH1 / EPWM0_CH4 / DAC1_ST
59
PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / I2C2_SDA / LCD_SEG24 /
BPWM0_CH0 / EPWM0_CH5 / DAC0_ST
60
Dec. 25, 2020
Page 42 of 233
Rev. 1.00
Pin M2354KJFAE Pin Function
61 VDDIO
62 PE.14 / EBI_AD8 / UART2_TXD / CAN0_TXD / LCD_SEG23
63 PE.15 / EBI_AD9 / UART2_RXD / CAN0_RXD / LCD_SEG22
64 nRESET
65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
67 PD.9 / EBI_AD7 / I2C2_SCL / UART2_nCTS / LCD_COM7/SEG40
68 PD.8 / EBI_AD6 / I2C2_SDA / UART2_nRTS / LCD_COM6/SEG41
PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / CAN0_TXD / UART4_TXD / EPWM1_CH0 /
LCD_COM5/SEG42
69
70
71
72
73
74
PC.4 / EBI_AD4 / QSPI0_MOSI1 / SC1_nCD / I2S0_BCLK / SPI1_I2SMCLK / UART2_RXD / I2C1_SDA / CAN0_RXD
/ UART4_RXD / EPWM1_CH1 / LCD_COM4/SEG43
PC.3 / EBI_AD3 / QSPI0_SS / SC1_PWR / I2S0_MCLK / SPI1_MISO / UART2_nRTS / I2C0_SMBAL / UART3_TXD /
EPWM1_CH2 / LCD_COM3
PC.2 / EBI_AD2 / QSPI0_CLK / SC1_RST / I2S0_DI / SPI1_MOSI / UART2_nCTS / I2C0_SMBSUS / UART3_RXD /
EPWM1_CH3 / LCD_COM2
PC.1 / EBI_AD1 / QSPI0_MISO0 / SC1_DAT / I2S0_DO / SPI1_CLK / UART2_TXD / I2C0_SCL / EPWM1_CH4 /
LCD_COM1 / ACMP0_O / EADC0_ST
PC.0 / EBI_AD0 / QSPI0_MOSI0 / SC1_CLK / I2S0_LRCK / SPI1_SS / UART2_RXD / I2C0_SDA / EPWM1_CH5 /
LCD_COM0 / ACMP1_O
75 VSS
76 VDD
77 PG.9 / EBI_AD0 / BPWM0_CH5 / LCD_SEG21
78 PG.10 / EBI_AD1 / BPWM0_CH4 / LCD_SEG20
79 PG.11 / EBI_AD2 / BPWM0_CH3 / LCD_SEG19
80 PG.12 / EBI_AD3 / BPWM0_CH2 / LCD_SEG18
81 PG.13 / EBI_AD4 / BPWM0_CH1 / LCD_SEG17
82 PG.14 / EBI_AD5 / BPWM0_CH0 / LCD_SEG16
83 PG.15 / LCD_SEG15 / CLKO / EADC0_ST
84 PD.7 / UART1_TXD / I2C0_SCL / SPI1_MISO / USCI1_CLK / SC1_PWR / LCD_SEG14
85 PD.6 / UART1_RXD / I2C0_SDA / SPI1_MOSI / USCI1_DAT1 / SC1_RST / LCD_SEG13
86 PD.5 / I2C1_SCL / SPI1_CLK / USCI1_DAT0 / SC1_DAT
87 PD.4 / USCI0_CTL0 / I2C1_SDA / SPI1_SS / USCI1_CTL1 / SC1_CLK / USB_VBUS_ST
88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / SC2_PWR / SC1_nCD / UART0_TXD
89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / SC2_RST / UART0_RXD
90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD / I2C2_SCL / SC2_DAT
Dec. 25, 2020
Page 43 of 233
Rev. 1.00
Pin M2354KJFAE Pin Function
91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / I2C2_SDA / SC2_CLK / TM2
92 VLCD
PA.12 / I2S0_BCLK / UART4_TXD / I2C1_SCL / SPI2_SS / CAN0_TXD / SC2_PWR / BPWM1_CH2 / QEI1_INDEX /
USB_VBUS
93
94
PA.13 / I2S0_MCLK / UART4_RXD / I2C1_SDA / SPI2_CLK / CAN0_RXD / SC2_RST / BPWM1_CH3 / QEI1_A /
USB_D-
95 PA.14 / I2S0_DI / UART0_TXD / SPI2_MISO / I2C2_SCL / SC2_DAT / BPWM1_CH4 / QEI1_B / USB_D+
PA.15 / I2S0_DO / UART0_RXD / SPI2_MOSI / I2C2_SDA / SC2_CLK / BPWM1_CH5 / EPWM0_SYNC_IN /
USB_OTG_ID
96
97 PE.7 / SD0_CMD / UART5_TXD / QEI1_INDEX / EPWM0_CH0 / BPWM0_CH5 / LCD_SEG12
PE.6 / SD0_CLK / SPI3_I2SMCLK / SC0_nCD / USCI0_CTL0 / UART5_RXD / QEI1_A / EPWM0_CH1 / BPWM0_CH4
/ LCD_SEG11
98
PE.5 / EBI_nRD / SD0_DAT3 / SPI3_SS / SC0_PWR / USCI0_CTL1 / QEI1_B / EPWM0_CH2 / BPWM0_CH3 /
LCD_SEG10
99
PE.4 / EBI_nWR / SD0_DAT2 / SPI3_CLK / SC0_RST / USCI0_DAT1 / QEI0_INDEX / EPWM0_CH3 / BPWM0_CH2 /
LCD_SEG9
100
PE.3 / EBI_MCLK / SD0_DAT1 / SPI3_MISO / SC0_DAT / USCI0_DAT0 / QEI0_A / EPWM0_CH4 / BPWM0_CH1 /
LCD_SEG8
101
PE.2 / EBI_ALE / SD0_DAT0 / SPI3_MOSI / SC0_CLK / USCI0_CLK / QEI0_B / EPWM0_CH5 / BPWM0_CH0 /
LCD_SEG7
102
103 VSS
104 VDD
PE.1 / EBI_AD10 / QSPI0_MISO0 / SC2_DAT / I2S0_BCLK / SPI1_MISO / UART3_TXD / I2C1_SCL / UART4_nCTS /
LCD_SEG6
105
PE.0 / EBI_AD11 / QSPI0_MOSI0 / SC2_CLK / I2S0_MCLK / SPI1_MOSI / UART3_RXD / I2C1_SDA / UART4_nRTS
/ LCD_SEG5
106
PH.8 / EBI_AD12 / QSPI0_CLK / SC2_PWR / I2S0_DI / SPI1_CLK / UART3_nRTS / I2C1_SMBAL / I2C2_SCL /
UART1_TXD / LCD_SEG4
107
PH.9 / EBI_AD13 / QSPI0_SS / SC2_RST / I2S0_DO / SPI1_SS / UART3_nCTS / I2C1_SMBSUS / I2C2_SDA /
UART1_RXD / LCD_SEG3
108
PH.10 / EBI_AD14 / QSPI0_MISO1 / SC2_nCD / I2S0_LRCK / SPI1_I2SMCLK / UART4_TXD / UART0_TXD /
LCD_SEG2
109
110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / EPWM0_CH5 / LCD_SEG1
111 PD.14 / EBI_nCS0 / SPI3_I2SMCLK / SC1_nCD / USCI0_CTL0 / SPI0_I2SMCLK / EPWM0_CH4 / LCD_SEG0
112 VSS
113 Vsw
114 VDD
115 LDO_CAP
PB.15 / EADC0_CH15 / EBI_AD12 / SC1_PWR / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD /
I2C2_SMBAL / EPWM1_CH0 / TM0_EXT / USB_VBUS_EN
116
Dec. 25, 2020
Page 44 of 233
Rev. 1.00
Pin M2354KJFAE Pin Function
PB.14 / EADC0_CH14 / EBI_AD13 / SC1_RST / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD /
I2C2_SMBSUS / EPWM0_BRAKE1 / EPWM1_CH1 / TM1_EXT / CLKO / USB_VBUS_ST
117
118
119
PB.13 / EADC0_CH13 / DAC1_OUT / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SC1_DAT / SPI0_MISO / USCI0_DAT0 /
UART0_TXD / UART3_nRTS / I2C2_SCL / EPWM1_CH2 / TM2_EXT / TM4_EXT
PB.12 / EADC0_CH12 / DAC0_OUT / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SC1_CLK / SPI0_MOSI / USCI0_CLK /
UART0_RXD / UART3_nCTS / I2C2_SDA / SD0_nCD / EPWM1_CH3 / TM3_EXT / TM5_EXT
120 AVDD
121 VREF
122 AVSS
PB.11 / EADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / CAN0_TXD / SPI0_I2SMCLK /
BPWM1_CH0 / SPI3_CLK
123
124
125
126
127
128
PB.10 / EADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / CAN0_RXD /
BPWM1_CH1 / SPI3_SS
PB.9 / EADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / I2C1_SMBAL / I2C0_SCL /
BPWM1_CH2 / SPI3_MISO / INT7
PB.8 / EADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / I2C1_SMBSUS / I2C0_SDA /
BPWM1_CH3 / SPI3_MOSI / INT6
PB.7 / EADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / EPWM1_BRAKE0 /
EPWM1_CH4 / INT5 / USB_VBUS_ST / ACMP0_O
PB.6 / EADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / EPWM1_BRAKE1 /
EPWM1_CH5 / INT4 / USB_VBUS_EN / ACMP1_O
Table 4.1-2 M2354KJFAE Multi-function Pin Table
Dec. 25, 2020
Page 45 of 233
Rev. 1.00
4.2
M2354 Pin Mapping
Different part number with same package might has different function. Please refer to the selection
guide in section 3.2, Pin Configuration in section 4.1 or NuTool - PinConfigure.
Corresponding Part Number: M2354
M2354
Pin Name
PB.6
48 Pin
64 Pin
128 Pin
128
1
1
2
3
4
5
PB.5
1
2
3
4
PB.4
2
PB.3
3
PB.2
4
PC.12
PC.11
PC.10
PC.9
PB.1
5
6
7
8
5
6
6
7
9
PB.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
VDD
PA.11
PA.10
PA.9
7
8
8
9
9
10
11
PA.8
10
PC.13
PD.12
PD.11
PD.10
PG.2
PG.3
PG.4
PF.11
PF.10
PF.9
PF.8
PF.7
Dec. 25, 2020
Page 46 of 233
Rev. 1.00
PF.6
VBAT
11
12
13
14
15
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
PF.5
PF.4
PH.4
PH.5
PH.6
PH.7
PF.3
PF.2
VSS
12
13
14
15
16
17
VDD
PE.8
PE.9
PE.10
PE.11
PE.12
PE.13
PC.8
PC.7
PC.6
PA.7
PA.6
VSS
18
19
20
21
22
23
24
25
26
27
28
29
30
31
16
17
VDD
LDO_CAP
PA.5
PA.4
PA.3
PA.2
PA.1
PA.0
VDDIO
PE.14
18
19
20
21
22
23
24
Dec. 25, 2020
Page 47 of 233
Rev. 1.00
PE.15
nRESET
PF.0
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
25
26
27
32
33
34
PF.1
PD.9
PD.8
PC.5
PC.4
PC.3
PC.2
PC.1
PC.0
VSS
28
29
30
31
32
33
35
36
37
38
39
40
VDD
PG.9
PG.10
PG.11
PG.12
PG.13
PG.14
PG.15
PD.7
PD.6
PD.5
PD.4
PD.3
PD.2
PD.1
PD.0
VLCD
41
42
43
44
45
46
47
48
PA.12
PA.13
PA.14
PA.15
34
35
36
37
Dec. 25, 2020
Page 48 of 233
Rev. 1.00
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
VSS
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
38
49
VDD
PE.1
PE.0
PH.8
PH.9
PH.10
PH.11
PD.14
VSS
Vsw
39
40
41
42
43
44
45
46
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD
LDO_CAP
PB.15
PB.14
PB.13
PB.12
AVDD
VREF
AVSS
PB.11
PB.10
PB.9
PB.8
PB.7
47
48
Dec. 25, 2020
Page 49 of 233
Rev. 1.00
4.3
M2354 Pin Functional Description
Group
Pin Name
GPIO
PB.3
MFP
Type
A
Description
ACMP0_N
MFP1
Analog comparator 0 negative input pin.
PC.12
PC.1
PB.7
MFP14
MFP14
MFP15
MFP1
O
ACMP0_O
O
Analog comparator 0 output pin.
O
ACMP0
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_P3
ACMP0_WLAT
ACMP1_N
PA.11
PB.2
A
Analog comparator 0 positive input 0 pin.
Analog comparator 0 positive input 1 pin.
Analog comparator 0 positive input 2 pin.
Analog comparator 0 positive input 3 pin.
Analog comparator 0 window latch input pin
Analog comparator 1 negative input pin.
MFP1
A
PB.12
PB.13
PA.7
MFP1
A
MFP1
A
MFP13
MFP1
I
PB.5
A
PB.6
MFP15
MFP14
MFP14
MFP1
O
ACMP1_O
PC.11
PC.0
PA.10
PB.4
O
Analog comparator 1 output pin.
O
ACMP1
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
ACMP1_WLAT
A
Analog comparator 1 positive input 0 pin.
Analog comparator 1 positive input 1 pin.
Analog comparator 1 positive input 2 pin.
Analog comparator 1 positive input 3 pin.
Analog comparator 1 window latch input pin
MFP1
A
PB.12
PB.13
PA.6
MFP1
A
MFP1
A
MFP13
MFP9
I
PA.11
PA.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MFP12
MFP12
MFP13
MFP9
BPWM0_CH0
BPWM0_CH1
BPWM0 channel 0 output/capture input.
BPWM0 channel 1 output/capture input.
PG.14
PE.2
PA.10
PA.1
MFP12
MFP12
MFP13
MFP9
PG.13
PE.3
BPWM0
PA.9
PA.2
MFP12
MFP12
MFP13
MFP9
BPWM0_CH2
BPWM0_CH3
BPWM0 channel 2 output/capture input.
BPWM0 channel 3 output/capture input.
PG.12
PE.4
PA.8
PA.3
MFP12
Dec. 25, 2020
Page 50 of 233
Rev. 1.00
Group
Pin Name
GPIO
PG.11
PE.5
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
MFP12
MFP13
MFP9
PC.13
PF.5
MFP8
BPWM0_CH4
PA.4
MFP12
MFP12
MFP13
MFP9
BPWM0 channel 4 output/capture input.
PG.10
PE.6
PD.12
PF.4
MFP8
BPWM0_CH5
PA.5
MFP12
MFP12
MFP13
MFP11
MFP12
MFP12
MFP10
MFP11
MFP12
MFP12
MFP10
MFP12
MFP11
MFP10
MFP12
MFP11
MFP10
MFP12
MFP11
MFP10
MFP10
MFP12
MFP11
MFP4
BPWM0 channel 5 output/capture input.
PG.9
PE.7
PF.3
PC.7
PF.0
BPWM1_CH0
BPWM1_CH1
BPWM1 channel 0 output/capture input.
BPWM1 channel 1 output/capture input.
PB.11
PF.2
PC.6
PF.1
PB.10
PA.7
BPWM1_CH2
BPWM1_CH3
BPWM1_CH4
PA.12
PB.9
BPWM1 channel 2 output/capture input.
BPWM1 channel 3 output/capture input.
BPWM1 channel 4 output/capture input.
BPWM1
PA.6
PA.13
PB.8
PC.8
PA.14
PB.7
PB.6
BPWM1_CH5
CAN0_RXD
PE.13
PA.15
PD.10
BPWM1 channel 5 output/capture input.
CAN0 bus receiver input.
CAN0
Dec. 25, 2020
Page 51 of 233
Rev. 1.00
Group
Pin Name
GPIO
PA.4
MFP
MFP10
MFP4
MFP10
MFP6
MFP8
MFP4
MFP10
MFP4
MFP10
MFP6
MFP8
MFP13
MFP13
MFP14
MFP14
MFP1
MFP1
MFP14
MFP15
MFP1
MFP1
MFP14
MFP15
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
Type
I
Description
PE.15
PC.4
I
I
PA.13
PB.10
PD.11
PA.5
I
I
O
O
O
O
O
O
O
O
O
O
A
A
I
PE.14
PC.5
CAN0_TXD
CAN0 bus transmitter output.
PA.12
PB.11
PC.13
PD.12
PG.15
PB.14
PB.12
PB.12
PA.10
PA.0
CLKO
DAC0
DAC1
CLKO
Clock Out
DAC0_OUT
DAC0_ST
DAC1_OUT
DAC1_ST
DAC0 channel analog output.
DAC0 external trigger input.
DAC1 channel analog output.
DAC1 external trigger input.
I
PB.13
PB.13
PA.11
PA.1
A
A
I
I
EADC0_CH0
EADC0_CH1
EADC0_CH2
EADC0_CH3
EADC0_CH4
EADC0_CH5
EADC0_CH6
EADC0_CH7
EADC0_CH8
EADC0_CH9
PB.0
A
A
A
A
A
A
A
A
A
A
EADC0 channel 0 analog input.
EADC0 channel 1 analog input.
EADC0 channel 2 analog input.
EADC0 channel 3 analog input.
EADC0 channel 4 analog input.
EADC0 channel 5 analog input.
EADC0 channel 6 analog input.
EADC0 channel 7 analog input.
EADC0 channel 8 analog input.
EADC0 channel 9 analog input.
PB.1
PB.2
PB.3
PB.4
EADC0
PB.5
PB.6
PB.7
PB.8
PB.9
Dec. 25, 2020
Page 52 of 233
Rev. 1.00
Group
Pin Name
GPIO
PB.10
PB.11
PB.12
PB.13
PB.14
PB.15
PC.13
PD.12
PF.5
MFP
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP14
MFP14
MFP11
MFP15
MFP15
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
Type
A
Description
EADC0_CH10
EADC0_CH11
EADC0_CH12
EADC0_CH13
EADC0_CH14
EADC0_CH15
EADC0 channel 10 analog input.
EADC0 channel 11 analog input.
EADC0 channel 12 analog input.
EADC0 channel 13 analog input.
EADC0 channel 14 analog input.
EADC0 channel 15 analog input.
A
A
A
A
A
I
I
EADC0_ST
I
EADC0 external trigger input.
PC.1
I
PG.15
PC.0
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EBI_AD0
EBI_AD1
EBI_AD2
EBI_AD3
EBI_AD4
EBI_AD5
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
EBI_AD10
EBI address/data bus bit 0.
EBI address/data bus bit 1.
EBI address/data bus bit 2.
EBI address/data bus bit 3.
EBI address/data bus bit 4.
EBI address/data bus bit 5.
EBI address/data bus bit 6.
EBI address/data bus bit 7.
EBI address/data bus bit 8.
EBI address/data bus bit 9.
EBI address/data bus bit 10.
PG.9
PC.1
PG.10
PC.2
PG.11
PC.3
PG.12
PC.4
PG.13
PC.5
EBI
PG.14
PA.6
PD.8
PA.7
PD.9
PC.6
PE.14
PC.7
PE.15
PD.3
PE.1
Dec. 25, 2020
Page 53 of 233
Rev. 1.00
Group
Pin Name
GPIO
PD.2
PE.0
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
EBI_AD11
EBI address/data bus bit 11.
EBI address/data bus bit 12.
PD.1
PH.8
PB.15
PD.0
PH.9
PB.14
PH.10
PB.13
PH.11
PB.12
PB.5
EBI_AD12
EBI_AD13
EBI address/data bus bit 13.
EBI_AD14
EBI_AD15
EBI_ADR0
EBI_ADR1
EBI_ADR2
EBI_ADR3
EBI address/data bus bit 14.
EBI address/data bus bit 15.
EBI address bus bit 0.
EBI address bus bit 1.
EBI address bus bit 2.
EBI address bus bit 3.
PH.7
PB.4
O
O
PH.6
PB.3
O
O
PH.5
PB.2
O
O
PH.4
PC.12
PC.11
PC.10
PC.9
PB.1
O
EBI_ADR4
EBI_ADR5
EBI_ADR6
EBI_ADR7
EBI_ADR8
EBI_ADR9
O
EBI address bus bit 4.
EBI address bus bit 5.
EBI address bus bit 6.
EBI address bus bit 7.
EBI address bus bit 8.
EBI address bus bit 9.
O
O
O
O
PB.0
O
PC.13
PE.8
O
EBI_ADR10
EBI_ADR11
EBI address bus bit 10.
EBI address bus bit 11.
O
PG.2
PE.9
O
O
PG.3
PE.10
PG.4
O
EBI_ADR12
EBI_ADR13
EBI address bus bit 12.
EBI address bus bit 13.
O
O
Dec. 25, 2020
Page 54 of 233
Rev. 1.00
Group
Pin Name
GPIO
PE.11
PF.11
PE.12
PF.10
PE.13
PF.9
MFP
Type
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Description
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP7
MFP2
MFP2
MFP8
MFP8
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
EBI_ADR14
EBI_ADR15
EBI address bus bit 14.
EBI address bus bit 15.
EBI_ADR16
PC.8
PB.11
PF.8
EBI address bus bit 16.
EBI_ADR17
EBI_ADR18
EBI_ADR19
EBI_ALE
EBI address bus bit 17.
EBI address bus bit 18.
EBI address bus bit 19.
PB.10
PF.7
PB.9
PF.6
PB.8
PA.8
EBI address latch enable output pin.
EBI external clock output pin.
PE.2
PA.9
EBI_MCLK
PE.3
PD.12
PF.6
EBI_nCS0
PF.3
EBI chip select 0 output pin.
PD.14
PB.7
PB.6
EBI_nCS1
PD.11
PF.2
EBI chip select 1 output pin.
EBI_nCS2
EBI_nRD
PD.10
PA.11
PE.5
EBI chip select 2 output pin.
EBI read enable output pin.
PA.10
PE.4
EBI_nWR
EBI write enable output pin.
EBI_nWRH
EBI_nWRL
PB.6
EBI high byte write enable output pin
EBI low byte write enable output pin.
PB.7
Dec. 25, 2020
Page 55 of 233
Rev. 1.00
Group
Pin Name
GPIO
PA.10
PE.8
PA.9
PE.9
PA.8
PE.10
PC.10
PE.13
PC.11
PE.12
PC.12
PE.11
PB.1
PE.8
PB.0
PE.9
PB.14
PB.5
PF.5
MFP
Type
Description
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP13
MFP11
MFP13
MFP11
MFP13
MFP13
MFP11
MFP13
MFP11
MFP10
MFP11
MFP7
I
I
ECAP0_IC0
Enhanced capture unit 0 input 0 pin.
Enhanced capture unit 0 input 1 pin.
Enhanced capture unit 0 input 2 pin.
Enhanced capture unit 1 input 0 pin.
Enhanced capture unit 1 input 1 pin.
Enhanced capture unit 1 input 2 pin.
EPWM0 Brake 0 input pin.
I
ECAP0
ECAP0_IC1
ECAP0_IC2
ECAP1_IC0
ECAP1_IC1
ECAP1_IC2
EPWM0_BRAKE0
I
I
I
I
I
I
ECAP1
I
I
I
I
I
I
EPWM0_BRAKE1
I
EPWM0 Brake 1 input pin.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EPWM0_CH0
PE.8
PA.5
PE.7
PB.4
PF.4
MFP10
MFP13
MFP12
MFP11
MFP7
EPWM0 channel 0 output/capture input.
EPWM0
EPWM0_CH1
PE.9
PA.4
PE.6
PB.3
PE.10
PA.3
PE.5
PB.2
PE.11
MFP10
MFP13
MFP12
MFP11
MFP10
MFP13
MFP12
MFP11
MFP10
EPWM0 channel 1 output/capture input.
EPWM0_CH2
EPWM0_CH3
EPWM0 channel 2 output/capture input.
EPWM0 channel 3 output/capture input.
Dec. 25, 2020
Page 56 of 233
Rev. 1.00
Group
Pin Name
GPIO
PA.2
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
MFP13
MFP12
MFP11
MFP10
MFP13
MFP12
MFP11
MFP11
MFP10
MFP13
MFP12
MFP11
MFP12
MFP10
MFP9
PE.4
PB.1
PE.12
PA.1
EPWM0_CH4
EPWM0 channel 4 output/capture input.
PE.3
PD.14
PB.0
PE.13
PA.0
EPWM0_CH5
EPWM0 channel 5 output/capture input.
PE.2
PH.11
PA.15
PA.11
PF.5
EPWM0_SYNC_IN
EPWM0 counter synchronous trigger input pin.
O
EPWM0 counter synchronous trigger output
pin.
EPWM0_SYNC_OUT
O
PE.10
PB.7
MFP11
MFP11
MFP11
MFP11
MFP15
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
I
EPWM1_BRAKE0
EPWM1_BRAKE1
EPWM1 Brake 0 input pin.
EPWM1 Brake 1 input pin.
I
PB.6
I
PE.11
PA.3
I
I
PC.12
PE.13
PC.5
PB.15
PC.11
PC.8
PC.4
PB.14
PC.10
PC.7
PC.3
PB.13
PC.9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EPWM1_CH0
EPWM1_CH1
EPWM1 channel 0 output/capture input.
EPWM1 channel 1 output/capture input.
EPWM1 channel 2 output/capture input.
EPWM1
EPWM1_CH2
EPWM1_CH3
EPWM1 channel 3 output/capture input.
Dec. 25, 2020
Page 57 of 233
Rev. 1.00
Group
Pin Name
GPIO
PC.6
PC.2
PB.12
PB.1
PA.7
PC.1
PB.7
PB.6
PB.0
PA.6
PC.0
PB.5
PC.12
PF.3
PE.13
PA.5
PC.1
PD.7
PB.9
PB.4
PC.11
PF.2
PC.8
PA.4
PC.0
PD.6
PB.8
PG.2
PA.3
PC.3
PG.3
PA.2
PC.2
MFP
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP12
MFP12
MFP12
MFP11
MFP12
MFP6
MFP4
MFP4
MFP4
MFP9
MFP9
MFP4
MFP9
MFP6
MFP4
MFP4
MFP4
MFP9
MFP9
MFP4
MFP9
MFP4
MFP10
MFP9
MFP4
MFP10
MFP9
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
EPWM1_CH4
EPWM1_CH5
EPWM1 channel 4 output/capture input.
EPWM1 channel 5 output/capture input.
I2C0_SCL
I2C0 clock pin.
I2C0
I2C0_SDA
I2C0 data input/output pin.
I2C0_SMBAL
O
I2C0 SMBus SMBALTER pin
O
O
I2C0 SMBus SMBSUS pin (PMBus CONTROL
pin)
I2C0_SMBSUS
O
O
Dec. 25, 2020
Page 58 of 233
Rev. 1.00
Group
Pin Name
GPIO
PB.3
PB.1
PG.2
PA.7
PA.3
PF.0
PC.5
PD.5
PA.12
PE.1
PB.11
PB.2
PB.0
PG.3
PA.6
PA.2
PF.1
PC.4
PD.4
PA.13
PE.0
PB.10
PC.7
PH.8
PB.9
PC.6
PH.9
PB.8
PA.11
PA.1
PD.9
PD.1
PA.14
MFP
MFP12
MFP9
MFP5
MFP8
MFP9
MFP3
MFP9
MFP4
MFP4
MFP8
MFP7
MFP12
MFP9
MFP5
MFP8
MFP9
MFP3
MFP9
MFP4
MFP4
MFP8
MFP7
MFP8
MFP8
MFP7
MFP8
MFP8
MFP7
MFP7
MFP9
MFP3
MFP6
MFP6
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
I2C1_SCL
I2C1 clock pin.
I2C1
I2C1_SDA
I2C1 data input/output pin.
I2C1_SMBAL
O
I2C1 SMBus SMBALTER pin
O
O
I2C1 SMBus SMBSUS pin (PMBus CONTROL
pin)
I2C1_SMBSUS
O
O
I/O
I/O
I/O
I/O
I/O
I2C2
I2C2_SCL
I2C2 clock pin.
Dec. 25, 2020
Page 59 of 233
Rev. 1.00
Group
Pin Name
GPIO
PH.8
MFP
MFP9
MFP8
MFP7
MFP9
MFP3
MFP6
MFP6
MFP9
MFP8
MFP8
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
PB.13
PA.10
PA.0
PD.8
I2C2_SDA
PD.0
I2C2 data input/output pin.
PA.15
PH.9
PB.12
PB.15
I2C2_SMBAL
I2C2 SMBus SMBALTER pin
I2C2 SMBus SMBSUS pin (PMBus CONTROL
pin)
I2C2_SMBSUS
PB.14
MFP8
O
PB.5
PF.10
PE.8
PC.4
PA.12
PE.1
PB.3
PF.8
MFP10
MFP4
MFP4
MFP6
MFP2
MFP5
MFP10
MFP4
MFP4
MFP6
MFP2
MFP5
MFP10
MFP4
MFP4
MFP6
MFP2
MFP5
MFP10
MFP4
MFP4
MFP6
O
O
O
O
O
O
I
I2S0_BCLK
I2S0 bit clock output pin.
I
PE.10
PC.2
PA.14
PH.8
PB.2
PF.7
I
I2S0_DI
I2S0 data input pin.
I
I
I2S0
I
O
O
O
O
O
O
O
O
O
O
PE.11
PC.1
PA.15
PH.9
PB.1
PF.6
I2S0_DO
I2S0 data output pin.
I2S0_LRCK
I2S0 left right channel clock output pin.
PE.12
PC.0
Dec. 25, 2020
Page 60 of 233
Rev. 1.00
Group
Pin Name
GPIO
PH.10
PB.4
PF.9
MFP
MFP5
MFP10
MFP4
MFP4
MFP6
MFP2
MFP5
Type
O
Description
O
O
PE.9
PC.3
PA.13
PE.0
O
I2S0_MCLK
I2S0 master clock output pin.
Serial wired debugger clock pin.
O
O
O
ICE_CLK
ICE_DAT
PF.1
PF.0
MFP14
MFP14
I
Note: It is recommended to use 100 kΩ pull-up
resistor on ICE_CLK pin.
ICE
Serial wired debugger data pin.
I/O
Note: It is recommended to use 100 kΩ pull-up
resistor on ICE_DAT pin.
PB.5
PA.6
PB.4
PA.7
PB.3
PC.6
PB.2
PC.7
PB.6
PA.8
PD.12
PB.7
PD.11
PB.8
PD.10
PB.9
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP13
MFP15
MFP15
MFP13
MFP15
MFP13
MFP15
MFP13
MFP13
MFP13
MFP15
MFP15
MFP15
MFP15
I
I
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
External interrupt 0 input pin.
External interrupt 1 input pin.
External interrupt 2 input pin.
External interrupt 3 input pin.
External interrupt 4 input pin.
External interrupt 5 input pin.
External interrupt 6 input pin.
External interrupt 7 input pin.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LCD_COM0
A
A
A
A
A
A
LCD common 0 output pin
LCD common 1 output pin
LCD common 2 output pin
LCD common 3 output pin
LCD common 4 output pin
LCD common 5 output pin
LCD_COM1
LCD_COM2
LCD
LCD_COM3
LCD_COM4/SEG43
LCD_COM5/SEG42
Dec. 25, 2020
Page 61 of 233
Rev. 1.00
Group
Pin Name
GPIO
PD.8
PD.9
PD.14
PH.11
PH.10
PH.9
PH.8
PE.0
MFP
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Description
LCD_COM6/SEG41
LCD_COM7/SEG40
LCD_SEG0
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP13
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP11
MFP11
MFP11
MFP11
MFP15
MFP15
MFP15
LCD common 6 output pin
LCD common 7 output pin
LCD segment 0 output pin
LCD segment 1 output pin
LCD segment 2 output pin
LCD segment 3 output pin
LCD segment 4 output pin
LCD segment 5 output pin
LCD segment 6 output pin
LCD segment 7 output pin
LCD segment 8 output pin
LCD segment 9 output pin
LCD segment 10 output pin
LCD segment 11 output pin
LCD segment 12 output pin
LCD segment 13 output pin
LCD segment 14 output pin
LCD segment 15 output pin
LCD segment 16 output pin
LCD segment 17 output pin
LCD segment 18 output pin
LCD segment 19 output pin
LCD segment 20 output pin
LCD segment 21 output pin
LCD segment 22 output pin
LCD segment 23 output pin
LCD segment 24 output pin
LCD segment 25 output pin
LCD segment 26 output pin
LCD segment 27 output pin
LCD segment 28 output pin
LCD segment 29 output pin
LCD segment 30 output pin
LCD_SEG1
LCD_SEG2
LCD_SEG3
LCD_SEG4
LCD_SEG5
LCD_SEG6
PE.1
LCD_SEG7
PE.2
LCD_SEG8
PE.3
LCD_SEG9
PE.4
LCD_SEG10
LCD_SEG11
LCD_SEG12
LCD_SEG13
LCD_SEG14
LCD_SEG15
LCD_SEG16
LCD_SEG17
LCD_SEG18
LCD_SEG19
LCD_SEG20
LCD_SEG21
LCD_SEG22
LCD_SEG23
LCD_SEG24
LCD_SEG25
LCD_SEG26
LCD_SEG27
LCD_SEG28
LCD_SEG29
LCD_SEG30
PE.5
PE.6
PE.7
PD.6
PD.7
PG.15
PG.14
PG.13
PG.12
PG.11
PG.10
PG.9
PE.15
PE.14
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PE.10
Dec. 25, 2020
Page 62 of 233
Rev. 1.00
Group
Pin Name
GPIO
PE.9
PE.8
PH.7
PH.6
PH.5
PH.4
PG.4
PG.3
PG.2
PD.11
PA.4
PE.3
PD.10
PA.3
PE.2
PD.12
PA.5
PE.4
PA.9
PA.13
PE.6
PA.8
PA.14
PE.5
PA.10
PA.12
PE.7
PF.2
PA.2
PC.2
PH.8
PA.1
PC.1
MFP
Type
Description
LCD_SEG31
LCD_SEG32
LCD_SEG33
LCD_SEG34
LCD_SEG35
LCD_SEG36
LCD_SEG37
LCD_SEG38
LCD_SEG39
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP10
MFP14
MFP11
MFP10
MFP14
MFP11
MFP10
MFP14
MFP11
MFP10
MFP12
MFP11
MFP10
MFP12
MFP11
MFP10
MFP12
MFP11
MFP5
A
LCD segment 31 output pin
LCD segment 32 output pin
LCD segment 33 output pin
LCD segment 34 output pin
LCD segment 35 output pin
LCD segment 36 output pin
LCD segment 37 output pin
LCD segment 38 output pin
LCD segment 39 output pin
A
A
A
A
A
A
A
A
I
QEI0_A
I
Quadrature encoder 0 phase A input
Quadrature encoder 0 phase B input
Quadrature encoder 0 index input
Quadrature encoder 1 phase A input
Quadrature encoder 1 phase B input
Quadrature encoder 1 index input
I
I
QEI0
QEI0_B
I
I
I
QEI0_INDEX
QEI1_A
I
I
I
I
I
I
QEI1
QEI1_B
I
I
I
QEI1_INDEX
I
I
I/O
I/O
I/O
I/O
I/O
I/O
MFP3
QSPI0_CLK
Quad SPI0 serial clock pin.
MFP4
QSPI0
MFP3
MFP3
QSPI0_MISO0
Quad SPI0 MISO0 (Master In, Slave Out) pin.
MFP4
Dec. 25, 2020
Page 63 of 233
Rev. 1.00
Group
Pin Name
GPIO
PE.1
PB.1
PA.5
PC.5
PH.10
PA.0
PC.0
PE.0
PB.0
PA.4
PC.4
PH.11
PA.3
PC.3
PH.9
PB.5
PF.6
PA.0
PE.2
PB.4
PF.7
PA.1
PE.3
PB.2
PF.9
PA.3
PE.5
PB.3
PF.8
PA.2
PE.4
PC.12
PF.10
MFP
MFP3
MFP15
MFP3
MFP4
MFP3
MFP3
MFP4
MFP3
MFP15
MFP3
MFP4
MFP3
MFP3
MFP4
MFP3
MFP9
MFP3
MFP6
MFP6
MFP9
MFP3
MFP6
MFP6
MFP9
MFP3
MFP6
MFP6
MFP9
MFP3
MFP6
MFP6
MFP9
MFP3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
QSPI0_MISO1
QSPI0_MOSI0
QSPI0_MOSI1
QSPI0_SS
Quad SPI0 MISO1 (Master In, Slave Out) pin.
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
Quad SPI0 slave select pin.
O
SC0_CLK
Smart Card 0 clock pin.
O
O
I/O
I/O
I/O
I/O
O
SC0_DAT
SC0_PWR
Smart Card 0 data pin.
Smart Card 0 power pin.
Smart Card 0 reset pin.
SC0
O
O
O
O
O
SC0_RST
SC0_nCD
O
O
I
Smart Card 0 card detect pin.
I
Dec. 25, 2020
Page 64 of 233
Rev. 1.00
Group
Pin Name
GPIO
PA.4
PE.6
PC.0
PD.4
PB.12
PC.1
PD.5
PB.13
PC.3
PD.7
PB.15
PC.2
PD.6
PB.14
PC.4
PD.3
PD.14
PA.8
PA.6
PD.0
PA.15
PE.0
PA.9
PA.7
PD.1
PA.14
PE.1
PA.11
PC.7
PD.3
PA.12
PH.8
PA.10
MFP
Type
I
Description
MFP6
MFP6
MFP5
MFP8
MFP3
MFP5
MFP8
MFP3
MFP5
MFP8
MFP3
MFP5
MFP8
MFP3
MFP5
MFP8
MFP4
MFP3
MFP6
MFP7
MFP7
MFP4
MFP3
MFP6
MFP7
MFP7
MFP4
MFP3
MFP6
MFP7
MFP7
MFP4
MFP3
I
O
SC1_CLK
SC1_DAT
SC1_PWR
SC1_RST
SC1_nCD
O
Smart Card 1 clock pin.
Smart Card 1 data pin.
O
I/O
I/O
I/O
O
SC1
O
Smart Card 1 power pin.
Smart Card 1 reset pin.
O
O
O
O
I
I
Smart Card 1 card detect pin.
I
O
O
SC2_CLK
O
Smart Card 2 clock pin.
O
O
I/O
I/O
I/O
I/O
I/O
O
SC2_DAT
Smart Card 2 data pin.
SC2
O
SC2_PWR
SC2_RST
O
Smart Card 2 power pin.
Smart Card 2 reset pin.
O
O
O
Dec. 25, 2020
Page 65 of 233
Rev. 1.00
Group
Pin Name
GPIO
PC.6
PD.2
PA.13
PH.9
PC.13
PA.5
PH.10
PB.1
PE.6
PB.0
PE.7
PB.2
PE.2
PB.3
PE.3
PB.4
PE.4
PB.5
PE.5
PB.12
PF.8
PA.2
PD.2
PB.14
PB.0
PF.10
PA.4
PD.14
PB.11
PF.7
PA.1
PD.1
PB.13
MFP
Type
O
Description
MFP6
MFP7
MFP7
MFP4
MFP3
MFP6
MFP4
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP9
MFP5
MFP4
MFP4
MFP4
MFP8
MFP5
MFP4
MFP6
MFP9
MFP5
MFP4
MFP4
MFP4
O
O
O
I
SC2_nCD
I
Smart Card 2 card detect pin.
I
O
SD0_CLK
SD0_CMD
SD0_DAT0
SD0_DAT1
SD0_DAT2
SD/SDIO0 clock output pin
SD/SDIO0 command/response pin
SD/SDIO0 data line bit 0.
SD/SDIO0 data line bit 1.
SD/SDIO0 data line bit 2.
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
SD0
SD0_DAT3
SD0_nCD
SD/SDIO0 data line bit 3.
SD/SDIO0 card detect input pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPI0_CLK
SPI0 serial clock pin.
SPI0
SPI0_I2SMCLK
SPI0 I2S master clock output pin
SPI0_MISO
SPI0 MISO (Master In, Slave Out) pin.
Dec. 25, 2020
Page 66 of 233
Rev. 1.00
Group
Pin Name
GPIO
PF.6
PA.0
PD.0
PB.12
PF.9
PA.3
PD.3
PB.15
PB.3
PH.6
PA.7
PC.1
PD.5
PH.8
PB.1
PA.5
PC.4
PH.10
PB.5
PH.4
PC.7
PC.3
PD.7
PE.1
PB.4
PH.5
PC.6
PC.2
PD.6
PE.0
PB.2
PH.7
PA.6
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
MFP5
MFP4
MFP4
MFP4
MFP5
MFP4
MFP4
MFP4
MFP5
MFP3
MFP4
MFP7
MFP5
MFP6
MFP5
MFP4
MFP7
MFP6
MFP5
MFP3
MFP4
MFP7
MFP5
MFP6
MFP5
MFP3
MFP4
MFP7
MFP5
MFP6
MFP5
MFP3
MFP4
SPI0_MOSI
SPI0 MOSI (Master Out, Slave In) pin.
SPI0_SS
SPI0 slave select pin.
SPI1_CLK
SPI1 serial clock pin.
SPI1_I2SMCLK
SPI1 I2S master clock output pin
SPI1
SPI1_MISO
SPI1 MISO (Master In, Slave Out) pin.
SPI1_MOSI
SPI1 MOSI (Master Out, Slave In) pin.
SPI1_SS
SPI1 slave select pin.
Dec. 25, 2020
Page 67 of 233
Rev. 1.00
Group
Pin Name
GPIO
PC.0
MFP
MFP7
MFP5
MFP6
MFP4
MFP3
MFP5
MFP5
MFP4
MFP4
MFP5
MFP4
MFP3
MFP5
MFP5
MFP4
MFP3
MFP5
MFP5
MFP4
MFP3
MFP5
MFP5
MFP6
MFP5
MFP11
MFP6
MFP9
MFP5
MFP3
MFP6
MFP5
MFP11
MFP6
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
PD.4
PH.9
PA.10
PG.3
PE.8
SPI2_CLK
SPI2 serial clock pin.
PA.13
PB.0
SPI2_I2SMCLK
SPI2_MISO
PC.13
PE.12
PA.9
SPI2 I2S master clock output pin
PG.4
PE.9
SPI2 MISO (Master In, Slave Out) pin.
SPI2
PA.14
PA.8
PF.11
PE.10
PA.15
PA.11
PG.2
PE.11
PA.12
PC.10
PE.4
SPI2_MOSI
SPI2 MOSI (Master Out, Slave In) pin.
SPI2_SS
SPI2 slave select pin.
SPI3_CLK
SPI3 serial clock pin.
PB.11
PB.1
PF.6
SPI3_I2SMCLK
SPI3 I2S master clock output pin
SPI3
PE.6
PD.14
PC.12
PE.3
SPI3_MISO
SPI3_MOSI
SPI3 MISO (Master In, Slave Out) pin.
SPI3 MOSI (Master Out, Slave In) pin.
PB.9
PC.11
Dec. 25, 2020
Page 68 of 233
Rev. 1.00
Group
Pin Name
GPIO
PE.2
PB.8
PC.9
PE.5
PB.10
PF.6
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
MFP5
MFP11
MFP6
SPI3_SS
MFP5
SPI3 slave select pin.
MFP11
MFP10
MFP10
MFP10
MFP10
MFP10
MFP10
MFP14
MFP13
MFP14
MFP13
MFP13
MFP14
MFP13
MFP14
MFP13
MFP13
MFP14
MFP13
MFP14
MFP14
MFP13
MFP13
MFP14
MFP13
MFP14
MFP13
MFP13
MFP13
TAMPER0
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
TAMPER0
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
TAMPER detector loop pin 0.
TAMPER detector loop pin 1.
TAMPER detector loop pin 2.
TAMPER detector loop pin 3.
TAMPER detector loop pin 4.
TAMPER detector loop pin 5.
PF.7
PF.8
PF.9
PF.10
PF.11
PB.5
PG.2
PC.7
PA.11
PB.15
PB.4
PG.3
PC.6
PA.10
PB.14
PB.3
PG.4
PA.7
PD.0
PA.9
PB.13
PB.2
PF.11
PA.6
PA.8
PB.12
PB.3
TM0
Timer0 event counter input/toggle output pin.
TM0
Timer0 external capture input/toggle output
pin.
TM0_EXT
TM1
Timer1 event counter input/toggle output pin.
TM1
Timer1 external capture input/toggle output
pin.
TM1_EXT
TM2
Timer2 event counter input/toggle output pin.
TM2
Timer2 external capture input/toggle output
pin.
TM2_EXT
TM3
Timer3 event counter input/toggle output pin.
TM3
TM4
Timer3 external capture input/toggle output
pin.
TM3_EXT
TM4
Timer4 event counter input/toggle output pin.
Dec. 25, 2020
Page 69 of 233
Rev. 1.00
Group
Pin Name
GPIO
PG.4
PA.7
PA.9
PB.13
PB.2
PF.11
PA.6
PA.8
PB.12
PE.12
PE.11
PE.10
PE.9
PE.8
PC.11
PF.2
MFP
MFP12
MFP10
MFP12
MFP14
MFP13
MFP12
MFP10
MFP12
MFP14
MFP14
MFP14
MFP14
MFP14
MFP14
MFP3
MFP3
MFP7
MFP11
MFP7
MFP4
MFP9
MFP3
MFP8
MFP6
MFP5
MFP3
MFP3
MFP7
MFP11
MFP7
MFP4
MFP9
MFP3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
Description
Timer4 external capture input/toggle output
pin.
TM4_EXT
TM5
Timer5 event counter input/toggle output pin.
TM5
Timer5 external capture input/toggle output
pin.
TM5_EXT
TRACE_CLK
ETM Trace Clock output pin
ETM Trace Data 0 output pin
ETM Trace Data 1 output pin
ETM Trace Data 2 output pin
ETM Trace Data 3 output pin
TRACE_DATA0
TRACE_DATA1
TRACE_DATA2
TRACE_DATA3
TRACE
I
PA.6
PA.4
PA.0
PF.1
I
I
I
UART0_RXD
I
UART0 data receiver input pin.
PD.2
PA.15
PH.11
PB.12
PB.8
PC.12
PF.3
I
I
I
UART0
I
I
O
O
O
O
O
O
O
O
PA.7
PA.5
PA.1
PF.0
UART0_TXD
UART0 data transmitter output pin.
PD.3
PA.14
Dec. 25, 2020
Page 70 of 233
Rev. 1.00
Group
Pin Name
GPIO
PH.10
PB.13
PB.9
PC.7
PA.5
PB.15
PB.11
PC.6
PA.4
PB.14
PB.10
PB.6
PB.2
PA.8
PD.10
PC.8
PA.2
PF.1
MFP
MFP8
MFP6
MFP5
MFP7
MFP7
MFP6
MFP5
MFP7
MFP7
MFP6
MFP5
MFP6
MFP6
MFP7
MFP3
MFP8
MFP8
MFP2
MFP3
MFP10
MFP6
MFP7
MFP3
MFP8
MFP8
MFP2
MFP3
MFP10
MFP6
MFP8
MFP8
MFP6
MFP8
Type
Description
O
O
O
I
I
UART0_nCTS
UART0_nRTS
UART0 clear to Send input pin.
I
I
O
O
O
O
I
UART0 request to Send output pin.
I
I
I
UART1_RXD
I
UART1 data receiver input pin.
I
I
PD.6
PH.9
PB.3
PA.9
PD.11
PE.13
PA.3
PF.0
I
I
O
O
O
O
O
O
O
O
O
I
UART1
UART1_TXD
UART1 data transmitter output pin.
PD.7
PH.8
PB.7
PE.11
PA.1
PB.9
PE.12
UART1_nCTS
UART1_nRTS
I
UART1 clear to Send input pin.
I
O
UART1 request to Send output pin.
Dec. 25, 2020
Page 71 of 233
Rev. 1.00
Group
Pin Name
GPIO
PA.0
PB.8
PB.4
PB.0
PD.12
PF.5
PE.9
PE.15
PC.4
PC.0
PB.5
PB.1
PC.13
PF.4
PE.8
PE.14
PC.5
PC.1
PF.5
PD.9
PC.2
PF.4
PD.8
PC.3
PC.9
PE.11
PC.2
PD.0
PE.0
PB.14
PC.10
PE.10
PC.3
MFP
MFP8
MFP6
MFP12
MFP7
MFP7
MFP2
MFP7
MFP3
MFP8
MFP8
MFP12
MFP7
MFP7
MFP2
MFP7
MFP3
MFP8
MFP8
MFP4
MFP4
MFP8
MFP4
MFP4
MFP8
MFP7
MFP7
MFP11
MFP5
MFP7
MFP7
MFP7
MFP7
MFP11
Type
Description
O
O
I
I
I
I
UART2_RXD
UART2 data receiver input pin.
I
I
I
I
O
O
O
O
O
O
O
O
I
UART2
UART2_TXD
UART2 data transmitter output pin.
UART2_nCTS
UART2_nRTS
I
UART2 clear to Send input pin.
I
O
O
O
I
UART2 request to Send output pin.
I
I
UART3_RXD
UART3 data receiver input pin.
I
UART3
I
I
O
O
O
UART3_TXD
UART3 data transmitter output pin.
Dec. 25, 2020
Page 72 of 233
Rev. 1.00
Group
Pin Name
GPIO
PD.1
PE.1
MFP
MFP5
MFP7
MFP7
MFP5
MFP7
MFP7
MFP5
MFP7
MFP7
MFP6
MFP5
MFP7
MFP11
MFP3
MFP7
MFP6
MFP6
MFP5
MFP7
MFP11
MFP3
MFP7
MFP6
MFP5
MFP9
MFP5
MFP9
MFP7
MFP6
MFP8
MFP8
MFP7
MFP6
Type
Description
O
O
O
I
PB.15
PD.2
PH.9
PB.12
PD.3
PH.8
PB.13
PF.6
UART3_nCTS
UART3_nRTS
I
UART3 clear to Send input pin.
I
O
O
O
I
UART3 request to Send output pin.
PC.6
PA.2
I
I
UART4_RXD
PC.4
PA.13
PH.11
PB.10
PF.7
I
UART4 data receiver input pin.
I
I
I
O
O
O
O
O
O
O
I
PC.7
PA.3
UART4
UART4_TXD
PC.5
PA.12
PH.10
PB.11
PC.8
PE.1
UART4 data transmitter output pin.
UART4_nCTS
UART4_nRTS
UART4 clear to Send input pin.
I
PE.13
PE.0
O
O
I
UART4 request to Send output pin.
PB.4
PF.10
PA.4
I
UART5_RXD
UART5_TXD
UART5 data receiver input pin.
I
UART5
PE.6
I
PB.5
O
O
UART5 data transmitter output pin.
PF.11
Dec. 25, 2020
Page 73 of 233
Rev. 1.00
Group
Pin Name
GPIO
PA.5
MFP
MFP8
MFP8
MFP7
MFP6
MFP7
MFP6
MFP14
MFP14
MFP14
MFP14
MFP14
MFP14
MFP14
MFP15
MFP14
MFP6
MFP3
MFP7
MFP5
MFP6
MFP3
MFP7
MFP5
MFP6
MFP3
MFP7
MFP5
MFP6
MFP3
MFP7
MFP5
MFP6
MFP3
Type
O
Description
PE.7
O
PB.2
I
UART5_nCTS
UART5_nRTS
UART5 clear to Send input pin.
PF.8
I
PB.3
O
UART5 request to Send output pin.
PF.9
O
USB_D+
PA.14
PA.13
PA.15
PA.12
PB.6
A
USB differential signal D+.
USB differential signal D-.
USB_ identification.
USB_D-
A
USB_OTG_ID
USB_VBUS
I
P
Power supply from USB host or HUB.
USB
O
USB_VBUS_EN
USB external VBUS regulator enable pin.
USB external VBUS regulator status pin.
PB.15
PD.4
PB.14
PB.7
O
I
USB_VBUS_ST
I
I
PA.11
PD.0
PE.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
USCI0_CLK
USCI0_CTL0
USCI0_CTL1
USCI0 clock pin.
PB.12
PC.13
PD.4
PE.6
USCI0 control 0 pin.
PD.14
PA.8
USCI0
PD.3
PE.5
USCI0 control 1 pin.
PB.15
PA.10
PD.1
PE.3
USCI0_DAT0
USCI0_DAT1
USCI0 data 0 pin.
USCI0 data 1 pin.
PB.13
PA.9
PD.2
Dec. 25, 2020
Page 74 of 233
Rev. 1.00
Group
Pin Name
GPIO
PE.4
PB.14
PB.1
PE.12
PD.7
PB.8
PB.5
PE.9
PD.3
PB.10
PB.4
PE.8
PD.4
PB.9
PB.2
PE.10
PD.5
PB.7
PB.6
PB.3
PE.11
PD.6
PF.5
PF.4
MFP
MFP7
MFP5
MFP8
MFP6
MFP6
MFP4
MFP8
MFP6
MFP6
MFP4
MFP8
MFP6
MFP6
MFP4
MFP8
MFP6
MFP6
MFP4
MFP4
MFP8
MFP6
MFP6
MFP10
MFP10
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
USCI1_CLK
USCI1_CTL0
USCI1_CTL1
USCI1_DAT0
USCI1_DAT1
USCI1 clock pin.
USCI1 control 0 pin.
USCI1 control 1 pin.
USCI1 data 0 pin.
USCI1 data 1 pin.
USCI1
X32_IN
External 32.768 kHz crystal input pin.
External 32.768 kHz crystal output pin.
X32
XT1
X32_OUT
O
External 4~24 MHz (high speed) crystal input
pin.
XT1_IN
PF.3
PF.2
MFP10
MFP10
I
External 4~24 MHz (high speed) crystal output
pin.
XT1_OUT
O
Dec. 25, 2020
Page 75 of 233
Rev. 1.00
5 BLOCK DIAGRAM
Memory
TrustZone
Security
Timer/PWM
Analog Interface
Arm®
APROM 1024 KB
(Dual Bank)
Secure Boot
ROM (S) 32 KB
IDAU
TRNG (APB)
Timer with PWM x4
12-bit ADC 16-ch
12-bit DAC x2
Cortex®
SHA/ ECC/ AES/
RSA/HMAC/SM2-4
Tamper pins
(APB)
SRAM 256 KB
WDT/WDT (S)
WWDT/WWDT (S)
SAU
FMC
SCU
M23
Voltage/Clock
Monitor
LDROM 16 KB
Up to
Key Store (S)
Comparator x2
PWM x24
96 MHz
Data Flash 8 KB
Life Cycle Control
Secure Debug
Temperature Sensor x1
USB 2.0 FS PHY
RTC (VBAT) (S)
OTP 3 KB
eXecute-Only Memory (XOM)
Bridge
AHB
Clock Control
APB
Connectivity / GPIO
Power Control
Connectivity / GPIO
MIRC 4 MHz
UART x6
I2C x3
CAN x1
VREF
SD Host x1
1.6V/ 2V/ 2.5V/ 3V
ISO-7816 x3
Input Capture x2
HIRC 12/48 MHz
LIRC 32 kHz
USB 2.0 FS Host/
Device/ FS OTG
PDMA0 (S)
8-ch
PDMA1
8-ch
POR/ LVR/ BOD
SPI (Quad) x1
I2S x1
QEI x2
CPU core LDO
1.26/ 1.2/1.1/0.9V
PLL 200 MHz
HXT 4~24 MHz
LXT 32.768 kHz
External Interrupt
(SPI/ I2S) x4
Tamper detect x6
DC-to-DC
1.26/ 1.2/1.1/0.9V
USCI x2
Voltage Adjustment
Interface (VAI) x6
External Bus Interface
(UART/ SPI/ I2S)
(S): Dedicated Secure World
Figure 5-1 M2354 Block Diagram
Dec. 25, 2020
Page 76 of 233
Rev. 1.00
6 FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M23 Core
The NuMicro® M2354 series is embedded with the Cortex® -M23 processor. The Cortex® -M23
processor is a low gate count, two-stage, and highly energy efficient 32-bit RISC processor, which has
an AMBA AHB5 interface supporting Arm® TrustZone® technology, a debug access port supporting
serial wire debug and single-cycle I/O ports. It has an NVIC component and MPU for memory-
protection functionality. The processor also supports Security Extension.Figure Figure 6.1-1 shows the
functional controller of the processor.
MTB AHB
Cortex-M23 processor
Micro Trace
Buffer
(MTB)
MTB
SRAM
interface
Cross
Trigger
Interface
(CTI)
Wakeup
Interrupt
Controller
(WIC)
Nested
Vectored
Interrupt
(NVIC)
Cortex-M23
processor
core
APB
IRQ and power
control interface
Embedded
Trace
Macrocell
(ETM)
ETM
ATB
interface
Memory Protection
Implementation
Defined Attribution
Unit (IDAU)
Security
Attribution
Unit (SAU)
Data
Watchpoint
and Trace
(DWT)
Flash Patch
and
Breakpoint Unit
(FPB)*
Secure
Memory
Protection Unit
(MPU_S)
Non-secure
Memory
Protection Unit
(MPU_NS)
Slave
AHB
interface
Bus matrix
Processor
ROM
table
Single-cycle
I/O port
AHB Master
Configurable
Optional
* Flash Patching is not supported in the Cortex-M23 processor.
Figure 6.1-1 Cortex® -M23 Block Diagram
Dec. 25, 2020
Page 77 of 233
Rev. 1.00
Cortex® -M23 processor features:
Arm® v8-M Baseline architecture.
Arm® v8-M Baseline Thumb® -2 instruction set that combines high code density with 32-bit
performance.
Support for single-cycle I/O access.
Power control optimization of system components.
Integrated sleep modes for low power consumption.
Optimized code fetching for reduced Flash and ROM power consumption.
A 32-bit Single cycle Hardware multiplier.
A 32-bit Hardware divider.
Deterministic, high-performance interrupt handling for time-critical applications.
Deterministic instruction cycle timing.
Support for system level debug authentication.
Support for Arm® Debug Interface Architecture ADIv5.1 Serial Wire Debug (SWD).
ETM for instruction trace.
Separated privileged and unprivileged modes.
Security Extension supporting a Secure and a Non-secure state.
Protected Memory System Architecture (PMSAv8) Memory Protection Units (MPUs) for
both Secure and Non-secure states.
Security Attribution Unit (SAU).
SysTick timers for both Secure and Non-secure states.
A Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor with
up to 240 interrupts.
Dec. 25, 2020
Page 78 of 233
Rev. 1.00
6.2 System Manager
6.2.1
Overview
System management includes the following sections:
System Reset
System Power Distribution
SRAM Memory Organization
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.2.2
Reset
The system reset can be issued by one of the events listed below. These reset event flags can be read
from SYS_RSTSTS register to determine the reset source. Hardware reset source are from peripheral
signals. Software reset can trigger reset through setting control registers.
Hardware Reset Sources
– Power-on Reset (POR)
– Low level on the nRESET pin
– Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
– Low Voltage Reset (LVR)
– Brown-out Detector Reset (BOD Reset)
– CPU Lockup Reset
Software Reset Sources
– CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
– System Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
– CPU Reset for Cortex® -M23 core only by writing 1 to CPURST (SYS_IPRST0[1])
Dec. 25, 2020
Page 79 of 233
Rev. 1.00
Glitch Filter
32 us
nRESET
VDD
~50k ohm
@3.3v
PORMASK(SYS_PORCTL0[15:0])
Power-on
Reset
POROFF(SYS_PORCTL1[15:0])
LVREN(SYS_BODCTL[7])
Reset Pulse Width
~3.2ms
Low Voltage
Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
System Reset
SYSRESETREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M23 only; the other reset sources will reset Cortex® -M23 and all peripherals. However, there
are small differences between each reset source and they are listed in Table 6.2-1.
Reset Sources
POR
NRESET
WDT
LVR
BOD
Lockup
CHIP
SYSTEM
CPU
Register
SYS_RSTSTS
Bit 0 = 1
0x0
Bit 1 = 1
-
Bit 2 = 1
-
Bit 3 = 1
-
Bit 4 = 1
-
Bit 8 = 1
-
Bit 0 = 1
-
Bit 5 = 1
-
Bit 7 = 1
-
CHIPRST
(SYS_IPRST0[0])
HCLKSEL
0x5
0x5
0x5
0x5
0x5
0x6
0x5
0x6
-
-
-
-
(CLK_CLKSEL0[2:0]) HIRC48
HIRC48
HIRC48
HIRC48
HIRC48
MIRC
HIRC48
MIRC
HCLKDIV
0x0
0x0
0x0
0x0
0x0
0x3
0x0
0x3
(CLK_CLKDIV0[3:0])
PLSTATUS
0x2
0x2
0x2
0x2
0x2
-
-
0x2
-
-
(SYS_PLSTS[9:8])
PL2
PL2
PL2
PL2
PL2
PL2
CURMVR
0x0
-
-
-
-
-
(SYS_PLSTS[12])
LDO
Dec. 25, 2020
Page 80 of 233
Rev. 1.00
Reset Sources
Register
POR
NRESET
WDT
LVR
BOD
Lockup
CHIP
SYSTEM
CPU
BODEN
Reload
from
Reload
from
Reload
from
Reload
from
-
Reload
from
Reload
from
Reload
from
-
(SYS_BODCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[18:1
6])
BODRSTEN
(SYS_BODCTL[3])
SYS_SRAMPC0
KS
0x0
0x0
-
-
-
-
-
-
-
-
-
-
-
0x0
0x0
0x0
0x0
0x2
-
0x0
(SYS_SRAMPC1[29:
28])
RSA
0x2
0x2
-
0x2
-
0x2
-
-
-
0x2
-
-
-
-
-
(SYS_SRAMPC1[27:
26])
SYS_SRAMPC1
0x0800_0
000
expect
[29:28])
KS(bit
and
RSA(bit[27:26])
LXTEN
0x0
0x1
0x3
0x0
0x0
0x0
0x0
0x0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_PWRCTL[1])
WDTCKEN
-
0x1
-
-
-
0x1
-
(CLK_APBCLK0[0])
WDTSEL
0x3
0x0
-
-
-
(CLK_CLKSEL1[1:0])
HXTSTB
0x0
-
0x0
-
0x0
-
(CLK_STATUS[0])
0x0
-
0x0
-
0x0
-
LXTSTB
(CLK_STATUS[1])
PLLSTB
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
(CLK_STATUS[2])
HIRCSTB
(CLK_STATUS[4])
CLKSFAIL
(CLK_STATUS[7])
CLK_PLLCTL
0x0009_4 0x0009_44 0x0009_4 0x0009_44 0x0009_4 0x0009_44 0x0009_4 0x0009_44 -
40A
0A
40A
0A
40A
0A
40A
0A
PDMSEL
0x0
-
-
-
-
-
-
-
-
-
(CLK_PMUCTL [2:0])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
Reload
from
-
(WDT_CTL[1])
Dec. 25, 2020
Page 81 of 233
Rev. 1.00
Reset Sources
Register
POR
NRESET
WDT
LVR
BOD
Lockup
CHIP
SYSTEM
CPU
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0800
0x0800
0x0800
0x0800
0x0800
-
0x0800
-
-
except bit 1 and bit 7.
WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
-
-
-
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
Other
Peripheral Reset Value
Registers
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be reset. The
nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the
state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the
previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset waveform.
nRESET
0.7 VDD
32 us
0.2 VDD
32 us
nRESET Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2
Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to
be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the
POR module will detect the rising voltage and generate reset signal to system until the voltage is ready
for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there is a
Dec. 25, 2020
Page 82 of 233
Rev. 1.00
POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3 shows
the power-on reset waveform.
VPOR
1.46V
VDD
Power-on Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3
Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, and wait LVR detection circuit stable flag (SYS_BODCTL[23]) to 1, LVR
detection circuit will be stable and the LVR function will be active. Then LVR function will detect AVDD
during system operation. When the AVDD voltage is lower than VLVR and the state keeps longer than
De-glitch time set by LVRDGSEL (SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control
the chip in reset state until the AVDD voltage rises above VLVR and the state keeps longer than De-glitch
time set by LVRDGSEL (SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled
without De-glitch function. Figure 6.2-4 shows the Low Voltage Reset waveform.
AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
Brown-out Detector Reset (BOD Reset)
6.2.2.4
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), and wait BOD detection circuit stable flag STB(SYS_BODCTL[23]) to 1,
Dec. 25, 2020
Page 83 of 233
Rev. 1.00
BOD detection circuit will be stable and the BOD function will be active. Brown-out Detector function
will detect AVDD during system operation. When the AVDD voltage is lower than VBOD that is decided by
BODEN and BODVL (SYS_BODCTL[18:16]) and the state keeps longer than De-glitch time set by
BODDGSEL (SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset
state until the AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by
BODDGSEL. The default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by
Flash controller user configuration register CBODEN (CONFIG0 [19]), CBOV (CONFIG0 [23:21]) and
CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the
CONFIG0 register. Figure 6.2-5 shows the Brown-out Detector waveform.
AVDD
VBODH
Hysteresis
VBODL
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
Watchdog Timer Reset (WDT)
6.2.2.5
In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used to
check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog
time-out. User may decide to enable system reset during watchdog time-out to recover the system and
take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6 CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
Dec. 25, 2020
Page 84 of 233
Rev. 1.00
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7 CPU Reset, CHIP Reset and System Reset
The CPU Reset means only Cortex® -M23 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The System Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the System Reset.
6.2.3
Power Modes and Wake-up Sources
The NuMicro® M2354 series has a power manager unit to support several operating modes for saving
power. Table 6.2-2 lists all power modes in the NuMicro® M2354 series.
Mode
CPU Operating Maximum
Speed
LDO_CAP Clock Disable
(V)
( MHz)
All clocks are disabled by control register.
Power level 0
Power level 1
Power level 2
96 MHz
1.26
1.2
CLK_AHBCLK,
CLK_APBCLK1.
CLK_APBCLK0
and
and
and
and
All clocks are disabled by control register.
84 MHz
48 MHz
CLK_AHBCLK,
CLK_APBCLK1.
CLK_APBCLK0
All clocks are disabled by control register.
1.1
CLK_AHBCLK,
CLK_APBCLK1.
CLK_APBCLK0
All clocks are disabled by control register.
Power level 3
Idle mode
4 MHz
0.9
CLK_AHBCLK,
CLK_APBCLK1.
CLK_APBCLK0
CPU enter Sleep mode
keep
Only CPU clock is disabled.
Most
LIRC/LXT/MIRC,
clocks
are
disabled
and
except
only
Power-down mode (PD)
CPU enters Deep Sleep mode
CPU enters Deep Sleep mode
keep
keep
RTC/WDT/EWDT/Timer/UART/LCD peripheral
clocks still enable if their clock sources are
selected as LIRC/LXT/MIRC.
Most
LIRC/LXT/MIRC,
clocks
are
disabled
and
except
only
Fast Wake-up Power-down
mode (FWPD)
RTC/WDT/EWDT/Timer/UART/LCD peripheral
clocks still enable if their clock sources are
selected as LIRC/LXT/MIRC.
Most
LIRC/LXT/MIRC,
RTC/WDT/EWDT/Timer/UART/LCD peripheral
clocks still enable if their clock sources are
selected as LIRC/LXT/MIRC.
clocks
are
disabled
and
except
only
Low leakage Power-down
mode
CPU enters Deep Sleep mode
CPU enters Deep Sleep mode
0.9
0.8
(LLPD)
Ultra Low leakage Power-down
mode
Most clocks are disabled except LIRC/LXT, and
only
RTC/WDT/EWDT/Timer/UART/LCD
Dec. 25, 2020
Page 85 of 233
Rev. 1.00
(ULLPD)
peripheral clocks still enable if their clock
sources are selected as LIRC/LXT.
Standby Power-down mode
(SPD)
Only LIRC/LXT still enable for RTC function and
wake-up timer usage.
0.9 or
keep
Power off
Power off
Deep Power-down mode
(DPD)
Only LIRC/LXT still enable for RTC function and
wake-up timer usage.
Floating
Table 6.2-2 Power Mode Table
Each power mode has different entry setting and leaving condition. Table 6.2-3 shows the entry setting
for each power mode. When chip power-on, chip is running in normal mode. User can enter each
mode by setting SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCT[7]) and PDMSEL (CLK_PMUCTL[2:0])
and execute WFI instruction.
Register/Instruction
Mode
SLEEPDEEP PDEN
PDMSEL
CPU Run WFI Instruction
(SCR[2])
(CLK_PWRCTL[7]) (CLK_PMUCTL[2:0])
Normal mode
0
0
1
1
1
0
0
1
1
1
0
0
0
1
3
NO
Idle mode
YES
YES
YES
YES
Power-down mode
Low leakage Power-down mode
Ultra Low leakage Power-down
mode
Fast Wake-up Power-down mode
Standby Power-down mode
Deep Power-down mode
1
1
1
1
1
1
2
4
6
YES
YES
YES
Table 6.2-3 Power Mode Entry Setting Table
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-4 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all clocks
stop except LXT and LIRC.
Entry Condition
Chip is in normal mode after CPU executes WFI instruction. CPU sets sleep mode enable and
system reset released
power down enable and executes
WFI instruction.
Wake-up Sources
N/A
All interrupts
EINT, GPIO, UART, USBD, USBH,
OTG, CAN, BOD, WDT, EWDT,
SDH, Timer, I²C, USCI, RTC,
ACMP, TAMPER and CLKD.
Available Clocks
After Wake-up
All
All except CPU clock
LXT, LIRC and MIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-4 Power Mode Difference Table
Dec. 25, 2020
Page 86 of 233
Rev. 1.00
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, HIRC48, MIRC, LXT, LIRC,
HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP(SCR[2]) = 1
2. PDEN(CLK_PWRCTL[7]) = 1
3. CPU executes WFI
Wake-up events
occur
Power-down Mode
CPU Clock OFF
HXT, HIRC, HIRC48, PCLK OFF
MIRC, LXT, LIRC ON
Flash Halt
Idle Mode
CPU Clock OFF
HXT, HIRC, HIRC48, PCLK ON
MIRC, LXT, LIRC ON
Figure 6.2-6 Power Mode State Machine
1. LXT ON or OFF depends on software setting in normal mode.
2. LIRC ON or OFF depends on software setting in normal mode.
3. MIRC ON or OFF depends on software setting in normal mode.
4. If TIMER clock source is selected as LIRC/LXT/MIRC and LIRC/LXT/MIRC is on.
5. If WDT clock source is selected as LIRC/LXT and LIRC/LXT is on.
6. If RTC clock source is selected as LIRC/LXT and LIRC/LXT is on.
7. If UART clock source is selected as LXT and LXT is on.
8. If LCD clock source is selected as LIRC/LXT and LIRC/LXT is on.
If LCD charge pump clock source is selected as MIRC/MIRC1P2M and MIRC/MIRC1P2M is on.
9. If EWDT clock source is selected as LIRC/LXT and LIRC/LXT is on.
Power-Down Mode
Power-Down Mode
(SPD/DPD)
Normal Mode
Idle Mode
(PD/FWPD/LLPD/ULLPD)
HXT
HIRC
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
ON
Halt
Halt
Halt
Halt
HIRC48
MIRC
Halt
Halt
ON/OFF3
ON/OFF1
ON/OFF2
Halt
OFF
LXT
ON/OFF1
ON/OFF2
Halt
LIRC
PLL
CPU
Halt
Halt
HCLK/PCLK
Halt
Halt
Dec. 25, 2020
Page 87 of 233
Rev. 1.00
FLASH
TIMER
WDT
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
Halt
Halt
ON/OFF4
ON/OFF5
ON/OFF6
ON/OFF7
ON/OFF8
ON/OFF9
Halt
Halt
RTC
ON/OFF6
Halt
UART
LCD
Halt
EWDT
Others
Halt
Halt
Table 6.2-5 Clocks in Power Modes
Wake-up sources in Power-down mode:
EINT, GPIO, UART, USBD, USBH, OTG, CAN, BOD, ACMP, WDT, EWDT, SDH, Timer, I²C, USCI,
RTC, TAMPER and CLKD.
After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table
6.2-6 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Power-down mode
PD
Wake-Up
Source
System Can Enter Power-Down Mode Again
Condition*
Wake-Up Condition
LLPD
ULLPD
FWPD
SPD DPD
After software writes
(SYS_BODCTL[4]).
1
to clear BODIF
Brown-out Detector Reset / Interrupt
Brown-out Detector Reset
V
-
-
V
-
-
-
-
-
BOD
LVR
After software writes
(CLK_PMUSTS[13]) when SPD mode is
entered.
1 to clear BODWK
After software writes
(SYS_RSTSTS[3])
1
to clear LVRF
V
-
LVR Reset
After software writes
(CLK_PMUSTS[12]) when SPD mode is
entered.
1 to clear LVRWK
V
After software writes
(SYS_RSTSTS[0]).
1
to clear PORF
POR
EINT
GPIO
POR Reset
External Interrupt
GPIO Interrupt
V
V
V
V
-
V
-
After software write 1 to clear the Px_INTSRC[n]
bit.
After software write 1 to clear the Px_INTSRC[n]
bit.
-
-
GPIO(PA6-
PA15,PB~P
D) Wake-up
pin
GPxWK(CLK_PMUSTS[11:8]) is cleared when
SPD mode is entered.
rising or falling edge event, 50-pin
rising or falling edge event, 1-pin
-
-
V
-
-
V
GPIO(PC.0)
PINWK0(CLK_PMUSTS[0]) is cleared when
Dec. 25, 2020
Page 88 of 233
Rev. 1.00
Wake-up pin
DPD mode is entered.
GPIO(PB.0)
Wake-up pin
PINWK1(CLK_PMUSTS[3]) is cleared when
DPD mode is entered.
rising or falling edge event, 1-pin
rising or falling edge event, 1-pin
-
-
-
-
V
V
GPIO(PB.2)
Wake-up pin
PINWK2(CLK_PMUSTS[4]) is cleared when
DPD mode is entered.
GPIO(PB.12
) Wake-up
pin
PINWK3(CLK_PMUSTS[5]) is cleared when
DPD mode is entered.
rising or falling edge event, 1-pin
rising or falling edge event, 1-pin
Timer Interrupt
-
-
-
-
-
V
V
-
GPIO(PF.6)
Wake-up pin
PINWK4(CLK_PMUSTS[6]) is cleared when
DPD mode is entered.
After software writes
(TIMERx_INTSTS[1])
(TIMERx_INTSTS[0]).
1
to clear TWKF
and TIF
TIMER
V
After software writes
(CLK_PMUSTS[1]) when SPD or DPD mode is
entered.
1 to clear TMRWK
Wakeup
timer
Wakeup by wake-up timer time-out
-
V
V
After software writes
(WDT_CTL[5]) (Write Protect).
1
to clear WKF
WDT
WDT Interrupt
EWDT Interrupt
V
V
V
V
V
-
-
-
-
-
After software writes
(EWDT_CTL[5]) (Write Protect).
1
to clear WKF
EWDT
After software writes
(RTC_INTSTS[0]).
1
1
to clear ALMIF
to clear TICKIF
to clear TAMPxIF
Alarm Interrupt
-
-
After software writes
(RTC_INTSTS[1]).
Time Tick Interrupt
RTC Tamper Interrupt
Wakeup by RTC alarm
-
-
After software writes
(RTC_INTSTS[8:13]).
1
-
-
RTC
RTCWK (CLK_PMUSTS[2]) is cleared when
DPD or SPD mode is entered.
V
V
RTCWK (CLK_PMUSTS[2]) is cleared when
DPD or SPD mode is entered.
Wakeup by RTC tick time
-
V
V
RTCWK (CLK_PMUSTS[2]) is cleared when
DPD or SPD mode is entered.
Wakeup by tamper event
nCTS wake-up
-
V
-
V
-
After software writes
(UARTx_WKSTS[0]).
1
1
to clear CTSWKF
to clear DATWKF
V
V
V
V
V
V
V
After software writes
(UARTx_WKSTS[1]).
RX Data wake-up
-
-
After software writes 1 to clear RFRTWKF
(UARTx_WKSTS[2]).
UART
Received FIFO Threshold Wake-up
RS-485 AAD Mode Wake-up
-
-
After software writes 1 to clear RS485WKF
(UARTx_WKSTS[3]).
-
-
Received FIFO Threshold Time-out
Wake-up
After software writes 1 to clear TOUTWKF
(UARTx_WKSTS[4]).
-
-
After software writes
(UUART_WKSTS[0]).
1
to clear WKF
CTS Toggle
Data Toggle
-
-
USCI UART
After software writes
(UUART_WKSTS[0]).
1
to clear WKF
-
-
Dec. 25, 2020
Page 89 of 233
Rev. 1.00
After software writes
(UI2C_WKSTS[0]).
1
to clear WKF
Data toggle
Address match
V
V
V
V
-
-
-
-
-
-
-
-
USCI I2C
After software writes 1 to clear WKAKDONE
(UI2C_PROTSTS[16], then writes 1 to clear
WKF (UI2C_WKSTS[0]).
After software writes
(USPI_WKSTS[0]).
1
to clear WKF
USCI SPI
I2C
SS Toggle
After software writes 1 to clear WKAKDONE
(I2C_WKSTS[1]). Then software writes 1 to
clear WKIF(I2C_WKSTS[0]).
Address match wake-up
1.Remote wake-up
2.Plug in wake-up
After software writes
(USBD_INTSTS[0]).
1
to clear BUSIF
USBD
USBH
V
V
-
-
-
-
1.After
write
1
to
to
to
clear
clear
clear
RHSC
RHSC
RHSC
(HcInterruptStatus[7]).
1.Connection detected
2.Disconnect detected
3.Remote-wakeup
2.After write
(HcInterruptStatus[7]).
3.After write
1
1
(HcInterruptStatus[7]). and port suspended.
After
software
writes
1
to
set
OTG
ID pin state be change
V
V
-
-
-
-
WKEN(OTG_CTL[5]).
After software writes
(ACMP_STATUS[8])
(ACMP_STATUS[9]).
1
to clear WKIF0
and WKIF1
Comparator Power-Down Wake-Up
Interrupt
ACMP
ACMPWK (CLK_PMUSTS[14]) is cleared when
SPD mode is entered.
ACMPO status change
Incoming Data Toggle
Card detection
-
V
-
-
-
-
-
-
-
After software writes 0 to clear WAKUP_STS
(CAN_WU_STATUS[0])
CAN
SDH
V
V
V
-
Clear CDIF0 (SDH_INTSTS[8]) after SDH wake-
up.
-
Clear TAMP_EVSTS or disable Enable in
TAMP_INTEVEN after TAMPER wake-up.
Event detection
-
TAMPER
CLKD
TAMPERWK (CLK_PMUSTS[15]) is cleared
when SPD mode is entered.
Wakeup by Event detection
LXT clock fail interrupt
V
-
After software writes
(CLK_CLKDSTS[1]).
1 to clear LXTFIF
V
Table 6.2-6 Condition of Entering Power-down Mode Again
6.2.4
System Power Distribution
In this chip, power distribution is divided into four segments:
Analog power from AVDD and AVSS provides the power for analog components operation.
Digital power from VDD and VSS supplies the power to the internal regulator which provides
a fixed 0.9V, 1.1V, 1.2V or 1.26V power for digital operation and I/O pins.
USB transceiver power from VDD offers the power for operating the USB transceiver.
RTC power from VBAT provides the power for RTC and 80 bytes backup registers.
The outputs of internal voltage regulators, LDO and VDD, require an external capacitor which should be
located close to the corresponding pin. Analog power (AVDD) should be the same voltage level of the
Dec. 25, 2020
Page 90 of 233
Rev. 1.00
digital power (VDD). If system enters SPD mode SW_SPD switch is turned off, and internal voltage
regulator can be set to LDO mode or DC-DC converter mode. Figure 6.2 7 shows the power
distribution.
Internal
Reference
Voltage
32.768 kHz
crystal
oscillator
RTC
POR
VDDIO
12-bit ADC
IO Cell
IO Cell
AVDD
AVSS
12-bit DAC
Temp. Sensor
Analog Comparator
VBAT
Voltage
Divider
32 KHz
LIRC
Oscillator
RTC &
80 bytes backup register
VBAT
Detector
LVDR
(Low Voltage Reset, Brown-out
Detector)
32 kHz
Digital
LIRC
Oscillator
4 MHz
MIRC
Oscillator
SRAM
(256K)
Flash
TRNG
POR12
Logic
0.9v/1.1v/
1.2V/1.26V
LDO_CAP
SW_SPD
4.7uF
12 MHz
HIRC
Oscillator
Key
Store
Power Management and
Holder Logic
48 MHz HIRC
Oscillator
PLL
Tamper
Controller
POR33/
Power
On
3.3V à
1.2V/1.26V
/1.1V/0.9V
Regulator
GPIO except
PF.4~PF.11 and
PA.0~PA.5
4~24 MHz
crystal
oscillator
LCD
Charge
Pump
32 kHz
LIRC
Oscillator
Over
Voltage
Detector
USB 1.1
OTG
PHY
Tamper
Regulator
IO Cell
Control
M2354 Power Distribution
Figure 6.2-7 Power Distribution Diagram
Dec. 25, 2020
Page 91 of 233
Rev. 1.00
6.2.5
Bus Matrix
M4
M3
PDMA1
USBH
Crypto
SDH0
M2
Only Crypto
M1
M0
PDMA0
Cortex-M23
S0
S1
S2
S3
S4
S5
S6
S7
S8
SRAM0
(32 KB)
SRAM1
(128 KB)
APB0
Peripheral
APB1
Peripheral
AHB
Peripheral
SRAM2
(96 KB)
FLASH
EBI
Key store
GMISC
Figure 6.2-2 M2354 Bus Matrix Architecture Diagram
Refer to Figure 6.2-2. This chip uses Advanced Microcontroller Bus Architecture (AMBA) protocol to
implement system bus. The system has five masters and nine slaves, in which a different master can
communicate with a different slave at the same time through Bus Matrix. The Cortex® -M23 core
processor acts as the master in Bus Matrix, located on M0 to communicate with any slaves through
Bus Matrix. PDMA0 and PDMA1 are Peripheral Direct Memory Access and act as the master in Bus
Matrix, respectively located on M1 and M4, which can communicate with any slaves through Bus
Matrix. SDH0 and Crypto share the same master bandwidth located on M2. USBH acts as the master
role in Bus Matrix and is located on M3. The slave AHB Peripheral is the Advanced High-performance
Bus (AHB) controller, and any master can communicate with any AHB peripheral through Bus Matrix.
6.2.6
System Memory Map
This chip provides 4G-byte addressing space. The memory locations assigned to each on-chip
controllers are shown in Table 6.2-7. The detailed register definition, memory space, and programming
will be described in the following sections for each on-chip peripheral. This chip implement Arm®
TrustZone Architecture as well as memory alias technique, secure code and non-secure code can run
together on the chip well, while both have different memory view. Secure code view is shown in Table
6.2-1 and non-secure code view is shown in Table 6.2-2.
The NuMicro® M2354 series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
Dec. 25, 2020
Page 92 of 233
Rev. 1.00
0x0000_0000 – 0x0003_FFFF
0x0000_0000 – 0x0007_FFFF
0x0000_0000 – 0x000F_FFFF
0x2000_0000 – 0x2000_7FFF
0x2000_8000 – 0x2002_7FFF
0x2002_8000 – 0x2003_FFFF
0x6000_0000 – 0x6FFF_FFFF
FLASH_BA
FLASH_BA
FLASH_BA
SRAM0_BA
SRAM1_BA
SRAM2_BA
EXTMEM_BA
FLASH Memory Space (256 KB)
FLASH Memory Space (512 KB)
FLASH Memory Space (1024 KB)
SRAM Memory Space (32 KB)
SRAM Memory Space (128 KB)
SRAM Memory Space (96 KB)
External Memory Space (256 MB)
Secure Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
0x4000_8000 – 0x4000_8FFF
0x4000_9000 – 0x4000_9FFF
0x4000_C000 – 0x4000_CFFF
0x4000_D000 – 0x4000_DFFF
0x4001_0000 – 0x4001_0FFF
0x4001_8000 – 0x4000_8FFF
0x4003_1000 – 0x4003_1FFF
0x4003_2000 – 0x4003_4FFF
0x4003_5000 – 0x4003_5FFF
0x4002_F000 – 0x4002_FFFF
SYS_BA
CLK_BA
System Control Registers (always secure)
Clock Control Registers (always secure)
NMI Control Registers (always secure)
GPIO Control Registers
NMI_BA
GPIO_BA
PDMA0_BA
USBH_BA
FMC_BA
SDH0_BA
EBI_BA
Peripheral DMA 0 Control Registers (always secure)
USB Host Control Registers
Flash Memory Control Registers (always secure )
SDHOST0 Control Registers
External Bus Interface Control Registers
Peripheral DMA 1 Control Registers (secure or non-secure)
CRC Generator Registers
PDMA1_BA
CRC_BA
CRPT_BA
KS_BA
Cryptographic Accelerator Registers
Key Store Registers (always secure)
SCU_BA
Secure Configuration Unit Registers (always secure)
Secure APB Controllers Space (0x4004_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_1000 – 0x4004_1FFF
0x4004_2000 – 0x4004_2FFF
0x4004_3000 – 0x4004_3FFF
0x4004_5000 – 0x4004_5FFF
0x4004_7000 – 0x4004_7FFF
0x4004_8000 – 0x4004_8FFF
0x4004_D000 – 0x4004_DFFF
0x4005_0000 – 0x4005_0FFF
0x4005_1000 – 0x4005_1FFF
0x4005_2000 – 0x4005_2FFF
WDT_BA
Watchdog Timer Control Registers (always secure)
Real Time Clock (RTC) Control Register (always secure)
Extra Watchdog Timer Control Registers
Enhanced Analog-Digital-Converter (EADC) Control Registers
Analog Comparator 0/1 Control Registers
DAC Control Registers
RTC_BA
EWDT_BA
EADC_BA
ACMP01_BA
DAC_BA
I2S0_BA
I2S0 Interface Control Registers
OTG_BA
OTG Control Registers
TMR01_BA
TMR23_BA
TMR45_BA
Timer0/Timer1 Control Registers (always secure)
Timer2/Timer3 Control Registers
Timer4/Timer5 Control Registers
Dec. 25, 2020
Page 93 of 233
Rev. 1.00
0x4005_8000 – 0x4005_8FFF
0x4005_9000 – 0x4005_9FFF
0x4005_A000 – 0x4005_AFFF
0x4005_B000 – 0x4005_BFFF
0x4006_0000 – 0x4006_0FFF
0x4006_1000 – 0x4006_1FFF
0x4006_2000 – 0x4006_2FFF
0x4006_3000 – 0x4006_3FFF
0x4006_4000 – 0x4006_4FFF
0x4007_0000 – 0x4007_0FFF
0x4007_1000 – 0x4007_1FFF
0x4007_2000 – 0x4007_2FFF
0x4007_3000 – 0x4007_3FFF
0x4007_4000 – 0x4007_4FFF
0x4007_5000 – 0x4007_5FFF
0x4008_0000 – 0x4008_0FFF
0x4008_1000 – 0x4008_1FFF
0x4008_2000 – 0x4008_2FFF
0x4009_0000 – 0x4009_0FFF
0x4009_1000 – 0x4009_1FFF
0x4009_2000 – 0x4009_2FFF
0x400A_0000 – 0x400A_0FFF
0x400B_0000 – 0x400B_0FFF
0x400B_1000 – 0x400B_1FFF
0x400B_4000 – 0x400B_4FFF
0x400B_5000 – 0x400B_5FFF
0x400B_9000 – 0x400B_9FFF
0x400B_B000 – 0x400B_BFFF
0x400B_D000 – 0x400B_DFFF
0x400C_0000 – 0x400C_0FFF
0x400D_0000 – 0x400D_0FFF
0x400D_1000 – 0x400D_1FFF
EPWM0_BA
EPWM1_BA
BPWM0_BA
BPWM1_BA
QSPI0_BA
SPI0_BA
EPWM0 Control Registers
EPWM1 Control Registers
BPWM0 Control Registers
BPWM1 Control Registers
QSPI0 Control Registers
SPI0 Control Registers
SPI1_BA
SPI1 Control Registers
SPI2_BA
SPI2 Control Registers
SPI3_BA
SPI3 Control Registers
UART0_BA
UART1_BA
UART2_BA
UART3_BA
UART4_BA
UART5_BA
I2C0_BA
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
UART3 Control Registers
UART4 Control Registers
UART5 Control Registers
I2C0 Control Registers
I2C1_BA
I2C1 Control Registers
I2C2_BA
I2C2 Control Registers
SC0_BA
Smartcard Host 0 Control Registers
Smartcard Host 1 Control Registers
Smartcard Host 2 Control Registers
CAN0 Bus Control Registers
QEI0 Control Registers
SC1_BA
SC2_BA
CAN0_BA
QEI0_BA
QEI1_BA
QEI1 Control Registers
ECAP0_BA
ECAP1_BA
TRNG_BA
LCD_BA
ECAP0 Control Registers
ECAP1 Control Registers
TRNG Control Registers
LCD Control Register
TAMPER_BA
USBD_BA
USCI0_BA
USCI1_BA
Tamper Control Register (always secure)
USB Device Control Register
USCI0 Control Registers
USCI1 Control Registers
Table 6.2-7 Address Space Assignments for On-Chip Controllers
Dec. 25, 2020
Page 94 of 233
Rev. 1.00
Address Space
Token
Controllers
Non-secure Peripheral Controllers Space (0x5000_0000 – 0x500F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_4000 – 0x5000_4FFF
0x5000_9000 – 0x5000_9FFF
0x5000_D000 – 0x5000_DFFF
0x5001_0000 – 0x5001_0FFF
0x5001_8000 – 0x5000_8FFF
0x5003_1000 – 0x5003_1FFF
0x5003_2000 – 0x5003_4FFF
SYS_BA_NS
GPIO_BA
USBH_BA
SDH0_BA
EBI_BA
System Control Registers
GPIO Control Registers
USB Host Control Registers
SDHOST0 Control Registers
External Bus Interface Control Registers
PDMA1_BA
CRC_BA
Peripheral DMA 1 Control Registers (secure or non-secure)
CRC Generator Registers
CRPT_BA
Cryptographic Accelerator Registers
Non-secure APB Controllers Space (0x5004_0000 ~ 0x500F_FFFF)
0x5004_2000 – 0x5004_2FFF
0x5004_3000 – 0x5004_3FFF
0x5004_5000 – 0x5004_5FFF
0x5004_7000 – 0x5004_7FFF
0x5004_8000 – 0x5004_8FFF
0x5004_D000 – 0x5004_DFFF
0x5005_1000 – 0x5005_1FFF
0x5005_2000 – 0x5005_2FFF
0x5005_8000 – 0x5005_8FFF
0x5005_9000 – 0x5005_9FFF
0x5005_A000 – 0x5005_AFFF
0x5005_B000 – 0x5005_BFFF
0x5006_0000 – 0x5006_0FFF
0x5006_1000 – 0x5006_1FFF
0x5006_2000 – 0x5006_2FFF
0x5006_3000 – 0x5006_3FFF
0x5006_4000 – 0x5006_4FFF
0x5007_0000 – 0x5007_0FFF
0x5007_1000 – 0x5007_1FFF
0x5007_2000 – 0x5007_2FFF
0x5007_3000 – 0x5007_3FFF
0x5007_4000 – 0x5007_4FFF
0x5007_5000 – 0x5007_5FFF
EWDT_BA
EADC_BA
ACMP01_BA
DAC_BA
Extra Watchdog Timer Control Registers
Enhanced Analog-Digital-Converter (EADC) Control Registers
Analog Comparator 0/ 1 Control Registers
DAC Control Registers
I2S0_BA
I2S0 Interface Control Registers
OTG Control Registers
OTG_BA
TMR23_BA
TMR45_BA
EPWM0_BA
EPWM1_BA
BPWM0_BA
BPWM1_BA
QSPI0_BA
SPI0_BA
Timer2/Timer3 Control Registers
Timer4/Timer5 Control Registers
EPWM0 Control Registers
EPWM1 Control Registers
BPWM0 Control Registers
BPWM1 Control Registers
QSPI0 Control Registers
SPI0 Control Registers
SPI1_BA
SPI1 Control Registers
SPI2_BA
SPI2 Control Registers
SPI3_BA
SPI3 Control Registers
UART0_BA
UART1_BA
UART2_BA
UART3_BA
UART4_BA
UART5_BA
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
UART3 Control Registers
UART4 Control Registers
UART5 Control Registers
Dec. 25, 2020
Page 95 of 233
Rev. 1.00
0x5008_0000 – 0x5008_0FFF
0x5008_1000 – 0x5008_1FFF
0x5008_2000 – 0x5008_2FFF
0x5009_0000 – 0x5009_0FFF
0x5009_1000 – 0x5009_1FFF
0x5009_2000 – 0x5009_2FFF
0x500A_0000 – 0x500A_0FFF
0x500B_0000 – 0x500B_0FFF
0x500B_1000 – 0x500B_1FFF
0x500B_4000 – 0x500B_4FFF
0x500B_5000 – 0x500B_5FFF
0x500B_9000 – 0x500B_9FFF
0x400B_B000 – 0x400B_BFFF
0x500C_0000 – 0x500C_0FFF
0x500D_0000 – 0x500D_0FFF
0x500D_1000 – 0x500D_1FFF
I2C0_BA
I2C1_BA
I2C2_BA
SC0_BA
I2C0 Control Registers
I2C1 Control Registers
I2C2 Control Registers
Smartcard Host 0 Control Registers
Smartcard Host 1 Control Registers
Smartcard Host 2 Control Registers
CAN0 Bus Control Registers
QEI0 Control Registers
SC1_BA
SC2_BA
CAN0_BA
QEI0_BA
QEI1_BA
ECAP0_BA
ECAP1_BA
TRNG_BA
LCD_BA
QEI1 Control Registers
ECAP0 Control Registers
ECAP1 Control Registers
TRNG Control Registers
LCD Control Register
USBD_BA
USCI0_BA
USCI1_BA
USB Device Control Register
USCI0 Control Registers
USCI1 Control Registers
Table 6.2-2 Non-secure Address Space Assignments for On-Chip Controllers
6.2.7
Implementation Defined Attribution Unit (IDAU)
6.2.7.1 Overview
The Arm® v8-M has the new feature called TrustZone® , which adds an additional security state to allow
full isolation of two security levels. The processor security state is decided by the memory definition.
For example, processor is in Secure state when the code is executed in the Secure region. The
memory map security state will be defined by the combination of:
Internal Security Attribution Unit (SAU)
Implementation Defined Attribution Unit (IDAU)
These attribution units define the memory space into four type regions:
Secure Region: contains Secure program code or data
Non-secure Callable Region (NSC): contains entry functions for Non-secure programs to
access Secure functions
Non-secure Region: contains Non-secure program code or data
Exempt Region: exempt region will be exempted from security check
For each memory region defined by the SAU and IDAU has a region number generated by the SAU or
by the IDAU. Region number is used for determining a group of memory share the same security
attribute. Overlapping region numbers are not allow. For testing security attributes and region
numbers, a new instruction “TT” (Test Target) is introduced. By using a TT instruction on the start and
end addresses of the memory range, and identifying that both reside in the same region number, user
can determine that the memory range is located entirely in same space. To be more specific, please
refer to the Arm® v8-M Architecture Reference Manual. The M2354 IDAU memory map attributions and
corresponding region numbers are shown in Figure 6.2-8. The address from 0xE000_0000 to
Dec. 25, 2020
Page 96 of 233
Rev. 1.00
0xFFFF_FFFF is marked as exempt regions because the behavior of the address is fixed, so their
security attributes do not control by the SAU or IDAU.
Region num
0xFFFF_FFFF
Device
System
Exempt
Exempt
15
14
13
12
11
10
9
0xF000_0000
0xE000_0000
0xD000_0000
0xC000_0000
0xB000_0000
0xA000_0000
0x9000_0000
0x8000_0000
0x7000_0000
0x6000_0000
0x5000_0000
0x4000_0000
0x3000_0000
0x2000_0000
NON-SECURE
SECURE
External Device
External RAM
NON-SECURE
SECURE
NON-SECURE
SECURE
8
NON-SECURE
SECURE
7
6
NON-SECURE
SECURE
5
Device
SRAM
4
NON-SECURE
NSC
3
2
NON-SECURE
1
0x1000_0000
0x0000_0800
0x0000_0000
Code
NSC
SECURE
16
0
Figure 6.2-8 IDAU Memory Map
6.2.7.2 IDAU Block Diagram
The IDAU block diagram is shown in Figure 6.2-9. IDAU is security attribute unit connected outside of
the processor. Both SAU and IDAU are responsible to response the security property of the address
from processor, the only difference is that the memory security attribute of the SAU is configurable and
the IDAU is fixed. After the processor compares the security property of the IDAU and SAU, it will take
the highest security attribute applied. The hierarchy of security levels from high to low is: Secure >
NSC > Non-secure.
Dec. 25, 2020
Page 97 of 233
Rev. 1.00
processor
CPU
address
IDAU
SAU
Other
Master
Other
Master
MPU MPU
Bus Matrix
Slave
Slave
Slave
Slave
Slave
Slave
Figure 6.2-9 IDAU Block Diagram
SRAM Memory Organization
6.2.8
This chip supports embedded SRAM with a total of 256 Kbytes size and the SRAM organization is
separated into three banks: SRAM bank0, SRAM bank1, and SRAM bank2. The first bank has 32
Kbytes address space, the second bank has 128Kbyte address space, and the third bank has 96Kbyte
address space. These three banks address space can be accessed simultaneously. The SRAM bank0
supports parity error check to make sure the chip is operating more stable.
Supports total 256 Kbytes SRAM
Supports byte / half word / word write
Supports parity error check function for SRAM bank0
Supports oversize response error
AHB interface
controller
SRAM decoder
SRAM bank0
SRAM bank1
SRAM bank2
AHB interface
controller
SRAM decoder
SRAM decoder
M23
AHB interface
controller
Dec. 25, 2020
Page 98 of 233
Rev. 1.00
Figure 6.2-10 SRAM Block Diagram
Figure 6.2-11 shows the SRAM organization. There are three SRAM banks. The bank0 is addressed
to 32 Kbytes, the bank1 is addressed to 128 Kbytes and the bank2 is addressed to 96 Kbytes. The
bank0 address space is from 0x2000_0000 to 0x2000_7FFF(Secure) or 0x3000_0000 to
0x3000_7FFF(Non-secure). The bank1 address space is from 0x2000_8000 to 0x2002_7FFF
(Secure) or 0x3000_8000 to 0x3002_7FFF (Non-secure). The bank2 address space is from
0x2002_8000 to 0x2003_FFFF (Secure) or 0x3002_8000 to 0x3003_FFFF (Non-secure). The address
between 0x2004_0000 to 0x2FFF_FFFF(Secure) and 0x3004_0000 to 0x3FFF_FFFF(Non-secure) is
illegal memory space and chip will enter hardfault if CPU accesses these illegal memory addresses.
0x3FFF_FFFF
0x2FFF_FFFF
Reserved
Reserved
0x2004_0000
0x2003_FFFF
0x3004_0000
0x3003_FFFF
96 Kbytes
96 Kbytes
SRAM bank2
SRAM bank2
0x3002_8000
0x3002_7FFF
0x2002_8000
0x2002_7FFF
128 Kbytes
128 Kbytes
SRAM bank1
SRAM bank1
0x3000_8000
0x3000_7FFF
0x2000_8000
0x2000_7FFF
32 Kbytes
32 Kbytes
SRAM bank0
SRAM bank0
0x3000_0000
0x2000_0000
256 Kbytes device
(secure)
256 Kbytes device
(non-secure)
Figure 6.2-11 SRAM Memory Organization
The SRAM bank0 has byte parity error check function. When CPU is accessing SRAM bank0, the
parity error checking mechanism is dynamic operating. As parity error occurs, the PERRIF
(SYS_SRAMSTS[0]) will be asserted to 1 and the SYS_SRAMEADR register will recode the address
with the parity error. Chip will enter interrupt when SRAM parity error occurs if PERRIEN
(SYS_SRAMICTL[0]) is set to 1. When SRAM parity error occurs, chip will stop detecting SRAM parity
error until user writes 1 to clear the PERRIF(SYS_SRAMSTS[0]) bit.
Dec. 25, 2020
Page 99 of 233
Rev. 1.00
SRAM Power Control
The SRAM bank0 and bank1, and bank2 have marco retention and power shut down function. Each
SRAM marco can be configured to retention or power shut down mode independently by
SRAMxPMn(SYS_SRAMPC0 and SYS_SRAMPC1, x=0-2 n=0-7). Figure 6.2-12 shows the SRAM
marco number in bank0, bank1 and bank2. When chip power down wake up, the SRAM marcos wake
up in the order of marco number, from SRAM marco0 to SRAM marco17.
0x3003_FFFF
0x2003_FFFF
16 Kbytes
SRAM Marco 17
16 Kbytes
SRAM Marco 17
0x3003_C000
0x3003_C000
0x2003_C000
0x2003_C000
16 Kbytes
SRAM Marco 16
16 Kbytes
SRAM Marco 16
0x3003_8000
0x3003_8000
0x2003_8000
0x2003_8000
-----------
-----------
0x3003_0000
0x3003_0000
0x2003_0000
0x2003_0000
16 Kbytes
SRAM Marco 13
16 Kbytes
SRAM Marco 13
0x3002_C000
0x3002_C000
0x2002_C000
0x2002_C000
16 Kbytes
SRAM Marco 12
16 Kbytes
SRAM Marco 12
0x3002_8000
0x3002_8000
0x3002_7FFF
0x2002_8000
0x2002_8000
0x2002_7FFF
16 Kbytes
16 Kbytes
SRAM Marco 11
SRAM Marco 11
0x3002_4000
0x2002_4000
0x2002_4000
16 Kbytes
SRAM Marco 10
16 Kbytes
SRAM Marco 10
0x2002_0000
0x2002_0000
0x3002_0000
0x3001_0000
-----------
-----------
0x2001_0000
0x2001_0000
16 Kbytes
16 Kbytes
SRAM Marco 5
SRAM Marco 5
0x3000_C000
0x2000_C000
0x2000_C000
16 Kbytes
16 Kbytes
SRAM Marco 4
SRAM Marco 4
0x3000_8000
0x3000_6000
0x2000_8000
0x2000_8000
8 Kbytes
SRAM Marco 3
8 Kbytes
SRAM Marco 3
0x2000_6000
0x2000_6000
8 Kbytes
8 Kbytes
SRAM Marco 2
SRAM Marco 2
0x3000_4000
0x2000_4000
0x2000_4000
8 Kbytes
8 Kbytes
SRAM Marco 1
SRAM Marco 1
0x3000_2000
0x3000_1000
0x2000_2000
0x2000_2000
4K+4Kbytes
SRAM Marco 0
4K+4K byte
SRAM Marco 0
0x2000_1000
0x2000_1000
0x3000_0000
0x2000_0000
0x2000_0000
256 Kbytes device
256 Kbytes device
256 Kbytes device
256 Kbytes device
(non secure)
(non secure)
(secure)
(secure)
Figure 6.2-12 SRAM Marco Organization
Dec. 25, 2020
Page 100 of 233
Rev. 1.00
For system SRAM (bank0, bank1, and bank2) and Key store SRAM, if the SRAM power mode is set to
normal mode, it automatically changes to retention mode when system enters PD/LLPD/ULLPD/SPD
Power-down mode, and then changes back to normal mode after wake-up. System and Key store
SRAM power mode do not change when system enters FWPD Power-down mode. When system
enters DPD Power-down mode, system and Key store SRAM is always operating in power shut down
mode and reset to normal mode after wake-up.
For other peripheral SRAM, when system enters PD/LLPD/ULLPD/SPD Power-down mode, if
peripheral SRAM power mode is set to normal mode, the peripheral SRAM power mode automatically
changes to retention mode, and then changes back to normal mode after wake-up, too.
But if entering SPD Power-down mode, peripheral SRAM resets to default power mode after wake-up.
When system enters DPD Power-down mode, peripheral SRAM is always operating in power shut
down
mode
and
reset
to
default
power
mode
after
wake-up.
Peripheral SRAM power mode does not change when system enters FWPD Power-down mode.
SRAM
Power-Down SRAM Power Mode Before And After Wake-Up
Mode
SRAM bank0/1/2 PD
Key Store SRAM
1.If SRAM power mode is set to normal mode, it changes to retention mode after
entering Power-down Mode, and changes back to normal mode after wake-up.
LLPD
2.If SRAM power mode is set to Retention or Power shut down mode, it keeps power
mode setting.
ULLPD
SPD
FWPD
DPD
SRAM power mode keeps power mode setting.
SRAM power mode is always operating in power shut down mode after entering Power-
down Mode, and resets to normal mode after wake-up.
Other Peripheral PD
1.If SRAM power mode is set to normal mode, it changes to retention mode after
entering Power-down Mode, and changes back to normal mode after wake-up.
SRAM
LLPD
2.If SRAM power mode is set to Retention or Power shut down mode, it keeps power
mode setting.
ULLPD
FWPD
SPD
SRAM power mode keeps power mode setting.
1. If SRAM power mode is set to normal mode, it changes to retention mode after
entering Power-down Mode.
2. If SRAM power mode is set to Retention or Power shut down mode, it keeps power
mode setting.
3. SRAM power mode is reset to default power mode after wake-up.
DPD
SRAM power mode is always operating in power shut down mode after entering Power-
down Mode, and resets to default power mode after wake-up.
Table 6.2-8 SRAM Power Mode Behavior
6.2.9
Auto Trim
This chip supports auto-trim function: the HIRC trim (12 MHz RC oscillator, 48 MHz RC oscillator),
according to the accurate external 32.768 kHz crystal oscillator or internal USB synchronous mode, to
automatically get accurate HIRC output frequency, 0.25 % deviation within all temperature ranges.
For instance, the system needs an accurate 12 MHz clock. In such case, if neither using PLL as the
system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL
(SYS_TCTL12M[10] reference clock selection) to “1”, set FREQSEL (SYS_TCTL12M[1:0] trim
frequency selection) to “01”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK
(SYS_TISTS12M[8] HIRC frequency lock status) “1” indicates the HIRC output frequency is accurate
Dec. 25, 2020
Page 101 of 233
Rev. 1.00
within 0.25% deviation. In another case, the system needs an accurate 48 MHz clock. In such case, if
neither using PLL as the system clock source nor soldering 32.768 kHz crystal in system, user has to
set REFCKSEL (SYS_TCTL48M[10] reference clock selection) to “1”, set FREQSEL
(SYS_TCTL48M[1:0] trim frequency selection) to “01”, and the auto-trim function will be enabled.
Interrupt status bit FREQLOCK (SYS_TISTS48M[8] HIRC48 frequency lock status) “1” indicates the
HIRC output frequency is accurate within 0.25% deviation.
HIRC trim can only work properly when the clock sources are stable. When the RC clock or the
reference clock are not stable or the system go into power down, HIRC trim will not be enable.
6.2.10 Register Lock Control
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These write-protected system control registers, as listed in Table 6.2-9, have write-
protection after the power-on reset till user disables register protection.
Before writing to these protected registers, user has to unlock the write-protected mechanism by
writing a register protection disable sequence to the REGLCTL register. The register protection disable
sequence is writing the data “59h”, “16h” “88h” sequentially. Any different data value, different
sequence or any other write to other address during these three data writing will abort the whole
sequence.
Once a register protection disable sequence is writing to the REGLCTL register successfully, These
write-protected registers will be unlocked and able to accept write access. It’s recommended to locked
these registers by writing any value to REGLCTL register.
6.2.10.1 Register Lock Control mechanism with Trustzone
For M2354, due to Trustzone technology, system resources are divided into secure and non-secure,
leading to type of register of peripheral is either secure or non-secure. Secure registers exist in
0x4nnn_nnnn region (i.e. bit[28] is 0), while non-secure registers exist in 0x5nnn_nnnn region (i.e.
bit[28] is 1).
The security types of registers are defined by which peripheral they belong to. Secure peripheral has
only secure registers while non-secure peripheral has only non-secure registers. Note that shared
registers in some peripherals are also defined as non-secure registers. Refer to SCU “Memory
Access Policy” section for more details.
There are two REGLCTL registers in system. Secure REGLCTL is SYS_REGLCTL register at address
0x40000100 for secure code to unlock write-protection of both secure and non-secure registers; Non-
secure REGLCTL is SYS_REGLCTLNS register at address 0x50000100, which can be seen as the
non-secure alias address of SYS_REGLCTL and is used for non-secure code to unlock write-
protection of non-secure registers. Note that address listed in Table 6.2-9 is the address of secure
register, for non-secure register, the first nibble of the address is 0x5.
Item
Security Type
Secure and Non-secure
Secure
Address
SYS_IPRST0
SYS_BODCTL
SYS_PORCTL
SYS_VREFCTL
SYS_USBPHY
SYS_SRAMPC0
0x4000_0008
0x4000_0018
0x4000_0024
0x4000_0028
0x4000_002C
0x4000_00DC
Secure
Secure
Secure
Secure
Dec. 25, 2020
Page 102 of 233
Rev. 1.00
SYS_SRAMPC1
SYS_PORCTL1
SYS_PSWCTL
SYS_PLCTL
Secure
0x4000_00E0
0x4000_01EC
0x4000_01F4
0x4000_01F8
0x4000_01FC
0x4000_0200
0x4000_0208
0x4000_0210
0x4000_0214
0x4000_0240
0x4000_0274
0x4000_0290
0x4000_0300
0x4000_0400
0x4000_C000
0x4000_C010
0x4000_C040
0x4000_C04C
0x4004_0000
0x4004_0004
0x4004_2000
0x4004_2004
0x4005_0000
0x4005_0100
0x4005_1000
0x4005_1100
0x4005_2000
0x4005_2100
0x4005_0040
0x4005_0140
0x4005_1040
0x4005_1140
0x4005_2040
0x4005_2140
Secure
Secure
Secure
SYS_PLSTS
Secure
CLK_PWRCTL
CLK_APBCLK0
CLK_CLKSEL0
CLK_CLKSEL1
CLK_PLLCTL
CLK_CLKDSTS
CLK_PMUCTL
NMIEN
Secure
Secure
Secure
Secure
Secure
Secure
Secure
Secure
AHBMCTL
Secure
FMC_ISPCTL
FMC_ISPTRG
FMC_ISPSTS
FMC_CYCCTL
WDT_CTL
Secure and Non-secure
Secure and Non-secure
Secure and Non-secure
Secure
Secure
WDT_ALTCTL
EWDT_CTL
Secure
Secure or Non-secure
Secure or Non-secure
Secure
EWDT_ALTCTL
TIMER0_CTL
TIMER1_CTL
TIMER2_CTL
TIMER3_CTL
TIMER4_CTL
TIMER5_CTL
TIMER0_PWMCTL
TIMER1_PWMCTL
TIMER2_PWMCTL
TIMER3_PWMCTL
TIMER4_PWMCTL
TIMER5_PWMCTL
Secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure
Secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Dec. 25, 2020
Page 103 of 233
Rev. 1.00
TIMER0_PWMDTCTL
TIMER1_PWMDTCTL
TIMER2_PWMDTCTL
TIMER3_PWMDTCTL
TIMER0_PWMBRKCTL
TIMER1_PWMBRKCTL
TIMER2_PWMBRKCTL
TIMER3_PWMBRKCTL
TIMER0_PWMSWBRK
TIMER1_PWMSWBRK
TIMER2_PWMSWBRK
TIMER3_PWMSWBRK
TIMER0_PWMINTSTS1
TIMER1_PWMINTSTS1
TIMER2_PWMINTSTS1
TIMER3_PWMINTSTS1
EPWM_CTL0
Secure
0x4005_0058
0x4005_0158
0x4005_1058
0x4005_1158
0x4005_0070
0x4005_0170
0x4005_1070
0x4005_1170
0x4005_007C
0x4005_017C
0x4005_107C
0x4005_117C
0x4005_008C
0x4005_018C
0x4005_108C
0x4005_118C
Secure
Secure or Non-secure
Secure or Non-secure
Secure
Secure
Secure or Non-secure
Secure or Non-secure
Secure
Secure
Secure or Non-secure
Secure or Non-secure
Secure
Secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
Secure or Non-secure
0x4005_8000/0x4005_9000
0x4005_8000/0x4005_9000
0x4005_8070/0x4005_9070
0x4005_8074/0x4005_9074
0x4005_8078/0x4005_9078
0x4005_80C8/0x4005_90C8
0x4005_80CC/0x4005_90CC
0x4005_80D0/0x4005_90D0
0x4005_80DC/0x4005_90DC
0x4005_80E4/0x4005_90E4
0x4005_80EC/0x4005_90EC
0x4005_A000/0x4005_B000
EPWM_CTL1
EPWM_DTCTL0_1
EPWM_DTCTL2_3
EPWM_DTCTL4_5
EPWM_BRKCTL0_1
EPWM_BRKCTL2_3
EPWM_BRKCTL4_5
EPWM_SWBRK
EPWM_INTEN1
EPWM_INTSTS1
BPWM_CTL0
Table 6.2-9 List of Registers with Write Protection
Dec. 25, 2020
Page 104 of 233
Rev. 1.00
6.2.11 System Timer (SysTick)
The Cortex® -M23 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-
on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be
used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register
(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter
transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than
an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “Arm® Cortex® -M23 Technical Reference Manual”
and “Arm® v8-M Architecture Reference Manual”.
6.2.12 Nested Vectored Interrupt Controller (NVIC)
The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the
stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC
from privileged mode. Any other user mode access causes a bus fault. You can access all NVIC
registers using byte, halfword, and word accesses unless otherwise stated. NVIC registers are located
within the SCS (System Control Space). All NVIC registers and system debug registers are little-
endian regardless of the endianness state of the processor.
The NVIC supports:
An implementation-defined number of interrupts, in the range 1-240 interrupts.
A programmable priority level of 0-3 for each interrupt; a higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority.
Interrupt tail-chaining.
An external Non maskable Interrupt (NMI)
WIC with Ultra-low Power Sleep mode support
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead. This provides low latency exception handling.
Dec. 25, 2020
Page 105 of 233
Rev. 1.00
6.2.13 Security Attribution Unit (SAU)
The Arm® Cortex® -M23 has an security attribution unit (SAU) to support hardware Arm® TrustZone®
technique. The NuMicro® M2354 supports up to 8 memory regions in SAU for secure code to
configure, and provides the memory alias architecture which can work only with proper setting of SAU,
IDAU and SCU. IDAU has already defined all memory regions that should be non-secure (refer to the
“Address Space Partition” section). Secure code should properly set these regions to non-secure by
setting SAU. However, secure code should overwrite NSC regions to secure regions to prevent from
being unexpectedly accessed by non-secure code.
SAU can be accessed by secure code. Non-secure access to all SAU registers will be RAZ/WI.
Dec. 25, 2020
Page 106 of 233
Rev. 1.00
6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
until CPU sets the Power-down enable bit PDEN (CLK_PWRCTL[7]) and core executes the WFI
instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to
leave Power-down mode. In Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal (HXT), 48 MHz internal high speed RC oscillator (HIRC48), 4 MHz internal medium
speed RC oscillator (MIRC) and 12 MHz internal high speed RC oscillator (HIRC) to reduce the overall
system power consumption. Figure 6.3-1 to Figure 6.3-3 show the clock generator and the overview of
the clock source control.
Dec. 25, 2020
Page 107 of 233
Rev. 1.00
BPWM0
CAN0
EADC
ECAP0
EPWM0
I2C0
CPU
CRC
CRYPTO
EBI
12 MHz
HIRC
HXT
1
0
PCLK0
PLL FOUT
4~24 MHz
FMC
CLK_PLLCTL[19]
GPIO
ISP
I2C2
I2S
KS
QEI0
12 MHz
4 MHz
HIRC
MIRC
PDMA0
PDMA1
SCU
111
RTC
110
101
SC0
48 MHz
HIRC48
LIRC
PLL
SC2
HCLK
32 kHz
SDH0
SRAM
USBH
1/(HCLKDIV+1)
011
010
001
QSPI0
SPI1
PLLFOUT
32.768 kHz
4~24 MHz
LXT
SPI3
HXT
000
TAMPER
TMR0
TMR1
TMR4
TMR5
TRNG
UART0
UART2
UART4
USBD
USCI0
WDT
CLK_CLKSEL0[2:0]
12 MHz
HIRC
1/2
1/2
1/2
111
011
010
001
000
HCLK
HCLK
HXT
LXT
CPUCLK
1
0
4~24 MHz
SysTick
32.768 kHz
4~24 MHz
HXT
SYST_CTRL[2]
CLK_CLKSEL0[5:3]
EWDT
PCLK1
ACMP
DAC
USBH
1
0
PLLFOUT
HIRC48
1/(USBDIV+1)
USBD
OTG
ECAP1
EPWM1
BPWM1
I2C1
CLK_CLKSEL0[8]
LCD
HIRC
11
10
01
00
OTG
HCLK
PLL
1/(SDH0DIV+1)
SDH0
QEI1
HXT
SC1
SPI0
CLK_CLKSEL0[21:20]
SPI2
TMR2
TMR3
UART1
UART3
UART5
USCI1
LIRC
11
10
01
LIRC
HCLK
11
10
WWDT
1/2048
HCLK
LXT
1/2048
WDT
EWWDT
32.768 kHz
EWDT
CLK_CLKSEL1[31:30]
CLK_CLKSEL1[7:6]
CLK_CLKSEL1[1:0]
CLK_CLKSEL1[5:4]
MIRC
LXT
1
1
0
LCD
LCDCP
0
MIRC1P2M
LIRC
CLK_CLKSEL1[3]
CLK_CLKSEL1[4]
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-1 Clock Generator Global View Diagram (1/3)
Dec. 25, 2020
Page 108 of 233
Rev. 1.00
12 MHz
HIRC
LIRC
111
101
TMR 0
TMR 1
TMR 4
TMR 5
TM0~TM1
PCLK0
EPWM 0
EPWM 1
BPWM 0
BPWM 1
PCLK0
TM0/TM1
PCLK0
LXT
011
010
32.768 kHz
4~24 MHz
001
000
HXT
PCLK1
PCLK0
CLK_CLKSEL1 [10: 8]
CLK_CLKSEL1 [14:12]
CLK_CLKSEL3 [10: 8]
CLK_CLKSEL3 [14:12]
12 MHz
HIRC
111
101
LIRC
PCLK1
TMR 2
TMR 3
TM2~TM3
TM2/TM3
011
010
PCLK1
PCLK1
32.768 kHz
001
000
LXT
12 MHz
PCLK0
4~24 MHz
HXT
HIRC
11
10
PCLK0
QSPI0
PLLFOUT
4~24 MHz
CLK_CLKSEL1 [18:16]
CLK_CLKSEL1 [22:20]
SPI1
SPI3
01
00
PLLFOUT
HXT
CLK_CLKSEL2[3:2]
CLK_CLKSEL2[7:6]
CLK_CLKSEL2[13:12]
PCLK
100
1/(UART0DIV+1)
1/(UART1DIV+1)
1/(UART2DIV+1)
1/(UART3DIV+1)
1/(UART4DIV+1)
1/(UART5DIV+1)
UART 0
UART 1
UART 2
UART 3
UART 4
UART 5
12 MHz
HIRC
LXT
011
010
001
000
12 MHz
HIRC
32.768 kHz
11
10
PCLK1
SPI0
SPI2
PCLK1
PLLFOUT
4~24 MHz
PLL
PLLFOUT
PLLFOUT
01
00
HXT
4~24 MHz
HXT
CLK_CLKSEL2[18:16]
CLK_CLKSEL2[22:20]
CLK_CLKSEL2[26:24]
CLK_CLKSEL2[30:28]
CLK_CLKSEL3[26:24]
CLK_CLKSEL3[30:28]
CLK_CLKSEL2[5:4]
CLK_CLKSEL2[11:10]
12 MHz
HIRC
11
10
PCLK0
PCLK0
1/(SC0DIV+1)
1/(SC2DIV+1)
SC0
SC2
PLLFOUT
PLL
01
00
4~24 MHz
HXT
12 MHz
CLK_CLKSEL3[1:0]
CLK_CLKSEL3[5:4]
11
HIRC
HCLK
LXT
HCLK
10
01
00
Clock Output
32.768 kHz
4~24 MHz
12 MHz
HIRC
11
10
HXT
PCLK1
PCLK1
1/(SC1DIV+1)
SC1
PLLFOUT
4~24 MHz
CLK_CLKSEL1[29:28]
PLL
01
00
HXT
Note:
Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
CLK_CLKSEL3[3:2]
Figure 6.3-2 Clock Generator Global View Diagram (2/3)
Dec. 25, 2020
Page 109 of 233
Rev. 1.00
LIRC
LXT
1
0
12 MHz
HIRC
PCLK0
PLL
11
10
RTC
1
0
LIRC32k
extLXT
PCLK0
I2S0
PLLFOUT
4~24 MHz
01
00
HXT
RTC_LXTCTL[7]
RTC_LXTCTL[6]
CLK_CLKSEL3[17:16]
PCLK1
1/(EADCDIV+1)
EADC
12MHz
HIRC
FMC
BOD
1
0
LIRC32k
extLXT
LIRC
TRNG
Note:
RTC_LXTCTL[6]
Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
Figure 6.3-3 Clock Generator Global View Diagram (3/3)
6.3.2
Clock Generator
The clock generator consists of 7 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from
external 4~24 MHz external high speed crystal (HXT) or 12 MHz internal high speed
oscillator (HIRC)
12 MHz internal high speed RC oscillator (HIRC)
4 MHz internal medium speed RC oscillator (MIRC)
48 MHz internal high speed RC oscillator (HIRC48)
32 kHz internal low speed RC oscillator (LIRC)
Dec. 25, 2020
Page 110 of 233
Rev. 1.00
LIRC32KEN (RTC_LXTCTL[0])
Internal 32 kHz
Oscillator
(LIRC32k)
C32KSEL(RTC_LXTCTL[6])
LXT
LXTEN (CLK_PWRCTL[1])
X32_IN
1
0
External 32.768
kHz Crystal
(extLXT)
X32_OUT
XT1_IN
HXTEN (CLK_PWRCTL[0])
HXT
External 4~24
MHz Crystal
(HXT)
PLLSRC (CLK_PLLCTL[19])
XT1_OUT
0
1
PLL FOUT
PLL
HIRCEN (CLK_PWRCTL[2])
Internal 12 MHz
Oscillator
(HIRC)
HIRC
LIRC
LIRCEN (CLK_PWRCTL[3])
Internal 32 kHz
Oscillator
(LIRC)
HIRC48EN (CLK_PWRCTL[18])
Internal 48 MHz
Oscillator
HIRC48
MIRC
(HIRC48)
MIRCEN (CLK_PWRCTL[21])
Internal 4 MHz
Oscillator
(MIRC)
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6.3-4 Clock Generator Block Diagram
Dec. 25, 2020
Page 111 of 233
Rev. 1.00
Each of these clock sources has certain stable time to wait for clock operating at stable frequency.
When clock source is enabled, a stable counter start counting and correlated clock stable index is set
to 1 after stable counter value reach a define value.
System and peripheral can use the clock as its operating clock only when correlate clock stable index
is set to 1. The clock stable index as shown in Table 6.3-1 will auto clear when user disables the clock
source.
Besides, the clock stable index of HXT, HIRC, MIRC, HIRC48 and PLL will auto clear when chip enter
power-down and clock stable counter will re-counting after chip wake-up if correlate clock is enabled.
Correlated Clock Stable
Index
Clock Source
Clock Source Enable Bit
HXT
LXT
HXTEN (CLK_PWRCTL[0])
HXTSTB (CLK_STATUS[0])
LXTSTB (CLK_STATUS[1])
PLLSTB (CLK_STATUS[2])
LIRCSTB (CLK_STATUS[3])
HIRCSTB (CLK_STATUS[4])
MIRCSTB (CLK_STATUS[5])
LXTEN (CLK_PWRCTL[1]) or LIRC32KEN (RTC_LXTCTL[0])
PD (CLK_PLLCTL[16])
PLL
LIRC
HIRC
MIRC
LIRCEN (CLK_PWRCTL[3])
HIRCEN (CLK_PWRCTL[2])
MIRCEN (CLK_PWRCTL[21])
HIRC48STB
(CLK_STATUS[6])
HIRC48
extLXT
LIRC32
HIRC48EN (CLK_PWRCTL[18])
LXTEN (CLK_PWRCTL[1])
EXTLXTSTB
(CLK_STATUS[8])
LIRC32STB
(CLK_STATUS[9])
LIRC32KEN (RTC_LXTCTL[0])
Table 6.3-1 Each Clock Source Enable Bit and Corresponding Stable Flag Table
System Clock and SysTick Clock
6.3.3
The system clock has 7 clock sources, which were generated from clock generator block. The clock
source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown
in Figure 6.3-5.
Dec. 25, 2020
Page 112 of 233
Rev. 1.00
HCLKSEL
(CLK_CLKSEL0[2:0])
111
110
100
HIRC
MIRC
CPUCLK
HIRC48
CPU
AHB
011
010
001
000
LIRC
HCLK
PCLK0
PCLK1
1/(HCLKDIV+1)
PLLFOUT
HCLKDIV
(CLK_CLKDIV0[3:0])
APB0
APB1
LXT
HXT
CPU in Power Down Mode
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-5 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled automatically.
When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop being
detected on the following condition: system clock source comes from HXT or system clock source
comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the HXTFIF
(CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE (CLK_CLKDCTL[5]) is set to 1.
HXT clock source stable flag, HXTSTB (CLK_STATUS[0]), will be cleared if HXT stops when using
HXT fail detector function. User can trying to recover HXT by disable HXT and enable HXT again to
check if the clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover
to oscillate after re-enable action and user can switch system clock to HXT again.
When LXT clock detector is enabled, the system clock will auto switch to LIRC if LXT clock stop being
detected on the following condition: system clock source comes from LXT. If LXT clock stop condition
is detected, the LXTFIF (CLK_CLKDSTS[1]) is set to 1 and chip will enter interrupt if LXTFIE
(CLK_CLKDCTL[5]) is set to 1. LXT clock source stable flag, LXTSTB (CLK_STATUS[1]), will be
cleared if LXT stops when using LXT fail detector function. User can trying to recover LXT by disable
LXT and enable LXT again to check if the clock stable bit is set to 1 or not. If LXT clock stable bit is set
to 1, it means LXT is recover to oscillate after re-enable action and user can switch system clock to
LXT again.
The HXT clock stopping detecting and system clock switch to HIRC procedure is shown in Figure 6.3-
6.
Dec. 25, 2020
Page 113 of 233
Rev. 1.00
Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC
Figure 6.3-6 HXT Stop Protect Procedure
HIRC
HCLK
1/2
1/2
1/2
other
011
010
001
000
CPUCLK
1
0
HXT
LXT
HXT
SysTick
EXSTCKEN
SYST_CTRL[2]
(CLK_AHBCLK[4])
CLK_CLKSEL0[5:3]
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-7 SysTick Clock Control Block Diagram
The clock source of SysTick in processor can use CPU clock or external clock (SYST_CTRL[2]). If
using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock source switch
depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block diagram is shown
in Figure 6.3-7.
6.3.4
Peripherals Clock
Each peripheral clock has its own clock source selection. Refer to the CLK_CLKSEL1, CLK_CLKSEL2
Dec. 25, 2020
Page 114 of 233
Rev. 1.00
and CLK_CLKSEL3 register.
6.3.5 Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are
disabled. Some clock sources and peripherals clock are still active in Power-down mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
– 32 kHz internal low speed RC oscillator (LIRC) clock
– 32.768 kHz external low speed crystal oscillator (LXT) clock
– 4 MHz internal medium speed RC oscillator (MIRC) clock when TIMER4~5 or LCDCP
select MIRC as peripheral clock source
Peripherals Clock
– when the modules adopt LXT or LIRC as clock source
– when TIMER4~5 or LCDCP select MIRC as peripheral clock source
6.3.6
Clock Output
This device is equipped with a power-of-2 frequency divider that is composed by 16 chained divide-by-
2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to CLKO function pin. Therefore, there are 16 options of power-of-2 divided clocks with the
frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]). When writing 1 to
CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to CLKOEN
(CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low state and
stays in low state.
If DIV1EN(CLK_CLKOCTL[5]) is set to 1, the clock output clock (CLKO_CLK) will bypass power-of-2
frequency divider. The output divider clock will be output to CLKO pin directly.
When entering Power-down mode, clock output does not output clock even if the CKO clock source is
LXT.
Dec. 25, 2020
Page 115 of 233
Rev. 1.00
Enable
divide-by-2 counter
FREQSEL
(CLK_CLKOCTL[3:0])
CLKOEN
(CLK_CLKOCTL[4])
16 chained
divide-by-2 counter
DIV1EN
(CLK_CLKOCTL[5])
1/2
1/22
1/23
…...
1/215 1/216
CLK1HZEN
0000
0001
:
(CLK_CLKOCTL[6])
CLKOCKEN
(CLK_APBCLK0[6])
16 to 1
MUX
HIRC
11
0
1
:
0
1
1110
CLKO
HCLK
10
1111
LXT
01
HXT
00
RTCCKSEL(RTC_LXTCTL[7])
CLKOSEL (CLK_CLKSEL1[29:28])
LIRC
LXT
0
1
1 Hz clock from RTC
/32768
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be turned on and
stable.
Figure 6.3-8 Clock Output Block Diagram
6.3.7
Share Registers
The clock controller shares part of register information to non-secure world with enable bits in
SYSSIAEN (SCU_SINFAEN[1]) register. Shared registers are enabled by default.
Shared Register Access
Clock Controller
R/W
NA
Read only
CLK_PWRCTL, CLK_AHBCLK, CLK_APBCLK0, CLK_APBCLK1, CLK_CLKSEL0,
CLK_CLKSEL1, CLK_CLKSEL2, CLK_CLKSEL3, CLK_CLKDIV0, CLK_CLKDIV1,
CLK_CLKDIV4, CLK_PLLCTL, CLK_STATUS
Write only
NA
Table 6.3-2 Clock Controller Share Register list
Dec. 25, 2020
Page 116 of 233
Rev. 1.00
6.4 Security Configuration Unit (SCU)
6.4.1 Overview
Security configuration unit is designed for Arm® TrustZone® , and used to configure the security and
privilege attribution of SRAM, GPIO and all other peripherals. SCU also collects AHB slaves’ security
and privilege violation response and generates SCU interrupt. SCU is also equipped with a timer to
monitor the duration of the core processor in non-secure state.
Note: For details on Arm® TrustZone® , refer to the section “Arm® TrustZone® ”
6.4.2
Features
Configure SRAM’s security and privilege attribution block by block
Configure GPIOs’ security and privilege attribution pin by pin
Configure peripherals’ security and privilege attribution
Generate secure and privilege violation interrupt
Equipped with a 24-bit timer as a non-secure state monitor
Monotonic firmware version counter
Debug protection mechanism
Product life-cycle management
Dec. 25, 2020
Page 117 of 233
Rev. 1.00
6.5
Arm® TrustZone®
The Arm® TrustZone® can be considered as a physical partition that divides the microcontroller into
Secure (Trusted) and Non-secure (Non-trusted) worlds according to memory address. The secure
world is an isolated execution environment, code and data loaded inside are protected and cannot be
accessed from Non-secure world. Code running at secure world is called secure code that can access
both secure and non-secure memories and peripherals; while code running at non-secure world is
called non-secure code that can only access non-secure memories and peripherals.
Figure 6.5-1 shows an example of a system divided into the secure world and non-secure world.
Green blocks indicate secure components, Red blocks indicate non-secure components and white
ones are both/either secure and/or non-secure accessible. When the core processor is in secure state
(left side of the figure), it belongs to secure world, which has its own MSP, PSP and VTOR registers
and can access the green, red, white blocks. Contrarily, when the core processor is in non-secure
state (right side of the figure), it belongs to non-secure world, which also has its own MSP, PSP and
VTOR registers, but, it can only access red and white blocks so that non-secure world components are
not able to impact secure world.
Secure World
Non-Secure World
SRAM
SRAM
CRYPTO
UART
I2C
CRYPTO
UART
I2C
Core
Processor
Core
Processor
SRAM
SRAM
MSP / PSP
VTOR
MSP / PSP
VTOR
DMA
Timer
RTC
DMA
Timer
RTC
Flash
Flash
Flash
Flash
SPI
SPI
NVIC
SCU
NVIC
SCU
By function calls
GPIO
GPIO
AHB5 / APB Bus
AHB5 / APB Bus
Figure 6.5-1 Secure World View and Non-secure World View on a Chip
In order to support TrustZone® to set up both secure world and non-secure world, Cortex® -M23
provides three security attributes. Each memory address is assigned with one of the security
attributes. These security attributes are listed below.
Non-secure (NS)
Addresses used for non-secure memory or non-secure peripheral's registers.
Secure (S)
Addresses used for secure memory or secure peripheral's registers.
Non-secure Callable (NSC)
A special type of secure memory region which can contain SG instructions. The SG
instruction allows a non-secure function calls to a secure function.
The address space partitioning is completed by Implementation Define Attribution Unit (IDAU) and
Security Attribution Unit (SAU) together. The IDAU is non-programmable, which defines static partition
Dec. 25, 2020
Page 118 of 233
Rev. 1.00
of address space. The static partition specifies the default security attribute of a memory region. In
contrast with IDAU, the SAU is programmable which provides dynamic partition of address space. The
dynamic partition is given by software programmer to specify the security attribute of a memory region.
The core processor is in secure state when executing instructions from secure memory. Otherwise, the
core processor is in non-secure state when executing instructions from non-secure memory. For
setting IDAU and SAU, refer to sections “Implementation Defined Attribution Unit (IDAU)” and “Security
Attribution Unit (SAU)” in “System Manager” chapter for more details.
The security attribute of Flash, SRAM and peripherals are assigned by TrustZone® related control
units. The NSCBA register in FMC is used to divide the APROM into two parts, one is secure and the
other is non-secure. The security attribute of SRAM and peripherals are assigned by programming
Secure Configuration Unit (SCU).
Whenever being reset, the M2354 is in secure state, that is, the core processor, Flash, SRAM and
peripherals are all in secure state. Therefore, the system boots in secure state. The boot code is
responsible to set up TrustZone® related control units in M2354 to partition address space and assign
non-secure resources that can be directly accessed from non-secure world.
6.5.1
Address Space Partition
The SAU and IDAU are the control units used to define security attribute of memory addresses. The
IDAU defines default partition of secure and non-secure addresses, while the SAU is programmable to
change the security attribute defined by IDAU.
6.5.1.1 Implementation Define Attribution Unit (IDAU)
The IDAU uses address bit 28 to distinguish between secure and non-secure world, i.e. the bit 28 of a
secure address is always 0, and the bit 28 of a non-secure address is always 1, except regions above
0xE000_0000.
The partition of 4GB address space is shown as Figure 6.5-2. Each region consists of a secure (bit 28
is 0) and a non-secure (bit 28 is 1) sub-regions, the size of a sub-region is 256 Mbytes. In order to
store entry functions for non-secure code, the security attribute of secure SRAM region is assigned as
non-secure callable (NSC). Similarly, the secure “Code” region is assigned as NSC but has an
exception at first 2 KB area. This first 2 KB area is defined as secure only to avoid accidental SG
instruction after power on.
Dec. 25, 2020
Page 119 of 233
Rev. 1.00
Region
Range
Memory Attribute
0xFFFFFFFF
0xF0000000
Exempted
Exempted
Non-secure
Secure
Device
System
0xE0000000
0xD0000000
0xC0000000
0xB0000000
0xA0000000
0x90000000
External Device
External RAM
Non-secure
Secure
Non-secure
Secure
0x80000000
0x70000000
Non-secure
Secure
0x60000000
0x50000000
Non-secure
Secure
Device
SRAM
Code
0x40000000
0x30000000
Non-secure
Secure+ NSC
Non-secure
Secure + NSC
0x20000000
0x10000000
0x00000800
0x00000000
Secure
0x00000000
Memory Partition
Figure 6.5-2 The 4 GB Memory Map Divided Into Secure and Non-secure Regions by IDAU
6.5.1.2 Security Attribution Unit (SAU)
The SAU is a MPU-like function unit inside Cortex® -M23. Up to 8 memory regions can be defined by
programming control registers of SAU.
Memory regions are enabled individually by programming SAU_RNR, SAU_RBAR and SAU_RLAR.
The memory region is enabled once RENABLE (SAU_RLAR[0]) is set to 1, and the security attribute is
defined by NSC (SAU_RLAR[1]):
NSC = 0, the memory region is Non-secure (NS).
NSC = 1, the memory region is Secure and Non-secure callable (NSC).
The security attribute of each memory region defined by SAU is either NS or NSC. Those memory
addresses not defined by SAU regions are treated as Secure. After all memory regions are set,
SAU_CTRL[0] should be set to 1 to enable SAU.
Both IDAU and SAU define the security attribute of a memory address. If the definitions are different,
the more secure attribute will be used for the memory address. The priority of the security attribute
from high to low is Secure > NSC > NS.
When the core processor attempts to access a target, e.g. a memory or peripheral register, the
security attribute of the target is decided by checking IDAU and SAU. If the core processor is non-
secure but the target is secure, a HardFault exception will be generated. Because non-specified
memory addresses are treated as secure, non-secure memory regions need to be defined for the core
Dec. 25, 2020
Page 120 of 233
Rev. 1.00
processor to access non-secure memory and non-secure peripheral registers. Besides, whole secure
code and SRAM regions are defined as NSC by IDAU. The size of NSC regions can be changed
according to the NSC entry functions included in application code. The example usage of SAU regions
is shown as Figure 6.5-3.
Not used
Not used
Not used
Not used
7
6
5
4
Allow core processor to successfully access
Non-secure peripherals
Define Non-secure peripheral region
(0x50000000~0x5FFFFFFF)
3
2
1
Define Non-secure SRAM region
(0x30000000~0x3FFFFFFF)
Allow core processor to successfully access
Non-secure SRAM
Define Non-secure code region
(0x10000000~0x1FFFFFFF)
Allow core processor to successfully access
Non-secure Flash
Define Non-secure callable area in
Secure code region
0
Figure 6.5-3 Typical Setting of SAU
Security Attribute Configuration
6.5.2
The previous section describes how to divide the address space of core processor view into secure
world and non-secure world. For M2354, the memory and peripherals can be assigned to either secure
or non-secure world during system initialization. The M2354 is designed to start execution in secure
state after reset. In other words, core processor and all system resources including Flash, SRAM and
peripherals are secure after reset. Then, the system initialization code may change some parts of the
system resources to be non-secure.
6.5.2.1 Security Attribute Configuration of Flash
The M2354 Flash memory is split into a number of different regions such as LDROM, APROM and
others. Most of the Flash regions are always secure and cannot be changed. The only one can be
changed is the APROM region. Non-secure APROM region is set by programming a special control
register, NSCBA (Non-secure base address). The NSCBA[23:0] indicates the starting address of non-
secure APROM and its value should be aligned with a Flash page size. The secure APROM region
starts from address 0x0 and ends at NSCBA[23:0] – 1, while the non-secure APROM region ranges
from NSCBA[23:0] to the end of APROM. For setting NSCBA, refer to FMC section for more details.
6.5.2.2 Security Attribute Configuration of SRAM and Peripherals
The secure state of SRAM blocks and all peripherals can be configured by Security Configuration Unit
(SCU), which contains a set of control registers used to assign the security attribute. Besides, the SCU
monitors bus transfers to detect unsecure access. The unsecure access is one of the following
conditions.
Dec. 25, 2020
Page 121 of 233
Rev. 1.00
Non-secure master peripheral tries to access a secure address (address bit 28 = 0).
Secure code or secure master peripheral uses non-secure address (address bit 28 = 1) to
access secure SRAM or peripheral.
When an unsecure access is detected, SCU blocks the access operation and generates a secure
alarm interrupt.
For more details, refer to the Security Configuration Unit (SCU) chapter.
6.5.3
System Address Map and Access Scheme
In the M2354 series, the Flash, SRAM and most peripherals can be assigned to be Secure or Non-
secure, but each of them can be accessed through either Secure address or Non-secure address
depending on its security attribute configuration. Core processor and master peripherals should use
correct address to access resources, i.e. the secure resource should be accessed by using secure
address. Similarly, the non-secure resource should be accessed by using non-secure address.
6.5.3.1 Permanent Secure Peripherals
The security attribute of some peripherals are always secure and cannot be changed for safety and
security. If necessary, the secure code should manage and provide functions for non-secure code to
access these peripherals. Table 6.5-1 lists these secure peripherals.
Peripheral
SYS
Function
Address
System Control Registers
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_8000 – 0x4000_8FFF
0x4000_C000 – 0x4000_CFFF
0x4002_F000 – 0x4002_FFFF
0x4004_0000 – 0x4004_0FFF
0x4005_0000 – 0x4005_0FFF
CLK
Clock Control Registers
NMI
NMI Control Registers
PDMA0
FMC
Peripheral DMA 0 Control Registers
Flash Memory Control Registers
Security Configuration Unit Registers
Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
SCU
WDT
TMR01
Table 6.5-1 Peripherals and Regions that are Always Secure
6.5.3.2 Secure Address vs. Non-secure Address
A memory or a peripheral register may have secure and non-secure address in system address map,
but the memory or register only responds to the address that is consistent with its security attribute.
The different access modes of secure and non-secure target are illustrated in Figure 6.5-4.
Suppose that SRAM block 0, 2, and 4 are in secure state, they will respond to an access when
address bit 28 is 0 (secure address), but will not respond to an access with address bit 28 is 1 (non-
secure address). In this example, SRAM block 1 and 3 are in non-secure state. Hence, these blocks
will only respond to an access when the address bit 28 is 1.
Dec. 25, 2020
Page 122 of 233
Rev. 1.00
SRAM Block 4
0x200XXXXX
inaccessible
Secure address
range
SRAM Block 2
inaccessible
SRAM Block 0
The same SRAM Memory which
contains secure and non-secure
blocks
inaccessible
SRAM Block 3
0x300XXXXX
Non-secure address
range
inaccessible
SRAM Block 1
Secure Region
inaccessible
Non-secure Region
Figure 6.5-4 Example of SRAM Divided Into Secure Block and Non-secure Block
6.5.3.3 Valid Access vs. Invalid Access
When core processor or a master peripheral is trying to access (read or write) a memory or register,
the result depends on the following conditions.
Non-secure code or master peripheral is not allowed to access a secure memory or
register.
A memory or register only responds to the related address which is consistent with its
security attribute.
Dec. 25, 2020
Page 123 of 233
Rev. 1.00
Secure
FMC
(NSCB
A)
SAU
(a)
(b-1)
(c-1)
Cortex-M23
Flash
IDAU
(
b
Non-secure
-
2
)
)
1
-
CPU bus
e
(
(c-2)
Secure
SRAM
Master
peripheral
(d)
(e-2)
SCU
Non-secure
(
c
-
2
)
(
e
-
Secure
3
)
Non-secure
Peripherals
Non-secure
Secure
Non-secure
AHB/APB Bus
Figure 6.5-5 Checking Point of Accesses
Figure 6.5-5 illustrates how the above conditions are checked by TrustZone® related control units.
When the core processor tries to fetch instructions or access data, the security attribute of the core
processor and target address are verified by SAU and IDAU (refer to (a)). If the core processor is in
non-secure state and target address is secure, a hard fault exception will be generated. The other
cases will go to next checkpoints (refer to (b-1) and (b-2)). If the non-secure code tries to read/write a
secure memory or register, the access will be blocked and a secure violation interrupt (SCU interrupt)
can be generated. If a secure code uses non-secure address to access a secure memory or register,
the operation has no effect. (refer to (c-1) and (c-2))
When a master peripheral tries to read/write a memory or register, the SCU will verify the access (refer
to (d)). When a non-secure master peripheral wants to access a secure memory or register, the
access will be blocked and a secure violation interrupt (SCU interrupt) can be generated. If a secure
master peripheral uses non-secure address to read/write a secure memory or register, the operation
has no effect.
The responses of the accesses from the core processor and master peripherals follow the rule called
memory access policy, which is described in the “Memory Access Policy (MAP)” section of “Security
Configuration Unit (SCU)” chapter.
Dec. 25, 2020
Page 124 of 233
Rev. 1.00
6.6 Flash Memory Controller (FMC)
6.6.1 Overview
The FMC is equipped with dual-bank on-chip embedded Flash (BANK0 and BANK1) for application.
Both BANK0 and BANK1 have 256/512 Kbytes space. Thus, the total size of application rom
(APROM) is 512K/1024K. A User Configuration block provides for system initiation in BANK0. A 16
Kbytes loader ROM (LDROM) is used for In-System-Programming (ISP) function in BANK0. A 3
Kbytes one-time-program ROM (OTP) is used for recording one-time-program data in BANK1. A 16K
Secure Bootloader is used to check boot code integrity and authenticity, and consists of native ISP
functions. A 4 Kbytes cache with zero wait cycle is used to improve Flash access performance. This
chip also supports In-Application-Programming (IAP) function. User switches the code executing
without chip reset after the embedded Flash is updated.
6.6.2
Features
Supports dual-bank Flash macro for safe firmware upgrade
Supports dual-bank remapping
Supports 512/1024 Kbytes application ROM (APROM)
Supports 16 Kbytes loader ROM (LDROM)
Supports 4 XOM (Execution Only Memory) regions to conceal user program in APROM.
Supports 8K Data Flash
Supports 16 bytes User Configuration block to control system initiation
Supports 3 Kbytes one-time-program ROM (OTP)
Supports 2 Kbytes page erase for all embedded Flash
Supports bank erase for APROM, except XOM regions.
Supports two level locks for protecting secure region and non-sec region.
Supports Secure Bootloader with native In-System-Programming (ISP) functions
Supports Secure Boot function for check boot code integrity and authenticity
Supports 32-bit/64-bit and multi-word Flash programming function
Supports fast Flash programming verification function
Supports CRC32 checksum calculation function
Supports Flash all one verification function
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory
Supports Non-Secure In-System-Programming (NS ISP) to update embedded Non-
Secure Flash memory
Supports cache memory to improve Flash access performance and reduce power
consumption
Dec. 25, 2020
Page 125 of 233
Rev. 1.00
6.7 General Purpose I/O (GPIO)
6.7.1 Overview
This chip has up to 106 General Purpose I/O pins to be shared with other function pins depending on
the chip configuration. These 106 pins are arranged in 8 ports named as PA, PB, PC, PD, PE, PF, PG
and PH. PA, PB and PE has 16 pins on port. PC and PD has 14 pins on port. PF has 12 pins on port.
PG has 10 pins on port. PH has 8 pins on port. Each of the 107 pins is independent and has the
corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
depending on CIOINI (CONFIG0[10]). Please refer to the M2354 Datasheet for detailed pin operation
voltage information about VDD, VDDIO and VBAT electrical characteristics. PA10, PA11, PA13~15,
PB0~15, PF2, PF3 are not support 5V tolerance.
6.7.2
Features
Four I/O modes:
– Quasi-bidirectional mode
– Push-Pull Output mode
– Open-Drain Output mode
– Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Drive and High Slew Rate I/O mode
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
– CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
– CIOINI = 1, all GPIO pins in input mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
Improve access efficiency by using single cycle I/O bus
Dec. 25, 2020
Page 126 of 233
Rev. 1.00
6.8 PDMA Controller (PDMA)
6.8.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.
There are two PDMA controller PDMA0 and PDMA1. PDMA0 is secure PDMA, PDMA1 can be
configured as secure or non-secure PDMA. Each PDMA controller has a total of 8 channels and each
channel can perform transfer between memory and peripherals or between memory and memory.
6.8.2
Features
Supports 8 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports 2 PDMA controller PDMA0 and PDMA1, PDMA0 is secure PDMA, PDMA1 can
be configured as secure or non-secure PDMA
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or
no increment
Supports software and USB, UART, USCI, SPI, EPWM, I2C, I2S, Timer, ADC, and DAC
request
Supports Scatter-gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
Supports stride function from channel 0 to channel 5
Supports enhanced stride function on channel 0 and channel1
Dec. 25, 2020
Page 127 of 233
Rev. 1.00
6.9 Timer Controller (TMR)
6.9.1 Overview
The timer controller includes six 32-bit timers, Timer0 ~ Timer5, allowing user to easily implement a
timer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement by
external capture pins.
The timer controller also provides the PWM generator function. In Timer0 ~ Timer3, each PWM
generator supports two PWM output channels in independent mode and complementary mode. The
output state of PWM output pin can be controlled by pin mask, polarity and break control, and dead-
time generator. In Timer4 and Timer5, each PWM generator supports only one PWM output channel.
The output state of PWM output pin can be controlled by polarity control, output enable control and
output channel select.
6.9.2
Features
6.9.2.1 Timer Function Features
Six sets of 32-bit timers, Timer0 ~ Timer5, each timer having one 24-bit up counter and
one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture event for interval measurement
Supports capture event to reset 24-bit up counter
Supports internal clock (HIRC, LIRC) and external clock (HXT, LXT) for capture event in
Timer0 ~ Timer3
Supports internal clock (HIRC, LIRC, MIRC) and external clock (HXT, LXT) for capture
event in Timer4 and Timer5
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Supports Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
EPWM, BPWM, EADC, DAC and PDMA function
Supports Timer4 and Timer5 time-out interrupt signal or capture interrupt signal to trigger
EADC and PDMA function
Supports internal capture triggered while internal ACMP output signal transition
Supports Inter-Timer trigger mode
Supports event counting source from internal USB SOF signal
6.9.2.2 PWM Function Features
In the Timer0 ~ Timer3 PWM,
Supports maximum clock frequency up to maximum PCLK
Supports independent mode for PWM generator with two output channels
Supports complementary mode for PWM generator with paired PWM output channel
Dec. 25, 2020
Page 128 of 233
Rev. 1.00
– 12-bit dead-time insertion with 12-bit prescale
Supports 12-bit prescale from 1 to 4096
Supports 16-bit PWM counter
– Up, down and up-down count operation type
– One-shot or auto-reload counter operation mode
Supports 16-bit compare register and period register and double buffer for period register
and compare register
Supports mask function and tri-state enable for each PWM output pin
Supports brake function
– Brake source from pin, analog comparator and system safety events (clock failed,
Brown-out detection, SRAM parity error and CPU lockup)
– Brake pin noise filter control for brake source
– Edge detect brake source to control brake state until brake status cleared
– Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
– PWM zero point, period point, up-count compared or down-count compared point
events
– Brake condition happened
Supports trigger EADC on the following events:
– PWM zero point, period, zero or period point, up-count compared or down-count
compared point events
In the Timer4 and Timer5 PWM,
Supports independent mode for PWM generator with one output channel
Supports 16-bit PWM counter
– Up count operation type
– One-shot or auto-reload counter operation mode
Supports 8-bit prescale from 1 to 256
Supports 16-bit compare register and period register and double buffer for period register
and compare register
Supports tri-state enable and polarity control for each PWM selectable output channel
Supports interrupt on the following events:
– PWM period point, up-count compared point events
Supports wake-up when interrupt occurs when clock source is LXT, LIRC or MIRC
PWM can generator output in Power-down mode
Supports trigger EADC and PDMA on the following events:
– PWM period point and up-count compared point events
Dec. 25, 2020
Page 129 of 233
Rev. 1.00
6.10 Watchdog Timer (WDT)
6.10.1 Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer
supports the function to wake up system from Idle/Power-down mode.
6.10.2 Features
20-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 220) and the time-out interval is 0.5 ms ~ 32.768 s if
WDT_CLK = 32 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026, 130, 18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]
in Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC
32kHz or LXT.
Dec. 25, 2020
Page 130 of 233
Rev. 1.00
6.11 Extra Watchdog Timer (EWDT)
6.11.1 Overview
The Extra Watchdog Timer (EWDT) is used to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake up system from Idle/Power-down mode.
6.11.2 Features
20-bit free running up counter for EWDT time-out interval
Selectable time-out interval (24 ~ 220) and the time-out interval is 0.5 ms ~ 32.768 s if
EWDT_CLK = 32 kHz.
System kept in reset state for a period of (1 / EWDT_CLK) * 63
Supports selectable EWDT reset delay period, including 1026, 130, 18 or 3 EWDT_CLK
reset delay period
Supports EWDT time-out wake-up function only if EWDT clock source is selected as LIRC
32kHz or LXT.
Dec. 25, 2020
Page 131 of 233
Rev. 1.00
6.12 Window Watchdog Timer (WWDT)
6.12.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software running to uncontrollable status by any unpredictable condition.
6.12.2 Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value
(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
Dec. 25, 2020
Page 132 of 233
Rev. 1.00
6.13 Extra Window Watchdog Timer (EWWDT)
6.13.1 Overview
The Extra Window Watchdog Timer (EWWDT) is used to perform a system reset within a specified
window period to prevent software running to uncontrollable status by any unpredictable condition.
6.13.2 Features
6-bit down counter value (CNTDAT, EWWDT_CNT[5:0]) and 6-bit compare value
(CMPDAT, EWWDT_CTL[21:16]) to make the EWWDT time-out window period flexible
Supports 4-bit value (PSCSEL, EWWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of EWWDT counter
EWWDT counter suspends in Idle/Power-down mode
Dec. 25, 2020
Page 133 of 233
Rev. 1.00
6.14 Real Time Clock (RTC)
6.14.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers
programmable time tick and alarm match interrupts. The data format of time and calendar messages
are expressed in BCD format. A digital frequency compensation feature is available to compensate
external crystal oscillator frequency accuracy.
6.14.2 Features
Supports external power pin VBAT.
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check.
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM.
Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable
in RTC_TAMSK and RTC_CAMSK.
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register.
Supports Leap Year indication in RTC_LEAPYEAR register.
Supports Day of the Week counter in RTC_WEEKDAY register.
Frequency of RTC clock source compensate by RTC_FREQADJ register.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm Match interrupt.
Supports 1 Hz clock output.
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated.
Supports Daylight Saving Time software control in RTC_DSTCTL.
Supports up 3 pairs dynamic loop tamper pin or 6 individual tamper pin.
Built-in LXT frequency monitor.
Supports 80 bytes spare registers and tamper pins detection to clear the content of these
spare registers.
Supports Flash mass erase operate will also clear the 80 bytes spare registers content.
Dec. 25, 2020
Page 134 of 233
Rev. 1.00
6.15 EPWM Generator and Capture Timer (EPWM)
6.15.1 Overview
The chip provides two EPWM generators － EPWM0 and EPWM1. Each EPWM supports 6 channels
of EPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
EPWM counter with 16-bit comparator. The EPWM counter supports up, down and up-down counter
types. EPWM uses comparator compared with counter to generate events. These events are used to
generate EPWM pulse, interrupt and trigger signal for EADC/DAC to start conversion.
The EPWM generator supports two standard EPWM output modes: Independent mode and
Complementary mode, they have different architecture. There are two output functions based on
standard output modes: Group function and Synchronous function. Group function can be enabled
under Independent mode or complementary mode. Synchronous function only enabled under
complementary mode. Complementary mode has two comparators to generate various EPWM pulse
with 12-bit dead-time generator and another free trigger comparator to generate trigger signal for
EADC. For EPWM output control unit, it supports polarity output, independent pin mask and brake
functions.
The EPWM generator also supports input capture function. It supports latch EPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition is
happened. Capture function also support PDMA to transfer captured data to memory.
6.15.2 Features
6.15.2.1 EPWM Function Features
Supports maximum clock frequency up to maximum PLL frequency
Supports up to two EPWM modules, each module provides 6 output channels
Supports independent mode for EPWM output/Capture input channel
Supports complementary mode for 3 complementary paired EPWM output channel
– Dead-time insertion with 12-bit resolution
– Synchronous function for phase control
– Two compared values during one period
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit resolution EPWM counter
– Up, down and up/down counter operation type
Supports one-shot or auto-reload counter operation mode
Supports group function
Supports synchronous function
Supports mask function and tri-state enable for each EPWM pin
Supports brake function
– Brake source from pin, analog comparator and system safety events (clock failed,
SRAM parity error, Brown-out detection and CPU lockup).
– Noise filter for brake source from pin
– Leading edge blanking (LEB) function for brake source from analog comparator
– Edge detect brake source to control brake state until brake interrupt cleared
Dec. 25, 2020
Page 135 of 233
Rev. 1.00
– Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
– EPWM counter matches 0, period value or compared value
– Brake condition happened
Supports trigger EADC/DAC on the following events:
– EPWM counter matches 0, period value or compared value
– EPWM counter match free trigger comparator compared value (only for EADC)
– Supports EPWM trigger EADC event prescaler feature
Supports EPWM output accumulator stop counter mode
Supports Fault Detect Function.
6.15.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for EPWM all channels
Dec. 25, 2020
Page 136 of 233
Rev. 1.00
6.16 Basic PWM Generator and Capture Timer (BPWM)
6.16.1 Overview
The chip provides two BPWM generators － BPWM0 and BPWM1. Each BPWM supports 6 channels
of BPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
BPWM counter with 16-bit comparator. The BPWM counter supports up, down and up-down counter
types, all 6 channels share one counter. BPWM uses the comparator compared with counter to
generate events. These events are used to generate BPWM pulse, interrupt and trigger signal for
EADC to start conversion. For BPWM output control unit, it supports polarity output, independent pin
mask and tri-state output enable.
The BPWM generator also supports input capture function to latch BPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition is
happened.
6.16.2 Features
6.16.2.1 BPWM Function Features
Supports maximum clock frequency up to maximum PLL frequency.
Supports up to two BPWM modules; each module provides 6 output channels
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit prescalar from 1 to 4096
Supports 16-bit resolution BPWM counter; each module provides 1 BPWM counter
– Up, down and up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt in the following events:
– BPWM counter matches 0, period value or compared value
Supports trigger EADC in the following events:
– BPWM counter matches 0, period value or compared value
6.16.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Dec. 25, 2020
Page 137 of 233
Rev. 1.00
6.17 Quadrature Encoder Interface (QEI)
6.17.1 Overview
There are two Quadrature Encoder Interfaces (QEI) controllers in this device. The QEI decodes speed
of rotation and motion sensor information and can be used in any application that uses a quadrature
encoder for feedback.
6.17.2 Features
Up to two QEI controllers, QEI0 and QEI1.
Two QEI phase inputs, QEA and QEB; One Index input.
A 32-bit up/down Quadrature Encoder Pulse Counter (QEI_CNT)
A 32-bit software-latch Quadrature Encoder Pulse Counter Hold Register
(QEI_CNTHOLD)
A 32-bit Quadrature Encoder Pulse Counter Index Latch Register (QEI_CNTLATCH)
A 32-bit Quadrature Encoder Pulse Counter Compare Register (QEI_CNTCMP) with a
Pre-set Maximum Count Register (QEI_CNTMAX)
One QEI control register (QEI_CTL) and one QEI Status Register (QEI_STATUS)
Four Quadrature encoder pulse counter operation modes
– Support x4 free-counting mode
– Support x2 free-counting mode
– Support x4 compare-counting mode
– Support x2 compare-counting mode
Encoder Pulse Width measurement mode
Input frequency of QEA/QEB/IDX without noise filter must be lower than PCLK/4
Input frequency of QEA/QEB/IDX with noise filter must be lower than Noise Filter Clk/8
Dec. 25, 2020
Page 138 of 233
Rev. 1.00
6.18 Enhanced Input Capture Timer (ECAP)
6.18.1 Overview
This device provides up to two units of Input Capture Timer/Counter whose capture function can detect
the digital edge-changed signal at channel inputs. Each unit has three input capture channels. The
timer/counter is equipped with up counting, reload and compare-match capabilities.
6.18.2 Features
Up to two Input Capture Timer/Counter units, CAP0 and CAP1.
Each unit has 3 input channels.
Each unit has its own interrupt vector.
Each input channel has its own capture counter hold register.
24-bit Input Capture up-counting timer/counter.
With noise filter in front end of input ports.
Edge detector with three options:
– Rising edge detection
– Falling edge detection
– Both edge detection
Captured events reset and/or reload capture counter.
Supports compare-match function.
Dec. 25, 2020
Page 139 of 233
Rev. 1.00
6.19 UART Interface Controller (UART)
6.19.1 Overview
The chip provides six channels of Universal Asynchronous Receiver/Transmitters (UART). The UART
controller performs Normal Speed UART and supports flow control function. The UART controller
performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial
conversion on data transmitted from the CPU. Each UART controller channel supports ten types of
interrupts. The UART controller also supports IrDA SIR, LIN and RS-485 function modes and auto-
baud rate measuring function.
6.19.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
– Support 9600 bps for UART_CLK is selected LXT.
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
– Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
– Supports for 3/16 bit duration for normal mode
Supports LIN function mode (Only UART0 /UART1 with LIN function)
– Supports LIN master/slave mode
– Supports programmable break generation function for transmitter
– Supports break detection function for receiver
Supports RS-485 function mode
– Supports RS-485 9-bit mode
– Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
Dec. 25, 2020
Page 140 of 233
Rev. 1.00
Support Single-wire function mode.
UART Feature
UART0/ UART1
UART2/UART3/
UART4/ UART5
SC_UART
USCI-UART
TX: 1byte
RX: 2byte
FIFO
16 Bytes
16 Bytes
4 Bytes
Auto Flow Control (CTS/RTS)
IrDA
√
√
√
√
√
√
√
√
-
-
-
-
-
-
-
√
-
LIN
-
RS-485 Function Mode
nCTS Wake-up
Incoming Data Wake-up
√
√
√
√
√
√
-
Received
Data
FIFO
reached
√
√
√
√
-
-
threshold Wake-up
RS-485 Address Match (AAD mode)
Wake-up
-
Auto-Baud Rate Measurement
STOP Bit Length
Word Length
√
√
-
√
1, 1.5, 2 bit
1, 1.5, 2 bit
1, 2 bit
1, 2 bit
5, 6, 7, 8 bits
5, 6, 7, 8 bits
5, 6, 7, 8 bits
6~13 bits
Even / Odd Parity
Stick Bit
√
√
√
√
√
√
-
-
Note: √= Supported
Table 6.19-1 NuMicro® M2354 Series UART Features
Dec. 25, 2020
Page 141 of 233
Rev. 1.00
6.20 Smart Card Host Interface (SC)
6.20.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.20.2 Features
ISO 7816-3 T = 0, T = 1 compliant
EMV2000 compliant
Three ISO 7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times
processing
Supports auto direct / inverse convention function
Supports transmitter and receiver error retry and error number limiting function
Supports hardware activation sequence process, and the time between PWR on and CLK
start is configurable
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detected the card removal
Supports UART mode
– Full duplex, asynchronous communications
– Separates receiving / transmitting 4 bytes entry FIFO for data payloads
– Supports programmable baud rate generator
– Supports programmable receiver buffer trigger level
– Programmable transmitting data delay time between the last stop bit leaving the TX-
FIFO and the de-assertion by setting EGT (SCn_EGT[7:0])
– Programmable even, odd or no parity bit generation and detection
– Programmable stop bit, 1- or 2- stop bit generation
Dec. 25, 2020
Page 142 of 233
Rev. 1.00
6.21 I2S Controller (I2S)
6.21.1 Overview
The I2S controller consists of I2S protocol to interface with external audio CODEC. Two 16-level depth
FIFO for reading path and writing path respectively are capable of handling 8/16/24/32 bits audio data
sizes. A PDMA controller handles the data movement between FIFO and memory.
6.21.2 Features
Supports Master mode and Slave mode
Capable of handling 8, 16, 24 and 32 bits data sizes in each audio channel
Supports monaural and stereo audio data
Supports I2S protocols: Philips standard, MSB-justified, and LSB-justified data format
Supports PCM protocols: PCM standard, MSB-justified, and LSB-justified data format
PCM protocol supports TDM multi-channel transmission in one audio sample, and the
number of data channel can be set as 2, 4, 6, or 8
Provides two 16-level FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two PDMA requests, one for transmitting and the other for receiving
Dec. 25, 2020
Page 143 of 233
Rev. 1.00
6.22 Serial Peripheral Interface (SPI)
6.22.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
M2354 series contains up to four sets of SPI controllers performing a serial-to-parallel conversion on
data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device. Each SPI controller can be configured as a master or a slave device and supports
the PDMA function to access the data buffer. Each SPI controller also supports I2S mode to connect
external audio CODEC.
6.22.2 Features
SPI Mode
– Up to four sets of SPI controllers
– Supports Master or Slave mode operation
– Configurable bit length of a transaction word from 8 to 32-bit
– Provides separate 4-level depth transmit and receive FIFO buffers
– Supports MSB first or LSB first transfer sequence
– Supports Byte Reorder function
– Supports Byte or Word Suspend mode
– Supports PDMA transfer
– Supports 3-Wire, no slave selection signal, bi-direction interface
– Supports one data channel half-duplex transfer
– Supports receive-only mode
I2S Mode
– Supports Master or Slave
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Each provides two 4-level FIFO data buffers, one for transmitting and the other for
receiving
– Supports monaural and stereo audio data
– Supports PCM mode A, PCM mode B, I2S and MSB justified data format
– Supports two PDMA requests, one for transmitting and the other for receiving
Dec. 25, 2020
Page 144 of 233
Rev. 1.00
6.23 Quad Serial Peripheral Interface (QSPI)
6.23.1 Overview
The Quad Serial Peripheral Interface (QSPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction
interface. The M2354 series contains one QSPI controller performing a serial-to-parallel conversion on
data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device.
The QSPI controller supports 2-bit transfer mode to perform full-duplex 2-bit data transfer and also
supports Dual and Quad I/O transfer mode and the controller supports the PDMA function to access
the data buffer.
6.23.2 Features
– Supports Master or Slave mode operation
– Supports 2-bit transfer mode
– Supports Dual and Quad I/O transfer mode
– Configurable bit length of a transaction word from 8 to 32-bit
– Provides separate 8-level depth transmit and receive FIFO buffers
– Supports MSB first or LSB first transfer sequence
– Supports Byte Reorder function
– Supports Byte or Word Suspend mode
– Supports PDMA transfer
– Supports 3-Wire, no slave selection signal, bi-direction interface
– Supports one data channel half-duplex transfer
– Supports Transmit Double Transfer Rate Mode (TX DTR mode)
– Supports receive-only mode
Dec. 25, 2020
Page 145 of 233
Rev. 1.00
6.24 USCI - Universal Serial Control Interface Controller (USCI)
6.24.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
6.24.2 Features
The controller can be individually configured to match the application needs. The following protocols
are supported:
UART
SPI
I2C
Dec. 25, 2020
Page 146 of 233
Rev. 1.00
6.25 I2C Serial Interface Controller (I2C)
6.25.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
There are three sets of I2C controllers which support Power-down wake-up function.
6.25.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the I2C bus include:
Supports up to three I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflow
Programmable clocks allow for versatile rate control
Supports 7-bit addressing and 10-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports setup/hold time programmable
Supports Bus Management (SM/PM compatible) function.
Dec. 25, 2020
Page 147 of 233
Rev. 1.00
6.26 USCI – UART Mode
6.26.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of asynchronous
data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a
parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter being
independent, frames can start at different points in time for transmission and reception.
The UART controller also provides auto flow control. There are two conditions to wake-up the system.
6.26.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Supports 9-bit Data Transfer (Support 9-bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports PDMA capability
Supports Wake-up function (Data and nCTS Wakeup Only)
Dec. 25, 2020
Page 148 of 233
Rev. 1.00
6.27 USCI - SPI Mode
6.27.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows full
duplex transfer. It supports both Master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The
SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1
This SPI protocol can operate as Master or Slave mode by setting the SLAVE (USPI_PROTCTL[0]) to
communicate with the off-chip SPI Slave or Master device. The application block diagrams in Master
and Slave mode are shown below.
USCI SPI Master
USCI SPI Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
Master Receive Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_SS
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
Note: x = 0, 1
Figure 6.27-1 SPI Master Mode Application Block Diagram
USCI SPI Slave
USCI SPI Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
Slave Transmit Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_SS
Note: x = 0, 1
Figure 6.27-2 SPI Slave Mode Application Block Diagram
6.27.2 Features
Supports Master or Slave mode operation (the maximum frequency -- Master < fPCLK / 2,
Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
Dec. 25, 2020
Page 149 of 233
Rev. 1.00
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
Dec. 25, 2020
Page 150 of 233
Rev. 1.00
6.28 USCI - I2C Mode
6.28.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA
lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse
for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred
byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL. A transition on the
SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure
6.28-1 for more detailed I2C BUS Timing.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD_STA
tSU_STA
tSU_STO
tSU_DAT
tHD_DAT
Figure 6.28-1 I2C Bus Timing
The device’s on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 100B. When enable this port, the USCI interfaces to the I2C bus via
two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins function to I2C in
advance.
Note: Pull-up resistor is needed for I2C operation because the SDA and SCL are set to open-drain
pins when USCI is selected to I2C operation mode.
6.28.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by received ‘START’ symbol or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
Dec. 25, 2020
Page 151 of 233
Rev. 1.00
6.29 Controller Area Network (CAN)
6.29.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface. The CAN Core performs communication according to the CAN protocol version 2.0
part A and B. The bit rate can be programmed to values up to 1 Mbytesit/s. For the connection to the
physical layer, additional transceiver hardware is required.
For communication on a CAN network, individual Message Objects are configured. The Message
Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message
RAM. All functions concerning the handling of messages are implemented in the Message Handler.
These functions include acceptance filtering, the transfer of messages between the CAN Core and the
Message RAM, and the handling of transmission requests as well as the generation of the module
interrupt.
The register set of the C_CAN can be accessed directly by the software through the module interface.
These registers are used to control/configure the CAN Core and the Message Handler and to access
the Message RAM.
6.29.2 Features
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 MBit/s
32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Objects)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
16-bit module interfaces to the AMBA APB bus
Supports wake-up function
Dec. 25, 2020
Page 152 of 233
Rev. 1.00
6.30 Secure Digital Host Controller (SDH)
6.30.1 Overview
The Secure Digital Host Controller (SD Host) has DMAC unit and SD unit. The DMAC unit provides a
DMA (Direct Memory Access) function for SD to exchange data between system memory and shared
buffer (128 bytes), and the SD unit controls the interface of SD/SDHC. The SD host controller can
support SD/SDHC and cooperated with DMAC to provide a fast data transfer between system memory
and cards.
6.30.2 Features
AMBA AHB master/slave interface compatible, for data transfer and register read/write.
Supports single DMA channel.
Supports hardware Scatter-Gather function.
Using single 128 Bytes shared buffer for data exchange between system memory and
cards.
Synchronous design for DMA with single clock domain, AHB bus clock (HCLK).
Interface with DMAC for register read/write and data transfer.
Supports SD/SDHC card.
Completely asynchronous design for Secure Digital with two clock domains, HCLK and
Engine clock, note that frequency of HCLK should be higher than the frequency of
peripheral clock.
Dec. 25, 2020
Page 153 of 233
Rev. 1.00
6.31 External Bus Interface (EBI)
6.31.1 Overview
This chip is equipped with an external bus interface (EBI) for external device use. To save the
connections between an external device and a chip, EBI is operating at address bus and data bus
multiplex mode. The EBI supports three chip selects that can connect three external devices with
different timing setting requirements.
6.31.2 Features
Supports up to three memory banks
Supports dedicated external chip select pin with polarity control for each bank
Supports accessible space up to 1 Mbytes for each bank, actually external addressable
space is dependent on package pin out
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports address bus and data bus multiplexe mode
Supports address bus and data bus separate mode
Supports Timing parameters individual adjustment for each memory block
Supports LCD interface i80 mode
Supports PDMA mode
Supports variable external bus base clock (MCLK) which based on HCLK
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
Dec. 25, 2020
Page 154 of 233
Rev. 1.00
6.32 USB 1.1 Device Controller (USBD)
6.32.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant
with USB 2.0 full-speed device specification and supports Control/Bulk/Interrupt/Isochronous transfer
types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes from
the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There
are 1 Kbytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to
write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the
effective starting address of SRAM for each endpoint buffer through buffer segmentation register
(USBD_BUFSEGx).
There are 12 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data sequential
synchronization, endpoint states, current start address, transaction status, and data buffer status for
each endpoint.
There are four different interrupt events in this controller. They are the no-event-wake-up, device plug-
in or plug-out event, USB events, like IN ACK and OUT ACK, etc, and BUS events, like suspend and
resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in
interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt occurring, and
then check the related USB Endpoint Status Register (USBD_EPSTS0 and USBD_EPSTS1) to
acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB controller
will force the output of USB_D+ and USB_D- to level low and its function is disabled. After disabling
the SE0 bit, host will enumerate the USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus Specification
Revision 1.1.
6.32.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBDET, USB and
BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3ms
Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 1 Kbytes buffer size
Provides remote wake-up capability
Dec. 25, 2020
Page 155 of 233
Rev. 1.00
6.33 USB 1.1 Host Controller (USBH)
6.33.1 Overview
This chip is equipped with a USB 1.1 Host Controller (USBH) that supports Open Host Controller
Interface (OpenHCI, OHCI) Specification, a register-level description of a host controller, to manage
the devices and data transfer of Universal Serial Bus (USB).
The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer
between system memory and USB bus, port power control and port overcurrent detection.
The USBH is responsible for detecting the connect and disconnect of USB devices, managing data
transfer, collecting status and activity of USB bus, providing power control and detecting overcurrent of
attached USB devices.
6.33.2 Features
Compliant with Universal Serial Bus (USB) Specification Revision 1.1.
Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.
Supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.
Supports Control, Bulk, Interrupt and Isochronous transfers.
Supports an integrated Root Hub.
Supports a USB host port shared with USB device (OTG function).
Supports port power control and port overcurrent detection.
Supports DMA for real-time data transfer.
Dec. 25, 2020
Page 156 of 233
Rev. 1.00
6.34 USB On-The-Go (OTG)
6.34.1 Overview
The OTG controller interfaces to USB PHY and USB controllers which consist of a USB 1.1 host
controller and a USB 2.0 FS device controller. The OTG controller supports HNP and SRP protocols
defined in the “On-The-Go and Embedded Host Supplement to the USB 2.0 Revision 2.0
Specification”.
USB frame, including USB host, USB device, and OTG controller, can be configured as Host-only,
Device-only, ID dependent or OTG device mode defined in USBROLE (SYS_USBPHY[1:0]). In Host-
only mode, USB frame acts as USB host. USB frame can support both full-speed and low-speed
transfer. In Device-only mode, USB frame acts as USB device. USB frame only supports full-speed
transfer. In ID dependent mode, USB frame can be USB Host or USB device depending on USB_ID
pin state. In OTG device mode, the role of USB frame depends on the definition of OTG specification.
USB frame only supports full-speed transfer when OTG device acts as a peripheral.
6.34.2 Features
Built in USB PHY
Configurable to operate as:
– Host-only
– Device-only
– ID dependent: The role of USB frame is only dependent on USB_ID pin value--as USB
Host (USB_ID pin is low) or USB Device (USB_ID pin is high). Not support HNP or SRP
protocol.
– OTG device: dependent on USB_ID pin status to be A-device (USB_ID pin is low) or B-
device (USB_ID pin is high). Support HNP and SRP protocols.
Dec. 25, 2020
Page 157 of 233
Rev. 1.00
6.35 CRC Controller (CRC)
6.35.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.35.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
– CRC-CCITT: X16 + X12 + X5 + 1
– CRC-8: X8 + X2 + X + 1
– CRC-16: X16 + X15 + X2 + 1
– CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
– 8-bit write mode: 1-AHB clock cycle operation
– 16-bit write mode: 2-AHB clock cycle operation
– 32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
Dec. 25, 2020
Page 158 of 233
Rev. 1.00
6.36 Cryptographic Accelerator (CRYPTO)
6.36.1 Overview
The Crypto (Cryptographic Accelerator) includes a secure pseudo random number generator (PRNG)
core and supports AES, SHA/HMAC, RSA, and ECC algorithms.
The PRNG core supports 128, 163, 192, 224, 233, 255, 256, 283, 384, 409, 512, 521 and 571 bits
random number generation. (283~571 bits are only generated for Key Store.)
The AES accelerator is an implementation fully compliant with the AES (Advance Encryption
Standard) encryption and decryption algorithm. The AES accelerator supports ECB, CBC, CFB, OFB,
CTR, CBC-CS1, CBC-CS2, CBC-CS3, CCM and GCM mode.
The SHA accelerator is an implementation fully compliant with the SM3, SHA-160, SHA-224, SHA-
256, SHA-384, SHA-512 and corresponding HMAC (Keyed-Hash Message Authentication Code)
algorithms.
The ECC accelerator is an implementation fully compliant with elliptic curve cryptography by using
polynomial basis in binary field and prime filed.
The RSA accelerator is an implementation fully compliant with RSA cryptography, CRT decryption
algorithm and side-channel attack countermeasures algorithm.
The Crypto can get key from key store and/or put key to key store determined by the function of each
accelerator.
6.36.2 Features
PRNG
– Supports 128, 163, 192, 224, 233, 255, 256, 283, 384, 409, 512, 521 and 571 bits
random number generation (283~571 bits only generated for Key Store)
– Able to take the true random number seed from TRNG
AES
– Supports FIPS NIST 197
– Supports SP800-38A and addendum
– Supports 128, 192, and 256 bits key
– Supports both encryption and decryption
– Supports ECB, CBC, CFB, OFB, CTR, CBC-CS1, CBC-CS2 and CBC-CS3 modes
– Supports CCM mode, GCM mode and GHASH function
– Supports SM4 block cipher algorithm
– Supports key expander
– Supports one technique to improve side-channel attack protection ability
SHA
– Supports FIPS NIST 180, 180-2, 180-4
– Supports SHA-160, SHA-224, SHA-256, SHA-384 and SHA-512
– Supports SM3 Cryptographic Hash Algorithm
ECC
– Supports both prime field GF(p) and binary filed GF(2m)
Dec. 25, 2020
Page 159 of 233
Rev. 1.00
– Supports NIST P-192, P-224, P-256, P-384, and P-521
– Supports NIST B-163, B-233, B-283, B-409, and B-571
– Supports NIST K-163, K-233, K-283, K-409, and K-571
– Supports Curve25519
– Supports Public Key Cryptographic Algorithm SM2 Based on Elliptic Curves
– Supports point multiplication, addition and doubling operations in GF(p) and GF(2m)
– Supports modulus division, multiplication, addition and subtraction operations in GF(p)
– Supports three techniques to improve side-channel attack protection ability
RSA
– Supports both encryption and decryption with 1024, 2048, 3072 and 4096 bits
– Supports CRT decryption with 2048, 3072 and 4096 bits
– Supports three techniques to improve side-channel attack protection ability
Dec. 25, 2020
Page 160 of 233
Rev. 1.00
6.37 Enhanced 12-bit Analog-to-Digital Converter (EADC)
6.37.1 Overview
The chip contains one 12-bit successive approximation analog-to-digital converter (SAR ADC
converter) with 16 external input channels and 3 internal channels. The ADC converter can be started
by software trigger, EPWM0/1 triggers, BPWM0/1 triggers, Timer0~5 overflow pulse triggers, ADINT0,
ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin (EADC0_ST) input signal.
6.37.2 Features
Analog input voltage range: 0~VREF (Max to 3.6V)
Reference voltage from VREF pin
12-bit resolution and 10-bit accuracy is guaranteed
Up to 16 single-end analog external input channels or 8 pair differential analog input
channels
Up to 3 internal channels, they are band-gap voltage (VBG), temperature sensor (VTEMP),
and Battery power (VBAT
)
Four ADC interrupts (ADINT0~3) with individual interrupt vector addresses
Maximum ADC clock frequency is 80 MHz
Up to 5.71 MSPS conversion rate
Configurable ADC internal sampling time.
12-bit, 10-bit, 8-bit, 6-bit configurable resolution.
Supports calibration and load calibration words capability.
Supports three power saving modes:
– Deep Power-down mode
– Power-down mode
– Standby mode
Up to 19 sample modules:
– Each of sample modules which is configurable for ADC converter channel
EADC_CH0~15 and trigger source
– Sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap
voltage, temperature sensor, and battery power (VBAT
– Double buffer for sample control logic module 0~3
– Configurable sampling time for each sample module
)
– Conversion results are held in 19 data registers with valid and overrun indicators
An ADC conversion can be started by:
– Write 1 to SWTRG (EADC_SWTRG[n], n = 0~18)
– External pin EADC0_ST
– Timer0~5 overflow pulse triggers
– ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers
– EPWM/BPWM triggers
Dec. 25, 2020
Page 161 of 233
Rev. 1.00
Supports PDMA transfer
Conversion Result Monitor by Compare Mode
Dec. 25, 2020
Page 162 of 233
Rev. 1.00
6.38 True Random Number Generator (TRNG)
6.38.1 Overview
The purpose of True Random Number Generator (TRNG) is to generate the randomness by extracting
from physical phenomena.
6.38.2 Features
800 random bits per second
Provides the true random number seed for PRNG
Dec. 25, 2020
Page 163 of 233
Rev. 1.00
6.39 Key Store (KS)
6.39.1 Overview
The Key Store (KS) is the key management device and has a 4 Kbytes SRAM, 2 Kbytes Flash and
OTP for key storage. The Key Store is capable of providing a crypto engine to access or storing the
key while encryption, decryption and generation. The Key Store supports revoke key operation if the
key is unused. The Key Store is able to protect the key by data scrambling, data remanence
prevention and silent access.
6.39.2 Features
Supports programming interface for key management
Supports multiple key size
Supports 4 Kbytes SRAM, 2 Kbytes Flash and 544bytes OTP for key storage
Supports 32 keys for SRAM, 32 keys for Flash and 8 keys for OTP at most
Supports crypto engine access or store key in key store directly
Supports ECDH operation with ECC and PRNG engine
Supports to store middle data for RSA CRT and SCAP mode
Supports revoke operation for each key
Supports erase key in SRAM/Flash and revoke key in OTP while tamper detected
Supports integrity checking
Supports data scrambling at SRAM, Flash and OTP
Supports data remanence prevention at SRAM
Supports silent access for side-channel protection at SRAM, Flash and OTP
Dec. 25, 2020
Page 164 of 233
Rev. 1.00
6.40 LCD Controller
6.40.1 Overview
The LCD controller controls the device’s built-in voltage/current drivers, which can drive externally
connected LCD panels with up to 8 common planes (or called common electrodes, COMs) and 44
segments (SEGs). Every COM or SEG output pin of the device can supply the necessary voltage
waveform to the connected LCD panels.
The LCD controller provides several configuration registers, by which users can effectively control a
variety of LCD panels with specific considerations for display modes, driving capability, and power
consumption.
6.40.2 Features
Supports the following maximum COM/SEG combinations:
– 320 pixels (8-COM x 40-SEG)
– 252 pixels (6-COM x 42-SEG)
– 176 pixels (4-COM x 44-SEG)
– 104 pixels (8-COM x 13-SEG) for 64-pin package
Supports up to 8 COM output pins, multiplexed with GPIO pins
Supports up to 44 SEG output pins, multiplexed with GPIO pins
Supports 3 bias levels: 1/2, 1/3, and 1/4
Supports 8 duty ratios: 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, and 1/8
Supports both types A and B waveforms
Supports a clock frequency divider, programmable from 0 to 1023, to generate the LCD
operating frequency (FLCD
)
Supports LCD operating voltage (VLCD) from 2.6 V to 3.6 V
Selectable LCD operating voltage sources:
– VLCD (External dedicated VDD pin for LCD) power
– AVDD (Analog VDD) power
– Built-in charge pump
A built-in resistive network to generate required bias voltages
– supports 2 drive modes: low-drive and high-drive modes
– supports voltage buffers which are active only in the low-drive mode
Supports a configurable power-saving mode. During this mode,
– the resistive network temporarily changes to the low-drive mode, or
– the voltage buffers are temporarily turned off.
At the end of every frame, a dedicated flag is set and an interrupt can be programmed to
occur.
Supports a frame counter. At the end of frame counting, a dedicated flag is set and an
interrupt can be programmed to occur.
Supports LCD blinking capability. By using the frame counter, users have more flexibility
Dec. 25, 2020
Page 165 of 233
Rev. 1.00
to adjust the blinking frequency.
The LCD clock source is LIRC or LXT. LCD display or blinking can keep working even
when the chip is in the power-down modes, only if at least one of LIRC and LXT is active.
Supports a charging timer for the charge pump. By using this timer, users can estimate
the loading of the charge pump, and adjust, if necessary, its charging power.
Dec. 25, 2020
Page 166 of 233
Rev. 1.00
6.41 Tamper Controller (TC)
6.41.1 Overview
To protect the content of the Internal secrets from being attacked by hackers, the Tamper controller
provides various attack detection and attack event response. The attack detection includes pins, clock
and system voltage. When an attack is detected, the sensitive data like crypto session keys can be
cleared by the attack event response.
6.41.2 Features
Includes voltage, clock and I/O tamper detectors:
-
Voltage detector: detects voltage glitch including low voltage domain (LV) and high
voltage domain (HV).
HV detector detects if VDD ﹥4.0V
LV detector detects if LDO_CAP ﹥± 20%
-
-
Clock detector: detects if external clock (LXT) is failed or stopped
I/O tamper detector: detects GPF6~11 pins
Active shield in SRAM with power/GND and tamper I/O.
Provides event response after an attack detected:
– Clear key or data content in SRAM and Flash of Key Store, and revoke the OTP in
Key Store
– Clear RTC spare register
– Reset Crypto
– Chip reset
– Interrupt
– Wake up the system
Not supported in Deep Power-down mode.
Dec. 25, 2020
Page 167 of 233
Rev. 1.00
6.42 Digital to Analog Converter (DAC)
6.42.1 Overview
The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be configured to 12-or 8-
bit output mode and can be used in conjunction with the PDMA controller. The DAC integrates a
voltage output buffer that can be used to reduce output impendence and drive external loads directly
without having to add an external operational amplifier.
6.42.2 Features
Analog output voltage range: 0~AVDD
Supports 12-or 8-bit output mode.
Rail to rail settle time 8us.
.
Supports up to two 12-bit 1 MSPS voltage type DAC.
Reference voltage from VREF pin.
DAC maximum conversion updating rate 1 MSPS.
Supports voltage output buffer mode and bypass voltage output buffer mode.
Supports software and hardware trigger, including Timer0~3, EPWM0, EPWM1, and
external trigger pin to start DAC conversion.
Supports PDMA mode.
Supports group mode of synchronized update capability for two DACs.
Dec. 25, 2020
Page 168 of 233
Rev. 1.00
6.43 Analog Comparator Controller (ACMP)
6.43.1 Overview
The chip provides two comparators. The comparator output is logic 1 when positive input is greater
than negative input; otherwise, the output is 0. Each comparator can be configured to generate an
interrupt when the comparator output value changes.
6.43.2 Features
Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)
Up to two rail-to-rail analog comparators
Supports hysteresis function
– Supports programmable hysteresis window: 0mV, 10mV, 20mV and 30mV
Supports wake-up function
Supports programmable propagaion speed and low power consumption
Selectable input sources of positive input and negative input
ACMP0 supports:
– 4 multiplexed I/O pins at positive sources:
ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
– 4 negative sources:
ACMP0_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC0 output (DAC0_OUT)
ACMP1 supports
– 4 multiplexed I/O pins at positive sources:
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
– 4 negative sources:
ACMP1_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC0 output (DAC0_OUT)
Shares one ACMP interrupt vector for all comparators
Interrupts generated when compare results change (Interrupt event condition is
programmable)
Supports triggers for break events and cycle-by-cycle control for PWM
Supports window compare mode and window latch mode
Dec. 25, 2020
Page 169 of 233
Rev. 1.00
6.44 Peripherals Interconnection
6.44.1 Overview
Some peripherals have interconnections which allow autonomous communication or synchronous
action between peripherals without needing to involve the CPU. Peripherals interact without CPU
saves CPU resources, reduces power consumption, operates with no software latency and fast
response.
Dec. 25, 2020
Page 170 of 233
Rev. 1.00
7 APPLICATION CIRCUIT
7.1 Power Supply Scheme with External VREF
as close to AVDD as possible
L=30Z
1uF+0.1uF+0.01uF
EXT_PWR
AVDD
AVSS
as close to LDO as possible
EXT_PWR
VDD
SW
10uF
4.7uH
2.2uF
LDO_CAP
VSS
as close to VREF as possible
as close to the EXT_PWR as possible
L=30Z
2.2uF+1uF+470pF
VREF
AVSS
as close to VBAT as possible
0.1uF
VBAT
VSS
10uF+0.1uF
L=30Z
as close to VDD as possible
0.1uF*N
as close to VDDIO as possible
0.1uF
VDDIO
VSS
VDD
VSS
EXT_VSS
EXT_VSS
Dec. 25, 2020
Page 171 of 233
Rev. 1.00
7.2 Peripheral Application scheme
5V
USB Full Speed
OTG Slot Power Switch
(OTG Host)
64K x 16-bit
SRAM
LATCH
USB_VBUS
D
Q
Addr[15:0]
33R
USB_D-
33R
En
ALE
USB_D+
USB_ID
nCE
nOE
nWE
nLB
nCS
nRD
DVCC
EBI
nWR
nWRL
nWRH
100K
nUB
AD[15:0]
Data[15:0]
VDD
ICE_CLK
SWD
Interface
DVCC
ICE_DAT
nRESET
VSS
20pF
CS
SPI_SS
SPI_CLK
VDD
CLK
SPI Device
XT1_IN
SPI_MISO
SPI_MOSI
MISO
MOSI
VSS
4~24 MHz
20pF
20pF
crystal
DVCC
DVCC
XT1_OUT
4.7K
4.7K
M2354 series
Crystal
X32_IN
CLK
DIO
VDD
VSS
I2C_SCL
I2C_SDA
I2C Device
32.768 kHz
crystal
20pF
DVCC
X32_OUT
DVCC
SC_PWR
Reset
Circuit
10K
SC_RST
SC_CLK
Smart Card Slot
nRST
SC_DAT
SC_nCD
10uF/10V
ODB Port
CAN Transceiver
CAN_TX
CAN_RX
D
R
CAN_H
CAN_L
LDO_CAP
CAN
2.2uF
LDO
PC COM Port
RS 232 Transceiver
Audio codec
NUC8822
RIN
UART_RXD
UART_TXD
ROUT
TIN
Line In
Line Out
I2S
UART
TOUT
*Note: USB_ID, HSUSB _ID could be floating using USB or USB HS without OTG.
Dec. 25, 2020
Page 172 of 233
Rev. 1.00
8 ELECTRICAL CHARACTERISTIC
8.1 Absolute Maximum Ratings
Stresses above the absolute maximum ratings may cause permanent damage to the device. The
limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
8.1.1
Voltage Characteristics
Symbol
Description
Min
Max
4.0
4.0
4.0
50
Unit
V
[*1]
VDD-VSS
DC power supply
-0.3
[*1]
VDDIO-VSS
VDDIO Power Supply
-0.3
V
[*1]
VBAT-VSS
VBAT Power Supply
-0.3
V
ΔVDD
Variations between different VDD power pins
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
Input voltage on 5V-tolerance GPIO
Input Voltage on RTC domain (PF.6 ~ PF.11)
Input Voltage on any other pin[*2]
-
mV
mV
mV
mV
V
|VDD –AVDD
|
-
50
ΔVSS
-
50
|VSS - AVSS
|
-
50
VSS-0.3
VSS-0.3
VSS-0.3
5.5
4.0
4.0
VIN
V
V
Notes:
1. All main power (VDD, VDDIO, VBAT, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
2. Non 5V-tolerance PIN: PA.10, 11, 13 ~ 15; PB.0 ~ 15; PF.2, 3
Table 8.1-1 Voltage characteristics
8.1.2
Current Characteristics
Symbol
Description
Min
Max
200
100
100
100
20
Unit
[*1]
ΣIDD
IDDIO
IBAT
Maximum current into VDD
Maximum Current into VDDIO
Maximum Current into VBAT
Maximum current out of VSS
-
-
-
-
-
-
-
-
-
-
ΣISS
Maximum current sunk by a I/O Pin
mA
Maximum current sourced by a I/O Pin
Maximum current sunk by total I/O Pins[*2]
Maximum current sourced by total I/O Pins[*2]
Maximum injected current by a I/O Pin
Maximum injected current by total I/O Pins
20
IIO
100
100
±5
[*3]
IINJ(PIN)
[*3]
ΣIINJ(PIN)
±25
Dec. 25, 2020
Page 173 of 233
Rev. 1.00
Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.
Table 8.1-2 Current characteristics
8.1.3
Thermal Characteristics
The average junction temperature can be calculated by using the following equation:
T
T
+ (P
x
)
J
=
A
D
θJA
TA = ambient temperature (℃)
θJA = thermal resistance junction-ambient (℃/Watt)
P
D
= sum of internal and I/O power dissipation
Symbol
Description
Min
Typ
Max
Unit
-40
105
T
A
Operating ambient temperature
Operating junction temperature
Storage temperature
-
-
-
-40
-65
125
150
T
J
℃
T
ST
Thermal resistance junction-ambient
48-pin LQFP(7x7 mm)
-
-
-
60
58
-
-
-
℃/Watt
℃/Watt
℃/Watt
Thermal resistance junction-ambient
64-pin LQFP(7x7 mm)
[*1]
θJA
Thermal resistance junction-ambient
128-pin LQFP(14x14 mm)
38.5
Note:
1. Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions
Table 8.1-3 Thermal characteristics
8.1.4
EMC Characteristics
8.1.4.1 Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
8.1.4.2 Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
Dec. 25, 2020
Page 174 of 233
Rev. 1.00
A current injection is applied to each input, output and configurable I/O pin
8.1.4.3 Electrical fast transients (EFT)
In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts of
narrow high-frequency transients on the power distribution system..
Inductive loads:
1. Relays, switch contactors
2. Heavy-duty motors when de-energized etc.
The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 by
International ElectrotechnicalCommission (IEC).
Symbol
Description
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[*3]
Min
-2000
-500
-400
-4.4
Typ
Max
2000
500
Unit
[*1]
VHBM
-
-
-
-
V
[*2]
VCDM
LU[*3]
mA
kV
400
[*4] [*5]
VEFT
Fast transient voltage burst
+4.4
Notes:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Table 8.1-4 EMC characteristics
8.1.5
Package Moisture Sensitivity(MSL)
The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing
Pacakge
48-pin LQFP(7x7 mm) [*1]
MSL
MSL 3
MSL 3
MSL 3
64-pin LQFP(7x7 mm) [*1]
128-pin LQFP(14x14 mm) [*1]
Note:
1. Determined according to IPC/JEDEC J-STD-020
Table 8.1-5 Package Moisture Sensitivity(MSL)
Dec. 25, 2020
Page 175 of 233
Rev. 1.00
8.1.6
Soldering Profile
Figure 8.1-1 Soldering profile from J-STD-020C
Porfile Feature
Pb Free Package
3℃/sec. max
Average ramp-up rate (217℃ to peak)
Preheat temperature 150℃ ~200℃
Temperature maintained above 217℃
Time with 5℃ of actual peak temperature
Peak temperature range
60 sec. to 120 sec.
60 sec. to 150 sec.
> 30 sec.
260℃
Ramp-down rate
6℃/sec ax.
8 min. max
Time 25℃ to peak temperature
Note:
1. Determined according to J-STD-020C
Table 8.1-6 Soldering Profile
Dec. 25, 2020
Page 176 of 233
Rev. 1.00
8.2
General Operating Conditions
(VDD -VSS = 1.7 ~ 3.6V, TA = 25C, HCLK = 96 MHz unless otherwise specified.)
Symbol
TA
Parameter
Temperature
Min
-40
-
Typ
Max
105
96
Unit
℃
Test Conditions
-
-
fHCLK
VDD
Internal AHB clock frequency
MHz
Operation voltage
1.7
1.7
1.7
-
-
-
3.6
3.6
3.6
[*4]
VDDIO
VDDIO Operation voltage
VBAT Operation voltage
VBAT
[*1]
AVDD
Analog operation voltage
Analog reference voltage
LDO output voltage (PL0)
LDO output voltage (PL1)
LDO output voltage (PL2)
LDO output voltage (PL3)
Band-gap voltage
VDD
-
V
VREF
VLDO
VLDO
VLDO
VLDO
VBG
1.6
1.134
1.08
0.99
0.81
1.182
3.6
1.386
1.32
1.21
0.99
1.218
1.26
1.2
1.1
0.9
1.200
mV
ADC sampling time when reading
the band-gap voltage
[*3]
50
-
-
TVBG_ADC
S
[*2]
CLDO
LDO output capacitor on each pin
ESR of CLDO output capacitor
4.7
-
µF
[*3]
RESR
-
-
0.5
Ω
InRush current on voltage
regulator power-on (POR or
wakeup from Standby)
[*3]
IRUSH
-
100mA
mA
Note:
1.It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and
AVDD can be tolerated during power-on and power-off operation .
2.To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and the
closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor.
Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease
output noise and improves the load transient response.
3.Guaranteed by design, not tested in production
4.VDDIO must higer than or equal to VDD.
Table 8.2-1 General operating conditions
Dec. 25, 2020
Page 177 of 233
Rev. 1.00
8.3
DC Electrical Characteristics
Supply Current Characteristics
8.3.1
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
FHCLK/ LDO : 96MHz/ 1.26 V (PL0), 84MHz /1.2 V (PL1),
48MHz-6MHz/ 1.1V (PL2), 4MHz-32KHz/0.9 (PL3)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 3.3V unless otherwise specified.
VDD = AVDD = VDDIO = VBAT
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK
Program run CoreMark® code in Flash.
.
8.3.1.1 LDO Run Mode
Typ [*1] [*2]
Max[*1][*2]
= 85 °C
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
T = 105 °C
A
A
A
A
8.58
7.47
4.18
3.81
8.74
7.57
4.29
3.94
11.41
9.91
6.12
5.66
13.67
11.93
7.79
96 MHz
84 MHz
48 MHz(PLL)
7.29
48MHz(HIRC48)
Normal run mode, executed
from Flash, VDD = 3.3V, Vsw
without Inductance, all
peripherals disable
1.80
0.80
0.50
0.39
0.16
0.16
1.98
0.92
0.56
0.45
0.22
0.22
3.76
2.64
1.63
1.52
1.29
1.29
30.97
26.22
14.89
14.54
6.22
4.11
2.45
2.06
1.51
1.52
5.42
4.27
2.73
2.61
2.38
2.38
33.38
28.36
16.62
16.16
7.88
5.74
3.56
3.17
2.62
2.62
12 MHz
6 MHz
4 MHz
2 MHz
32.768 KHz
32 KHz
IDD_RUN
mA
27.81
23.53
12.73
12.62
4.17
27.97
23.64
12.91
12.82
4.40
96 MHz
84 MHz
48 MHz(PLL)
48MHz(HIRC48)
12 MHz
Normal run mode, executed
from Flash, VDD = 3.3V, Vsw
without Inductance all
peripherals enable
2.17
2.33
6 MHz
1.26
1.34
4 MHz
0.88
0.96
2 MHz
0.34
0.43
32.768 KHz
32 KHz
0.34
0.43
Dec. 25, 2020
Page 178 of 233
Rev. 1.00
Notes:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-1 Current consumption in LDO Normal Run mode
8.3.1.2 DC-DC Run Mode
Typ [*1] [*2]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
3.81
3.72
4.75
5.65
96 MHz
3.19
1.69
1.58
1.12
0.38
0.24
0.20
0.10
0.10
3.11
1.70
1.60
1.22
0.42
0.26
0.22
0.12
0.12
3.98
2.34
2.22
1.91
1.06
0.61
0.57
0.47
0.47
4.76
2.97
2.83
2.55
1.67
0.97
0.93
0.83
0.83
13.79
11.26
6.22
6.09
3.45
2.21
1.22
1.11
0.90
0.90
84 MHz
48 MHz(PLL)
48MHz(HIRC48)
12 MHz
Normal run mode, executed
from Flash, VDD = 3.3V,
Vsw with Inductance, all
peripherals disable
6 MHz
4 MHz
2 MHz
32.768 KHz
32 KHz
IDD_RUN
mA
12.25
9.93
5.01
5.00
2.05
0.91
0.49
0.36
0.16
0.16
11.71
9.52
4.93
4.93
2.13
0.96
0.51
0.39
0.19
0.19
12.82
10.43
5.58
5.49
2.82
1.60
0.87
0.74
0.54
0.54
96 MHz
84 MHz
48 MHz(PLL)
48MHz(HIRC48)
12 MHz
Normal run mode, executed
from Flash, VDD = 3.3V,
Vsw with Inductance all
peripherals enable
6 MHz
4 MHz
2 MHz
32.768 KHz
32 KHz
Notes:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-2 Current consumption in DC-DC Normal Run mode
Dec. 25, 2020
Page 179 of 233
Rev. 1.00
8.3.1.3 LDO Idle Mode
Typ [*1] [*2]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
3.03
2.84
1.75
1.39
1.20
0.50
0.33
0.31
0.16
0.16
3.21
2.97
1.86
1.51
1.37
0.61
0.39
0.37
0.22
0.22
5.73
5.20
3.64
3.23
3.15
2.32
1.46
1.44
1.28
1.28
7.92
7.17
5.28
4.85
4.80
3.94
2.55
2.52
2.37
2.37
26.77
22.87
13.70
13.33
7.16
5.35
3.34
3.05
2.60
2.60
96 MHz
84 MHz
48MHz(PLL)
48MHz(HIRC48)
12 MHz
Idle mode, executed from
Flash, VDD = 3.3V, Vsw
without Inductance all
peripherals disable
6 MHz
4 MHz
2 MHz
32.768 KHz
32 KHz
IDD_IDLE
mA
21.39
18.17
9.91
9.81
3.47
1.81
1.06
0.77
0.34
0.34
21.57
18.27
10.08
10.00
3.69
24.43
20.78
12.00
11.72
5.50
96 MHz
84 MHz
48MHz(PLL)
48MHz(HIRC48)
12 MHz
Idle mode, executed from
Flash, VDD = 3.3V, Vsw
without Inductance all
peripherals enable
1.96
3.73
6 MHz
1.14
2.24
4 MHz
0.86
1.95
2 MHz
0.42
1.51
32.768 KHz
32 KHz
0.43
1.51
Notes:
1. When analog peripheral blocks such as USB, ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional
power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-3 Current consumption in Idle mode
Dec. 25, 2020
Page 180 of 233
Rev. 1.00
8.3.1.4 DC-DC Idle Mode
Typ [*1] [*2]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
1.38
1.25
0.75
0.64
0.89
0.26
0.18
0.17
0.10
0.10
9.41
7.66
3.91
3.91
1.77
0.77
0.42
0.33
0.16
0.15
1.41
1.27
0.78
0.68
0.99
0.31
0.20
0.20
0.12
0.12
9.05
7.36
3.87
3.88
1.87
0.82
0.45
0.35
0.19
0.19
2.42
2.12
1.43
1.31
1.68
0.95
0.55
0.54
0.47
0.47
3.32
2.90
2.04
1.93
2.32
1.55
0.91
0.90
0.83
0.83
11.07
9.09
5.14
5.04
3.19
2.07
1.16
1.07
0.90
0.90
96 MHz
84 MHz
48MHz(PLL)
48MHz(HIRC48)
12 MHz
Idle mode, executed
from Flash, VDD = 3.3V,
Vsw with Inductance all
peripherals disable
6 MHz
4 MHz
2 MHz
32.768 KHz
32 KHz
IDD_IDLE
mA
10.12
8.28
4.52
4.45
2.56
1.46
0.80
0.71
0.54
0.54
96 MHz
84 MHz
48MHz(PLL)
48MHz(HIRC48)
12 MHz
Idle mode, executed
from Flash, VDD = 3.3V,
Vsw with Inductance all
peripherals enable
6 MHz
4 MHz
2 MHz
32.768 KHz
32 KHz
Notes:
1. When analog peripheral blocks such as USB, ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional
power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-4 Current consumption in DC-DC mode
Dec. 25, 2020
Page 181 of 233
Rev. 1.00
8.3.1.5 LDO Power-down Mode
TYP(TA = 25
°C)
MAX(TA =
105 °C)
Symbol
Conditions
LXT
LIRC
PLL
Power
Level
uint
1.7V
3.3V
3.6V
Fast
wake-up
-
-
-
-
-
-
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
258.91
237.98
200.91
152.19
264.62
242.46
203.59
154.04
264.88
242.50
203.48
153.88
266.16
243.87
204.58
154.77
274.93
245.17
207.21
157.42
281.11
250.07
210.15
159.54
281.41
250.11
210.08
159.16
282.84
251.61
211.28
160.33
4875.96
4314.36
3574.94
2329.90
4981.02
4372.59
3605.65
2352.31
5005.93
4390.12
3619.03
2353.85
5017.18
4407.97
3629.72
2362.64
Power-down mode,
all
disabled
(All sram banks
keep as normal
mode)
peripherals
Fast
wake-up
V
-
Power-down mode,
RTC/WDT/Timer/UA
RT/LCD
(All sram banks
keep as normal
mode)
enable
IDD_FWPD
Fast
wake-up
-
V
V
Power-down mode,
RTC/WDT/Timer/LC
D
(All sram banks
keep as normal
mode)
uA
enable
Fast
wake-up
V
Power-down mode,
WDT/Timer
LIRC,
RTC/UART/LCD use
LXT
(All sram banks
keep as normal
mode)
use
Power-down mode,
-
-
-
-
-
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
62.38
54.12
39.49
21.21
64.17
55.81
41.22
22.71
63.79
55.49
40.72
22.36
68.59
56.84
41.98
23.52
70.57
58.65
43.86
25.24
70.21
58.40
43.45
24.86
1565.83
1406.20
1187.61
848.59
all
peripherals
disabled
(All sram banks
keep as normal
mode)
Power-down mode,
RTC/WDT/Timer/UA
V
-
1563.98
1410.20
1187.92
851.84
RT/LCD
enable
(All sram banks
keep as normal
mode)
IDD_PD
Power-down mode,
RTC/WDT/Timer/LC
-
V
1565.23
1411.01
1187.97
851.80
D
use
LIRC
(All sram banks
keep as normal
mode)
Dec. 25, 2020
Page 182 of 233
Rev. 1.00
Power-down mode,
V
V
-
1.26
1.2
1.1
0.9
65.07
56.74
41.92
23.54
71.65
59.79
44.71
26.19
1566.51
1417.95
1194.93
854.18
WDT/Timer
LIRC,
use
RTC/UART/LCD use
LXT
(All sram banks
keep as normal
mode)
Low leakage Power-
-
-
-
-
-
0.9
0.9
24.72
26.31
27.08
28.84
924.27
926.48
down
mode,
all
peripherals disabled
Low leakage Power-
V
down
RTC/WDT/Timer/UA
RT enable
(All sram banks
mode,
keep as
mode)
normal
Low leakage Power-
down mode,
RTC/WDT/Timer
enable
(All sram banks
keep as normal
mode)
-
V
V
-
-
0.9
0.9
25.87
26.86
28.30
29.47
925.65
927.54
IDD_LLPD
Low leakage Power-
V
down
WDT/Timer
mode,
use
LIRC,
use
RTC/UART
LXT
(All sram banks
keep as
mode)
normal
Ultra Low leakage
Power-down mode,
-
-
-
-
-
-
0.8
0.8
0.8
0.8
17.77
19.34
18.80
19.81
20.09
21.72
21.30
22.35
771.97
773.86
773.14
all
peripherals
disabled
(All sram banks
keep as normal
mode)
Ultra Low leakage
Power-down mode,
RTC/WDT/Timer/UA
V
-
RT
enable
(All sram banks
keep as normal
mode)
IDD_ULLPD
Ultra Low leakage
Power-down mode,
RTC/WDT/Timer
enable
(All sram banks
keep as normal
mode)
-
V
V
Ultra Low leakage
Power-down mode,
V
774.62
WDT/Timer
use
LIRC,
use
RTC/UART
LXT
(All sram banks
Dec. 25, 2020
Page 183 of 233
Rev. 1.00
keep as normal
mode)
Standby
down mode(SPD),
all
disabled
(All sram banks
keep as normal
mode)
Power-
-
-
-
-
-
-
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
85.66
72.97
52.35
26.79
86.57
73.92
53.13
27.65
86.01
73.56
52.75
27.11
3.86
91.24
74.33
53.43
27.57
92.33
75.48
54.40
28.53
91.75
75.00
53.97
28.02
4.55
2402.94
2120.93
1711.06
1090.40
2404.77
2120.36
1711.70
1093.12
2403.02
2116.68
1711.99
1093.21
107.33
peripherals
Standby
down mode(SPD),
RTC enable
(All sram banks
keep as normal
mode)
Power-
V
-
IDD_SPD
Standby
down mode(SPD),
RTC enable
(All sram banks
keep as normal
mode)
Power-
-
V
Standby
down mode(SPD),
all
disabled
(Only
Power-
-
-
peripherals
3.44
3.97
96.84
bank0
2.71
3.23
81.60
sram0(4k) keep as
retention mode,
1.71
2.23
60.13
others set as shut
down mode )
Standby
down mode(SPD),
RTC
(Only
sram0(4k) keep as
retention mode,
others set as shut
down mode )
Power-
V
-
-
-
-
1.26
1.2
1.1
0.9
4.73
4.31
3.58
2.58
5.58
5.01
4.27
3.26
109.13
98.16
83.29
61.31
enable
bank0
IDD_SPD2
Standby
down mode(SPD),
RTC
(Only
sram0(4k) keep as
retention mode,
others set as shut
down mode )
Power-
-
V
1.26
1.2
1.1
0.9
4.26
3.84
3.11
2.11
5.08
4.51
3.77
2.76
108.15
97.30
82.57
60.93
enable
bank0
Deep Power-down
-
-
Floating
0.07
0.48
17.94
mode(DPD),
all
peripherals disabled
(all sram are in
power shut down
mode)
IDD_DPD
Dec. 25, 2020
Page 184 of 233
Rev. 1.00
Deep Power-down
V
-
-
-
Floating
Floating
0.93
0.06
1.50
0.47
19.22
mode(DPD),
enable
RTC
(all sram are in
power shut down
mode)
Deep Power-down
-
V
17.67
mode(DPD),
enable
RTC
(all sram are in
power shut down
mode)
Table 8.3-5 Chip Current Consumption in LDO Power-down mode
8.3.1.6 DC-DC Power-down Mode
TYP(TA = 25
°C)
MAX(TA =
105 °C)
Symbol
Conditions
LXT
LIRC
PLL
Power
Level
uint
1.7V
3.3V
3.6V
Fast
wake-up
-
-
-
-
-
-
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
231.27
201.00
153.86
106.86
231.69
203.22
156.89
109.37
236.18
206.94
159.08
110.21
241.40
211.04
162.05
112.04
155.29
137.95
117.09
93.33
2045.03
1755.97
1386.10
810.34
Power-down mode,
all
disabled
(All sram banks
keep as normal
mode)
peripherals
Fast
wake-up
V
-
155.86
139.60
119.17
95.21
2100.01
1783.92
1401.13
817.92
Power-down mode,
RTC/WDT/Timer/UA
RT/LCD
(All sram banks
keep as normal
mode)
enable
IDD_FWPD
Fast
wake-up
-
V
V
157.98
141.13
120.16
95.52
2097.15
1788.92
1410.10
819.93
Power-down mode,
RTC/WDT/Timer/LC
D
(All sram banks
keep as normal
mode)
uA
enable
Fast
wake-up
V
161.38
143.74
122.20
97.10
2113.30
1792.01
1411.26
822.89
Power-down mode,
WDT/Timer
LIRC,
RTC/UART/LCD use
LXT
(All sram banks
keep as normal
mode)
use
IDD_PD
Power-down mode,
-
-
-
1.26
1.2
1.1
0.9
73.40
61.49
40.24
18.72
40.60
33.20
23.86
12.96
742.08
640.11
516.23
316.42
all
peripherals
disabled
(All sram banks
keep as normal
mode)
Dec. 25, 2020
Page 185 of 233
Rev. 1.00
Power-down mode,
RTC/WDT/Timer/UA
V
-
-
-
-
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
75.78
63.34
41.88
20.06
76.05
63.61
41.87
19.80
77.30
65.02
43.28
21.09
42.39
34.62
25.24
14.21
42.38
34.66
25.04
13.85
43.56
35.88
26.26
15.14
744.41
643.06
518.44
318.96
743.49
643.01
517.96
318.33
746.19
645.97
520.28
319.84
RT/LCD
enable
(All sram banks
keep as normal
mode)
Power-down mode,
RTC/WDT/Timer/LC
-
V
V
D
use
LIRC
(All sram banks
keep as normal
mode)
Power-down mode,
V
WDT/Timer
LIRC,
use
RTC/UART/LCD use
LXT
(All sram banks
keep as normal
mode)
Low leakage Power-
-
-
-
-
-
0.9
0.9
19.30
20.64
13.25
14.54
317.03
319.06
down
mode,
all
peripherals disabled
Low leakage Power-
V
down
RTC/WDT/Timer/UA
RT enable
mode,
(All sram banks
keep as normal
mode)
Low leakage Power-
-
V
V
-
-
0.9
0.9
20.09
20.96
14.03
14.93
318.37
320.79
IDD_LLPD
down
mode,
RTC/WDT/Timer
enable
(All sram banks
keep as normal
mode)
Low leakage Power-
V
down
WDT/Timer
mode,
use
LIRC,
use
RTC/UART
LXT
(All sram banks
keep as normal
mode)
IDD_ULLPD
Ultra Low leakage
Power-down mode,
-
-
-
-
-
0.8
0.8
12.76
13.96
9.91
244.62
all
peripherals
disabled
(All sram banks
keep as normal
mode)
Ultra Low leakage
Power-down mode,
RTC/WDT/Timer/UA
V
11.18
246.49
RT
enable
(All sram banks
keep as normal
Dec. 25, 2020
Page 186 of 233
Rev. 1.00
mode)
Ultra Low leakage
Power-down mode,
RTC/WDT/Timer
enable
(All sram banks
keep as normal
mode)
-
V
V
-
-
0.8
0.8
13.52
14.50
10.74
11.79
245.57
247.25
Ultra Low leakage
Power-down mode,
V
WDT/Timer
use
LIRC,
use
RTC/UART
LXT
(All sram banks
keep as normal
mode)
Standby
down mode(SPD),
all
disabled
(All sram banks
keep as normal
mode)
Power-
-
-
-
-
-
-
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
1.26
1.2
1.1
0.9
108.38
88.16
56.42
24.20
109.22
89.02
57.11
24.97
108.26
88.35
56.57
24.46
4.35
55.40
43.81
29.75
13.44
56.41
44.88
30.71
14.43
55.67
44.19
30.15
13.92
3.00
1188.96
1008.70
776.52
420.41
1199.34
1009.90
778.44
422.16
1195.08
1009.44
778.36
421.71
58.97
peripherals
Standby
down mode(SPD),
RTC enable
(All sram banks
keep as normal
mode)
Power-
V
-
IDD_SPD
Standby
down mode(SPD),
RTC enable
(All sram banks
keep as normal
mode)
Power-
-
V
Standby
down mode(SPD),
all
disabled
(Only
Power-
-
-
peripherals
3.73
2.62
52.88
bank0
2.62
2.14
45.03
sram0(4k) keep as
retention mode,
1.43
1.53
33.05
others set as shut
down mode )
Standby
down mode(SPD),
RTC
(Only
sram0(4k) keep as
retention mode,
others set as shut
down mode )
Power-
V
-
-
1.26
1.2
1.1
0.9
5.25
4.59
3.48
2.31
4.03
3.65
3.17
2.58
60.32
54.04
46.59
34.78
enable
bank0
IDD_SPD2
Standby
Power-
-
V
-
1.26
4.72
3.52
59.67
Dec. 25, 2020
Page 187 of 233
Rev. 1.00
down mode(SPD),
1.2
1.1
0.9
4.09
2.99
1.83
3.15
2.66
2.06
53.64
46.08
33.94
RTC
enable
(Only
bank0
sram0(4k) keep as
retention mode,
others set as shut
down mode )
Deep Power-down
-
-
-
Floating
0.06
0.54
18.14
mode(DPD),
all
peripherals disabled
(all sram are in
power shut down
mode)
IDD_DPD
Deep Power-down
V
-
-
-
Floating
Floating
0.94
0.06
1.57
0.53
19.06
17.86
mode(DPD),
enable
RTC
(all sram are in
power shut down
mode)
Deep Power-down
-
V
mode(DPD),
enable
RTC
(all sram are in
power shut down
mode)
Table 8.3-6 Chip Current Consumption in DC-DC Power-down mode
Dec. 25, 2020
Page 188 of 233
Rev. 1.00
8.3.1.7 Current Consumption for RTC Domain
T
Symbol
Conditions
LXT
LDO
DCDC
Unit
A
1.08
1.97
3.93
8.19
12.94
1.00
1.42
2.38
4.81
7.93
0.80
0.98
1.10
1.35
1.66
0.11
0.89
2.76
6.92
11.65
0.09
0.39
1.27
3.63
6.67
0.08
0.11
0.15
0.31
0.59
1.08
2.12
3.92
8.09
12.99
1.00
1.49
2.38
4.79
7.96
0.80
0.99
1.10
1.36
1.70
0.11
1.01
2.75
6.91
11.51
0.09
0.44
1.27
3.62
6.53
0.08
0.11
0.15
0.31
0.51
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
RTC enabled, operating current, VBAT = 3.6V
V
RTC enabled, operating current, VBAT = 3.3V
RTC enabled, operating current, VBAT = 1.7V
RTC disabled, operating current, VBAT = 3.6V
RTC disabled, operating current, VBAT = 3.3V
RTC disabled, operating current, VBAT = 1.7V
V
V
V
V
V
IBAT
uA
Note: Guaranteed by characterization results, not tested in production.
Dec. 25, 2020
Page 189 of 233
Rev. 1.00
Table 8.3-7 Chip Current Consumption for RTC
On-Chip Peripheral Current Consumption
8.3.2
The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.
All GPIO pins are set as output high of push pull mode without multi-function
LDO = 1.26.
HCLK is the system clock, fHCLK = 96 MHz, fPCLK0, 1 = fHCLK
.
The result value is calculated by measuring the difference of current consumption
between all peripherals clocked off and only one peripheral clocked on
[*1]
Peripheral
IDD
Unit
PDMA0
422
423
PDMA1
ISP
0
EBI
266
158
1452
200
259
463
6
EXST
SDH0
CRC
CRPT
KS
TRACE
FMC
304
1248
201
462
361
85
USBH
SRAM0
SRAM1
SRAM2
GPA
uA
GPB
254
251
263
256
237
236
232
633
GPC
GPD
GPE
GPF
GPG
GPH
WDT
Dec. 25, 2020
Page 190 of 233
Rev. 1.00
RTC
TMR0
TMR1
TMR2
TMR3
CLKO
ACMP01
I2C0
189
770
788
455
487
192
253
573
258
559
1430
812
1346
827
1401
937
1285
775
1221
779
514
713
981
1298
562
1107
649
986
605
1005
831
829
1372
I2C1
I2C2
QSPI0
SPI0
SPI1
SPI2
UART0
UART1
UART2
UART3
UART4
UART5
TAMPER
CAN0
OTG
USBD
EADC
I2S0
EWDT
SC0
SC1
SC2
TMR4
TMR5
SPI3
Dec. 25, 2020
Page 191 of 233
Rev. 1.00
USCI0
USCI1
DAC
605
272
212
767
459
576
230
548
225
266
1036
547
217
4
EPWM0
EPWM1
BPWM0
BPWM1
QEI0
QEI1
LCD
TRNG
ECAP0
ECAP1
LCDFC
Note:
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part.
4. When the USB is turned on, add an additional power consumption per USB for the analog part.
5. When the DAC is turned on, add an additional power consumption per DAC for the analog part.
Table 8.3-8 Peripheral Current Consumption
8.3.3
Wakeup Timefrom Low-Power Modes
The wakeup times given in Table 8.2-1 is measured on a wakeup phase with a 12 MHz HIRC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
–
Fast-wakeup, power down, low leakage Power-down mode: the clock source is the RC
oscillator
–
Standby and Deep Power-down mode: the clock source is the clock that was set before
entering Sleep mode.
The wakeup times are measured from the wakeup event to the point in which the application
code reads the first instruction.
The clock source is the RC oscillator from HIRC
Symbol
Parameter
Typ
Unit
[*1]
0.835
tWU_IDLE
Wakeup from IDLE mode
[*1]
9.795
tWU_FWPD
Wakeup from Fast-wakeup Power-down mode
Wakeup from normal Power-down mode
µs
[*1]
21.295
tWU_NPD
Dec. 25, 2020
Page 192 of 233
Rev. 1.00
[*1]
[*1]
68.995
tWU_LLPD
Wakeup from low leakage Power-down mode
Wakeup from ultra low leakage power down
Wakeup from Standby Power-down mode (SPD)
Deep Power-down mode (DPD)
67.875
226.4
10445
0.5
tWU_ULLPD
[*1]
tWU_SPD
[*1]
tWU_DPD
[*2]
tET_IDLE
Enter to IDLE mode
[*2]
95.695
55.34
56.458
56.178
5.912
5.495
tET_DPD
Enter to deep Power-down mode
[*2]
tET_SPD
Enter to standby Power-down mode
Enter to ultra low Power-down mode
Enter to low Power-down mode
[*2]
tET_ULLPD
µs
[*2]
tET_LLPD
[*2]
tET_NPD
Enter to normal Power-down mode
Enter to fast wake-up Power-down mode
[*2]
tET_FWPD
Note:
1. Guaranteed by characterization results, not tested in production.
2. Guaranteed by Design
3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
Table 8.3-9 Low-power mode wakeup timings
8.3.4
I/O DC Characteristics
8.3.4.1 PIN input Characteristics
Symbol
Parameter
Min
Typ
Max Unit
Test Conditions
VDD = VDDIO = 3.6 V
VDD = VDDIO = 1.7 V
VDD = VDDIO = 3.6V
-
-
-
-
-
-
0.8
0.7
-
V
V
V
V
VIL1
Input Low Voltage (TTL input)
2.0
VIH1
VIL2
VIH2
Input High Voltage (TTL input)
Input Low Voltage (Schmitt input)
-
1.0
VDD = VDDIO = 1.7V
VDD = VDDIO = 3.6V
VDD = VDDIO = 1.7V
VDD = VDDIO = 3.6V
VDD = VDDIO = 1.7V
VDD =3.6V
-
-
-
0.3*VDD
V
-
0.3*VDD
0.7*VDD
0.7*VDD
-
-
-
-
-
-
V
V
Input High Voltage (Schmitt input)
Hysteresis voltage of (Schmitt input)
Input Leakage Current
[*1]
0.75
-
VHY
VDD = VDDIO = 3.6V, 0 < VIN
VDD, Open-drain or input only
mode
<
[*2]
-1
1
A
ILK
69
52
53
52
53
uA
KΩ
KΩ
KΩ
KΩ
VDD = VDDIO = 3.6V, VIN = 0V
VDD = VDDIO = 3.3V
IIL
Logic 0 Input Current (Quasi-bidirectional mode)
Input Pull Up Resistor
-
-
-
-
-
-
-
-
[*1]
RPU
VDD = VDDIO = 1.8V
VDD = VDDIO = 3.3V
[*1]
RPD
Input Pull down Resistor
VDD = VDDIO = 1.8V
Dec. 25, 2020
Page 193 of 233
Rev. 1.00
Notes:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
Table 8.3-10 I/O input characteristics
8.3.4.2
I/O Output Characteristics
Typ
Max
Symbol
Parameter
Min
Unit
Test Conditions
VDD = VDDIO = 3.3V
VIN=(VDD-0.4) V
[*1] [*2]
7.66
-
7.86
Source Current
ISR1
uA
(Quasi-bidirectional Mode, Set GPIO to output
HIGH, Apply GPIO pin VIN=(VDD-0.4)V for VDD
and measure the source current)
VDD = VDDIO = 1.8V
VIN=(VDD-0.4) V
[*1] [*2]
7.51
18.1
-
-
-
-
7.69
18.98
10.79
17.75
ISR2
uA
mA
mA
mA
VDD = VDDIO = 3.3V
VIN=(VDD-0.4) V
[*1] [*2]
Source Current
ISR3
(Push-pull Mode, Set GPIO to output HIGH,
Apply GPIO pin VIN=(VDD-0.4)V for VDD and
measure the source current)
VDD = VDDIO = 1.8V
VIN=(VDD-0.4) V
[*1] [*2]
10.04
17.10
ISR4
VDD = VDDIO = 3.3V
VIN= 0.4 V
Sink Current
[*1] [*2]
ISK1
(Quasi-bidirectional, Push-pull Mode, Set GPIO
to output LOW, Apply GPIO pin
VIN=(VSS+0.4)V for VSS and measure the
source current)
VDD = VDDIO = 1.8V
VIN= 0.4 V
[*1] [*2]
10.44
-
-
10.83
-
ISK2
mA
pF
[*1]
CIO
I/O pin capacitance
4.2
Notes:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS.
Table 8.3-11 I/O output characteristics
8.3.4.3
nRESET Output Characteristics
Min[*1]
Max[*1]
Symbol
Parameter
Typ
unit
Test Conditions
Negative going threshold
(Schmitt input), nRESET
-
-
0.3*VDD
V
VDD = 3.3V
VILR
Positive going threshold
(Schmitt Input), nRESET
0.7*VDD
-
-
V
VDD = 3.3V
VIHR
[*1]
53.40
54
32
32
32
32
32
54.51
KΩ
RRST
Internal nRESET pin pull up resistor
-
-
-
-
-
-
-
-
-
-
nRESET input filtered time
nRESET input filtered time under FWPD mode
nRESET input filtered time under PD mode
nRESET input filtered time under LLPD mode
nRESET input filtered time under ULLPD mode
[*1]
uS
VDD = 3.3V
tFR1
Dec. 25, 2020
Page 194 of 233
Rev. 1.00
0
0
-
-
-
-
nRESET input filtered time under SPD mode
nRESET input filtered time under DPD mode
Notes:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
Table 8.3-12 nRESET Input Characteristics
Dec. 25, 2020
Page 195 of 233
Rev. 1.00
8.4
AC Electrical Characteristics
8.4.1
12MHz Internal High Speed RC Oscillator (HIRC)
Symbol.
Parameter
Operating voltage
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
VDD
1.7
3
3.6
V
TA = 25 °C,
VDD = 3.3 V
Oscillator frequnecy
12
-
MHz
%
-
-
TA = 25 °C,
VDD = 3.3 V
-0.25
+0.25
fHRC
Frequency drift over temperarure and
volatge
TA = -40C ~ +105 °C,
-4
-
-
50
-
+4
70
20
%
µA
µs
VDD = 1.7 ~ 3.6V
[*1]
IHRC
Operating current
Stable time
TA = -40C ~ +105 °C,
[*2]
TS
-
VDD = 1.7 ~ 3.6V
Notes:
1. Guaranteed by characterization result, not tested in production.
2. Guaranteed by design.
Table 8.4-1 12 MHz Internal High Speed RC Oscillator(HIRC) characteristics
8.4.2
48MHz Internal High Speed RC Oscillator (HIRC48)
Symbol.
Parameter
Operating voltage
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
VDD
1.7
3.3
3.6
V
TA = 25 °C,
VDD = 3.3 V
Oscillator frequnecy
-
48
-
-
MHz
%
TA = 25 °C,
VDD = 3.3 V
-0.25
-4
+0.25
fHRC
Frequency drift over temperarure and
volatge
TA = -40C ~ +105 °C,
-
146
-
+4
230
20
%
µA
µs
VDD = 1.7 ~ 3.6V
[*1]
IHRC
Operating current
Stable time
TA = -40C ~ +105 °C,
[*2]
TS
-
VDD = 1.7 ~ 3.6V
Notes:
1. Guaranteed by characterization result, not tested in production
2. Guaranteed by design.
Table 8.4-2 48 MHz Internal High Speed RC Oscillator(HIRC) characteristics
Dec. 25, 2020
Page 196 of 233
Rev. 1.00
8.4.3
32 kHz Internal Low Speed RC Oscillator (LIRC)
Min[*1]
Typ
Max[*1]
Unit
Symbol
Parameter
Operating voltage
Test Conditions
VDD
1.7
3
3.6
V
TA = 25 °C,
VDD = 3.3 V
Oscillator frequnecy
-
32
-
-
kHz
%
TA = 25 °C,
VDD = 3.3 V
[*2]
FLRC
-0.4
+0.4
Frequency drift over temperarure
and volatge
TA=-40~105°C
VDD=1.7V~3.6V
-15
-
0.6
-
+15
0.8
%
µA
μs
[*1]
ILRC
Operating current
Stable time
-
-
VDD = 3.3V
TA=-40~105°C
VDD=1.7V~3.6V
[*2]
TS
500
Notes:
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design.
Table 8.4-3 32 kHz Internal Low Speed RC Oscillator(LIRC) characteristics
8.4.4
32kHz Internal Low Speed RC Oscillator in VBAT domain (LIRC)
Min[*1]
Typ
Max[*1]
Unit
Symbol
Parameter
Operating voltage
Test Conditions
VDD
1.7
3
3.6
V
TA = 25 °C,
VDD = 3.3 V
Oscillator frequnecy
-
32
-
-
kHz
%
TA = 25 °C,
VDD = 3.3 V
[*2]
FLRC
-0.4
+0.4
Frequency drift over temperarure
and volatge
TA=-40~105°C
VDD=1.7V~3.6V
-15
-
0.6
-
+15
0.8
%
µA
μs
[*1]
ILRC
Operating current
Stable time
-
-
VDD = 3.3V
TA=-40~105°C
VDD=1.7V~3.6V
[*2]
TS
500
Notes:
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design.
Table 8.4-4 32 kHz Internal Low Speed RC Oscillator(LIRC_ VBAT) characteristics
8.4.5
4MHz internal medium speed RC oscillator (MIRC)
Min[*1]
Typ
Max[*1]
Unit
Symbol
Parameter
Operating voltage
Oscillator frequnecy
Test Conditions
VDD
1.7
3
3.6
V
TA = 25 °C,
VDD = 3.3 V
[*2]
FLRC
-
4
-
MHz
Dec. 25, 2020
Page 197 of 233
Rev. 1.00
Min[*1]
Typ
Max[*1]
Unit
Symbol
Parameter
Test Conditions
TA = 25 °C,
VDD = 3.3 V
-0.25
-
+0.25
%
Frequency drift over temperarure
and volatge
TA=-40~105°C
VDD=1.7V~3.6V
-4
-
-
70
-
+4
85
20
%
µA
μs
[*1]
ILRC
Operating current
Stable time
VDD = 3.3V
TA=-40~105°C
VDD=1.7V~3.6V
[*2]
TS
-
Notes:
1.
2.
Guaranteed by characterization, not tested in production.
Guaranteed by design.
Table 8.4-5 4MHz internal medium speed RC oscillator (MIRC) characteristics
8.4.6
External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Operating voltage
Min[*1]
Typ
Max[*1]
3.6
-
Unit
V
Test Conditions
1.7
-
Rf
Internal feedback resister
Oscillator frequency
Temperature Range
1000
kΩ
fHXT
4
-
-
24
MHz
C
THXT
-40
105
4 MHz, Gain = L0, CL = 12.5
pF
-
-
-
-
-
-
-
300
450
560
720
1802
560
408
250
400
500
12 MHz, Gain = L1, CL = 12.5
pF
IHXT
Current consumption
µA
16 Mhz, Gain = L2, CL = 12.5
pF
24 MHz, Gain = L3, CL = 12.5
pF
640
-
4 MHz, Gain = L0, CL = 12.5
pF
12 MHz, Gain = L1, CL = 12.5
pF
-
-
TS
Stable time
Duty cycle
µs
%
16 Mhz, Gain = L2, CL = 12.5
pF
24 MHz, Gain = L3, CL = 12.5
pF
-
-
348
55
DuHXT
45
50
Dec. 25, 2020
Page 198 of 233
Rev. 1.00
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
4 MHz, Gain = L0, CL = 12.5
pF
-
120
400
12 MHz, Gain = L1, CL = 12.5
pF
-
-
-
25
25
25
100
75
Rs
Equivalent series resisotr(ESR)
Ω
16 Mhz, Gain = L2, CL = 12.5
pF
24 MHz, Gain = L3, CL = 12.5
pF
50
Notes:
1. Guaranteed by characterization, not tested in production.
1
2. 퐶퐿 =
ꢂ 퐶푝푎푟푎푠푖푡푖푐 .
ꢀ
ꢀ
+
ꢁꢀ ꢁ2
3. Safety factor (Sf) must be higher than 5 for HXT to determine the oscillator safe operation during the application life. If
Safety factor isn’t enough, the HXT gain need be changed to higher driving level.
−푅
푅
+ 푅
퐴퐷퐷 ꢉ
푆푓 =
=
ꢃꢄ푦ꢅꢆꢇ푙 퐸ꢈ푅
푅
ꢉ
RADD: The value of smallest series resistance preventing the oscillator from starting up successfully. This resistance is
only used to measure Safety factor (Sf) of crystal in engineer stage, not for mass produciton.
XT1_OUT
XT1_IN
RADD
C2
C1
Table 8.4-6 External 4~24 MHz High Speed Crystal (HXT) Oscillator
8.4.6.1
Typical Crystal Application Circuits
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 20 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing C1 and C2.
CRYSTAL
C1
C2
R1
4 MHz ~ 24 MHz
20pF
20pF
without
Dec. 25, 2020
Page 199 of 233
Rev. 1.00
XT1_OUT
XT1_IN
R1
C1
C2
Figure 8.4-1 Typical Crystal Application Circuit
External 4~24 MHz High Speed Clock Input Signal Characteristics
8.4.7
For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
External user clock source
frequency
fHXT_ext
0.032768
-
24
MHz
tCHCX
tCLCX
tCLCH
Clock high time
Clock low time
18
18
-
-
-
-
-
ns
ns
10
Low (10%) to high level (90%)
rise time
Clock rise time
Clock fall time
-
-
ns
ns
-
10
High (90%) to low level (10%)
fall time
tCHCL
VIH
VIL
Input high voltage
Input low voltage
0.7*VDD
VSS
-
-
VDD
V
V
0.3*VDD
External
clock source
XT1_IN
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Notes:
1. Guaranteed by characterization, not tested in production.
2. Duty cycle is 50%.
Dec. 25, 2020
Page 200 of 233
Rev. 1.00
Table 8.4-7 External 4~24 MHz High Speed Clock Input Signal
External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
8.4.8
The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in
order to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Min[*1]
1.7
-40
-
Typ Max[*1] Unit
Test Conditions
Operation voltage
-
-
3.6
105
-
V
Temperature range
TLXT
C
Rf
Internal feedback resistor
Oscillator frequency
6.35
32.768
MΩ
kHz
FLXT
130
270
750
ESR=35 kΩ, CL = 6 pF, Gain = L1
ESR=35 kΩ, CL = 12.5 pF, Gain =
L3
195
230
390
450
960
ESR=35 kΩ, CL = 12.5 pF, Gain =
L4
ILXT
Current consumption
nA
1060
ESR=70 kΩ, CL = 12.5 pF, Gain =
L6
370
500
680
920
1500
1950
ESR=70 kΩ, CL = 12.5 pF, Gain =
L7
TsLXT
DuLXT
Stable time
Duty cycle
-
30
-
-
50
2000
70
-
ms
%
VDD =3.3V，L7
Vpp Peak-to-peak amplitude
Rs Equivalnet Series Resisotr(ESR)
Notes:
0.557
35
V
-
70
kΩ
Crystal @32.768 kHz
1. Guaranteed by characterization, not tested in production.
2. Not supported gain = L0/ L2/ L5
1
3. 퐶퐿 =
ꢂ 퐶푝푎푟푎푠푖푡푖푐 .
ꢀ
ꢀ
+
ꢁꢀ ꢁ2
Table 8.4-8 External 32.768 kHz Low Speed Crystal (LXT) Oscillator
8.4.8.1
Typical Crystal Application Circuits
CRYSTAL
C1
C2
R1
32.768 kHz, ESR < 70 KΩ
20pF
20pF
without
Dec. 25, 2020
Page 201 of 233
Rev. 1.00
X32_OUT
X32_IN
R1
C1
C2
Figure 8.4-2 Typical 32.768 kHz Crystal Application Circuit
External 32.768 kHz Low Speed Clock Input Signal Characteristics
8.4.9
For clock input mode the LXT oscillator is switched off and X32_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
fLSE_ext
tCHCX
Parameter
External clock source frequency
Clock high time
Min[*1]
-
Typ
Max[*1]
Unit
kHz
ns
Test Conditions
32.768
-
-
-
450
450
-
-
tCLCX
Clock low time
ns
tCLCH
Clock rise time
Low (10%) to high level (90%)
rise time
-
-
-
-
50
50
ns
ns
tCHCL
Clock fall time
High (90%) to low level (10%) fall
time
Xin_VIH
Xin_VIL
LXT input pin input high voltage
LXT input pin input low voltage
0.7*VDD
VSS
-
-
VDD
V
V
0.3*VDD
External
clock source
X32_IN
tCLCL
tCLCH
90%
10%
VIH
tCLCX
VIL
tCHCL
tCHCX
Notes:
1. Guaranteed by design, not tested in production
Table 8.4-9 External 32.768 kHz Low Speed Clock Input Signal
Dec. 25, 2020
Page 202 of 233
Rev. 1.00
8.4.10 PLL Characteristics
Symbol
fPLL_in
Parameter
PLL input clock
Min[*1]
Typ
Max[*1]
24
Unit
MHz
MHz
MHz
MHz
µs
Test Conditions
4
24
2
-
-
-
-
-
fPLL_OUT
fPLL_REF
fPLL_VCO
TL
PLL multiplier output clock
PLL reference clock
200
8
PLL voltage controlled oscillator
PLL locking time
96
-
200
100
Jitter
IDD
Cycle-to-cycle Jitter
Power consumption
-
-
250
0.9
-
-
ps
Peak to peak @ 200MHz
f
VDD =3.3V @ PLL_VCO = 200
mA
MHz
Notes:
1. Guaranteed by design, not tested in production
Table 8.4-10 PLL characteristics
8.4.11 I/O AC Characteristics
Symbol
Parameter
Typ.
Max[*1]
.
Unit
Test Conditions[*2]
-
VDD = 3.6 V ,CL = 51 pF
4.09
3.23
10.05
7.82
3.47
2.45
7.37
5.96
4.14
3.32
9.3
Output high (90%) to low level (10%) fall time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD = 3.6 V ,CL = 30 pF
VDD = 1.7 V, CL = 51 pF
VDD = 1.7 V, CL = 30 pF
VDD = 3.6 V ,CL = 51 pF
VDD = 3.6 V ,CL = 30 pF
VDD = 1.7 V, CL = 51 pF
VDD = 1.7 V, CL = 30 pF
VDD = 3.6 V ,CL = 51 pF
VDD = 3.6 V ,CL = 30 pF
VDD = 1.7 V, CL = 51 pF
VDD = 1.7 V, CL = 30 pF
VDD = 3.6 V ,CL = 51 pF
VDD = 3.6 V ,CL = 30 pF
VDD = 1.7 V, CL = 51 pF
(Normal Slew Rate)
tf(IO)out
ns
Output high (90%) to low level (10%) fall time
(High Slew Rate)
Output low (10%) to high level (90%) rise time
(Normal Slew Rate)
ns
ns
tr(IO)out
7.5
3.08
2.17
6.3
Output low (10%) to high level (90%) rise time
(High Slew Rate)
Dec. 25, 2020
Page 203 of 233
Rev. 1.00
-
-
-
-
-
-
-
-
-
VDD = 1.7 V, CL = 30 pF
VDD = 3.6 V ,CL = 51 pF
VDD = 3.6 V ,CL = 30 pF
VDD = 1.7 V, CL = 51 pF
VDD = 1.7 V, CL = 30 pF
VDD = 3.6 V ,CL = 51 pF
VDD = 3.6 V ,CL = 30 pF
VDD = 1.7 V, CL = 51 pF
VDD = 1.7 V, CL = 30 pF
4.73
81
I/O maximum frequency
(Normal Slew Rate)
101.7
34.4
43.5
101.7
144.3
48.7
62.3
MHz
[*3]
fmax(IO)out
I/O maximum frequency
(High Slew Rate)
MHz
Notes:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
ꢋ
3. The maximum frequency is defined by ꢊ푚ꢇ푥
=
.
)
ꢍ
3 × (ꢆ +ꢆ
ꢌ
Table 8.4-11 I/O AC characteristics
Dec. 25, 2020
Page 204 of 233
Rev. 1.00
8.5
Analog Characteristics
LDO
8.5.1
Symbol
VDD
Parameter
Min
Typ
Max
Unit
V
Test Condition
DC Power Supply
1.7
-
3.6
V
Turbo mode[4]
Normal run mode
1.134
1.08
0.99
0.81
1.26
1.2
1.1
0.9
1.386
1.32
1.21
0.99
V
V
Normal run mode
VLDO
Output Voltage
V
Low Power Normal run mode
Ultra low leakage Power-
down mode
-
-
0.8
-
V
IOUT_MAX
Maximum Output Current
Temperature
50
mA
VIN>1.7V
-
TA
-40
-
125
℃
Note:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 4.7μF Capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
3. VLDO is only used to supply internal power.
4. Trubo mode is availabe when VDD between 1.8V~3.6V
Table 8.5-1 LDO characteristics
8.5.2
DC-DC
Typical values are at VDD = 3.3V, TA = 25°C, Vsw is connected to 4.7uH inductance and LDO_CAP is
connected to 4.7uF capacitance unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Unit
V
Test Condition
VIN
Input Voltage Range
1.7
-
3.6
V
Turbo mode[3]
Normal run mode
1.134
1.08
0.99
0.81
1.26
1.2
1.1
0.9
1.386
1.32
1.21
0.99
V
V
Normal run mode
VOUT
Output Voltage Range
V
Low Power Normal run mode
Ultra low leakage Power-down
mode
-
0.8
-
V
mA
uA
%
-
-
IOUT_MAX
IQ_DCDC
VLINE
Maximum DC Output Current
Quiescent Current
50
6
VIN>1.7V
-
4
No load, normal mode, only
buck regulator
Line Regulation
-5
-
+5
IOUT=30mA, VIN=1.7V to 3.6V
Dec. 25, 2020
Page 205 of 233
Rev. 1.00
VLOAD
Load Regulation
Power Efficiency
-5
-
-
+5
-
%
%
IOUT=0.2mA to 30mA
IOUT= 2~30mA
PEFF
80
LOUT = 4.7uH, DCR ≤ 180mΩ
Note:
1. It is recommended a 2.2μF and 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 4.7μF Capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
3. Trubo mode is availabe when VDD between 1.8V~3.6V
Table 8.5-2 LDO characteristics
8.5.3
Low-Voltage Reset
Symbol
AVDD
TA
Parameter
Supply Voltage
Temperature
Min Typ Max Unit
Test Condition
1.45
-40
-
-
3.6
125
0.6
V
℃
uA
V
25
0.3
-
AVDD = 3.6V
(BOD_EN = 0)
ILVR
Operating Current
Threshold Voltage
Operating Current
1.50
30
VLVR *
IBOD
1.45
-
1.65
40
μA
AVDD = 3.6V
BODVL
(SYS_BODCTL[18:16])
= 111
BODVL
(SYS_BODCTL[18:16])
= 110
BODVL
(SYS_BODCTL[18:16])
= 101
BODVL
(SYS_BODCTL[18:16])
= 100
BODVL
(SYS_BODCTL[18:16])
= 011
BODVL
(SYS_BODCTL[18:16])
= 010
BODVL
(SYS_BODCTL[18:16])
= 001
BODVL
(SYS_BODCTL[18:16])
= 000
BODVL
(SYS_BODCTL[18:16])
= 111
BODVL
(SYS_BODCTL[18:16])
= 110
BODVL
(SYS_BODCTL[18:16])
= 101
BODVL
(SYS_BODCTL[18:16])
= 100
2.90 3.00 3.10
2.70 2.80 2.90
2.50 2.60 2.70
2.30 2.40 2.50
2.10 2.20 2.30
1.90 2.00 2.10
1.70 1.80 1.90
1.50 1.60 1.70
2.98 3.08 3.18
2.78 2.88 2.98
2.58 2.68 2.78
2.38 2.48 2.58
V
V
V
V
V
V
V
V
V
V
V
V
Brown-out Voltage
(Falling edge)
VBOD_F
Brown-out Voltage
(Rising edge)
VBOD_R
Dec. 25, 2020
Page 206 of 233
Rev. 1.00
BODVL
(SYS_BODCTL[18:16])
= 011
BODVL
(SYS_BODCTL[18:16])
= 010
BODVL
(SYS_BODCTL[18:16])
= 001
BODVL
(SYS_BODCTL[18:16])
= 000
2.18 2.28 2.38
1.98 2.08 2.18
1.78 1.88 1.98
1.58 1.68 1.78
V
V
V
V
-
-
0.03
20
TBOD_RE
TLVR_RE
VPOR
Respond Time
Respond Time
Reset Voltage
-
-
ms
us
Sampled by LIRC *1
1.38 1.46 1.54
V
VDD Raising Rate to Ensure
Power-on Reset
-
-
-
-
-
-
POR Enabled
LVR Enabled
RRVDD
10
10
us/V
BOD 1.6V Enabled,
Normal mode
200
90
60
40
35
30
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BOD 1.8V Enabled,
Normal mode
BOD 2.0V Enabled,
Normal mode
VDD Falling Rate to Ensure
Power-on Reset
BOD 2.2V Enabled,
us/V
Normal mode
FRVDD
BOD 2.4V Enabled,
Normal mode
BOD 2.6V Enabled,
Normal mode
BOD 2.8V Enabled,
Normal mode
BOD 3.0V Enabled,
Normal mode
20
10
Minimum Time for VDD Stays at VPOR to Ensure Power-on
Reset
tPOR
Note :
us
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
Table 8.5-3 LVR characteristics
Dec. 25, 2020
Page 207 of 233
Rev. 1.00
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
Figure 8.5-1 Power Ramp Up/Down Condition
8.5.4
12-bit SAR Analog To Digital Converter (ADC)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
TA
Temperature
-40
105
-
℃
AV
=
AVDD
VREF
VIN
Analog operating voltage
Reference voltage
1.7
1.7
0
-
-
-
3.6
V
V
V
VDD
DD
AVDD
VREF
ADC channel input voltage
AVDD = VDD =VREF = 3.3 V
FADC = 80 MHz
ADC Operating current (AVDD
current)
+ VREF
[*1]
IADC
450
-
490
µA
Bit
TCONV = 14 * TADC
NR
Resolution
12
-
[*1]
FADC
ADC Clock frequency
0.14
80
MHz High Speed Channel
1/TADC
TSMP
Sampling Time
Conversion time
2
-
-
257
269
1/FADC
TCONV
14
1/FADC TCONV = TSMP + 14 * TADC
High Speed Channel
[*1]
FSPS
Sampling Rate
-
-
5.71 MSPS FSPS = FADC / TCONV
INL[*1]
Integral Non-Linearity Error
Differential Non-Linearity Error
Gain error
-4.42
1.81
0.75
-
-
-
9.89
9.31
2.25
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
DNL[*1]
[*1]
EG
Dec. 25, 2020
Page 208 of 233
Rev. 1.00
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
[*1]
EO
Offset error
-0.12
-
1.69
LSB VREF = AVDD
T
[*1]
EA
Absolute Error
8.25
-
10.48
LSB VREF = AVDD
ENOB[*1]
SINAD[*1]
SNR[*1]
Effective number of bits
Signal-to-noise and distortion ratio
Signal-to-noise ratio
-
-
-
-
-
9.8
67
67
-72
5
-
-
-
-
-
bits FADC = 80 MHz
AVDD = VDD =VREF = 3.3 V
Input Frequency = 20 kHz
TA = 25 °C
dB
pF
THD[*1]
Total harmonic distortion
Internal Capacitance
[*1]
CIN
Notes:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and
is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
푘
ꢎ퐸푋
=
ꢒ ꢎ퐼푁
ꢊ
ꢏꢐꢃ
× 퐶퐼푁 × ln(ꢑ푁+ꢋ
)
Table 8.5-4 12-bit SAR Analog To Digital Converter
Low Speed Channel
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
TA
Temperature
-40
105
-
℃
AV
=
AVDD
VREF
VIN
Analog operating voltage
Reference voltage
1.7
1.7
0
-
-
-
3.6
V
V
V
VDD
DD
AVDD
VREF
ADC channel input voltage
AVDD = VDD =VREF = 3.3V
ADC Clock Rate = 30 MHz
low speed channel
230
150
112
72
-
-
-
-
250
170
119
75
IADC1
uA
AVDD = VDD =VREF = 1.7V
ADC Clock Rate = 30 MHz
low speed channel
Operating current (AVDD current)
(Enable ADC and disable all other analog
modules)
AVDD = VDD =VREF = 3.3V
ADC Clock Rate = 14 MHz
low speed channel
IADC2
uA
Bit
AVDD = VDD =VREF = 1.7V
ADC Clock Rate = 14 MHz
low speed channel
NR
Resolution
12
-
[*1]
FADC
ADC Clock frequency
Sampling Time
0.14
2
30
MHz Low Speed Channel
1/FADC
1/TADC
TSMP
257
Dec. 25, 2020
Page 209 of 233
Rev. 1.00
Symbol
Parameter
Conversion time
Min
Typ
Max
Unit
Test Conditions
TCONV
14
269
1/FADC TCONV = TSMP + 14 * TADC
Low Speed Channel
[*1]
FSPS
Sampling Rate
-
-
2.14 MSPS
FSPS = FADC / TCONV
INL[*1]
Integral Non-Linearity Error
-1.79
0.96
2.12
2.37
2.12
7.69
LSB VREF = AVDD
DNL[*1]
Differential Non-Linearity Error
Gain error
-1
-
-
-
-
LSB VREF = AVDD
[*1]
EG
0.19
-0.12
2.94
LSB VREF = AVDD
LSB VREF = AVDD
[*1]
EO
Offset error
T
[*1]
EA
Absolute Error
LSB VREF = AVDD
ENOB[*1]
SINAD[*1]
SNR[*1]
Effective number of bits
Signal-to-noise and distortion ratio
Signal-to-noise ratio
-
-
-
-
-
10.2
67
-
-
-
-
-
bits FADC = 30 MHz
AVDD = VDD =VREF = 3.3 V
Input Frequency = 20 kHz
TA = 25 °C
67
dB
pF
THD[*1]
Total harmonic distortion
Internal Capacitance
-72
5
[*1]
CIN
Notes:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and
is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
푘
ꢎ퐸푋
=
ꢒ ꢎ퐼푁
ꢊ
ꢏꢐꢃ
× 퐶퐼푁 × ln(ꢑ푁+ꢋ
)
Table 8.5-5 12-bit SAR Analog To Digital Converter-low speed
Dec. 25, 2020
Page 210 of 233
Rev. 1.00
VDD
EADC_CHx
CEX
RIN
REX
12-bit
Converter
VEX
CIN
Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins
should be avoided to protect the conversion being performed on another analog input. It is
recommended to add Schottky diodes (pin to ground and pin to power) to analog pins which may
potentially inject currents.
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
Dec. 25, 2020
Page 211 of 233
Rev. 1.00
8.5.5
Digital to Analog Converter (DAC)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values
for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Analog supply voltage
Min
Typ
Max
Unit
Test Condition
AVDD
1.8
-
3.6
V
-
-
NR
Resolution
12
-
bit
V
VREF
VREF ≤ AVDD
Reference supply voltage
1.5
-2
3.6
2
-
-
-
-
LSB 12-bit mode
LSB 10-bit mode
DNL[*2]
INL[*2]
Differential non-linearity error
Integral non-linearity error
-0.5
-4
-0.5
4
12-bit mode
LSB
-1
-1
LSB 10-bit mode
12-bit mode
LSB
-8
-
8
DACOUT buffer ON
OE[*2]
12-bit mode
Offset Error
-4
-2
-
-
-
4
LSB
DACOUT buffer OFF
-2
10
LSB 10-bit mode
12-bit mode
LSB
-10
DACOUT buffer ON
GE[*2]
12-bit mode
Gain Error
-4
-2
-
-
-
4
LSB
DACOUT buffer OFF
-2
10
LSB 10-bit mode
12-bit mode
LSB
-10
DACOUT buffer ON
AE[*2]
12-bit mode
Absolute Error
-4
-2
-
-
4
LSB
DACOUT buffer OFF
-2
LSB 10-bit mode
-
-
Monotonic
10-bit guaranteed
-
AVDD-
0.2
DACOUT buffer ON
DACOUT buffer OFF
0.2
-
-
V
[*1]
VO
Output Voltage
VREF – 1
LSB
1 LSB
[*2] [*3]
RLOAD
Resistive load
DACOUT buffer ON
DACOUT buffer OFF
DACOUT buffer OFF
7.5
-
-
-
kΩ
kΩ
pF
[*2]
RO
Output impedance
Capacitive load
-
-
9.8
-
[*2] [*4]
CLOAD
20
Dec. 25, 2020
Page 212 of 233
Rev. 1.00
AVDD
= 3.6V, no load, lowest code
-
-
132
338
-
-
(0x000)
[*2]
IDAC_AVDD
A
A
μs
DAC operating current on AVDD supply
DAC operating current on VREF supply
AVDD
= 3.6V, no load, middle code
(0x800)
VREF =3.6V, no load, middle code
(0x800)
[*2]
IDAC_VREF
-
130
140
Full scale: for a 12-bit input code
transition between the lowest and the
highest input codes when DAC_OUT
reaches final value +/-1 LSB,
[*2]
TB
Settling Time
-
-
5
-
6
1
CLOAD ≤ 50pF, RLOAD ≥ 5kΩ
Max. frequency for
MSPS DAC_OUT change from core i to
a
correct
FS
Update Rate
i+1LSB, CLOAD ≤ 50pF, RLOAD ≥ 5kΩ
Wakeup time from OFF state. Input
code between lowest and highest
possible codes.
TWAKEUP
Wake-up Time
-
-
5
10
μs
DAC clock source = 1MHz
PSRR[*1] Power Supply Rejection Ratio
-60
-40
dB
No RLOAD, CLOAD = 50pF
Note:
1. Guaranteed by design, not tested in production
2. Guaranteed by characteristic, not tested in production.
3. Resistive load between DACOUT and AVSS
.
4. Capacitive load at DACOUT pin.
Table 8.5-6 Digital to Analog Converter
Analog Comparator Controller (ACMP)
8.5.6
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values
for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VDD = AVDD
3.6
1.8
-40
3.3
-
AVDD
Analog supply voltage
V
125
TA
Temperature
℃
-
75
10
3
-
-
-
-
MODESEL = 11
MODESEL = 10
MODESEL = 01
MODESEL = 00
-
-
[*2]
IACMP
ACMP operating current
A
-
1.2
0.1
1/2 AVDD
[*2]
VCM
Input common mode voltage range
AVDD
-0.1
[*2]
10
-
20
5
-
VDI
Differential input voltage sensitivity
Input offset voltage
mV Hysteresis disable (HYSSEL = 00)
mV Hysteresis disable (HYSSEL = 00)
[*2]
10
Voffset
Dec. 25, 2020
Page 213 of 233
Rev. 1.00
-
-
-
-
10
20
30
70
-
-
-
-
mV HYSSEL = 01
[*2]
Vhys
Hysteresis window
DC voltage Gain
HYSSEL = 10
HYSSEL = 11
Av[*1]
dB
ns
Hysteresis disable
MODESEL[1:0] = 00
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4500
2000
600
Hysteresis disable
MODESEL[1:0] = 01
[*2]
Td
Propagation delay
Hysteresis disable
MODESEL[1:0] = 10
Hysteresis disable
MODESEL[1:0] = 11
200
Hysteresis disable
MODESEL[1:0] = 00
4750
2250
850
Hysteresis disable
MODESEL[1:0] = 01
[*2]
TSetup
Setup time
ns
Hysteresis disable
MODESEL[1:0] = 10
Hysteresis disable
MODESEL[1:0] = 11
450
[*2]
-5%
-
+5%
ACRV
CRV output voltage
Unit resistor value
Operating current
%
AVDD x (1/6+CRVCTL/24)
[*2]
-
-
4.2k
32.7
-
-
RCRV
kΩ
A
[*2]
IDD_CRV
Notes:
1. Guaranteed by design, not tested in production
2. Guaranteed by characteristic, not tested in production
Table 8.5-7 Analog Comparator Controller
Temperature Sensor
8.5.7
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the
typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
Typ
Max Unit
Test Conditions
Tempereture sensor
voltage
offset
[*1]
710
720
730
mV
TA = 0°C
VTEMP_OS
[*1]
-1.77
-
-1.82
3
-1.86
TC
Temperature Coefficient
Stable time
mV/°C
[*2]
-
TS
S
ADC sampling time when reading
the temperature
[*1]
-
-
3
-
TTEMP_ADC
S
[*1]
16
-
ITEMP
A
OPA operating current
Dec. 25, 2020
Page 214 of 233
Rev. 1.00
Note:
8.1.4.3.1.1
8.1.4.3.1.2
8.1.4.3.1.3
Guaranteed by characterization, not tested in production
Guaranteed by design, not tested in production
VTEMP (mV) = TC (mV/°C) x Temperature (°C) + VTEMP_OS (mV)
Table 8.5-8 Temprature Sensor
8.5.8
LCD controller
Symbol
Parameter
Supply voltage
Min[*1]
1.6
Typ
Max[*1] Unit
Test Conditions
VDD
-
-
3.6
85
V
TA
Temperature
-20
℃
LCD external voltage
2.6
-
3.6
2.7
2.6
2.5
2.7
VSEL = 0 @ VDD = 1.8V
2.8
3
2.9
3.1
3.3
3.5
3.7
2
VSEL = 1 @ VDD = 1.8V
VSEL = 2 @ VDD = 1.8V
VSEL = 3 @ VDD = 1.8V
VSEL = 4 @ VDD = 1.8V
VSEL = 5 @ VDD = 1.8V
BUFEN = 0 Without buffer mode
BUFEN = 1 With buffer mode
2.9
3.1
3.3
3.5
-
VLCD
V
LCD internal voltage
3.2
3.4
3.6
1
CLCD
VLCD external capacitance
F
A
-
1
2
VSRC = 2, BUFEN = 0, VLCD = 2.6V,
VDD = 1.6V
-
-
-
-
-
-
-
-
-
89.6
138
65.4
105
2.85
3.15
2.13
2.5
-
-
-
-
-
-
-
-
-
VSRC = 2, BUFEN = 0, VLCD = 3.6V,
VDD = 3.6V
Supply current from VDD with built-in
charge pump and buffer mode
[*2]
ILCD
VSRC = 2, BUFEN = 1, VLCD = 2.6V,
VDD = 1.6V
VSRC = 2, BUFEN = 1, VLCD = 3.6V,
VDD = 3.6V
VSRC = 0, BUFEN = 1, VLCD = 2.6V,
buffer mode
VSRC = 0, BUFEN = 1, VLCD = 3.6V,
buffer mode
VSRC = 0, RES_MODE = 1, VLCD
2.6V, low drive mode
=
=
=
=
Supply current from VLCD without Bulit-In
Charge Pump
[*2]
IVLCD
A
VSRC = 0, RES_MODE = 1, VLCD
3.6V, low drive mode
VSRC = 0, RES_MODE = 1, VLCD
2.6V, high drive mode
13
VSRC = 0, RES_MODE = 1, VLCD
3.6V, high drive mode
-
-
17.5
5.5
-
-
RLCD_INT Internal total LCD resistor value
MΩ Low drive
Dec. 25, 2020
Page 215 of 233
Rev. 1.00
-
240
-
kΩ High drive
Note:
1. Guaranteed by design, not tested in production
2. LCD COM/SEG is set to 1/8 duty, 1/4 bias, 30 Hz frame rate, all pixels active, type B waveform, no LCD
panel loading.
Table 8.5-9 LCD controller
Dec. 25, 2020
Page 216 of 233
Rev. 1.00
8.6
Commucications Characteristics
SPI Dynamic Characteristics
8.6.1
Symbol
Parameter
Min
Typ
Max
Unit
SPI Master Mode (VDD = 3.0~3.6 V, 30 PF loading Capacitor)
ns
ns
tCLKL
tCLKH
tDS
Clock output High time [*1]
Clock output Low time [*1]
Data setup time
-
-
-
-
TSPICLK / 2
TSPICLK / 2
0
10
-
-
-
-
ns
ns
ns
tDH
Data hold time
-
tV
Data output valid time
0
15
Table 8.6-1 SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-1 SPI Master Mode Timing Diagram
Parameter Min Typ
SPI Slave Mode (VDD = 3.0~3.6V, 30 PF Loading Capacitor)
Symbol
Max
Unit
tCLKL
tCLKH
tSS
Clock output High time [*1]
Clock output Low time [*1]
Slave select setup time
Slave select hold time
-
-
-
TSPICLK / 2
Peripheral clock
Peripheral clock
Peripheral clock
Peripheral clock
TSPICLK / 2
1 TSPICLK + 2ns
1 TSPICLK
-
-
-
-
tSH
Dec. 25, 2020
Page 217 of 233
Rev. 1.00
tDS
tDH
Data input setup time
Data input hold time
0
6
-
-
-
-
-
-
-
ns
ns
ns
ns
tV
Data output valid time
Clock output High time [*1]
11.5
tCLKH
-
TSPICLK / 2
Note: The minimum clock period for SPICLK is 41.67 ns (24 MHz).
Table 8.6-2 SPI Slave Mode Characteristics
tSS
SSACTPOL=1
SSACTPOL=0
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.6-2 SPI Slave Mode Timing Diagram
Dec. 25, 2020
Page 218 of 233
Rev. 1.00
8.6.2
SPI - I2S Dynamic Characteristics
Symbol
Parameter
I2S clock high time
I2S clock low time
WS valid time
Min[*1]
Max[*1]
Unit
Test Conditions
tw(CKH)
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
39
39
2
-
-
Master fPCLK = MHz, data: 24 bits, audio
frequency = 128 kHz
12
-
Master mode
Master mode
Slave mode
Slave mode
ns
WS hold time
1
WS setup time
WS hold time
24
0
-
-
I2S slave input clock duty
cycle
DuCy(SCK)
35
65
%
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Note:
22
10
7
-
-
Master receiver
Data input setup time
Data input hold time
Slave receiver
-
Master receiver
8
-
Slave receiver
ns
Data output valid time
Data output hold time
Data output valid time
Data output hold time
-
21
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
4
-
7
-
0
1.Guaranteed by design.
Table 8.6-3 I2S Characteristics
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
tv(WS)
WS output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.6-3 I2S Master Mode Timing Diagram
Dec. 25, 2020
Page 219 of 233
Rev. 1.00
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(WS)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.6-4 I2S Slave Mode Timing Diagram
Dec. 25, 2020
Page 220 of 233
Rev. 1.00
8.6.3
I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
Max
Min
Max
4.7
1.2
tLOW
SCL low period
-
-
-
-
-
-
-
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
pF
4
4.7
4
0.6
0.6
0.6
0.6
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
-
-
4
-
4.7 [3]
1.2 [3]
-
tSU;DAT
tHD;DAT
tr
Data setup time
250
100
-
Data hold time
0 [4]
3.45 [5]
1000
0[4]
0.8[5]
300
300
400
SCL/SDA rise time
-
-
-
20+0.1 Cb
300
400
tf
SCL/SDA fall time
-
-
Cb
Capacitive load for each bus line
Notes:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-4 I2C characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-5 I2C Timing Diagram
Dec. 25, 2020
Page 221 of 233
Rev. 1.00
8.6.4
USCI - SPI Dynamic Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
SPI Master Mode (VDD = 3.0~3.6 V, 30 PF loading Capacitor)
ns
ns
tCLKL
tCLKH
tDS
Clock output High time [*1]
Clock output Low time [*1]
Data setup time
-
-
-
-
TSPICLK / 2
TSPICLK / 2
0
2
-
-
-
-
ns
ns
ns
tDH
Data hold time
-
tV
Data output valid time
0
1
Table 8.6-5 USCI-SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-6 USCI-SPI Master Mode Timing Diagram
8.6.5
USCI - I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.2
0.6
0.6
0.6
0.6
Max
tLOW
SCL low period
-
-
-
-
-
-
-
-
-
-
µs
µs
µs
µs
µs
tHIGH
SCL high period
tSU; STA
tHD; STA
tSU; STO
Repeated START condition setup time
START condition hold time
STOP condition setup time
4.7
4
4
Dec. 25, 2020
Page 222 of 233
Rev. 1.00
tBUF
tSU;DAT
tHD;DAT
tr
Bus free time
4.7 [3]
-
-
1.2 [3]
-
µs
ns
µs
ns
ns
pF
Data setup time
250
100
-
Data hold time
0 [4]
3.45 [5]
1000
300
400
0 [4]
0.8[5]
300
300
400
SCL/SDA rise time
SCL/SDA fall time
Capacitive load for each bus line
-
-
-
20+0.1 Cb
tf
-
-
Cb
Notes:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-6 USCI-I2C characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-7 USCI-I2C Timing Diagram
8.6.6
USB Characteristics
8.6.6.1 USB Full-Speed Characteristics
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
USB full speed transceiver
operating voltage
VBUS
3.0
3.3
3.6
V
VIH
VIL
VDI
Input high (driven)
Input low
2
-
-
-
-
0.8
-
V
V
V
-
-
Differential input sensitivity
-
0.2
|(USB_D+) - (USB_D-)|
Differential
VCM
0.8
-
2.5
V
Includes VDI range
common-mode range
Single-ended receiver threshold
Receiver hysteresis
0.8
-
-
2.0
-
V
mV
V
-
-
-
-
VSE
200
VOL
VOH
Output low (driven)
0
-
-
0.3
3.6
Output high (driven)
2.8
V
Dec. 25, 2020
Page 223 of 233
Rev. 1.00
RPD
RPU
Pull-down Resistor
Pull-up resistor
14.25
1.425
-
-
24.8
3.09
kΩ
kΩ
-
Termination voltage for
upstream port pull-up (RPU)
VTRM
3.0
-
3.6
V
[*2]
ZDRV
Driver output resistance
Transceiver capacitance
-
-
10
-
-
Ω
Steady state drive
Pin to GND
CIN
26
pF
Notes:
1. Guaranteed by characterization result, not tested in production.
2. USB_D+ and USB_D- must be connected with external series resistors to fit USB Full-speed spec request (28 ~
44Ω).
Table 8.6-7 USB Full-Speed Characteristics
8.6.6.2 USB Full-Speed PHY Characteristics
Symbol
TFR
Parameter
Min[*1]
Typ
Max[*1]
20
Unit
ns
Test Conditions
CL=50 pF
rise time
fall time
4
4
-
-
-
TFF
20
ns
CL=50 pF
TFRFF
rise and fall time matching
90
111.11
%
TFRFF = TFR/TFF
Note:
1. Guaranteed by characterization result, not tested in production.
Table 8.6-8 USB Full-Speed PHY Characteristics
SDIO Characteristics
8.6.7
Default Mode Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
SD_CLK Period
TP_SD_CLK
40
-
-
ns
-
(Data Transfer Mode)
SD_CLK Period
TP_SD_CLK_ID
2,500
-
-
ns
(Identification Mode)
TH_SD_CLK
TL_SD_CLK
SD_CLK High Time
-
-
20
20
-
-
ns
ns
-
-
SD_CLK Low Time
SD_DATA Setup Time to
SD_CLK Rising
TSU_SD_IN
THD_SD_IN
5
5
-
-
-
-
-
-
ns
ns
ns
-
-
-
SD_DATA Hold Time from SD_CLK Rising
SD_CLK Falling to
TDLY_SD_OUT
14
Valid SD_DATA Delay
Table 8.6-9 SDIO Characteristics
Dec. 25, 2020
Page 224 of 233
Rev. 1.00
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
Figure 8.6-8 SDIO Default Mode
SDIO Dynamic Characteristics
Symbol
TP_SD_CLK
TH_SD_CLK
TL_SD_CLK
Parameter
Min
20
7
Typ
Max
Unit
ns
Test Condition
SD_CLK Period
SD_CLK High Time
SD_CLK Low Time
-
-
-
-
-
-
-
-
-
ns
7
ns
SD_DATA Setup Time to
SD_CLK Rising
TSU_SD_IN
THD_SD_IN
6
2
-
-
-
-
-
-
ns
ns
ns
ns
-
-
-
-
SD_DATA Hold Time from SD_CLK Rising
SD_CLK Falling to
TDLY_SD_OUT
-
14
-
Valid SD_DATA Delay
THD_SD_OUT SD_DATA Hold Time from SD_CLK Rising
2.5
Table 8.6-10 SDIO Dynamic Characteristics
Dec. 25, 2020
Page 225 of 233
Rev. 1.00
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
THD_SD_OUT
Figure 8.6-9 SDIO High-speed Mode
Dec. 25, 2020
Page 226 of 233
Rev. 1.00
8.7
Flash DC Eletrical Charateristics
The devices are shipped to customers with the Flash memory erased.
Symbol
Parameter
Supply voltage
Min
Typ
Max
Unit
V
Test Condition
[1]
VFLA
0.81
1.2
1.32
TERASE
TPROG
IDD1
Page erase time
Program time
Read current
93
160
ms
µs
1237
-
1800
TA = 25℃
42
-
50
4.12
5
mA
mA
mA
IDD2
Program current
Erase current
IDD3
-
NENDUR
Endurance
-
10000
-
5
cycles[2]
year
TJ = -40℃~125℃
20 kcycle[3] TJ = 55℃
20 kcycle[3] TJ = 85℃
20 kcycle[3] TJ = 125℃
-
-
-
TRET
Data retention
-
-
year
10
year
Notes:
1. VFLA is source from chip internal LDO output voltage, and the Flash memoy can support just read operation when
VFLA < 1.08V
2. Number of program/erase cycles.
3. Guaranteed by design.
Table 8.7-1 Flash DC Eletrical Characteristics
Dec. 25, 2020
Page 227 of 233
Rev. 1.00
9 PACKAGE DIMENSIONS
9.1 LQFP 48 (7x7x1.4 mm3 Footprint 2.0 mm)
Dec. 25, 2020
Page 228 of 233
Rev. 1.00
9.2 LQFP 64 (7x7x1.4 mm3 Footprint 2.0 mm)
Dec. 25, 2020
Page 229 of 233
Rev. 1.00
9.3 LQFP 128 (14x14x1.4 mm3 Footprint 2.0 mm)
Dec. 25, 2020
Page 230 of 233
Rev. 1.00
10 ABBREVIATIONS
10.1 Abbreviations
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
Advanced High-Performance Bus
Brown-out Detection
BOD
CAN
DAP
Controller Area Network
Debug Access Port
DES
Data Encryption Standard
EADC
EBI
Enhanced Analog-to-Digital Converter
External Bus Interface
EMAC
EPWM
FIFO
FMC
FPU
Ethernet MAC Controller
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
12 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
Dec. 25, 2020
Page 231 of 233
Rev. 1.00
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital
SD
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TK
Triple Data Encryption Standard
Touch Key
TMR
UART
UCID
USB
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
Watchdog Timer
Window Watchdog Timer
Table 10.1-1 List of Abbreviations
Dec. 25, 2020
Page 232 of 233
Rev. 1.00
11 REVISION HISTORY
Date
Revision
Description
2020.12.25
1.00
Initial version.
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Dec. 25, 2020
Page 233 of 233
Rev. 1.00
相关型号：
M235FAN1.5000MHZ
HCMOS/TTL Output Clock Oscillator, 1.5MHz Min, 135MHz Max, 1.5MHz Nom, ROHS COMPLIANT, LEADLESS, CERAMIC PACKAGE-4
MTRONPTI
M235FAN8.0000MHZ
HCMOS/TTL Output Clock Oscillator, 8MHz Nom, ROHS COMPLIANT, LEADLESS, CERAMIC PACKAGE-4
MTRONPTI
M235FANFREQ
HCMOS/TTL Output Clock Oscillator, 1.5MHz Min, 135MHz Max, ROHS COMPLIANT, LCC-4
MTRONPTI
M235FANFREQ1
HCMOS/TTL Output Clock Oscillator, 1.5MHz Min, 135MHz Max, ROHS COMPLIANT, LEADLESS, CERAMIC PACKAGE-4
MTRONPTI
M235FCN01.5000MHZ
HCMOS Output Clock Oscillator, 1.5MHz Min, 135MHz Max, 1.5MHz Nom, ROHS COMPLIANT, LEADLESS PACKAGE-4
MTRONPTI
M235FCN1.0000MHZ
HCMOS Output Clock Oscillator, 1MHz Nom, ROHS COMPLIANT, LEADLESS, CERAMIC PACKAGE-4
MTRONPTI
M235FCN1.5000MHZ
HCMOS Output Clock Oscillator, 1.5MHz Min, 135MHz Max, 1.5MHz Nom, ROHS COMPLIANT, LEADLESS, CERAMIC PACKAGE-4
MTRONPTI
©2020 ICPDF网 联系我们和版权申明