MINI57-TE [NUVOTON]
ARM Cortex®-M0 32-bit Microcontroller;
| 型号： | MINI57-TE |
| 厂家： | 
NUVOTON |
| 描述： | ARM Cortex®-M0 32-bit Microcontroller 微控制器 |
| 文件： | 总131页 (文件大小：2525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Mini57
ARM Cortex® -M0
32-bit Microcontroller
NuMicro® Family
Mini57 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Apr. 06, 2017
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TABLE OF CONTENTS
1GENERAL DESCRIPTION.................................................................................7
2FEATURES ........................................................................................................8
3ABBREVIATIONS............................................................................................12
4PARTS INFORMATION LIST AND PIN CONFIGURATION............................13
4.1
4.2
4.3
NuMicro® Mini57 Naming Rule................................................................................... 13
NuMicro® Mini57 Series Selection Guide................................................................... 14
Pin Configuration........................................................................................................ 15
4.3.1 TSSOP 28-Pin................................................................................................................15
4.3.2 TSSOP 20-Pin................................................................................................................16
4.3.3 QFN 33-Pin ....................................................................................................................17
Pin Description ........................................................................................................... 19
4.4
4.4.1 Mini57 Series Pin Description.........................................................................................19
4.4.2 GPIO Multi-function Pin Summary..................................................................................31
5BLOCK DIAGRAM...........................................................................................34
5.1
NuMicro® Mini57 Block Diagram................................................................................ 34
6FUNCTIONAL DESCRIPTION.........................................................................35
6.1
6.2
ARM® Cortex® -M0 Core ............................................................................................. 35
6.1.1 Overview ........................................................................................................................35
6.1.2 Features .........................................................................................................................36
System Manager ........................................................................................................ 37
6.2.1 Overview ........................................................................................................................37
6.2.2 System Reset.................................................................................................................37
6.2.3 Power Modes and Wake-up Sources .............................................................................43
6.2.4 System Power Architecture ............................................................................................46
6.2.5 System Memory Mapping...............................................................................................47
6.2.6 Register Protection.........................................................................................................48
6.2.7 Memory Organization .....................................................................................................50
6.2.8 System Timer (SysTick) .................................................................................................53
6.2.9 Nested Vectored Interrupt Control (NVIC)......................................................................58
6.2.10 System Control Registers...............................................................................................78
Clock Controller.......................................................................................................... 87
6.3
6.4
6.3.1 Overview ........................................................................................................................87
6.3.2 Auto Trim........................................................................................................................89
6.3.3 System Clock and SysTick Clock ...................................................................................89
6.3.4 Peripherals Clock Source Selection ...............................................................................90
6.3.5 Power-down Mode Clock................................................................................................92
6.3.6 Frequency Divider Output...............................................................................................92
Flash Memory Controller (FMC)................................................................................. 94
6.4.1 Overview ........................................................................................................................94
6.4.2 Features .........................................................................................................................94
General Purpose I/O (GPIO)...................................................................................... 95
6.5
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6.5.1 Overview ........................................................................................................................95
6.5.2 Features .........................................................................................................................95
6.5.3 GPIO Interrupt and Wake-up Function ...........................................................................96
Timer Controller (TIMER)........................................................................................... 97
6.6
6.7
6.8
6.9
6.6.1 Overview ........................................................................................................................97
6.6.2 Features .........................................................................................................................97
Enhanced Input Capture Timer (ECAP)..................................................................... 98
6.7.1 Overview ........................................................................................................................98
6.7.2 Features .........................................................................................................................98
Enhanced PWM Generator (EPWM) ......................................................................... 99
6.8.1 Overview ........................................................................................................................99
6.8.2 Features .........................................................................................................................99
Basic PWM Generator (BPWM)............................................................................... 101
6.9.1 Overview ......................................................................................................................101
6.9.2 Features .......................................................................................................................101
6.10 Watchdog Timer (WDT) ........................................................................................... 102
6.10.1 Overview ......................................................................................................................102
6.10.2 Features .......................................................................................................................102
6.11 USCI – Universal Serial Control Interface Controller............................................... 103
6.11.1 Overview ......................................................................................................................103
6.11.2 Features .......................................................................................................................103
6.12 USCI – UART Mode................................................................................................. 104
6.12.1 Overview ......................................................................................................................104
6.12.2 Features .......................................................................................................................104
6.13 USCI – SPI Mode..................................................................................................... 105
6.13.1 Overview ......................................................................................................................105
6.13.2 Features .......................................................................................................................105
6.14 USCI – I2C Mode...................................................................................................... 107
6.14.1 Overview ......................................................................................................................107
6.14.2 Features .......................................................................................................................107
6.15 Hardware Divider (HDIV).......................................................................................... 108
6.15.1 Overview ......................................................................................................................108
6.15.2 Features .......................................................................................................................108
6.16 Analog to Digital Converter (ADC) ........................................................................... 109
6.16.1 Overview ......................................................................................................................109
6.16.2 Features .......................................................................................................................109
6.17 Analog Comparator (ACMP) .................................................................................... 110
6.17.1 Overview ......................................................................................................................110
6.17.2 Features .......................................................................................................................110
6.18 Programmable Gain Amplifier (PGA)....................................................................... 111
6.18.1 Overview ......................................................................................................................111
6.18.2 Features .......................................................................................................................111
7APPLICATION CIRCUIT................................................................................112
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8ELECTRICAL CHARACTERISTICS..............................................................113
8.1
8.2
8.3
Absolute Maximum Ratings ..................................................................................... 113
DC Electrical Characteristics.................................................................................... 114
AC Electrical Characteristics.................................................................................... 119
8.3.1 External Input Clock .....................................................................................................119
8.3.2 External 4~24 MHz High Speed Crystal (HXT).............................................................119
8.3.3 External 32.768 kHz XTAL Oscillator (LXT) .................................................................119
8.3.4 Typical Crystal Application Circuits...............................................................................119
8.3.5 48 MHz Internal High Speed RC Oscillator (HIRC) ......................................................120
8.3.6 10 kHz Internal Low Speed RC Oscillator (LIRC).........................................................120
Analog Characteristics ............................................................................................. 121
8.4
8.4.1 12-bit SAR ADC............................................................................................................121
8.4.2 LDO & Power Management..........................................................................................122
8.4.3 Low Voltage Reset .......................................................................................................122
8.4.4 Brown-out Detector.......................................................................................................123
8.4.5 Power-on Reset............................................................................................................123
8.4.6 Comparator ..................................................................................................................124
8.4.7 PGA..............................................................................................................................124
Flash DC Electrical Characteristics.......................................................................... 126
8.5
9PACKAGE DIMENSIONS..............................................................................127
9.1
9.2
9.3
28-Pin TSSOP (4.4x9.7x1.0 mm)............................................................................. 127
20-Pin TSSOP (4.4x6.5x0.9 mm)............................................................................. 128
33-pin QFN33 (4x4x0.8 mm).................................................................................... 129
10 REVISION HISTORY.................................................................................130
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List of Figures
Figure 4.1-1 NuMicro® Mini57 Series Selection Code ................................................................... 13
Figure 4.3-1 NuMicro® Mini57 Series TSSOP 28-pin Diagram...................................................... 15
Figure 4.3-2 NuMicro® Mini57 Series TSSOP 28-pin Multi-function Diagram ............................... 15
Figure 4.3-3 NuMicro® Mini57 Series TSSOP 20-pin Diagram...................................................... 16
Figure 4.3-4 NuMicro® Mini57 Series TSSOP 20-pin Multi-function Diagram ............................... 16
Figure 4.3-5 NuMicro® Mini57 Series QFN 33-pin Diagram .......................................................... 17
Figure 4.3-6 NuMicro® Mini57 Series QFN 33-pin Multi-function Diagram.................................... 18
Figure 5.1-1 NuMicro® Mini57 Block Diagram ............................................................................... 34
Figure 6.1-1 Functional Block Diagram.......................................................................................... 35
Figure 6.2-1 System Reset Resources.......................................................................................... 38
Figure 6.2-2 nRESET Reset Waveform......................................................................................... 40
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 40
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 41
Figure 6.2-5 Brown-out Detector (BOD) Waveform....................................................................... 42
Figure 6.2-6 Power Mode State Machine ...................................................................................... 43
Figure 6.2-7 NuMicro® Mini57 Series Power Architecture Diagram .............................................. 46
Figure 6.2-8 NuMicro® Mini57 Flash, Security and Configuration Map ......................................... 50
Figure 6.2-9 SRAM Block Diagram................................................................................................ 52
Figure 6.3-1 Clock Generator Block Diagram................................................................................ 87
Figure 6.3-2 Clock Generator Global View Diagram...................................................................... 88
Figure 6.3-3 System Clock Block Diagram .................................................................................... 89
Figure 6.3-4 SysTick Clock Control Block Diagram....................................................................... 90
Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK ................................................... 91
Figure 6.3-6 Clock Source of Frequency Divider........................................................................... 93
Figure 6.3-7 Block Diagram of Frequency Divider......................................................................... 93
Figure 6.5-1 I/O Pin Block Diagram ............................................................................................... 95
Figure 6.13-1 SPI Master Mode Application Block Diagram (x=0, 1) .......................................... 105
Figure 6.13-2 SPI Slave Mode Application Block Diagram (x=0, 1) ............................................ 105
Figure 6.14-1 I2C Bus Timing....................................................................................................... 107
Figure 8.3-1 Mini57 Typical Crystal Application Circuit................................................................ 120
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List of Tables
Table 3-1 List of Abbreviations....................................................................................................... 12
Table 4.2-1 NuMicro® Mini57 Series Selection Guide ................................................................... 14
Table 4.4-1 TSSOP28 Pin Description .......................................................................................... 22
Table 4.4-2 TSSOP20 Pin Description .......................................................................................... 26
Table 4.4-3 QFN33 Pin Description............................................................................................... 30
Table 4.4-4 TSSOP20 Multi-function Pin Summary....................................................................... 33
Table 6.2-1 Reset Value of Registers............................................................................................ 39
Table 6.2-2 Power Mode Difference Table .................................................................................... 43
Table 6.2-3 Clocks in Power Modes .............................................................................................. 44
Table 6.2-4 Condition of Entering Power-down Mode Again......................................................... 45
Table 6.2-5 Memory Mapping Table .............................................................................................. 47
Table 6.2-6 Protected Registers .................................................................................................... 49
Table 6.2-7 Address Space Assignments for On-Chip Modules ................................................... 51
Table 6.2-8 Exception Model ......................................................................................................... 59
Table 6.2-9 System Interrupt Map Vector Table............................................................................ 60
Table 6.2-10 Vector Table Format ................................................................................................. 60
Table 6.3-1 Peripheral Clock Source Selection Table ................................................................... 92
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1 GENERAL DESCRIPTION
The NuMicro® Mini57 series 32-bit microcontrollers are embedded with ARM® Cortex® -M0 core for
industrial applications which need high performance, high integration, and low cost. The Cortex® -
M0 is the newest ARM® embedded processor with 32-bit performance at a cost equivalent to the
traditional 8-bit microcontroller.
The Mini57 series can run up to 48 MHz and operate at 2.1V ~ 5.5V, -40℃ ~ 105℃, and thus can
support a variety of industrial control applications which need high CPU performance. The Mini57
offers 29.5 Kbytes embedded program Flash, size configurable Data Flash (shared with program
Flash), 2 Kbytes Flash for the ISP, 1.5 Kbytes SPROM for security, and 4 Kbytes SRAM.
Many system level peripheral functions, such as I/O Port, Timer, UART, SPI, I2C, PWM, ADC,
Watchdog Timer, Analog Comparator and Brown-out Detector, have been incorporated into the
Mini57 to reduce component count, board space and system cost. These useful functions make
the Mini57 powerful for a wide range of applications.
Additionally, the Mini57 series is equipped with ISP (In-System Programming) and ICP (In-Circuit
Programming) functions, which allow the user to update program memory without removing the
chip from the actual end product.
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2 FEATURES
Core
-
-
-
-
-
-
ARM® Cortex® -M0 core running up to 48 MHz
One 24-bit system timer
Supports low power Idle mode
A single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-level of priority
Supports Serial Wire Debug (SWD) interface and two watchpoints/four
breakpoints
Built-in LDO for wide operating voltage ranged: 2.1V to 5.5V
Memory
-
-
-
-
-
29.5 Kbytes Flash memory for program memory (APROM)
Configurable Flash memory for data memory (Data Flash)
2 KB Flash memory for loader (LDROM)
Three 0.5 KB Flash memory for security protection (SPROM)
4 KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
-
Programmable system clock source
Switch clock sources on-the-fly
-
-
4 ~ 24 MHz external crystal input (HXT)
32.768 kHz external crystal input (LXT) for idle wake-up and system operation
clock
-
48 MHz internal oscillator (HIRC) (±1% accuracy at 250C, 5V)
Dynamically calibrating the HIRC OSC to 48 MHz ±1% from -40℃ to 105℃
by external 32.768K crystal oscillator (LXT)
-
10 kHz internal low-power oscillator (LIRC) for Watchdog Timer and idle wake-
up
I/O Port
-
-
Up to 22 general-purpose I/O (GPIO) pins and 1 Reset pin for QFN-33 package
Four I/O modes:
Quasi-bidirectional input/output
Push-Pull output
Open-Drain output
Input only with high impendence
-
-
-
Optional TTL/Schmitt trigger input
I/O pin can be configured as interrupt source with edge/level setting
Supports high driver and high sink I/O mode
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-
-
Supports software selectable slew rate control
GPIO built-in Pull-up/Pull-low resistor for selection
Timer
-
Provides two channel 32-bit Timers; one 8-bit pre-scalar counter with 24-bit up-
timer for each timer
-
-
-
-
Independent clock source for each timer
Provides One-shot, Periodic, Toggle and Continuous operation modes
24-bit up counter value is readable through CNT (Timer Data Register)
Provides trigger counting/free counting/counter reset function triggered by
external capture pin or internal comparator signal
-
-
-
-
Supports event counter function
Supports Toggle Output mode
Supports wake-up from Idle or Power-down mode
Timer0, Timer1 and Systick provided with Continuous capture function to
capture at most 4 edges continuously on one signal
Continuous Capture
-
Timer0, Timer1 and Systick have support Continuous capture function can
Continuous Capture 4 edge on one signal
Enhanced Input Capture
-
-
One unit of 24-bit input capture counter
Capture surce:
I/O inputs: ECAP0, ECAP1 and ECAP2
PWM Trigger
ADC Trigger
WDT (Watchdog Timer)
-
Programmable clock source and time-out period
-
Supports wake-up function in Power-down mode and Idle mode
Interrupt or reset selectable on watchdog time-out
-
PWM
-
Supports a built-in 16-bit PWM clock generators, providing six PWM outputs or
three complementary paired PWM outputs
-
-
-
-
-
-
-
Shared same as clock source, clock divider, period and dead-zone generator
Supports group/synchronous/independent/ complementary modes
Supports One-shot or Auto-reload mode
Supports Edge-aligned and Center-aligned type
Supports Asymmetric mode
Programmable dead-zone insertion between complementary channels
Each output has independent polarity setting control
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Mini57
-
-
-
-
-
Hardware fault brake and software brake protections
Supports rising, falling, central, period, and fault break interrupts
Supports duty/period trigger A/D conversion
Timer comparing matching event trigger PWM to do phase change
Supports comparator event trigger PWM to force PWM output low for current
period
-
Provides interrupt accumulation function
USCI (Universal Serial Control Interface Controller)
-
-
-
Two USCI devices
Supports to be configured as UART, SPI or I²C individually
Supports programmable baud-rate generator
ADC (Analog-to-Digital Converter)
-
-
-
-
12-bit ADC with 700 kSPS
Supports 2 sample/hold
Up to 8-ch single-end input from I/O and one internal input from band-gap.
Conversion started either by software trigger, PWM trigger, ACMP trigger or
external pin trigger
-
-
Supports temperature sensor for measurement chip temperature
Supports Simultaneous and Sequential function to continuous conversion 4
channels maximum.
Programmable Gain Amplifier (PGA)
-
-
Supports 8 level gain selects from 1, 2, 3, 5, 7, 9, 11 and 13
Unity gain frequency up to 8 MHz
Analog Comparator
-
-
-
-
Two analog comparators with programmable 16-level internal voltage reference
Built-in CRV (comparator reference voltage)
Supports Hysteresis function
Interrupt when compared results changed
Hardware Divider
-
-
-
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends
to 32-bit)
-
-
-
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Waiting for calculation ready automatically when reading quotient and remainder
ISP (In-System Programming) and ICP (In-Circuit Programming)
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BOD (Brown-out Detector)
-
-
8 programmable threshold levels: 4.3V/4.0V/3.7V/3.0V/2.7V/2.4V/2.2V/2.0V
Supports Brown-out interrupt and reset option
96-bit unique ID
LVR (Low Voltage Reset)
Operating Temperature: -40℃~105℃
Reliability: EFT > ± 4KV, ESD HBM pass 4KV
Packages:
-
-
Green package (RoHS)
20-pin TSSOP, 28-pin TSSOP, 33-pin QFN
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3 ABBREVIATIONS
Acronym
ACMP
ADC
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced High-Performance Bus
Advanced Peripheral Bus
AHB
APB
BOD
BPWM
DAP
Brown-out Detection
Basic Pulse Width Modulation
Debug Access Port
EPWM
FIFO
FMC
GPIO
HCLK
HIRC
HXT
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
48 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Circuit Programming
ICP
ISP
In System Programming
ISR
Interrupt Service Routine
LDO
Low Dropout Regulator
LIRC
LXT
10 kHz internal low speed RC oscillator (LIRC)
32.768 kHz External Low Speed Crystal Oscillator
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Pulse Width Modulation
NVIC
PCLK
PWM
SPI
Serial Peripheral Interface
SPS
Samples per Second
TMR
UART
UCID
WDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Watchdog Timer
Table 3-1 List of Abbreviations
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4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® Mini57 Naming Rule
ARM–Based
32-bit Microcontroller
Mini57-X X X
CPU Core
®
Corte -M0
Temperature
E: -40oC ~ +105oC
Flash ROM
57 : 29.5 KB Flash ROM
Reserved
Package Type
F: TSSOP 20
E: TSSOP 28
T: QFN 33 4x4mm
Figure 4.1-1 NuMicro® Mini57 Series Selection Code
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4.2 NuMicro® Mini57 Series Selection Guide
* USCI can be set to UART, SPI or I2C
IRC
Connectivity
ISP
APROM RAM Data Flash Loader
ROM
ISP
Comp. PWM ADC PGA ICP
IAP
Part
Number
I/O
Timer
10 kHz
48 MHz
Package
USCI*
Mini57TDE 29.5 KB 4 KB Configurable 2.5 KB up to 22 2x32-bit
Mini57EDE 29.5 KB 4 KB Configurable 2.5 KB up to 22 2x32-bit
Mini57FDE 29.5 KB 4 KB Configurable 2.5 KB up to 18 2x32-bit
2
2
2
2
2
2
8
8
8
8x12-bit
8x12-bit
8x12-bit
v
v
v
v
v
v
v
v
v
QFN33(4x4)
TSSOP28
TSSOP20
Table 4.2-1 NuMicro® Mini57 Series Selection Guide
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4.3 Pin Configuration
4.3.1 TSSOP 28-Pin
VDD
1
2
3
4
5
6
7
8
9
10
VSS
28
27
26
25
24
23
22
PD.6
LDO_CAP
PC.4
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.5
PC.3
PD.1
PB.0
PB.1
PB.2
PB.4
PC.1
nRESET
PB.3
21
20
19
18
PC.2
PD.2
11
12
PD.3
17
16
13
14
NC
NC
PD.4
PC.0
15
Figure 4.3-1 NuMicro® Mini57 Series TSSOP 28-pin Diagram
VDD
1
VSS
28
27
26
25
24
23
22
PD.6/UART0_RXD
2
LDO_CAP
PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0
PB.1/ADC0_CH1/ACMP0_P1/ECAP_P1
3
PC.4/ECAP_P3
4
PA.0/CLKO/EPWM_CH0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
PA.1/EPWM_CH1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
PA.2/EPWM_CH2/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
PA.3/EPWM_CH3/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
PA.4/XT_IN/EPWM_CH4
PB.2/ADC0_CH2/BPWM_CH1/ACMP0_P2/ECAP_P2
PB.4/ADC1_CH0/ACMP0_N/TM1
5
6
PC.1/ADC0_CH4/STADC/ACMP0_P3/ACMP1_P1/SPI0_MOSI/SPI1_MISO
nRESET
7
8
21
20
19
18
PB.3/ACMP1_N/PGA_I/TM0
9
PA.5/XT_OUT/EPWM_CH5/ACMP0_O
PD.5/UART0_TXD
PC.2/ADC1_CH2/BRAKE/CCAP_P1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
PD.2/ICE_DAT/ADC1_CH1/CCAP_P0/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
PD.3/BPWM_CH1/UART1_TXD
10
PC.3/ACMP1_O/PGA_O/SPI0_CLK/SPI1_SS
11
12
17
16
PD.1/ICE_CLK/ACMP1_P2/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
13
14
NC
NC
PD.4/BPWM_CH0/UART1_RXD
15
PC.0/ADC0_CH3/BPWM_CH0/ACMP1_P0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
Figure 4.3-2 NuMicro® Mini57 Series TSSOP 28-pin Multi-function Diagram
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4.3.2 TSSOP 20-Pin
VDD
PB.0
1
2
3
4
5
6
7
8
9
10
VSS
20
19
18
17
16
15
14
13
12
11
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PC.3
PD.1
PC.0
PB.1
PB.2
PB.4
PC.1
nRESET
PB.3
PC.2
PD.2
Figure 4.3-3 NuMicro® Mini57 Series TSSOP 20-pin Diagram
VDD
PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0
1
VSS
20
19
18
17
16
15
14
13
12
11
2
PA.0/CLKO/EPWM_CH0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
PA.1/EPWM_CH1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
PA.2/EPWM_CH2/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
PA.3/EPWM_CH3/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
PA.4/XT_IN/EPWM_CH4
PB.1/ADC0_CH1/ACMP0_P1/ECAP_P1
3
PB.2/ADC0_CH2/BPWM_CH1/ACMP0_P2/ECAP_P2
PB.4/ADC1_CH0/ACMP0_N/TM1
4
5
PC.1/ADC0_CH4/STADC/ACMP0_P3/ACMP1_P1/SPI0_MOSI/SPI1_MISO
nRESET
6
7
PA.5/XT_OUT/EPWM_CH5/ACMP0_O
PB.3/ACMP1_N/PGA_I/TM0
8
PC.3/ACMP1_O/PGA_O/SPI0_CLK/SPI1_SS
PC.2/ADC1_CH2/BRAKE/CCAP_P1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
PD.2/ICE_DAT/ADC1_CH1/CCAP_P0/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
9
PD.1/ICE_CLK/ACMP1_P2/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
PC.0/ADC0_CH3/BPWM_CH0/ACMP1_P0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
10
Figure 4.3-4 NuMicro® Mini57 Series TSSOP 20-pin Multi-function Diagram
Apr. 06, 2017
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4.3.3 QFN 33-Pin
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
LDO_CAP
PA.2
PA.3
VSS
VDD
NC
PD.6
PB.0
Mini57
QFN 33-pin
PA.4
PA.5
PD.5
NC
PB.1
PB.2
PB.4
33 VSS
NC
9
10 11 12 13 14 15 16
Figure 4.3-5 NuMicro® Mini57 Series QFN 33-pin Diagram
Apr. 06, 2017
Page 17 of 131
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Mini57
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
LDO_CAP
PA.2/EPWM_CH2/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
VSS
VDD
PA.3/EPWM_CH3/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
NC
PD.6/UART0_RXD
Mini57
QFN 33-pin
PA.4/XT_IN/EPWM_CH4
PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0
PA.5/XT_OUT/EPWM_CH5/ACMP0_O
PD.5/UART0_TXD
PB.1/ADC0_CH1/ACMP0_P1/ECAP_P1
PB.2/ADC0_CH2/BPWM_CH1/ACMP0_P2/ECAP_P2
PB.4/ADC1_CH0/ACMP0_N/TM1
NC
NC
33 VSS
9
10 11 12 13 14 15 16
Figure 4.3-6 NuMicro® Mini57 Series QFN 33-pin Multi-function Diagram
Apr. 06, 2017
Page 18 of 131
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4.4 Pin Description
4.4.1 Mini57 Series Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFP)
PA.0 MFP0 means SYS_GPA_MFP[3:0]=0x0.
PA.4 MFP5 means SYS_GPA_MFP[19:16]=0x5.
MFP only configures the ouput data or input data of PAD; the direction of PAD is configured by PMD.
The priority of MFP in the same multi-function was GPA > GPB > GPC > GPD.
The type A of multi-function needs to be configured to be input port.
4.4.1.1 Mini57 Series TSSOP28 Pin Description
Pin No.
Pin Name
Type
MFP*
Description
1
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
2
3
PD.6
I/O
I
MFP0
MFPB
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
MFP3
MFP4
MFP7
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
General purpose digital I/O pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
ADC0 channel0 analog input.
UART0_RXD
PB.0
I/O
A
ADC0_CH0
ACMP0_P0
ECAP_P0
PB.1
A
Analog comparator0 positive input pin.
Enhanced Input Capture input pin
General purpose digital I/O pin.
ADC0 channel1 analog input.
I
4
5
I/O
A
ADC0_CH1
ACMP0_P1
ECAP_P1
PB.2
A
Analog comparator0 positive input pin.
Enhanced Input Capture input pin
General purpose digital I/O pin.
ADC0 channel2 analog input.
I
I/O
A
ADC0_CH2
BPWM_CH1
ACMP0_P2
ECAP_P2
PB.4
I/O
A
PWM channel1 output/capture input.
Analog comparator0 positive input pin.
Enhanced Input Capture input pin
General purpose digital I/O pin.
ADC1 channel0 analog input.
I
6
7
I/O
A
ADC1_CH0
ACMP0_N
TM1
A
Analog comparator0 negative input pin.
Timer1 event counter input / toggle output
General purpose digital I/O pin.
ADC0 channel4 analog input.
I/O
I/O
A
PC.1
ADC0_CH4
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Pin No.
Pin Name
STADC
Type
MFP*
MFP3
MFP4
MFP5
MFP9
MFPA
MFP0
Description
I
A
ADC external trigger input.
ACMP0_P3
ACMP1_P1
SPI0_MOSI
SPI1_MISO
nRESET
Analog comparator0 positive input pin.
Analog comparator1 positive input pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin.
A
I/O
I/O
I
8
9
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
PB.3
I/O
A
MFP0
MFP5
MFP6
MFP7
MFP0
MFP2
MFP3
MFP7
MFP8
MFP9
MFPA
MFPB
MFP0
MFP1
MFP2
MFP7
MFP8
MFP9
MFPA
MFPB
MFP0
MFP3
MFPB
General purpose digital I/O pin.
Analog comparator1 negative input pin.
PGA input pin
ACMP1_N
PGA_I
A
TM0
I/O
I/O
A
Timer0event counter input / toggle output
General purpose digital I/O pin.
ADC1 channel2 analog input.
Brake input pin of EPWM.
10
11
12
PC.2
ADC1_CH2
BRAKE
I
CCAP_P1
I2C1_SDA
SPI0_MISO
SPI1_MOSI
UART1_RXD
PD.2
I
Timer Continuous Capture input pin
I2C1 data input/output pin.
I/O
I/O
I/O
I
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Serial wired debugger data pin
ADC1 channel1 analog input.
Timer Continuous Capture input pin
I2C0 data input/output pin.
I/O
I/O
A
ICE_DAT
ADC1_CH1
CCAP_P0
I2C0_SDA
SPI0_MOSI
SPI1_MISO
UART0_RXD
PD.3
I
I/O
I/O
I/O
I
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
PWM channel1 output/capture input.
Data transmitter output pin for UART1.
No Connection
I/O
I/O
O
BPWM_CH1
UART1_TXD
NC
13
14
15
NC
No Connection
PC.0
I/O
A
MFP0
MFP2
General purpose digital I/O pin.
ADC0 channel3 analog input.
ADC0_CH3
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Pin No.
Pin Name
BPWM_CH0
ACMP1_P0
I2C1_SCL
SPI0_SS
SPI1_CLK
UART1_TXD
PD.4
Type
I/O
A
MFP*
MFP3
MFP5
MFP8
MFP9
MFPA
MFPB
MFP0
MFP3
MFPB
MFP0
MFP1
MFP5
MFP8
MFP9
MFPA
MFPB
MFP0
MFP5
MFP6
MFP9
MFPA
MFP0
MFPB
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP3
MFP0
MFP3
MFP8
Description
PWM channel0 output/capture input.
Analog comparator1 positive input pin.
I2C1 clock pin.
I/O
I/O
I/O
O
SPI0 slave select pin.
SPI1 serial clock pin
Data transmitter output pin for UART1.
General purpose digital I/O pin.
PWM channel0 output/capture input.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Serial wired debugger clock pin
Analog comparator1 positive input pin.
I2C0 clock pin.
16
17
I/O
I/O
I
BPWM_CH0
UART1_RXD
PD.1
I/O
I
ICE_CLK
ACMP1_P2
I2C0_SCL
SPI0_CLK
SPI1_SS
UART0_TXD
PC.3
A
I/O
I/O
I/O
O
SPI0 serial clock pin.
SPI1 slave select pin
Data transmitter output pin for UART0.
General purpose digital I/O pin.
Analog comparator1 output.
PGA output pin
18
I/O
O
ACMP1_O
PGA_O
A
SPI0_CLK
SPI1_SS
PD.5
I/O
I/O
I/O
O
SPI0 serial clock pin.
SPI1 slave select pin
19
20
General purpose digital I/O pin.
Data transmitter output pin for UART0.
General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal output pin.
PWM channel5 output/capture input.
Analog comparator0 output.
General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal input pin.
PWM channel4 output/capture input.
General purpose digital I/O pin.
PWM channel3 output/capture input.
I2C0 clock pin.
UART0_TXD
PA.5
I/O
O
XT_OUT
EPWM_CH5
ACMP0_O
PA.4
I/O
O
21
22
I/O
I
XT_IN
EPWM_CH4
PA.3
I/O
I/O
I/O
I/O
EPWM_CH3
I2C0_SCL
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Pin No.
Pin Name
SPI0_CLK
SPI1_SS
UART0_TXD
PA.2
Type
I/O
I/O
O
MFP*
MFP9
MFPA
MFPB
MFP0
MFP3
MFP8
MFP9
MFPA
MFPB
MFP0
MFP3
MFP8
MFP9
MFPA
MFPB
MFP0
MFP1
MFP3
MFP8
MFP9
MFPA
MFPB
MFP0
MFP7
MFP0
MFP0
Description
SPI0 serial clock pin.
SPI1 slave select pin
Data transmitter output pin for UART0.
General purpose digital I/O pin.
PWM channel2 output/capture input.
I2C0 data input/output pin.
23
I/O
I/O
I/O
I/O
I/O
I
EPWM_CH2
I2C0_SDA
SPI0_MOSI
SPI1_MISO
UART0_RXD
PA.1
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
PWM channel1 output/capture input.
I2C1 data input/output pin.
24
I/O
I/O
I/O
I/O
I/O
I
EPWM_CH1
I2C1_SDA
SPI0_MISO
SPI1_MOSI
UART1_RXD
PA.0
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Clock Out
25
I/O
O
CLKO
EPWM_CH0
I2C1_SCL
SPI0_SS
SPI1_CLK
UART1_TXD
PC.4
I/O
I/O
I/O
I/O
O
PWM channel0 output/capture input.
I2C1 clock pin.
SPI0 slave select pin.
SPI1 serial clock pin
Data transmitter output pin for UART1.
General purpose digital I/O pin.
Enhanced Input Capture input pin
LDO output pin.
26
I/O
I
ECAP_P3
LDO_CAP
VSS
27
28
A
A
Ground pin for digital circuit.
Table 4.4-1 TSSOP28 Pin Description
Apr. 06, 2017
Page 22 of 131
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Mini57
4.4.1.2 Mini57 Series TSSOP20 Pin Description
Pin No.
Pin Name
Type
MFP*
Description
1
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
2
3
4
PB.0
I/O
A
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
MFP3
MFP4
MFP7
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP9
MFPA
MFP0
General purpose digital I/O pin.
ADC0 channel0 analog input.
ADC0_CH0
ACMP0_P0
ECAP_P0
PB.1
A
Analog comparator0 positive input pin.
Enhanced Input Capture input pin
General purpose digital I/O pin.
ADC0 channel1 analog input.
I
I/O
A
ADC0_CH1
ACMP0_P1
ECAP_P1
PB.2
A
Analog comparator0 positive input pin.
Enhanced Input Capture input pin
General purpose digital I/O pin.
ADC0 channel2 analog input.
I
I/O
A
ADC0_CH2
BPWM_CH1
ACMP0_P2
ECAP_P2
PB.4
I/O
A
PWM channel1 output/capture input.
Analog comparator0 positive input pin.
Enhanced Input Capture input pin
General purpose digital I/O pin.
ADC1 channel0 analog input.
I
5
6
I/O
A
ADC1_CH0
ACMP0_N
TM1
A
Analog comparator0 negative input pin.
Timer1 event counter input / toggle output
General purpose digital I/O pin.
ADC0 channel4 analog input.
I/O
I/O
A
PC.1
ADC0_CH4
STADC
I
ADC external trigger input.
ACMP0_P3
ACMP1_P1
SPI0_MOSI
SPI1_MISO
nRESET
A
Analog comparator0 positive input pin.
Analog comparator1 positive input pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin.
A
I/O
I/O
I
7
8
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
PB.3
I/O
A
MFP0
MFP5
MFP6
MFP7
MFP0
General purpose digital I/O pin.
Analog comparator1 negative input pin.
PGA input pin
ACMP1_N
PGA_I
TM0
A
I/O
I/O
Timer0event counter input / toggle output
General purpose digital I/O pin.
9
PC.2
Apr. 06, 2017
Page 23 of 131
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Mini57
Pin No.
Pin Name
ADC1_CH2
BRAKE
Type
A
MFP*
MFP2
MFP3
MFP7
MFP8
MFP9
MFPA
MFPB
MFP0
MFP1
MFP2
MFP7
MFP8
MFP9
MFPA
MFPB
MFP0
MFP2
MFP3
MFP5
MFP8
MFP9
MFPA
MFPB
MFP0
MFP1
MFP5
MFP8
MFP9
MFPA
MFPB
MFP0
MFP5
MFP6
Description
ADC1 channel2 analog input.
Brake input pin of EPWM.
I
CCAP_P1
I2C1_SDA
SPI0_MISO
SPI1_MOSI
UART1_RXD
PD.2
I
Timer Continuous Capture input pin
I2C1 data input/output pin.
I/O
I/O
I/O
I
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Serial wired debugger data pin
ADC1 channel1 analog input.
Timer Continuous Capture input pin
I2C0 data input/output pin.
10
I/O
I/O
A
ICE_DAT
ADC1_CH1
CCAP_P0
I2C0_SDA
SPI0_MOSI
SPI1_MISO
UART0_RXD
PC.0
I
I/O
I/O
I/O
I
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
ADC0 channel3 analog input.
PWM channel0 output/capture input.
Analog comparator1 positive input pin.
I2C1 clock pin.
11
I/O
A
ADC0_CH3
BPWM_CH0
ACMP1_P0
I2C1_SCL
SPI0_SS
I/O
A
I/O
I/O
I/O
O
SPI0 slave select pin.
SPI1_CLK
UART1_TXD
PD.1
SPI1 serial clock pin
Data transmitter output pin for UART1.
General purpose digital I/O pin.
Serial wired debugger clock pin
Analog comparator1 positive input pin.
I2C0 clock pin.
12
I/O
I
ICE_CLK
ACMP1_P2
I2C0_SCL
SPI0_CLK
SPI1_SS
A
I/O
I/O
I/O
O
SPI0 serial clock pin.
SPI1 slave select pin
UART0_TXD
PC.3
Data transmitter output pin for UART0.
General purpose digital I/O pin.
Analog comparator1 output.
PGA output pin
13
I/O
O
ACMP1_O
PGA_O
A
Apr. 06, 2017
Page 24 of 131
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Mini57
Pin No.
Pin Name
SPI0_CLK
SPI1_SS
PA.5
Type
I/O
I/O
I/O
O
MFP*
MFP9
MFPA
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP3
MFP0
MFP3
MFP8
MFP9
MFPA
MFPB
MFP0
MFP3
MFP8
MFP9
MFPA
MFPB
MFP0
MFP3
MFP8
MFP9
MFPA
MFPB
MFP0
MFP1
MFP3
MFP8
MFP9
MFPA
Description
SPI0 serial clock pin.
SPI1 slave select pin
14
General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal output pin.
PWM channel5 output/capture input.
Analog comparator0 output.
General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal input pin.
PWM channel4 output/capture input.
General purpose digital I/O pin.
PWM channel3 output/capture input.
I2C0 clock pin.
XT_OUT
EPWM_CH5
ACMP0_O
PA.4
I/O
O
15
16
I/O
I
XT_IN
EPWM_CH4
PA.3
I/O
I/O
I/O
I/O
I/O
I/O
O
EPWM_CH3
I2C0_SCL
SPI0_CLK
SPI1_SS
UART0_TXD
PA.2
SPI0 serial clock pin.
SPI1 slave select pin
Data transmitter output pin for UART0.
General purpose digital I/O pin.
PWM channel2 output/capture input.
I2C0 data input/output pin.
17
18
19
I/O
I/O
I/O
I/O
I/O
I
EPWM_CH2
I2C0_SDA
SPI0_MOSI
SPI1_MISO
UART0_RXD
PA.1
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
PWM channel1 output/capture input.
I2C1 data input/output pin.
I/O
I/O
I/O
I/O
I/O
I
EPWM_CH1
I2C1_SDA
SPI0_MISO
SPI1_MOSI
UART1_RXD
PA.0
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Clock Out
I/O
O
CLKO
EPWM_CH0
I2C1_SCL
SPI0_SS
SPI1_CLK
I/O
I/O
I/O
I/O
PWM channel0 output/capture input.
I2C1 clock pin.
SPI0 slave select pin.
SPI1 serial clock pin
Apr. 06, 2017
Page 25 of 131
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Mini57
Pin No.
Pin Name
UART1_TXD
VSS
Type
O
MFP*
MFPB
MFP0
Description
Data transmitter output pin for UART1.
Ground pin for digital circuit.
20
A
Table 4.4-2 TSSOP20 Pin Description
Apr. 06, 2017
Page 26 of 131
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Mini57
4.4.1.3 Mini57 Series QFN33 Pin Description
QFN33 Pin
Pin Name
Type
MFP* Description
No.
1
LDO_CAP
A
MFP0 LDO output pin.
2
VSS
A
A
MFP0 Ground pin for digital circuit.
33
Power supply for I/O ports and LDO source for internal PLL and digital
3
4
VDD
MFP0
function.
PD.6
I/O
I
MFP0 General purpose digital I/O pin.
MFPB Data receiver input pin for UART0.
MFP0 General purpose digital I/O pin.
MFP2 ADC0 channel0 analog input.
UART0_RXD
PB.0
I/O
A
ADC0_CH0
ACMP0_P0
ECAP_P0
PB.1
5
6
A
MFP4 Analog comparator0 positive input pin.
MFP7 Enhanced Input Capture input pin
MFP0 General purpose digital I/O pin.
MFP2 ADC0 channel1 analog input.
I
I/O
A
ADC0_CH1
ACMP0_P1
ECAP_P1
PB.2
A
MFP4 Analog comparator0 positive input pin.
MFP7 Enhanced Input Capture input pin
MFP0 General purpose digital I/O pin.
MFP2 ADC0 channel2 analog input.
I
I/O
A
ADC0_CH2
BPWM_CH1
ACMP0_P2
ECAP_P2
PB.4
7
I/O
A
MFP3 PWM channel1 output/capture input.
MFP4 Analog comparator0 positive input pin.
MFP7 Enhanced Input Capture input pin
MFP0 General purpose digital I/O pin.
MFP2 ADC1 channel0 analog input.
I
I/O
A
ADC1_CH0
ACMP0_N
TM1
8
A
MFP4 Analog comparator0 negative input pin.
MFP7 Timer1 event counter input / toggle output
MFP0 General purpose digital I/O pin.
MFP2 ADC0 channel4 analog input.
I/O
I/O
A
PC.1
ADC0_CH4
STADC
I
MFP3 ADC external trigger input.
9
ACMP0_P3
ACMP1_P1
SPI0_MOSI
SPI1_MISO
A
MFP4 Analog comparator0 positive input pin.
MFP5 Analog comparator1 positive input pin.
MFP9 SPI0 1st MOSI (Master Out, Slave In) pin.
MFPA SPI1 MISO (Master In, Slave Out) pin.
A
I/O
I/O
External reset input: active LOW, with an internal pull-up. Set this pin low
reset to initial state.
10
nRESET
I
MFP0
Apr. 06, 2017
Page 27 of 131
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Mini57
PB.3
I/O
A
MFP0 General purpose digital I/O pin.
MFP5 Analog comparator1 negative input pin.
MFP6 PGA input pin
ACMP1_N
PGA_I
11
A
TM0
I/O
I/O
A
MFP7 Timer0event counter input / toggle output
MFP0 General purpose digital I/O pin.
MFP2 ADC1 channel2 analog input.
MFP3 Brake input pin of EPWM.
PC.2
ADC1_CH2
BRAKE
I
CCAP_P1
I2C1_SDA
SPI0_MISO
SPI1_MOSI
UART1_RXD
PD.2
I
MFP7 Timer Continuous Capture input pin
MFP8 I2C1 data input/output pin.
12
I/O
I/O
I/O
I
MFP9 SPI0 1st MISO (Master In, Slave Out) pin.
MFPA SPI1 MOSI (Master Out, Slave In) pin.
MFPB Data receiver input pin for UART1.
MFP0 General purpose digital I/O pin.
MFP1 Serial wired debugger data pin
MFP2 ADC1 channel1 analog input.
MFP7 Timer Continuous Capture input pin
MFP8 I2C0 data input/output pin.
I/O
I/O
A
ICE_DAT
ADC1_CH1
CCAP_P0
I2C0_SDA
SPI0_MOSI
SPI1_MISO
UART0_RXD
PD.3
I
13
I/O
I/O
I/O
I
MFP9 SPI0 1st MOSI (Master Out, Slave In) pin.
MFPA SPI1 MISO (Master In, Slave Out) pin.
MFPB Data receiver input pin for UART0.
MFP0 General purpose digital I/O pin.
MFP3 PWM channel1 output/capture input.
MFPB Data transmitter output pin for UART1.
No Connection
I/O
I/O
O
14
BPWM_CH1
UART1_TXD
NC
15
16
17
18
NC
No Connection
NC
No Connection
NC
No Connection
PD.5
I/O
O
MFP0 General purpose digital I/O pin.
MFPB Data transmitter output pin for UART0.
MFP0 General purpose digital I/O pin.
MFP1 External 4~24 MHz (high speed) crystal output pin.
MFP3 PWM channel5 output/capture input.
MFP4 Analog comparator0 output.
MFP0 General purpose digital I/O pin.
19
UART0_TXD
PA.5
I/O
O
XT_OUT
EPWM_CH5
ACMP0_O
PA.4
20
21
I/O
O
I/O
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XT_IN
I
MFP1 External 4~24 MHz (high speed) crystal input pin.
MFP3 PWM channel4 output/capture input.
No Connection
EPWM_CH4
NC
I/O
22
23
PA.3
I/O
I/O
I/O
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP3 PWM channel3 output/capture input.
MFP8 I2C0 clock pin.
EPWM_CH3
I2C0_SCL
SPI0_CLK
SPI1_SS
UART0_TXD
PA.2
MFP9 SPI0 serial clock pin.
MFPA SPI1 slave select pin
MFPB Data transmitter output pin for UART0.
MFP0 General purpose digital I/O pin.
MFP3 PWM channel2 output/capture input.
MFP8 I2C0 data input/output pin.
I/O
I/O
I/O
I/O
I/O
I
EPWM_CH2
I2C0_SDA
SPI0_MOSI
SPI1_MISO
UART0_RXD
PA.1
24
MFP9 SPI0 1st MOSI (Master Out, Slave In) pin.
MFPA SPI1 MISO (Master In, Slave Out) pin.
MFPB Data receiver input pin for UART0.
MFP0 General purpose digital I/O pin.
MFP3 PWM channel1 output/capture input.
MFP8 I2C1 data input/output pin.
I/O
I/O
I/O
I/O
I/O
I
EPWM_CH1
I2C1_SDA
SPI0_MISO
SPI1_MOSI
UART1_RXD
PA.0
25
MFP9 SPI0 1st MISO (Master In, Slave Out) pin.
MFPA SPI1 MOSI (Master Out, Slave In) pin.
MFPB Data receiver input pin for UART1.
MFP0 General purpose digital I/O pin.
MFP1 Clock Out
I/O
O
CLKO
EPWM_CH0
I2C1_SCL
SPI0_SS
SPI1_CLK
UART1_TXD
PC.4
I/O
I/O
I/O
I/O
O
MFP3 PWM channel0 output/capture input.
MFP8 I2C1 clock pin.
26
MFP9 SPI0 slave select pin.
MFPA SPI1 serial clock pin
MFPB Data transmitter output pin for UART1.
MFP0 General purpose digital I/O pin.
MFP7 Enhanced Input Capture input pin
MFP0 General purpose digital I/O pin.
MFP2 ADC0 channel3 analog input.
MFP3 PWM channel0 output/capture input.
MFP5 Analog comparator1 positive input pin.
I/O
I
27
28
ECAP_P3
PC.0
I/O
A
ADC0_CH3
BPWM_CH0
ACMP1_P0
I/O
A
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I2C1_SCL
SPI0_SS
SPI1_CLK
UART1_TXD
PD.4
I/O
I/O
I/O
O
MFP8 I2C1 clock pin.
MFP9 SPI0 slave select pin.
MFPA SPI1 serial clock pin
MFPB Data transmitter output pin for UART1.
MFP0 General purpose digital I/O pin.
MFP3 PWM channel0 output/capture input.
MFPB Data receiver input pin for UART1.
MFP0 General purpose digital I/O pin.
MFP1 Serial wired debugger clock pin
MFP5 Analog comparator1 positive input pin.
MFP8 I2C0 clock pin.
I/O
I/O
I
29
BPWM_CH0
UART1_RXD
PD.1
I/O
I
ICE_CLK
ACMP1_P2
I2C0_SCL
SPI0_CLK
SPI1_SS
UART0_TXD
PC.3
A
30
I/O
I/O
I/O
O
MFP9 SPI0 serial clock pin.
MFPA SPI1 slave select pin
MFPB Data transmitter output pin for UART0.
MFP0 General purpose digital I/O pin.
MFP5 Analog comparator1 output.
MFP6 PGA output pin
I/O
O
ACMP1_O
PGA_O
31
32
A
SPI0_CLK
SPI1_SS
NC
I/O
I/O
MFP9 SPI0 serial clock pin.
MFPA SPI1 slave select pin
No Connection
Table 4.4-3 QFN33 Pin Description
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4.4.2 GPIO Multi-function Pin Summary
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFP)
PA.0 MFP0 means SYS_GPA_MFP[3:0]=0x0.
PA.4 MFP5 means SYS_GPA_MFP[19:16]=0x5.
Group
Pin Name
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_N
ACMP0_P3
ACMP0_O
ACMP1_P1
ACMP1_N
ACMP1_O
ACMP1_P2
ACMP1_P0
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH4
ADC0_CH3
ADC1_CH0
ADC1_CH2
ADC1_CH1
BPWM_CH1
BPWM_CH0
BPWM_CH1
BPWM_CH0
CCAP_P1
CCAP_P0
CLKO
GPIO
PB.0
PB.1
PB.2
PB.4
PC.1
PA.5
PC.1
PB.3
PC.3
PD.1
PC.0
PB.0
PB.1
PB.2
PC.1
PC.0
PB.4
PC.2
PD.2
PB.2
PC.0
PD.3
PD.4
PC.2
PD.2
PA.0
PB.0
PB.1
PB.2
MFP*
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP5
MFP5
MPF5
MFP5
MFP5
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP3
MFP3
MFP3
MFP3
MFP7
MFP7
MFP1
MFP7
MFP7
MFP7
Type Description
Comparator0 positive input pin.
A
A
A
A
A
O
A
A
O
A
A
A
A
A
A
A
A
A
A
O
O
O
O
I
Comparator0 positive input pin.
Comparator0 positive input pin.
Comparator0 negative input pin.
Comparator0 positive input pin.
Comparator0 output pin.
ACMP0
Comparator1 positive input pin.
Comparator1 negative input pin.
Comparator1 output pin.
ACMP1
Comparator1 positive input pin.
Comparator1 positive input pin.
ADC0 analog input channel 0.
ADC0 analog input channel 1.
ADC0 analog input channel 2.
ADC0 analog input channel 4.
ADC0 analog input channel 3.
ADC1 analog input channel 0.
ADC1 analog input channel 2.
ADC1 analog input channel 1.
Basic PWM channel 1 output
Basic PWM channel 0 output
Basic PWM channel 1 output
Basic PWM channel 0 output
Continuous Capture Input
ADC0
ADC1
BPWM
CCAP
CLKO
I
Continuous Capture Input
O
I
Clock output pin.
ECAP_P0
Input capture channel 0
ECAP
ECAP_P1
I
Input capture channel 1
ECAP_P2
I
Input capture channel 2
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BRAKE
PC.2
PA.5
PA.4
PA.3
PA.2
PA.1
PA.0
PC.2
PD.2
PD.1
PC.0
PA.3
PA.2
PA.1
PA.0
PD.2
PD.1
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP1
MFP1
I
EPWM brake pin.
EPWM_CH5
EPWM_CH4
EPWM_CH3
EPWM_CH2
EPWM_CH1
EPWM_CH0
I2C1_SDA
I2C0_SDA
I2C0_SCL
I2C1_SCL
I2C0_SCL
I2C0_SDA
I2C1_SDA
I2C1_SCL
ICE_DAT
O
Enhanced PWM output pin.
Enhanced PWM output pin.
Enhanced PWM output pin.
Enhanced PWM output pin.
Enhanced PWM output pin.
Enhanced PWM output pin.
I2C1 data pin.
O
EPWM
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I2C0 data pin.
I2C0 clock pin.
I2C1 clock pin.
I2C
I2C0 clock pin.
I2C0 data pin.
I2C1 data pin.
I2C1 clock pin.
Serial wired debugger data pin
Serial wired debugger clock pin
External reset pin, internal pull-high.
PGA analog input pin.
ICE
ICE_CLK
nRESET
PGA
nRESET
I
PGA_I
PB.3
PC.3
PC.1
PC.2
PD.2
PC.3
PD.1
PC.0
PA.3
PA.2
PA.1
PA.0
PC.1
PC.2
PD.2
PC.3
MFP6
MFP6
MFP9
MFP9
MFP9
MFP9
MFP9
MFP9
MFP9
MFP9
MFP9
MFP9
MFPA
MFPA
MFPA
MFPA
A
PGA_O
A
PGA analog output pin.
SPI0 MOSI (Master Out, Slave In) pin.
SPI0 MISO (Master In, Slave Out) pin.
SPI0 MOSI (Master Out, Slave In) pin.
SPI0 clock pin.
SPI0_MOSI
SPI0_MISO
SPI0_MOSI
SPI0_CLK
SPI0_CLK
SPI0_SS
I/O
I/O
I/O
I/O
I/O
I
SPI0 clock pin.
SPI0
SPI0 slave selection pin.
SPI0 clock pin.
SPI0_CLK
SPI0_MOSI
SPI0_MISO
SPI0_SS
I/O
I/O
I/O
I
SPI0 MOSI (Master Out, Slave In) pin.
SPI0 MISO (Master In, Slave Out) pin.
SPI0 slave selection pin.
SPI1 MISO (Master In, Slave Out) pin
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin
SPI1 Slave Select
SPI1_MISO
SPI1_MOSI
SPI1_MISO
SPI1_SS
I/O
I/O
I/O
I/O
SPI1
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SPI1_SS
PD.1
PC.0
PA.3
PA.2
PA.1
PA.0
PC.1
PB.3
PB.4
PD.2
PD.1
PA.3
PA.2
PD.5
PD.6
PC.2
PC.0
PA.1
PA.0
PD.3
PD.4
PA.5
PA.4
MFPA
MFPA
MFPA
MFPA
MFPA
MFPA
MFP3
MFP7
MFP7
MFPB
MFPB
MFPB
MFPB
MFPB
MFPB
MFPB
MFPB
MFPB
MFPB
MFPB
MFPB
MPF1
MFP1
I/O
I/O
I
SPI1 Slave Select
SPI1_CLK
SPI1_SS
SPI1 clock pin.
SPI1 slave selection pin.
SPI1_MISO
SPI1_MOSI
SPI1_CLK
STADC
I/O
I/O
I/O
I
SPI1 MISO (Master In, Slave Out) pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 clock pin.
STADC
TM0
External ADC trigger input pin.
Timer0 event counter input / toggle output
Timer1 event counter input / toggle output
UART0 data receiver input pin.
UART0 data transmitter output pin.
UART0 data transmitter output pin.
UART0 data receiver input pin.
UART0 data transmitter output pin.
UART0 data receiver input pin.
UART1 data receiver input pin.
UART1 data transmitter output pin.
UART1 data receiver input pin.
UART1 data transmitter output pin.
UART1 data transmitter output pin.
UART1 data receiver input pin.
External crystal output pin.
TM0
I
TM1
TM1
I
UART0_RXD
UART0_TXD
UART0_TXD
UART0_RXD
UART0_TXD
UART0_RXD
UART1_RXD
UART1_TXD
UART1_RXD
UART1_TXD
UART1_TXD
UART1_RXD
XT_OUT
I
O
O
I
UART0
O
I
I
O
I
UART1
O
O
I
A
A
XT
XT_IN
External crystal input pin.
Table 4.4-4 TSSOP20 Multi-function Pin Summary
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5 BLOCK DIAGRAM
5.1 NuMicro® Mini57 Block Diagram
Figure 5.1-1 NuMicro® Mini57 Block Diagram
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6 FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
6.1.1 Overview
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes – Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6.1-1 shows the functional controller of processor.
Cortex-M0 Components
Cortex-M0 Processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6.1-1 Functional Block Diagram
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6.1.2 Features
The implemented device provides:
A low gate count processor:
-
-
-
-
-
-
-
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
-
-
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
-
-
-
-
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support:
-
-
-
-
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
-
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
-
Single 32-bit slave port that supports the DAP (Debug Access Port)
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6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Reset
System Power Architecture
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset, and multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset can reset chip
through peripheral reset signals. Software reset can trigger reset through control registers.
Hardware Reset Sources
-
-
-
-
-
Power-on Reset (POR)
Low level on the nRESET pin
Watchdog Timer Time-out Reset (WDT)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD Reset)
Software Reset Sources
-
-
CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
MCU Reset to reboot but keeping the booting setting from APROM or LDROM
by writing 1 to SYSRESETREQ (SCS_AIRCR[2])
-
CPU Reset for Cortex® -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1])
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Glitch Filter
16.8 us
nRESET
~50k ohm
@5v
Power-on
Reset
VDD
Reset Pulse Width
3.2ms
Low Voltage
Reset
VDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT
Reset
Reset Pulse Width
64 WDT clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(SCS_AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Resources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M0 only; the other reset sources will reset Cortex® -M0 and all peripherals. However,
there are small differences between each reset source and they are listed in Table 6.2-5.
Reset Sources
POR
nRESET
WDT
LVR
BOD
CHIP
MCU
CPU
Register
SYS_RSTSTS
0x001
0x0
Bit 1 = 1
-
Bit 2 = 1
-
0x001
-
Bit 4 = 1
-
Bit 0 = 1
-
Bit 5 = 1
-
Bit 7 = 1
-
CHIPRST
(SYS_IPRST0[0])
BODEN
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG
0
-
Reload
from
CONFIG0
Reload
from
CONFIG0
-
(SYS_BODCTL[0])
BODVL
(SYS_BODCTL[2:1])
BODRSTEN
(SYS_BODCTL[3])
XTLEN
0x0
0x1
0x0
-
0x0
0x1
0x0
-
0x0
-
0x0
0x1
0x0
-
(CLK_PWRCTL[1:0])
WDTCKEN
-
(CLK_APBCLK0[0])
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HCLKSEL
0x8
0x3
0x0
0x0
0x0
0x0
0x8
0x3
-
0x8
0x8
0x8
0x8
0x8
-
-
-
(CLK_CLKSEL0[1:0])
WDTSEL
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
XLTSTB
(CLK_STATUS[0])
LIRCSTB
(CLK_STATUS[3])
HIRCSTB
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_STATUS[4])
CLKSFAIL
0x0
(CLK_STATUS[7])
WDT_CTL
0x0700
0x0000
0x0000
0x3F0800
0x0700
0x0000
0x0000
0x3F0800
0x0700
0x0000
0x0000
0x3F0800
0x0700
0x0000
0x0000
0x0700
0x0000
0x0000
0x3F0800
0x0700
0x0000
0x0000
0x3F0800
-
-
-
-
-
-
-
-
WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x3F080
0
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
-
-
-
-
-
-
BS
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG
0
Reload
from
CONFIG0
Reload
from
CONFIG0
(FMC_ISPCTL[1])
ISPEN
(FMC_ISPCTL[16])
FMC_DFBA
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG
1
Reload
from
CONFIG1
Reload
from
CONFIG1
-
-
-
-
-
-
CBS
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG
0
Reload
from
CONFIG0
Reload
from
CONFIG0
(FMC_ISPSTS[2:1))
VECMAP
Reload
base on
CONFIG0
Reload
base on
CONFIG0
Reload
base on
CONFIG0
Reload
base on
CONFIG
0
Reload
base on
CONFIG0
Reload
base on
CONFIG0
(FMC_ISPSTS[20:9])
Other
Registers
Peripheral
Reset Value
Reset Value
FMC Registers
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET
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voltage is lower than 0.2 VDD and the state keeps longer than 16.8 us (glitch filter), chip will be
reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above
0.7 VDD and the state keeps longer than 36 us (glitch filter). The PINRF (SYS_RSTSTS[1]) will be
set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset
waveform.
nRESET
0.7 VDD
16.8 us
0.2 VDD
16.8 us
nRESET Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2 Power-On Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the
system to be reset when power-on to avoid unexpected behavior of MCU. When applying the
power to MCU, the POR module will detect the rising voltage and generate reset signal to system
until the voltage is ready for MCU operation. At POR reset, the PORF (SYS_RSTSTS[0]) will be
set to 1 to indicate there is a POR reset event. The PORF (SYS_RSTSTS[0]) bit can be cleared
by writing 1 to it. Figure 6.2-3 shows the waveform of Power-On reset.
VPOR
0.1V
VDD
Power On
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3 Low Voltage Reset (LVR)
Low Voltage Reset detects AVDD during system operation. When the AVDD voltage is lower than
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VLVR and the state keeps longer than De-glitch time (16*HCLK cycles), chip will be reset. The LVR
reset will control the chip in reset state until the AVDD voltage rises above VLVR and the state
keeps longer than De-glitch time. The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous
reset source is nRESET reset. Figure 6.2-4 shows the Low Voltage Reset waveform.
AVDD
VLVR
T1
T2
( < de-glitch time) ( = de-glitch time)
Low Voltage Reset
T3
( = de-glitch time)
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-Out Detector function will detect AVDD during system
operation. When the AVDD voltage is lower than VBOD which is decided by BODEN
(SYS_BODCTL[0]) and BODVL (SYS_BODCTL[2:1]) and the state keeps longer than De-glitch
time (Max(20*HCLK cycles, 1*LIRC cycle)), chip will be reset. The BOD reset will control the chip
in reset state until the AVDD voltage rises above VBOD and the state keeps longer than De-glitch
time. The default value of BODEN, BODVL and BODRSTEN is set by Flash controller user
configuration register CBODEN (CONFIG0[12]), CBOV (CONFIG0[15:13]) and CBORST
(CONFIG0[12]) respectively. User can determine the initial BOD setting by setting the CONFIG0
register. Figure 6.2-5 shows the Brown-Out Detector waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< de-glitch time) (= de-glitch time)
BODOUT
T3
(= de-glitch time)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5 Watchdog Timer Reset
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watchdog timer (WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may
cause the watchdog time-out. User may decide to enable system reset during watchdog time-out
to recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking WDTRF
(SYS_RSTSTS[2]).
6.2.2.6 CPU Reset, CHIP Reset and SYSTEM Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST (SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and BS
(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG setting. User can set the CHIPRST
(SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS (FMC_ISPCTL[1]) will not
be reloaded from CONFIG setting and keep its original software setting for booting from APROM
or LDROM. User can set the SYSRESETREQ (SCS_AIRCR[2]) to 1 to assert the MCU Reset.
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6.2.3 Power Modes and Wake-up Sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the
available clocks for each power mode.
Power Mode
Definition
Normal Mode
Idle Mode
Power-Down Mode
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer, UART, SPI,
ACMP, BOD and GPIO
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-2 Power Mode Difference Table
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP (SCS_SCR[2]) = 1
2. PDEN (CLK_PWRCTL[7]) = 1 and
PDWKIF (CLK_PWRCTL[8]) = 1
3. CPU executes WFI
Wake-up events
occur
Idle Mode
Power-down Mode
CPU Clock OFF
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash Halt
Flash Halt
Figure 6.2-6 Power Mode State Machine
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode.
2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
Normal Mode
Idle Mode
Power-Down Mode
HXT (4~20 MHz XTL)
ON
ON
ON
ON
Halt
Halt
HIRC (12/16 MHz OSC)
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LXT (32768 Hz XTL)
LIRC (10 kHz OSC)
LDO
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON/OFF1
ON/OFF2
ON
CPU
Halt
HCLK/PCLK
SRAM retention
FLASH
Halt
ON
Halt
GPIO
Halt
TIMER
ON/OFF3
Halt
BPWM
EPWM
Halt
WDT
ON/OFF4
Halt
USCI
ADC
Halt
ACMP
Halt
ECAP
Halt
HDIV
Halt
PGA
Halt
Table 6.2-3 Clocks in Power Modes
Wake-up sources in Power-down mode:
WDT, I²C, Timer, UART, SPI, BOD, ACMP and GPIO
After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN (CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
Source
BOD
Brown-Out Detector Interrupt After software writes 1 to clear SYS_BODCTL[BODIF].
GPIO
GPIO Interrupt
Timer Interrupt
After software write 1 to clear the Px_INTSRC[n] bit.
TIMER
After software writes
(TIMERx_INTSTS[0]).
1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
WDT
WDT Interrupt
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
After software writes 1 to clear WKF (UUART_WKSTS[0]).
USCI UART
Incoming data wake-up
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USCI SPI
USCI I2C
SS transaction wake-up
Data toggle
After software writes 1 to clear WKF (USPI_WKSTS[0]).
After software writes 1 to clear WKF (UI2C_WKSTS[0]).
After software writes 1 to clear WKAKDONE (UI2C_PROTSTS[16], then writes 1
to clear WKF (UI2C_WKSTS[0]).
Address match
ACMP
Comparator Power-down After software writes 1 to clear ACMPF0 (ACMP_STATUS[0]) and ACMPF1
Wake-Up Interrupt (ACMP_STATUS[1]).
Table 6.2-4 Condition of Entering Power-down Mode Again
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6.2.4 System Power Architecture
In this chip, the power distribution is divided into three segments.
Analog power from AVDD and AVSS provides the power for analog components
operation. AVDD must be equal to VDD to avoid leakage current.
Digital power from VDD and VSS supplies power to the I/O pins and internal regulator
which provides a fixed 1.5V power for digital operation.
A built-in capacitor for internal voltage regulator
The output of internal voltage regulator, LDO, does not require an external capacitor and doesn’t
bond out to external pin. Analog power (AVDD) should be the same voltage level of the digital
power (VDD).
Temperature
SRAM
Flash
Digital Logic
Sensor
1.5V
10 kHz
LIRC
Oscillator
48 MHz HIRC
Oscillator
POR15
4~24 MHz or
32.768 kHz
crystal oscillator
2.1~5.5V
to 1.5V
LDO
XT_OUT
XT_IN
Power On
Control
GPIO
POR50
IO Cell
Brown-out
Detector
Low Voltage
Reset
Analog
Comparator
12-bit ADC
Mini57 power distribution
Figure 6.2-7 NuMicro® Mini57 Series Power Architecture Diagram
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6.2.5 System Memory Mapping
Mini57
System Control
System Control
4 GB
0xFFFF_FFFF
0xE000_ED00 SCS_BA
0xE000_E100 SCS_BA
0xE000_E010 SCS_BA
Reserved
System Control
Reserved
Reserved
Reserved
AHB
|
External Interrupt Control
System Timer Control
0xE000_F000
0xE000_EFFF
0xE000_E000
0xE000_E00F
|
0x6002_0000
0x6001_FFFF
0x6000_0000
0x5FFF_FFFF
|
0x5020_0000
0x501F_FFFF
0x5000_0000
0x4FFF_FFFF
AHB peripherals
FMC
0x5000_C000 FMC_BA
0x5000_4000 GP_BA
GPIO Control
Interrupt Multiplexer Control 0x5000_0300 INT_BA
Clock Control
0x5000_0200 CLK_BA
0x5000_0000 SYS_BA
Reserved
|
System Global Control
0x4020_0000
0x401F_FFFF
APB
|
1 GB
0x4000_0000
0x3FFF_FFFF
APB peripherals
ECAP Control
0x401B_0000 ECAP_BA
0x4017_0000 USCI1_BA
0x4014_0000 BPWM_BA
0x400F_0000 PGA_BA
0x400E_0000 ADC_BA
0x400D_0000 ACMP_BA
0x4007_0000 USCI0_BA
0x4004_0000 EPWM_BA
0x4001_0000 TMR01_BA
0x4000_4000 WDT_BA
USCI1 Control
BPWM Control
Reserved
|
PGA Control
ADC Control
0x2000_1000
0x2000_0FFF
0x2000_0000
0x1FFF_FFFF
ACMP 0/1 Control
USCI0 Control
EPWM Control
4 KB SRAM
Reserved
0.5 GB
Timer0/Timer1 Control
WDT Control
|
0x0000_7600
0x0000_75FF
|
29.5 KB on-chip Flash (Mini57)
0 GB
0x0000_0000
Table 6.2-5 Memory Mapping Table
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6.2.6 Register Protection
Some of the system control registers need to be protected to avoid inadvertent write and disturb
the chip operation. These system control registers are protected after the power on reset till user
to disable register protection. For user to program these protected registers, a register protection
disable sequence needs to be followed by a special programming. The register protection disable
sequence is writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL continuously. Any
different data value, different sequence or any other write to other address during these three
data writing will abort the whole sequence.
After the protection is disabled, user can check REGLCTL (SYS_REGLCTL [0]), “1” is protection
disable, “0” is protection enable. Then user can update the target protected register value and
then write any data to SYS_REGLCTL to enable register protection.
The protected registers are listed in Table 6.2-6.
Register
Bit
Description
[1] CPURST
[0] CHIPRST
[15] LVREN
[6] BODLPM
[4] BODRSTEN
[3:1] BODVL
[0] BODEN
Processor Core One-shot Reset (Write Protect)
Chip One-shot Reset (Write Protect)
SYS_IPRST0
Low Voltage Reset Enable Control (Write Protect)
Brown-out Detector Low Power Mode (Write Protect)
Brown-out Reset Enable Control (Write Protect)
Brown-out Detector Threshold Voltage Selection (Write Protect)
Brown-out Detector Enable Control (Write Protect)
Power-on Reset Enable Control (Write Protect)
NMI Interrupt Enable Control (Write Protected)
HXT Gain Control (Write Protect)
SYS_BODCTL
SYS_PORCTL
INT_NMICTL
[15:0] POROFF
[8] NMISELEN
[11:10] HXTGAIN
[7] PDEN
System Power-down Enable Control (Write Protect)
Power-down Mode Wake-up Interrupt Enable Control (Write Protect)
Wake-up Delay Counter Enable Control (Write Protect)
LIRC Enable Control (Write Protect)
[5] PDWKIEN
[4] PDWKDLY
[3] LIRCEN
CLK_PWRCTL
[2] HIRCEN
[1:0] XTLEN
[0] WDTCKEN
[4:3] STCLKSEL
[1:0] HCLKSEL
[1:0] WDTSEL
[6] ISPFF
HIRC Enable Control (Write Protect)
XTL Enable Control (Write Protect)
CLK_APBCLK
CLK_CLKSEL0
CLK_CLKSEL1
Watchdog Timer Clock Enable Control (Write Protect)
Cortex® -M0 SysTick Clock Source Selection (Write Protect)
HCLK Clock Source Selection (Write Protect)
Watchdog Timer Clock Source Selection (Write Protect)
ISP Fail Flag (Write Protect)
FMC_ISPCTL
[5] LDUEN
LDROM Update Enable Control (Write Protect)
CONFIG Update Enable Control (Write Protect)
[4] CFGUEN
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[3] APUEN
[2] SPUEN
[1] BS
APROM Update Enable Control (Write Protect)
SPROM Update Enable Control (Write Protect)
Boot Select (Write Protect)
[0] ISPEN
ISP Enable Control (Write Protect)
FMC_ISPTRG
FMC_ISPSTS
TIMER0_CTL
TIMER1_CTL
[0] ISPGO
ISP Start Trigger (Write Protect)
[6] ISPFF
ISP Fail Flag (Write Protect)
[31] ICEDEBUG
[31] ICEDEBUG
[31] ICEDEBUG
[7] WDTEN
[6] INTEN
ICE Debug Mode Acknowledge Disable Control (Write Protect)
ICE Debug Mode Acknowledge Disable Control (Write Protect)
ICE Debug Mode Acknowledge Disable Control (Write Protect)
Watchdog Timer Enable Control (Write Protect)
Watchdog Timer Time-out Interrupt Enable Control (Write Protect)
Watchdog Timer Time-out Wake-up Function Control (Write Protect)
Watchdog Timer Time-out Reset Enable Control (Write Protect)
Reset Watchdog Timer Up Counter (Write Protect)
WDT_CTL
[4] WKEN
[1] RSTEN
[0] RSTCNT
Table 6.2-6 Protected Registers
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6.2.7 Memory Organization
6.2.7.1 Overview
The NuMicro® Mini57 series provides 4G-byte addressing space. The addressing space assigned
to each on-chip controllers is shown in Figure 6.2-8. The detailed register definition, addressing
space, and programming details will be described in the following sections for each on-chip
peripheral. The Mini57 series only supports little-endian data format.
Reserved
Reserved
User Configuration
User Configuration
0x0030_0004
0x0030_0000
(8B)
(8B)
Reserved
Reserved
0x0028_01FF
0x0028_0000
Security Protection
Security Protection
ROM2
(SPROM1 512B)
(SPROM1 512B)
ROM2
Reserved
Reserved
0x0024_01FF
0x0024_0000
Security Protection
Security Protection
ROM1
(SPROM1 512B)
(SPROM1 512B)
ROM1
Reserved
Reserved
0x0020_01FF
0x0020_0000
Security Protection
Security Protection
ROM0
(SPROM0 512B)
(SPROM0 512B)
ROM0
Reserved
Reserved
0x0010_07FF
0x0010_0000
Loader ROM
Loader ROM
(LDROM 2KB)
(LDROM 2KB)
Reserved
Reserved
0x0000_75FF
ApplicationROM
ApplicationROM
(APROM 29.5KB)
(APROM 29.5KB)
0x0000_0000
Figure 6.2-8 NuMicro® Mini57 Flash, Security and Configuration Map
6.2.7.2 System Memory Map
The Mini57 series provides 4G-byte addressing space. The memory locations assigned to each
on-chip controllers are shown in Table 6.2-7. The detailed register definition, memory space, and
programming will be described in the following sections for each on-chip peripheral. The Mini57
series only supports little-endian data format.
The memory locations assigned to each on-chip controllers are shown in Table 6.2-7.
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Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0000_75FF
0x0010_0000 – 0x0010_07FF
FLASH_BA
LD_BA
FLASH Memory Space (29.5KB)
Loader Memory Space (2 KB)
0x0020_0000 – 0x0020_01FF
0x0024_0000 – 0x0024_01FF
0x0028_0000 – 0x0028_01FF
0x2000_0000 – 0x2000_0FFF
SP0_BA
SP1_BA
SP2_BA
SRAM_BA
Security Program Memory 0 Space (0.5 KB)
Security Program Memory 1 Space (0.5 KB)
Security Program Memory 2 Space (0.5 KB)
SRAM Memory Space (4 KB)
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_C000 – 0x5000_FFFF
0x5001_4000 – 0x5001_7FFF
SYS_BA
CLK_BA
INT_BA
System Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
FMC_BA
HDIV_BA
Flash Memory Control Registers
Hardware Divider Control Register
APB Controllers Space (0x4000_0000 ~ 0x401F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4001_0000 – 0x4001_3FFF
0x4004_0000 – 0x4004_3FFF
0x4007_0000 – 0x4007_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_3FFF
0x400F_0000 – 0x400F_3FFF
0x4014_0000 – 0x4014_3FFF
0x4017_0000 – 0x4017_3FFF
0x401B_0000 – 0x401B_3FFF
WDT_BA
Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
Enhance PWM Control Registers
USCI0 Control Registers
TMR01_BA
EPWM_BA
USCI0_BA
ACMP_BA
ADC_BA
Analog Comparator 0/1 Control Registers
ADC Control Registers
PGA_BA
Programmable Gain Amplifier Control Register
Basic PWM Control Registers
BPWM_BA
USCI1_BA
ECAP_BA
USCI1 Control Registers
Enhanced Input Capture Timer Register
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6.2-7 Address Space Assignments for On-Chip Modules
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6.2.7.3 SRAM Memory Organization
The Mini57 supports embedded SRAM with total 4 Kbytes size.
Supports total 4 Kbytes SRAM
Supports byte / half word / word write
Supports oversize response error
AHB interface
controller
SRAM decoder
SRAM 4KB
Figure 6.2-9 SRAM Block Diagram
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6.2.8 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
cleared-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used in several different ways, for example:
An RTOS tick timer fires at a programmable rate (for example 100Hz) and invokes a SysTick
routine.
A high-speed alarm timer uses Core clock.
A variable rate alarm or signal timer – the duration range is dependent on the reference clock
used and the dynamic range of the counter.
A simple counter can be used by software to measure task completion time.
An internal Clock Source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
When enabled, the timer will count down from the value in the SysTick Current Value Register
(SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock edge, and then decrement on subsequent clocks. When the
counter transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on read.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.8.1 System Timer Control Register Map
R: read only, W: write only, R/W: both read and write, W&C: write 1 to clear
Register
Offset
R/W Description
Reset Value
SCS Base Address:
SCS_BA = 0xE000_E000
SYST_CTL
SYST_RVR
SYST_CVR
SCS_BA+0x10
R/W SysTick Control and Status
R/W SysTick Reload Value Register
R/W SysTick Current Value Register
0x0000_0004
0xXXXX_XXXX
0xXXXX_XXXX
SCS_BA+0x14
SCS_BA+0x18
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6.2.8.2
System Timer Control Register Description
SysTick Control and Status （SYST_CTL）
Register
Offset
R/W Description
Reset Value
SYST_CTL
SCS_BA+0x10
R/W SysTick Control and Status
0x0000_0004
31
23
15
7
30
22
14
6
29
21
13
28
20
27
19
11
3
26
18
10
25
17
9
24
Reserved
16
Reserved
12
COUNTFLAG
8
Reserved
5
4
2
1
0
Reserved
CLKSRC
TICKINT
ENABLE
Bits
Description
Reserved
[31:17]
Reserved.
System Tick Counter Flag
Return 1 If Timer Counted to 0 Since Last Time this Register Was Read
[16]
COUNTFLAG
0 = COUNTFLAG is cleared on read or by a write to the Current Value register.
1 = COUNTFLAG is set by a count transition from 1 to 0.
[15:3]
[2]
Reserved
CLKSRC
Reserved.
System Tick Clock Source Select Bit
0 = Clock source is optional, refer to STCLKSEL.
1 = Core clock used for SysTick timer.
System Tick Interrupt Enable Bit
0 = Counting down to 0 will not cause the SysTick exception to be pended. User can use
COUNTFLAG to determine if a count to zero has occurred.
[1]
[0]
TICKINT
ENABLE
1 = Counting down to 0 will cause the SysTick exception to be pended. Clearing the
SysTick Current Value register by a register write in software will not cause SysTick to be
pended.
System Tick Counter Enable Bit
0 = System Tick counter Disabled.
1 = System Tick counter will operate in a multi-shot manner.
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SysTick Reload Value Register (SYST_RVR）
Register
Offset
R/W Description
Reset Value
SYST_RVR
SCS_BA+0x14
R/W SysTick Reload Value Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
RELOAD
RELOAD
RELOAD
1
0
Bits
Description
Reserved
[31:24]
Reserved.
System Tick Reload Value
[23:0]
RELOAD
Value to load into the Current Value register when the counter reaches 0.
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SysTick Current Value Register （SYST_CVR）
Register
Offset
R/W Description
Reset Value
SYST_CVR
SCS_BA+0x18
R/W SysTick Current Value Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
CURRENT
CURRENT
CURRENT
1
0
Bits
Description
Reserved
[31:24]
Reserved.
System Tick Current Value
Current counter value. This is the value of the counter at the time it is sampled. The
counter does not provide read-modify-write protection. The register is write-clear. A
software write of any value will clear the register to 0.
[23:0]
CURRENT
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6.2.9 Nested Vectored Interrupt Control (NVIC)
6.2.9.1 Overview
The Cortex® -M0 CPU provides an interrupt controller as an integral part of the exception mode,
named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the
processor core and provides following features.
6.2.9.2 Features
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Dynamic priority change
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the Interrupt Service Routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
6.2.9.3 Exception Model and System Interrupt Map
Table 6.2-8 lists the exception model supported by the Mini57 series. Software can set four levels
of priority on some of these exceptions as well as on all interrupts. The highest user-configurable
priority is denoted as 0 and the lowest priority is denoted as 3. The default priority of all the user-
configurable interrupts is 0. Note that the priority 0 is treated as the fourth priority on the system,
after three system exceptions “Reset”, “NMI” and “Hard Fault”.
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Exception Name
Reset
Vector Number
Priority
-3
1
2
NMI
-2
Hard Fault
Reserved
3
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
Reserved
12 ~ 13
14
PendSV
SysTick
15
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 6.2-8 Exception Model
Interrupt Number
Vector
Number
Interrupt Name
Interrupt
Interrupt Description
(Bit
In
Registers)
0 ~ 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
-
-
System exceptions
0
BOD_OUT
WDTPINT
USCI0
Brown-Out low voltage detected interrupt
Watchdog Timer interrupt
USCI0 interrupt
1
2
3
USCI1
USCI1 interrupt
4
GP_INT
External interrupt from GPA ~ GPD pins
EPWM interrupt
5
EPWM_INT
BRAKE0_INT
BRAKE1_INT
BPWM0_INT
BPWM1_INT
Reserved
Reserved
Reserved
Reserved
Reserved
ECAP_INT
CCAP_INT
Reserved
6
EPWM brake interrupt from PWM0 or PWM_BRAKE pin
7
EPWM brake interrupt from PWM1
BPWM0 interrupt
BPWM1 interrupt
Reserved
8
9
10
11
12
13
14
15
16
17
Reserved
Reserved
Reserved
Reserved
Enhanced Input Capture interrupt
Continues Input Capture interrupt
Reserved
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34
35
36
37
38
39
40
41
42
43
44
45
46
47
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HIRCTRIM_INT
TMR0_INT
TMR1_INT
Reserved
HIRC TRIM interrupt
Timer 0 interrupt
Timer 1 interrupt
Reserved
Reserved
Reserved
ACMP_INT
Reserved
Analog Comparator 0 or Comparator 1 interrupt
Reserved
PWRWU_INT
ADC0_INT
ADC1_INT
Chip wake-up from Power-down state interrupt
ADC0 interrupt
ADC1 interrupt
ADCWCMP_INT ADC Window Compare interrupt
Table 6.2-9 System Interrupt Map Vector Table
6.2.9.4 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table
based address is fixed at 0x00000000. The vector table contains the initialization value for the
stack pointer on reset, and the entry point addresses for all exception handlers. The vector
number on previous page defines the order of entries in the vector table associated with the
exception handler entry as illustrated in previous section.
Vector Table Word Offset (Bytes)
0x00
Description
Initial Stack Pointer Value
Exception Number * 0x04
Exception Entry Pointer using that Exception Number
Table 6.2-10 Vector Table Format
6.2.9.5 Operation Description
The NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
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to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.2.9.6 NVIC Control Registers Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Reset Value
SCS Base Address:
SCS_BA = 0xE000_E000
NVIC_ISER
NVIC_ICER
NVIC_ISPR
NVIC_ICPR
NVIC_IPR0
NVIC_IPR1
NVIC_IPR2
NVIC_IPR3
NVIC_IPR4
NVIC_IPR5
NVIC_IPR6
NVIC_IPR7
SCS_BA+0x100
R/W IRQ0 ~ IRQ31 Set-Enable Control Register
R/W IRQ0 ~ IRQ31 Clear-Enable Control Register
R/W IRQ0 ~ IRQ31 Set-Pending Control Register
R/W IRQ0 ~ IRQ31 Clear-Pending Control Register
R/W IRQ0 ~ IRQ3 Interrupt Priority Control Register
R/W IRQ4 ~ IRQ7 Interrupt Priority Control Register
R/W IRQ8 ~ IRQ11 Interrupt Priority Control Register
R/W IRQ12 ~ IRQ15 Interrupt Priority Control Register
R/W IRQ16 ~ IRQ19 Interrupt Priority Control Register
R/W IRQ20 ~ IRQ23 Interrupt Priority Control Register
R/W IRQ24 ~ IRQ27 Interrupt Priority Control Register
R/W IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
SCS_BA+0x180
SCS_BA+0x200
SCS_BA+0x280
SCS_BA+0x400
SCS_BA+0x404
SCS_BA+0x408
SCS_BA+0x40C
SCS_BA+0x410
SCS_BA+0x414
SCS_BA+0x418
SCS_BA+0x41C
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IRQ0 ~ IRQ31 Set-enable Control Register (NVIC_ISER)
Register
Offset
R/W Description
Reset Value
NVIC_ISER
SCS_BA+0x100
R/W IRQ0 ~ IRQ31 Set-Enable Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
SETENA
SETENA
SETENA
SETENA
1
0
Bits
Description
Interrupt Enable Register
Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~
IRQ31 (Vector number from 16 ~ 47).
Write operation:
0 = No effect.
[31:0]
SETENA
1 = Write 1 to enable associated interrupt.
Read operation:
0 = Associated interrupt status Disabled.
1 = Associated interrupt status Enabled.
Read value indicates the current enable status.
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IRQ0 ~ IRQ31 Clear-enable Control Register (NVIC_ICER)
Register
Offset
R/W Description
Reset Value
NVIC_ICER
SCS_BA+0x180
R/W IRQ0 ~ IRQ31 Clear-Enable Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
CLRENA
CLRENA
CLRENA
CLRENA
1
0
Bits
Description
Interrupt Disable Register
Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~
IRQ31 (Vector number from 16 ~ 47).
Write operation:
0 = No effect.
[31:0]
CLRENA
1 = Write 1 to disable associated interrupt.
Read operation:
0 = Associated interrupt status Disabled.
1 = Associated interrupt status Enabled.
Note: Read value indicates the current enable status.
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IRQ0 ~ IRQ31 Set-pending Control Register (NVIC_ISPR)
Register
Offset
R/W Description
Reset Value
NVIC_ISPR
SCS_BA+0x200
R/W IRQ0 ~ IRQ31 Set-Pending Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
SETPEND
SETPEND
SETPEND
SETPEND
1
0
Bits
Description
SETPEND
Set Interrupt Pending Register
Write operation:
0 = No effect.
1 = Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~
IRQ31 (Vector number from 16 ~ 47).
[31:0]
Read operation:
0 = Associated interrupt in not in pending status.
1 = Associated interrupt is in pending status.
Note: Read value indicates the current pending status.
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IRQ0 ~ IRQ31 Clear-pending Control Register (NVIC_ICPR)
Register
Offset
R/W Description
Reset Value
NVIC_ICPR
SCS_BA+0x280
R/W IRQ0 ~ IRQ31 Clear-Pending Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
CLRPEND
CLRPEND
CLRPEND
CLRPEND
1
0
Bits
Description
CLRPEND
Clear Interrupt Pending Register
Write operation:
0 = No effect.
1 = Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~
IRQ31 (Vector number from 16 ~ 47).
[31:0]
Read operation:
0 = Associated interrupt in not in pending status.
1 = Associated interrupt is in pending status.
Note: Read value indicates the current pending status.
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IRQ0 ~ IRQ3 Interrupt Priority Register (NVIC_IPR0)
Register
Offset
R/W Description
Reset Value
NVIC_IPR0
SCS_BA+0x400
R/W IRQ0 ~ IRQ3 Interrupt Priority Control Register
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_3
Reserved
Reserved
Reserved
Reserved
22
14
6
PRI_2
PRI_1
PRI_0
1
0
Bits
Description
PRI_3
Priority of IRQ3
[31:30]
[29:24]
[23:22]
[21:16]
[15:14]
[13:8]
[7:6]
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_2
Reserved.
Priority of IRQ2
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_1
Reserved.
Priority of IRQ1
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_0
Reserved.
Priority of IRQ0
0 denotes the highest priority and 3 denotes the lowest priority.
[5:0]
Reserved
Reserved.
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IRQ4 ~ IRQ7 Interrupt Priority Register (NVIC_IPR1)
Register
Offset
R/W Description
Reset Value
NVIC_IPR1
SCS_BA+0x404
R/W IRQ4 ~ IRQ7 Interrupt Priority Control Register
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_7
Reserved
Reserved
Reserved
Reserved
22
14
6
PRI_6
PRI_5
PRI_4
1
0
Bits
Description
PRI_7
Priority of IRQ7
[31:30]
[29:24]
[23:22]
[21:16]
[15:14]
[13:8]
[7:6]
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_6
Reserved.
Priority of IRQ6
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_5
Reserved.
Priority of IRQ5
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_4
Reserved.
Priority of IRQ4
0 denotes the highest priority and 3 denotes the lowest priority.
[5:0]
Reserved
Reserved.
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IRQ8 ~ IRQ11 Interrupt Priority Register (NVIC_IPR2)
Register
Offset
R/W Description
Reset Value
NVIC_IPR2
SCS_BA+0x408
R/W IRQ8 ~ IRQ11 Interrupt Priority Control Register
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_11
Reserved
Reserved
Reserved
Reserved
22
14
6
PRI_10
PRI_9
PRI_8
1
0
Bits
Description
PRI_11
Priority of IRQ11
[31:30]
[29:24]
[23:22]
[21:16]
[15:14]
[13:8]
[7:6]
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_10
Reserved.
Priority of IRQ10
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_9
Reserved.
Priority of IRQ9
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_8
Reserved.
Priority of IRQ8
0 denotes the highest priority and 3 denotes the lowest priority.
[5:0]
Reserved
Reserved.
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IRQ12 ~ IRQ15 Interrupt Priority Register (NVIC_IPR3)
Register
Offset
R/W Description
Reset Value
NVIC_IPR3
SCS_BA+0x40C
R/W IRQ12 ~ IRQ15 Interrupt Priority Control Register
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_15
Reserved
Reserved
Reserved
Reserved
22
14
6
PRI_14
PRI_13
PRI_12
1
0
Bits
Description
PRI_15
Priority of IRQ15
[31:30]
[29:24]
[23:22]
[21:16]
[15:14]
[13:8]
[7:6]
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_14
Reserved.
Priority of IRQ14
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_13
Reserved.
Priority of IRQ13
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_12
Reserved.
Priority of IRQ12
0 denotes the highest priority and 3 denotes the lowest priority.
[5:0]
Reserved
Reserved.
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IRQ16 ~ IRQ19 Interrupt Priority Register (NVIC_IPR4)
Register
Offset
R/W Description
Reset Value
NVIC_IPR4
SCS_BA+0x410
R/W IRQ16 ~ IRQ19 Interrupt Priority Control Register
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_19
Reserved
Reserved
Reserved
Reserved
22
14
6
PRI_18
PRI_17
PRI_16
1
0
Bits
Description
PRI_19
Priority of IRQ19
[31:30]
[29:24]
[23:22]
[21:16]
[15:14]
[13:8]
[7:6]
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_18
Reserved.
Priority of IRQ18
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_17
Reserved.
Priority of IRQ17
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_16
Reserved.
Priority of IRQ16
0 denotes the highest priority and 3 denotes the lowest priority.
[5:0]
Reserved
Reserved.
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IRQ20 ~ IRQ23 Interrupt Priority Register (NVIC_IPR5)
Register
Offset
R/W Description
Reset Value
NVIC_IPR5
SCS_BA+0x414
R/W IRQ20 ~ IRQ23 Interrupt Priority Control Register
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_23
Reserved
Reserved
Reserved
Reserved
22
14
6
PRI_22
PRI_21
PRI_20
1
0
Bits
Description
PRI_23
Priority of IRQ23
[31:30]
[29:24]
[23:22]
[21:16]
[15:14]
[13:8]
[7:6]
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_22
Reserved.
Priority of IRQ22
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_21
Reserved.
Priority of IRQ21
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_20
Reserved.
Priority of IRQ20
0 denotes the highest priority and 3 denotes the lowest priority.
[5:0]
Reserved
Reserved.
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IRQ24 ~ IRQ27 Interrupt Priority Register (NVIC_IPR6)
Register
Offset
R/W Description
Reset Value
NVIC_IPR6
SCS_BA+0x418
R/W IRQ24 ~ IRQ27 Interrupt Priority Control Register
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_27
Reserved
Reserved
Reserved
Reserved
22
14
6
PRI_26
PRI_25
PRI_24
1
0
Bits
Description
PRI_27
Priority of IRQ27
[31:30]
[29:24]
[23:22]
[21:16]
[15:14]
[13:8]
[7:6]
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_26
Reserved.
Priority of IRQ26
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_25
Reserved.
Priority of IRQ25
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_24
Reserved.
Priority of IRQ24
0 denotes the highest priority and 3 denotes the lowest priority.
[5:0]
Reserved
Reserved.
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IRQ28 ~ IRQ31 Interrupt Priority Register (NVIC_IPR7)
Register
Offset
R/W Description
Reset Value
NVIC_IPR7
SCS_BA+0x41C
R/W IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_31
Reserved
Reserved
Reserved
Reserved
22
14
6
PRI_30
PRI_29
PRI_28
1
0
Bits
Description
PRI_31
Priority of IRQ31
[31:30]
[29:24]
[23:22]
[21:16]
[15:14]
[13:8]
[7:6]
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_30
Reserved.
Priority of IRQ30
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_29
Reserved.
Priority of IRQ29
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved
PRI_28
Reserved.
Priority of IRQ28
0 denotes the highest priority and 3 denotes the lowest priority.
[5:0]
Reserved
Reserved.
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6.2.9.7 Interrupt Source Control Registers
Besides the interrupt control registers associated with the NVIC, the Mini57 series also
implements some specific control registers to facilitate the interrupt functions, including ”NMI
source selection” and “IRQ number identity”, which are described below.
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Reset Value
INT Base Address:
INT_BA = 0x5000_0300
INT_NMICTL INT_BA+0x80
INT_IRQSTS INT_BA+0x84
R/W NMI Source Interrupt Select Control Register
R/W MCU IRQ Number Identity Register
0x0000_0000
0x0000_0000
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NMI Interrupt Source Select Control Register (INT_NMICTL)
Register
Offset
R/W Description
Reset Value
INT_NMICTL INT_BA+0x80
R/W NMI Source Interrupt Select Control Register
0x0000_0000
31
23
15
7
30
22
14
29
21
13
5
28
20
12
27
19
11
3
26
18
10
25
17
9
24
16
Reserved
Reserved
8
Reserved
4
NMISELEN
0
6
2
1
Reserved
NMISEL
Bits
Description
Reserved
[31:9]
Reserved.
NMI Interrupt Enable Bit (Write Protected)
0 = NMI interrupt Disabled.
1 = NMI interrupt Enabled.
[8]
NMISELEN
Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88
to address 0x5000_0100 to disable register protection. Refer to the register
SYS_REGLCTL at address SYS_BA+0x100.
[7:5]
[4:0]
Reserved
NMISEL
Reserved.
NMI Interrupt Source Selection
The NMI interrupt to Cortex® -M0 can be selected from one of the peripheral interrupt by
setting NMTSEL.
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MCU Interrupt Request Source Register (INT_IRQSTS)
Register
Offset
R/W Description
Reset Value
INT_IRQSTS INT_BA+0x84
R/W MCU IRQ Number Identity Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
IRQ
IRQ
IRQ
IRQ
1
0
Bits
Description
MCU IRQ Source Register
The IRQ collects all the interrupts from the peripherals and generates the synchronous
interrupt to Cortex® -M0 core. There is one mode to generate interrupt to Cortex® -M0 - the
normal mode.
[31:0]
IRQ
The IRQ collects all interrupts from each peripheral and synchronizes them then interrupts
the Cortex® -M0.
When the IRQ[n] is 0, setting IRQ[n] to 1 will generate an interrupt to Cortex® -M0 NVIC[n].
When the IRQ[n] is 1 (i.e. an interrupt is assert), setting 1 to the MCU_bit[n] will clear the
interrupt and setting IRQ[n] 0 has no effect.
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6.2.10 System Control Registers
Key control and status features of Cortex® -M0 are managed centrally in a System Control Block
within the System Control Registers.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.10.1 System Control Register Memory Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Reset Value
SCS Base Address:
SCS_BA = 0xE000_E000
SCS_CPUID
SCS_ICSR
SCS_BA+0xD00
R
CPUID Base Register
0x410C_C200
0x0000_0000
SCS_BA+0xD04
SCS_BA+0xD0C
SCS_BA+0xD10
R/W Interrupt Control State Register
Application Interrupt and Reset Control
Register
SCS_AIRCR
SCS_SCR
R/W
0xFA05_0000
R/W System Control Register
0x0000_0000
0x0000_0000
0x0000_0000
SCS_SHPR2 SCS_BA+0xD1C
SCS_SHPR3 SCS_BA+0xD20
R/W System Handler Priority Register 2
R/W System Handler Priority Register 3
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6.2.10.2 System Control Register Description
CPUID Base Register (CPUID)
Register
Offset
R/W Description
Reset Value
SCS_CPUID
SCS_BA+0xD00
R
CPUID Base Register
0x410C_C200
31
23
15
7
30
22
29
21
13
5
28
27
19
11
3
26
18
10
2
25
17
9
24
16
8
IMPLEMENTER
20
12
4
Reserved
PART
14
6
PARTNO
1
0
PARTNO
REVISION
Bits
Description
IMPLEMENTER
Reserved
Implementer Code
[31:24]
[23:20]
[19:16]
Implementer code assigned by ARM ( ARM = 0x41).
Reserved.
Architecture of the Processor
PART
Reads as 0xC for ARMv6-M parts
Part Number of the Processor
[15:4]
[3:0]
PARTNO
Reads as 0xC20.
Revision Number
REVISION
Reads as 0x0
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Interrupt Control State Register (ICSR)
Register
Offset
R/W Description
Reset Value
SCS_ICSR
SCS_BA+0xD04
R/W Interrupt Control State Register
0x0000_0000
31
NMIPENDSET
23
30
29
28
27
26
25
24
Reserved
16
Reserved
PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR
22
21
Reserved
13
20
12
4
19
11
3
18
17
9
ISRPREEMPT ISRPENDING
VECTPENDING
15
14
10
Reserved
2
8
VECTPENDING
VECTACTIVE
0
7
6
5
1
VECTACTIVE
Bits
Description
NMI Set-pending Bit
Write Operation:
0 = No effect.
1 = Changes NMI exception state to pending.
Read Operation:
[31]
NMIPENDSET
0 = NMI exception not pending.
1 = NMI exception pending.
Note: Because NMI is the highest-priority exception, normally the processor entersthe
NMI exception handler as soon as it detects a write of 1 to this bit. Entering thehandler
then clears this bit to 0. This means a read of this bit by the NMI exceptionhandler returns
1 only if the NMI signal is reasserted while the processor is executingthat handler.
[30:29]
Reserved
Reserved.
PendSV Set-pending Bit
Write Operation:
0 = No effect.
1 = Changes PendSV exception state to pending.
Read Operation:
[28]
PENDSVSET
0 = PendSV exception is not pending.
1 = PendSV exception is pending.
Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending
PendSV Clear-pending Bit
Write Operation:
0 = No effect.
[27]
PENDSVCLR
PENDSTSET
1 = Removes the pending state from the PendSV exception.
This bit is write-only. To clear the PENDSV bit, you must “write 0 to PENDSVSET
andwrite 1 to PENDSVCLR” at the same time.
[26]
SysTick Exception Set-pending Bit
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Write Operation:
0 = No effect.
1 = Changes SysTick exception state to pending.
Read Operation:
0 = SysTick exception is not pending.
1 = SysTick exception is pending.
SysTick Exception Clear-pending Bit
Write Operation:
0 = No effect.
[25]
PENDSTCLR
1 = Removes the pending state from the SysTick exception.
Note: This bit is write-only. When you want to clear PENDST bit, you must “write 0
toPENDSTSET and write 1 to PENDSTCLR” at the same time.
[24]
[23]
Reserved
Reserved.
Interrupt Preempt Bit(Read Only)
ISRPREEMPT
If set, a pending exception will be serviced on exit from the debug halt state
Interrupt Pending Flag,Excluding NMI and Faults (Read Only)
0 = Interrupt not pending.
[22]
ISRPENDING
Reserved
1 = Interrupt pending.
[21]
Reserved.
Exception Number of the Highest Priority Pending Enabled Exception
[20:12]
[11:9]
[8:0]
VECTPENDING 0 = No pending exceptions.
Non-zero = Exception number of the highest priority pending enabled exception.
Reserved
Reserved.
Contains the Active Exception Number
0 = Thread mode.
VECTACTIVE
Non-zero = Exception number of the currently active exception.
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Application Interrupt and Reset Control Register (AIRCR)
Register
Offset
R/W Description
Reset Value
SCS_AIRCR SCS_BA+0xD0C R/W Application Interrupt and Reset Control Register
0xFA05_0000
31
23
15
7
30
22
14
6
29
21
13
28
27
19
26
18
10
2
25
17
9
24
16
8
VECTORKEY
20
12
4
VECTORKEY
11
Reserved
5
3
1
0
Reserved
SYSRESETRE VECTCLRAC
Reserved
Bits
Description
Register Access Key
Write Operation:
When writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise
the write operation would be ignored. The VECTORKEY filed is used to prevent accidental
write to this register from resetting the system or clearing of the exception status.
[31:16]
VECTORKEY
Read Operation:
Read as 0xFA05.
[15:3]
[2]
Reserved
Reserved.
System Reset Request
Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is
requested.
SYSRESETREQ
The bit is a write only bit and self-clears as part of the reset sequence.
Exception Active Status Clear Bit
[1]
[0]
VECTCLRACTIVE
Reserved
Reserved for debug use. When writing to the register, user must write 0 to this bit,
otherwise behavior is unpredictable.
Reserved.
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System Control Register (SCR)
Register
Offset
R/W Description
Reset Value
SCS_SCR
SCS_BA+0xD10
R/W System Control Register
0x0000_0000
31
23
15
7
30
22
14
29
21
13
5
28
27
19
11
3
26
25
17
9
24
16
8
Reserved
Reserved
Reserved
20
12
18
10
2
6
4
1
0
Reserved
SEVONPEND
Reserved
SLEEPDEEP SLEEPONEXI
Reserved
Bits
Description
Reserved
[31:5]
Reserved.
Send Event on Pending Bit
0 = Only enabled interrupts or events can wake-up the processor, disabled interrupts
areexcluded.
1 = Enabled events and all interrupts, including disabled interrupts, can wake-up
theprocessor.
[4]
SEVONPEND
When an event or interrupt enters pending state, the event signal wakes up the
processorfrom WFE. If the processor is not waiting for an event, the event is registered
and affectsthe next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
[3]
[2]
Reserved
Reserved.
Processor Deep Sleep and Sleep Mode Selection
Controls whether the processor uses sleep or deep sleep as its low power mode:
0 = Sleep mode.
SLEEPDEEP
1 = Deep Sleep mode.
Sleep-on-exit Enable Bit
This bit indicates sleep-on-exit when returning from Handler mode to Thread mode.
0 = Do not sleep when returning to Thread mode.
[1]
[0]
SLEEPONEXIT
Reserved
1 = Enter Sleep or Deep Sleep when returning from ISR to Thread mode.Setting this bit
to 1 enables an interrupt driven application to avoid returning to an emptymain
application.
Reserved.
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System Handler Priority Register 2 (SHPR2)
Register
Offset
R/W Description
Reset Value
SCS_SHPR2 SCS_BA+0xD1C
R/W System Handler Priority Register 2
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_11
Reserved
Reserved
Reserved
Reserved
1
0
Bits
Description
PRI_11
Priority of System Handler 11 – SVCall
[31:30]
[29:0]
“0” denotes the highest priority and “3” denotes the lowest priority.
Reserved
Reserved.
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System Handler Priority Register 3 (SHPR3)
Register
Offset
R/W Description
Reset Value
SCS_SHPR3 SCS_BA+0xD20
R/W System Handler Priority Register 3
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_15
PRI_14
Reserved
Reserved
Reserved
Reserved
1
0
Bits
Description
PRI_15
Priority of System Handler 15 – SysTick
[31:30]
[29:24]
[23:22]
[21:0]
“0” denotes the highest priority and “3” denotes the lowest priority.
Reserved
PRI_14
Reserved.
Priority of System Handler 14 – PendSV
“0” denotes the highest priority and “3” denotes the lowest priority.
Reserved
Reserved.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when the Cortex® -M0 core executes the WFI instruction only if the PDEN
(CLK_PWRCTL[7]) bit set to 1. After that, chip enters Power-down mode and waits for wake-up
interrupt source triggered to exit Power-down mode. In Power-down mode, the clock controller
turns off the 4~24 MHz external high speed crystal (HXT) and 48 MHz internal high speed RC
oscillator (HIRC) to reduce the overall system power consumption. Figure 6.3-2 shows the clock
generator and the overview of the clock source control.
The clock generator consists of 4 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
48 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
LXTEN (CLK_PWRCTL[1])
XT_IN
External 32.768
kHz Crystal
(LXT)
LXT
HXT
HIRC
XT_OUT
HXTEN (CLK_PWRCTL[0])
External 4~24
MHz Crystal
(HXT)
HIRCEN (CLK_PWRCTL[2])
Internal 48 MHz
Oscillator
(HIRC)
LIRCEN (CLK_PWRCTL[3])
Internal 10 kHz
Oscillator
(LIRC)
LIRC
Figure 6.3-1 Clock Generator Block Diagram
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HIRC
HXT
LXT
CPUCLK
48 MHz
11
1/(HCLKDIV+1)
HCLK
PCLK
10 kHz
01
00
4~24 MHz/32.768kHz
LIRC
CLK_CLKSEL0[1:0]
48 MHz
111
TMR 0
TMR 1
10 kHz
T0~T1
HCLK
BOD
011
010
48 MHz
FMC
10 kHz
001
000
HCLK
HCLK
HDIV
4~24 MHz/32.768kHz
ECAP
ACMP
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
HCLK
HCLK
1/(PGADIV+1)
PGA
48 MHz
HCLK
1/2
1/2
1/2
11
10
01
CPUCLK
1
4~24 MHz/32.768kHz
SysTick
0
48 MHz
HCLK
11
10
4~24 MHz/32.768kHz
SYST_CTL[2]
00
Clock Output
CLK_CLKSEL0[4:3]
4~24 MHz/32.768kHz
CLK_CLKSEL1[31:30]
00
48 MHz
HCLK
11
10
HCLK
PWM 10
1/(ADCDIV+1)
ADC
4~24 MHz/32.768kHz
CLK_CLKSEL1[5:4]
00
HCLK
HCLK
PWM 32
4~24MHz/32.768kHz
HCLK
1
0
USCI0
USCI1
PWM 54
USCI0_BRGEN[0]
USCI1_BRGEN[0]
10 kHz
1/2048
11
HCLK
10
00
WDT
4~24MHz/32.768kHz
CLK_CLKSEL1[1:0]
Figure 6.3-2 Clock Generator Global View Diagram
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6.3.2 Auto Trim
This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator), according to the accurate
LXT (32.768 kHz crystal oscillator), automatically gets accurate HIRC output frequency, 0.25 %
deviation within all temperature ranges.
For instance, the system needs an accurate 48MHz clock. In such case, if users do not want to use
PLL as the system clock source, they need to solder 32.768 kHz crystal in system, and set FREQSEL
(SYS_IRCTCTL[0] trim frequency selection) to “1”, and the auto-trim function will be enabled. Interrupt
status bit FREQLOCK (SYS_IRCTISTS[0] HIRC frequency lock status) “1” indicates the HIRC output
frequency is accurate within 0.25% deviation. To get better results, it is recommended to set both
LOOPSEL (SYS_IRCTCTL[5:4] trim calculation loop) and RETRYCNT (SYS_IRCTCTL[7:6] trim value
update limitation count) to “11”.
6.3.3 System Clock and SysTick Clock
The system clock has three clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[1:0]). The block diagram is
shown in Figure 6.3-3.
HCLKSEL (CLK_CLKSEL0[1:0])
48 MHz HIRC
11
10 kHz LXT
01
CPUCLK
CPU
HCLK
1/(HCLKDIV+1)
AHB
APB
HCLKDIV (CLK_CLKDIV[3:0])
PCLK
4~24 MHz HXT or
32.768 kHz LXT
00
CPU in Power Down Mode
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-3 System Clock Block Diagram
The clock source of SysTick in the Cortex® -M0 core can use CPU clock or external clock
CLKSRC(SYST_CTL[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources.
The clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[4:3]).
The block diagram is shown in Figure 6.3-4.
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48 MHz HIRC
HCLK
1/2
1/2
11
10
01
CPUCLK
1
0
4~24 MHz HXT or
32.768 kHz LXT
SysTick
1/2
4~24 MHz HXT or
32.768 kHz LXT
SYST_CTL[2]
00
CLK_CLKSEL0[4:3]
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-4 SysTick Clock Control Block Diagram
6.3.4 Peripherals Clock Source Selection
The peripheral clock has different clock source switch settings depending on different peripherals.
Please note that, while switching clock source from one to another, user must wait until both clock
sources are running stabled.
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PCLK
Watch Dog Timer
Timer0
WDTCKEN (CLK_APBCLK[0])
TMR0CKEN (CLK_APBCLK[2])
Timer1
TMR1CKEN (CLK_APBCLK[3])
CLKOCKEN (CLK_APBCLK[6])
Frequency Divider
ECAP
ECAPCKEN (CLK_APBCLK[8])
PGA
PGACKEN (CLK_APBCLK[12])
EPWMCKEN (CLK_APBCLK[20])
EPWM
BPWM
UART1
BPWMCKEN (CLK_APBCLK[16])
UART1CKEN (CLK_APBCLK[17])
USCI0CKEN (CLK_APBCLK[24])
USCI1CKEN (CLK_APBCLK[25])
ADCCKEN (CLK_APBCLK[28])
ACMPCKEN (CLK_APBCLK[30])
USCI0
USCI1
ADC
ACMP
Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK
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Ext. CLK
Peripheral Clock Selectable
HIRC
LIRC
HCLK
(HXT Or LXT)
WDT
WWDT
Timer0
Timer1
USCI0
USCI1
ADC
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
ACMP
ECAP
EBWM
BPWM
HDIV
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Table 6.3-1 Peripheral Clock Source Selection Table
Note: For the peripherals those peripheral clock are not selectable, its clock source is fixed to
PCLK.
6.3.5 Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
10 kHz internal low speed oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator (LXT) clock (If PDLXT = 1 and
XTLEN[1:0] = 10)
Peripherals Clock (When 10 kHz low speed oscillator is adopted as clock source)
Watchdog Clock
Timer 0/1 Clock
6.3.6 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed of 16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
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multiplexer is reflected to the CKO pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stay in low state.
if DIV1EN(CLK_CLKOCTL[5]) set to 1, the frequency divider clock will bypass power-of-2
frequency divider. The frequency divider clock will be output to CLKO pin directly.
CLKOSEL (CLK_CLKSEL1[31:30])
CLKOCKEN (CLK_APBCLK[6])
48 MHz HIRC
11
HCLK
CLKO_CLK
10
01
00
Reserved
4~24 MHz HXT or
32.768 kHz LXT
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
LXT = 32.768 kHz external low speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
Figure 6.3-6 Clock Source of Frequency Divider
CLKOEN
(CLK_CLKOCTL[4])
Enable
divide-by-2 counter
FREQSEL
16 chained
(CLK_CLKOCTL[3:0])
divide-by-2 counter
CLKO_CLK
1/22
1/23
…...
1/215 1/216
DIV1EN
(CLK_CLKOCTL[5])
1/2
000
000
0
1
:
16 to 1
MUX
0
:
CLKO
111
111
1
0
1
Figure 6.3-7 Block Diagram of Frequency Divider
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The Mini57 series is equipped with 29.5 Kbytes on chip embedded Flash for application program
memory (APROM) that can be updated through ISP procedure. In System Programming (ISP)
function enables user to update program memory when chip is soldered on PCB. After chip
powered on Cortex® -M0 CPU fetches code from APROM or LDROM decided by boot select
(CBS) in Config0. By the way, the Mini57 series also provides Data Flash Region, where the Data
Flash is shared with original program memory and its start address is configurable and defined by
user in Config1. The Data Flash size is defined by user depending on the application request.
Security program memory (SPROM) provides user to protect any program code within SPROM.
6.4.2 Features
Running up to 48 MHz with one wait state and 24 MHz without wait state for
discontinuous address read access
29.5 Kbytes application program memory (APROM)
2 Kbytes in system programming (ISP) loader program memory (LDROM)
Programmable Data Flash start address and memory size with 512 bytes page erase
unit
Three 512 bytes security program memory (SPROM)
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory.
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
The Mini57 series has up to 22 General Purpose I/O pins. These pins could be shared with other
functions depending on the chip configuration. 22 pins are arranged in 4 ports named as PA, PB,
PC, and PD. Each of the 22 pins is independent and has the corresponding register bits to control
the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull
output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all
pins are depending on CIOIN (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up
resistor which is about 110 k ~ 300 k for VDD is from 5.0 V to 2.5 V.
PIN[n]
(Px_PIN)
PULLSEL[0]
(Px_PUEN)
DOUT[n]
(Px_DOUT)
PAD
MODE[n]
(Px_MODE)
PULLSEL[1]
(Px_PUEN)
Note: Px_ means PA_, PB_, PC_, or PD_
Figure 6.5-1 I/O Pin Block Diagram
6.5.2 Features
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
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Supports High Drive and High Sink I/O mode
Supports software selectable slew rate control
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
CIOIN = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
CIOIN = 1, all GPIO pins in input mode after chip reset
GPIOA supports the pull-up and pull-low resistor enabled in four I/O modes
GPIOB to GPIOD internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
6.5.3 GPIO Interrupt and Wake-up Function
Each GPIO pin can be set as chip interrupt source by setting correlative RHIEN
(Px_INTEN[n+16])/ FLIEN (Px_INTEN[n]) bit and TYPE (Px_INTTYPE[n]). There are five types of
interrupt conditions to be selected: low level trigger, high level trigger, falling edge trigger, rising
edge trigger and both rising and falling edge trigger. For edge trigger condition, user can enable
input signal de-bounce function to prevent unexpected interrupt happened which caused by noise.
The de-bounce clock source and sampling cycle period can be set through DBCLKSRC
(GPIO_DBCTL[4]) and DBCLKSEL (GPIO_DBCTL[3:0]) register.
The GPIO can also be the chip wake-up source when chip enters Idle/Power-down mode. The
setting of wake-up trigger condition is the same as GPIO interrupt trigger.
1. To ensure the I/O status before entering Idle/Power-down mode
When using toggle GPIO to wake-up system, user must make sure the I/O status before entering
Idle/Power-down mode according to the relative wake-up settings.
For example, if configuring the wake-up event occurred by I/O rising edge/high level trigger, user
must make sure the I/O status of specified pin is at low level before entering Idle/Power-down
mode; and if configuring I/O falling edge/low level trigger to trigger a wake-up event, user must
make sure the I/O status of specified pin is at high level before entering Power-down mode.
2. To disable the I/O de-bounce function before entering Idle/Power-down mode
If the specified wake-up I/O pin with enabling input signal de-bounce function, system will
encounter two GPIO interrupt events while the system is woken up by this GPIO pin. One
interrupt event is caused by wake-up function, the other is caused by I/O input de-bounce
function. User should be disable the de-bounce function before entering Idle/Power-down mode to
avoid the second interrupt event occurred after system woken up.
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6.6 Timer Controller (TIMER)
6.6.1 Overview
The Timer Controller includes two 32-bit timers, TIMER0 ~ TIMER1, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.6.2 Features
Supports two sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Supports independent clock source for each channel (TMR0_CLK, TMR1_CLK)
Supports four timer counting modes: one-shot, periodic, toggle and continuous
counting
Time-out period = (period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
CMPDAT)
Supports maximum counting cycle time = (1 / T MHz) * (28) * (224); T is the period of
timer clock
24-bit up counter value is readable through TIMERx_CNT (Timer Data Register)
Supports event counting function to count the event from external pin (TM0, TM1)
Supports internal capture triggered while internal ACMP output signal transition
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
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6.7 Enhanced Input Capture Timer (ECAP)
6.7.1 Overview
This device provides an Input Capture Timer/Counter whose capture function can detect the
digital edge-changed signal at channel inputs. This unit has three input capture channels. The
timer/counter is equipped with up counting, reload and compare-match capabilities.
6.7.2 Features
24-bit Input Capture up-counting timer/counter.
3 input channels thatl has its own capture counter hold register.
Noise filter in front end of input ports.
Edge detector with three options.
Rising edge detection.
Falling edge detection.
Both edge detection.
Supports ADC compare output and ACMP output as input sources
Captured events reset and/or reload capture counter.
Supports compare-match function.
Supports interrupt function.
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6.8 Enhanced PWM Generator (EPWM)
6.8.1 Overview
The Mini57 series has built in one PWM unit which is specially designed for motor driving control
applications. The PWM unit supports six PWM generators which can be configured as six
independent PWM outputs, PWM0~PWM5, or as three complementary PWM pairs, (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5) with three programmable dead-zone generators.
Every complementary PWM pairs share one clock divider providing nine divided frequencies (1,
1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256) for each channel. Each PWM output shares one 16-
bit counter for PWM period control, and 16-bit comparators for PWM duty control. The six PWM
generators provide fourteen independent PWM interrupt flags which are set by hardware when
the corresponding PWM period counter comparison matched period and duty. Each PWM
interrupt source with its corresponding enable bit can request PWM interrupt. The PWM
generators can be configured as One-shot mode to produce only one PWM cycle signal or Auto-
reload mode to output PWM waveform continuously.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period up counter and 16-
bit comparator are implemented with double buffer. When user writes data to counter/comparator
buffer registers, the updated value will be loaded into the 16-bit counter/comparator at the end of
current period. The double buffering feature avoids glitch at PWM outputs.
Besides PWM, Motor controlling also need Timer, ACMP and ADC to work together. To control
motor more precisely, some registers are provided to configure not only PWM but also Timer,
ADC and ACMP. By doing so, it can save more CPU time and control motor with ease especially
in BLDC.
6.8.2 Features
Supports one PWM clock timer and one 9 level Divider (1, 1/2, 1/4, 1/8, 1/16, 1/32,
1/64, 1/128, 1/256).
Supports six independent 16-bit PWM duty control units with maximum six port pins:
Six independent PWM outputs – PWM0, PWM1, PWM2, PWM3, PWM4, and
PWM5
Three complementary PWM pairs, with each pin in a pair mutually complement
to each other and capable of programmable dead-zone insertion – (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5)
Three synchronous PWM pairs, with each pin in a pair in-phase – (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5)
Supports group function.
Supports one-shot (only edge alignment mode) or auto-reload mode PWM
Supports 16-bit resolution PWM counter
Supports Edge-aligned and Center-aligned mode
Supports Programmable dead-zone insertion between complementary paired PWMs
Supports hardware fault brake protections
Two Interrupt source types:
one type is brake directed, and one type can resume from brake.
fault brake source:
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BRK0: ACMP0, ACMP1, EADC and External pin (BRAKE).
BRK1: ACMP0, ACMP1, EADC and External pin (BRAKE).
The PWM signals before polarity control stage are defined in the view of positive
logic. The PWM ports is active high or active low are controlled by polarity control
register.
Supports independently falling CMPDAT matching, central matching (in Center-
aligned mode), rising CMPDAT matching (in Center-aligned mode), period matching
to trigger EADC conversion
Supports ACMP output event trigger PWM to force PWM output at most one period
low, this feature is usually for step motor control
Supports interrupt accumulation function
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6.9 Basic PWM Generator (BPWM)
6.9.1 Overview
The Mini57 series has one set of BPWM group supporting one set of PWM generator that can be
configured as 2 independent PWM outputs, BPWM CH0~BPWM CH1, or as 1 complementary
PWM pairs, (BPWM CH0, BPWM CH1) with programmable Dead-zone generators.
The PWM generator has one 8-bit pre-scalar, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-counters for
PWM period control, two 16-bit comparators for PWM duty control and one dead-zone generator.
The PWM generator provides two independent PWM interrupt flags which are set by hardware
when the corresponding PWM period down counter reaches zero. Each PWM interrupt source
with its corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators
can be configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode
to output PWM waveform continuously.
When DTCNT01(BPWM_CTL[4]) is set, BPWM CH0 and BPWM CH1 perform complementary; the
paired PWM timing, period, duty and dead-time are determined by PWM0 timer and Dead-zone
generator 0.
To prevent PWM driving output pin from glitches, the 16-bit period down counter and 16-bit
comparator are implemented with double buffer. When user writes data to counter/comparator
buffer registers the updated value will be load into the 16-bit down counter/ comparator at the time
down counter reaching zero. The double buffering feature avoids glitch at PWM outputs.
When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWM-
timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with BPWM
Counter Register(BPWM_PERIODx, x=0,1) automatically then start decreasing, repeatedly. If the
PWM-timer is set as one-shot mode, the down counter will stop and generate one interrupt
request when it reaches zero.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
6.9.2 Features
One PWM generator which supports one 8-bit pre-scalar, one clock divider, two PWM
timers (down counter), one dead-zone generator and two PWM outputs.
Up to 16-bit resolution
PWM Interrupt request synchronized with PWM period
One-shot or Auto-reload mode PWM
Edge-aligned type or Center-aligned type option
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6.10 Watchdog Timer (WDT)
6.10.1 Overview
The Watchdog Timer is used to perform a system reset when system runs into an unknown state.
This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer
supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for Watchdog Timer time-out interval
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval
period is 104 ms ~ 26.3168 s if WDT_CLK = 10 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports Watchdog Timer time-out wake-up function only if WDT clock source is
selected as 10 kHz
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6.11 USCI – Universal Serial Control Interface Controller
6.11.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
Note: For detailed USCI UART, I2C and SPI information, please refer to section 6.12, 6.13 and
6.14.
6.11.2 Features
The controller can be individually configured to match the application needs. The following
protocols are supported:
UART
SPI
I2C
To increase readability, the registers of USCI have different alias names that depending on the
selected protocol. For example, register USCI_CTL has alias name UUART_CTL for protocol
UART, has alias name USPI_CTL for protocol SPI, and has alias name UI2C_CTL for protocol
I2C.
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6.12 USCI – UART Mode
6.12.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of
asynchronous data frames. It performs a serial-to-parallel conversion on data received from the
peripheral, and a parallel-to-serial conversion on data transmitted from the controller. The receiver
and transmitter are independent, frames can start at different points in time for transmission and
reception.
The UART controller also provides the LIN function. There is incoming data to wake up the
system.
6.12.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports programmable baud-rate generator
Supports 9-Bit Data Transfer
Supports LIN function
Supports baud rate detection by built-in capture event of baud rate generator
Supports Wake-up function
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6.13 USCI – SPI Mode
6.13.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows
full duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received
from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral
device. The SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1.
The SPI protocol can operate as master or Slave mode by setting the SLAVE
(USPI_PROTCTL[0]) to communicate with the off-chip SPI Slave or master device. The
application block diagrams in master and Slave mode are shown as Figure 6.13-1 and Figure
6.13-2.
USCI SPI Master
USCI SPI Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
Master Receive Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_SS
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
Note: x = 0, 1
Figure 6.13-1 SPI Master Mode Application Block Diagram (x=0, 1)
USCI SPI Slave
USCI SPI Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
Slave Transmit Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_SS
Note: x = 0, 1
Figure 6.13-2 SPI Slave Mode Application Block Diagram (x=0, 1)
6.13.2 Features
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Supports master or slave mode operation (the maximum frequency for Master = fPCLK
2, for Slave < fPCLK / 5)
/
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
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6.14 USCI – I2C Mode
6.14.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and
SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL
clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows
each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line
may be changed only during the low period of SCL and must be held stable during the high period
of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or
STOP). Please refer to Figure 6.14-1 for more detailed I2C BUS Timing.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD_STA
tSU_STA
tSU_STO
tSU_DAT
tHD_DAT
Figure 6.14-1 I2C Bus Timing
The device on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 0100B. When this port is enabled, the USCI interfaces to the I2C
bus via two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins
function to I2C in advance.
Note: A pull-up resistor is needed for I2C operation because the SDA and SCL are set to open-
drain pins when USCI is selected to I2C operation mode.
6.14.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
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6.15 Hardware Divider (HDIV)
6.15.1 Overview
The hardware divider (HDIV) is useful to the high performance application. The hardware divider
is a signed, integer divider with both quotient and remainder outputs.
6.15.2 Features
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-
bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Write divisor to trigger calculation
Waiting for calculation ready automatically when reading quotient and remainder
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6.16 Analog to Digital Converter (ADC)
6.16.1 Overview
The Mini57 series contains one 12-bit successive approximation analog-to-digital converter (SAR
A/D converter) with 8 single-end external input channels. The A/D converters can be started by
software, external pin (STADC/PC.1) or PWM trigger.
6.16.2 Features
Analog input voltage range: 0~VDD.
12-bit resolution and 10-bit accuracy guaranteed.
Up to 8 single-end analog input channels.
ADC clock frequency up to 16MHz.
Configurable ADC internal sampling time.
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6.17 Analog Comparator (ACMP)
6.17.1 Overview
The Mini57 series contains two comparators which can be used in a number of different
configurations. The comparator output is logic 1 when positive input greater than negative input,
otherwise the output is 0. Each comparator can be configured to generate interrupt when the
comparator output value changes.
6.17.2 Features
Analog input voltage range: 0 ~ VDD
Supports Hysteresis function
Optional internal reference voltage source for each comparator negative input
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6.18 Programmable Gain Amplifier (PGA)
6.18.1 Overview
The Mini57 series contains a programmable gain amplifier (PGA) which can be enabled through
the PGAEN bit. User can measure the outputs of the programmable gain amplifier as the
programmable gain amplifier output to the integrated A/D converter channel, where digital results
can be taken. Furthermore, user can adjust gain to 1, 2, 3, 5, 7, 9, 11, and 13.
Note: The analog input port pins must be configured as input type before the PGA function is
enabled.
6.18.2 Features
Supports analog input voltage range: 0~ VDD.
Supports programmable gain: 1,2, 3,5,7,9.11,13
Supports PGA output as input of ADC and ACMP
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7 APPLICATION CIRCUIT
DVCC
[1]
AVCC
AVDD
SPI_SS
SPI_CLK
CS
CLK
VDD
SPI Device
FB
FB
DVCC
MISO
MOSI
SPI_MISO
SPI_MOSI
VDD
VSS
Power
0.1uF
0.1uF
VSS
AVSS
VDD
DVCC
4.7K
DVCC
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
4.7K
20p
20p
[2]
CLK
DIO
XT_IN
I2Cx_SCL
I2Cx_SDA
VDD
Mini57EDE
TSSOP28
I2C Device
4~24 MHz
or
32.768 kHz
crystal
VSS
Crystal
XT_OUT
DVCC
10K
Reset
Circuit
RS232 Transceiver
ROUT RIN
PC COM Port
nRESET
[2]
UARTx_RXD
UARTx_TXD
10uF/25V
UART
TIN
TOUT
LDO_CAP
1uF
Note 1: For the SPI device, the Mini57 chip
supply voltage must be equal to SPI device
working voltage. For example, when the SPI
LDO
Flash working voltage is 3.3 V, the Mini57 chip
supply voltage must also be 3.3V.
Note 2: x denotes 0 or 1.
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8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Symbol
VDD VSS
VIN
Parameter
Min
Max
+7.0
VDD +0.3
24
Unit
V
DC Power Supply
-0.3
Input Voltage
VSS -0.3
V
1/tCLCL
TA
Oscillator Frequency
4
MHz
Operating Temperature
-40
+105
+150
120
℃
TST
Storage Temperature
-55
IDD
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by an I/O pin
Maximum Current sourced by an I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
ISS
120
35
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the life
and reliability of the device.
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8.2 DC Electrical Characteristics
(VDD - VSS = 2.1 ~ 5.5 V, TA = 25C)
Symbol Parameter
Min
Typ
Max Unit Test Conditions
VDD
Operation voltage
2.1
-
5.5
V
VDD = 2.1V ~ 5.5V up to 48 MHz
VSS / AVSS Power Ground
VLDO LDO Output Voltage
-0.3
-
-
V
V
1.5
VDD = 3.0V ~ 5.5V,
VBG
Band-gap Voltage
1.2
9.7
V
TA = -40C~105C
All Digital
Modules
VDD
HXT
HIRC
IDD5
-
-
mA
Operating Current
Normal Run Mode
HCLK = 48 MHz
while(1){}
5.5V
5.5V
3V
X
X
X
X
48 MHz
48 MHz
48 MHz
48 MHz
V
X
V
X
IDD6
IDD7
IDD8
-
-
-
7.4
9.7
7.4
-
-
-
mA
mA
mA
Executed from Flash
3V
All Digital
Modules
VDD
HXT
HIRC
IDD1
-
5.4
-
mA
Operating Current
Normal Run Mode
HCLK = 24 MHz
while(1){}
5.5V
5.5V
3V
24 MHz
24 MHz
24 MHz
24 MHz
X
X
X
X
V
X
V
X
IDD2
IDD3
IDD4
-
-
-
4.4
5.4
4.4
-
-
-
mA
mA
mA
Executed from Flash
3V
All Digital
Modules
VDD
HXT
HIRC
3.7
IDD9
-
-
mA
Operating Current
Normal Run Mode
HCLK = 16 MHz
while(1){}
5.5V
5.5V
3V
16 MHz
16 MHz
16 MHz
16 MHz
X
X
X
X
V
X
V
X
IDD10
IDD11
IDD12
-
-
-
3.0
3.7
3.1
-
-
-
mA
mA
mA
Executed from Flash
3V
All Digital
Modules
Operating Current
Normal Run Mode
HCLK = 12 MHz
VDD
HXT
HIRC
X
IDD9
-
2.8
-
mA
5.5V
12 MHz
V
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while(1){}
IDD10
IDD11
IDD12
-
-
-
2.3
2.8
2.3
-
-
-
mA
mA
mA
5.5V
3V
12 MHz
12 MHz
12 MHz
X
X
X
X
V
X
Executed from Flash
3V
All Digital
Modules
VDD
HXT
HIRC
IDD13
-
1.2
-
mA
Operating Current
Normal Run Mode
HCLK = 4 MHz
while(1){}
5.5V
5.5V
3V
4 MHz
4 MHz
4 MHz
4 MHz
X
X
X
X
V
X
V
X
IDD14
IDD15
IDD16
-
-
-
1.0
1.2
1.0
-
-
-
mA
mA
mA
Executed from Flash
3V
All Digital
Modules
VDD
LXT
LIRC
IDD17
-
291.7
-
μA
Operating Current
Normal Run Mode
HCLK = 32 kHz
while(1){}
5.5V
5.5V
3V
32 kHz
32 kHz
32 kHz
32 kHz
V
V
V
V
V[1]
X
IDD18
IDD19
IDD20
-
-
-
290.7
280.8
281.4
-
-
-
μA
μA
μA
V[1]
X
Executed from Flash
3V
All Digital
Modules
VDD
HXT
LIRC
IDD17
-
248.0
-
μA
Operating Current
Normal Run Mode
HCLK = 10 kHz
while(1){}
5.5V
5.5V
3V
X
X
X
X
10 kHz
10 kHz
10 kHz
10 kHz
V[2]
X
IDD18
IDD19
IDD20
-
-
-
247.7
237.9
237.5
-
-
-
μA
μA
μA
V[2]
X
Executed from Flash
3V
All Digital
Modules
VDD
HXT
HIRC
IIDLE5
-
4.9
-
mA
5.5V
5.5V
3V
X
X
X
X
V
V
V
V
V
X
V
X
Operating Current
Idle Mode
IIDLE6
IIDLE7
IIDLE8
-
-
-
2.6
4.9
2.6
-
-
-
mA
mA
mA
HCLK= 48 MHz
3V
All Digital
Modules
Operating Current
Idle Mode
VDD
HXT
HIRC
X
IIDLE1
-
2.8
-
mA
HCLK = 24 MHz
5.5V
24 MHz
V
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IIDLE2
IIDLE3
IIDLE4
-
-
-
1.9
2.8
1.9
-
-
-
mA
mA
mA
5.5V
3V
24 MHz
24 MHz
24 MHz
X
X
X
X
V
X
3V
All Digital
Modules
VDD
HXT
HIRC
IIDLE9
-
2.0
-
mA
5.5V
5.5V
3V
V
V
V
V
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE10
IIDLE11
IIDLE12
-
-
-
1.3
2.0
1.4
-
-
-
mA
mA
mA
HCLK = 16 MHz
3V
All Digital
Modules
VDD
HXT
HIRC
IIDLE9
-
1.5
-
mA
5.5V
5.5V
3V
V
V
V
V
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE10
IIDLE11
IIDLE12
-
-
-
1.0
1.5
1.0
-
-
-
mA
mA
mA
HCLK = 12 MHz
3V
All Digital
Modules
VDD
HXT
HIRC
IIDLE13
-
0.8
-
mA
5.5V
5.5V
3V
V
V
V
V
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE14
IIDLE15
IIDLE16
-
-
-
0.6
0.7
0.6
-
-
-
mA
mA
mA
HCLK = 4 MHz
3V
All Digital
Modules
VDD
HXT
LIRC
IDD17
-
274.3
-
μA
5.5V
5.5V
3V
X
X
X
X
V
V
V
V
V[1]
X
Operating Current
Idle Mode
IDD18
IDD19
IDD20
-
-
-
273.0
265.0
263.9
-
-
-
μA
μA
μA
HCLK = 32 kHz
V[1]
X
3V
All Digital
Modules
Operating Current
Idle Mode
VDD
HXT
X
LIRC
V
IDD17
-
232.6
-
μA
HCLK = 10 kHz
5.5V
V[2]
Apr. 06, 2017
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Mini57
IDD18
IDD19
IDD20
-
-
-
232.2
222.5
222.1
-
-
-
μA
μA
μA
5.5V
3V
X
X
X
V
V
V
X
V[2]
X
3V
VDD = 5.5 V, All oscillators and analog blocks
turned off.
IPWD1
-
-
1.9
1.7
-
-
A
A
Standby Current
Power-down Mode
(Deep Sleep Mode)
VDD = 3 V, All oscillators and analog blocks
turned off.
IPWD2
VDD = 5.5 V, 0 < VIN< VDD
Input Leakage Current
PA/PB/PC/PD
ILK
-1
-
+1
A
Open-drain or input only mode
-0.3
-0.3
1.33
1
VDD = 5.5 V
VDD = 3.3 V
VDD = 5.5 V
VDD = 3.3 V
Input Low Voltage
PA/PB/PC/PD (TTL Input)
VIL1
V
1.47
1.08
VDD + 0.3
VDD + 0.3
Input High Voltage
PA/PB/PC/PD (TTL Input)
VIH1
V
V
Negative-going Threshold
VILS
-
-
-
0.3VDD
-
(Schmitt Input), nRESET
Positive-going Threshold
VIHS
0.7VDD
48
-
V
-
(Schmitt Input), nRESET
Internal nRESET Pin Pull-
up Resistor
RRST
148
kΩ
VDD = 2.1 V ~ 5.5V
Negative-going Threshold
VILS
-
-
-
0.3VDD
V
V
-
-
(Schmitt input),
PA/PB/PC/PD
Positive-going Threshold
VIHS
0.7VDD
-
(Schmitt input),
PA/PB/PC/PD
Logic 0 Input Current
PA/PB/PC/PD (Quasi-
bidirectional Mode)
IIL
-
-
-63.65
-566.7
VDD = 5.5 V, VIN = 0V
VDD = 5.5 V
A
A
Logic 1 to 0 Transition
Current PA/PB/PC/PD
ITL
-
ISR11
ISR12
ISR13
ISR21
ISR22
ISR23
ISK11
ISK12
-
-
-
-
-
-
-
-
-372
-76.8
-37.3
-19.2
-4
-
-
-
-
-
-
-
-
VDD = 4.5 V, VIN = 2.4 V
VDD = 2.7 V, VIN = 2.2 V
VDD = 2.1 V, VIN = 1.8 V
VDD = 4.5 V, VIN = 2.4 V
VDD = 2.7 V, VIN = 2.2 V
VDD = 2.1 V, VIN = 1.8 V
VDD = 4.5 V, VIN = 0.4 V
VDD = 2.7 V, VIN = 0.4 V
A
Source Current
PA/PB/PC/PD (Quasi-
bidirectional Mode)
A
A
mA
mA
mA
mA
mA
Source Current
PA/PB/PC/PD (Push-pull
Mode)
-2
12.8
8.1
Sink Current
PA/PB/PC/PD (Quasi-
bidirectional, Open-Drain
Apr. 06, 2017
Page 117 of 131
Rev.1.00
Mini57
and Push-pull Mode)
ISK13
-
6
-
mA
VDD = 2.1 V, VIN = 0.4 V
Notes:
1. Only enable modules which support 32 kHz LIRC clock source
2. Only enable modules which support 10 kHz LIRC clock source
Apr. 06, 2017
Page 118 of 131
Rev.1.00
Mini57
8.3 AC Electrical Characteristics
8.3.1 External Input Clock
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
tCHCX
Parameter
Min
10
10
2
Typ
Max
-
Unit
ns
Test Conditions
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
-
-
-
-
-
-
-
-
tCLCX
-
ns
tCLCH
15
15
ns
tCHCL
2
ns
8.3.2 External 4~24 MHz High Speed Crystal (HXT)
Symbol
VHXT
Parameter
Min.
2.1
-40
-
Typ.
Max
5.5
105
-
Unit
V
Test Conditions
Operation Voltage
Temperature
-
-
-
TA
℃
-
414
407
-
uA
12 MHz, VDD = 5.5V
IHXT
Operating Current
Clock Frequency
-
-
uA
12 MHz, VDD = 3.3V
fHXT
4
24
MHz
-
8.3.3 External 32.768 kHz XTAL Oscillator (LXT)
SPECIFICATIONS
SYM.
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
fLXTAL
TLXTAL
ILXTAL
Oscillator frequency
Temperature
32.768
kHz
oC
-40
105
Operating current
17
VDD=2.1V
A
8.3.4 Typical Crystal Application Circuits
Crystal
C1
C2
4 MHz ~ 24 MHz
20 pF
20 pF
20 pF
32.768 kHz
20 pF
Apr. 06, 2017
Page 119 of 131
Rev.1.00
Mini57
XT_IN
XT_OUT
4~24 MHz
or
32.768 kHz
Crystal
C1
C2
Vss
Vss
Figure 8.3-1 Mini57 Typical Crystal Application Circuit
8.3.5 48 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
Min
Typ
1.5
48
Max
Unit
V
Test Conditions
VHRC
Supply Voltage
Center Frequency
-
-
-
-
-
-
MHz
TA = 25 ℃
-1
-
+1
%
fHRC
VDD = 5.5 V
Calibrated Internal
Oscillator Frequency
TA = -40℃~105℃
-2
2
%
VDD=2.1 V~ 5.5 V
TA = 25 ℃,VDD = 5 V
IHRC
Operating Current
-
1.1
-
mA
8.3.6 10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
Parameter
Min
Typ
1.5V
10
Max
Unit
V
Test Conditions
VLRC
Supply Voltage
Center Frequency
-
-
-
-
-
-
kHz
fLRC
VDD = 2.1 V ~ 5.5 V
Oscillator Frequency
-50[1]
-
+50[1]
0.5
%
TA = -40℃ ~ +105℃
TA = 25 ℃,VDD = 5 V
ILRC
Operating Current
-
0.3
μA
Note: These parameters are characterized but not tested.
Apr. 06, 2017
Page 120 of 131
Rev.1.00
Mini57
8.4 Analog Characteristics
8.4.1 12-bit SAR ADC
Symbol
-
Parameter
Min
Typ
Max
Unit
Bit
Test Condition
-
Resolution
-
-
-
-
-
-
-
12
-
DNL
INL
EO
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
2
LSB
LSB
LSB
LSB
LSB
-
VDD = 3.0~5.5 V
VDD = 3.0~5.5 V
VDD = 3.0~5.5 V
VDD = 3.0~5.5 V
VDD = 3.0~5.5 V
-
±2
-
±1
-
EG
Gain Error (Transfer Gain)
Absolute Error
-1
-
EA
±3
Guaranteed
12
-
-
Monotonic
FADC
FS
ADC Clock Frequency
16
MHz
kSPS
VDD = 3.0 ~5.5 V
VDD = 3.0~5.5 V
VDD = 3.0 ~5.5 V
Sample Rate (FADC/TCONV
)
700
N+1
200
1/FADC
ns
N
is sampling counter,
TACQ
Acquisition Time (Sample Stage)
N=1~1024
VDD = 3.0~5.5 V
TCONV
VDD
IDDA
VIN
Conversion Time
Supply Voltage
1000
1050 ns
VDD = 3.0~5.5 V
3.0
-
1
5.5
V
-
Supply Current (Avg.)
Analog Input Voltage
Input Capacitance
Input Load
-
0
-
-
mA
V
VDD = 5.5 V
-
AVDD
-
-
-
CIN
1.6
2.5
-
-
pF
kΩ
RIN
-
Note: ADC voltage reference is same with VDD
Apr. 06, 2017
Page 121 of 131
Rev.1.00
Mini57
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
8.4.2 LDO & Power Management
Symbol
VDD
Parameter
Min
Typ
-
Max
Unit
V
Test Condition
DC Power Supply
Output Voltage
Temperature
2.1
5.5
-
-
VLDO
TA
1.5
25
V
℃
-40
105
Note: It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the
device.
8.4.3 Low Voltage Reset
Symbol
AVDD
TA
Parameter
Min
Typ
Max
5.5
105
Unit
V
Test Condition
Supply Voltage
Temperature
2.1
-
-
-
℃
-40
25
Apr. 06, 2017
Page 122 of 131
Rev.1.00
Mini57
ILVR
Quiescent Current
Threshold Voltage
1
μA
TA=25℃
TA = -40 ~ +105
VLVR
1.8
1.9
2.0
V
8.4.4 Brown-out Detector
Symbol
AVDD
TA
Parameter
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
-
Supply Voltage
Temperature
℃
μA
V
-40
25
105
-
-
IBOD
Quiescent Current
-
100
4.3
4.0
3.7
3.0
2.7
2.4
2.2
2.0
4.3
4.0
3.7
3.0
2.7
2.4
2.2
2.0
AVDD =5.5V
4.33
4.03
3.73
3.02
2.72
2.42
2.22
2.02
4.39
4.10
3.79
3.09
2.79
2.49
2.30
2.09
BOV_VL [2:0] = 3
BOV_VL [2:0] = 2
BOV_VL [2:0] = 7
BOV_VL [2:0] = 1
BOV_VL [2:0] = 6
BOV_VL [2:0] = 0
BOV_VL [2:0] = 5
BOV_VL [2:0] = 4
BOV_VL [2:0] = 3
BOV_VL [2:0] = 2
BOV_VL [2:0] = 7
BOV_VL [2:0] = 1
BOV_VL [2:0] = 6
BOV_VL [2:0] = 0
BOV_VL [2:0] = 5
BOV_VL [2:0] = 4
V
V
V
VBOD
Brown-out Hysteresis
V
V
V
V
V
V
V
V
VBOD
Brown-out Detector
V
V
V
V
8.4.5 Power-on Reset
Symbol
TA
Parameter
Min
Typ
25
Max
Unit
℃
Test Condition
Temperature
-40
105
-
VPOR
Threshold Voltage
1.75
V
VDD = 5.0 V
VDD Start Voltage to Ensure
Power-on Reset
VPOR
RRVDD
tPOR
TBD
TBD
TBD
mV
VDD Raising Rate to Ensure
Power-on Reset
V/ms
ms
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
Apr. 06, 2017
Page 123 of 131
Rev.1.00
Mini57
8.4.6 Comparator
Symbol
VCMP
TA
Parameter
Min
2.1
-40
-
Typ
-
Max
5.5
Unit
V
Test Condition
Supply Voltage
Temperature
℃
25
46
±10
-
105
-
ICMP
Operation Current
Input Offset Voltage
Output Swing
μA
mV
V
VDD=3.3V
VOFF
VSW
-
-
-
-
0
VDD
VCOM
-
Input Common Mode Range
DC Gain[1]
0.1
-
AVDD – 0.1
V
-
-
-
-
-
60
225
10
90
1.06
-
-
-
-
-
dB
ns
TPGD
VHYS
VHYS
TSTB
Propagation Delay
Hysteresis
mV
mV
μs
ACMPPHYSEN = 01
ACMPPHYSEN = 10
Hysteresis
Stable time
Note: Guaranteed by design, not test in production.
8.4.7 PGA
Symbol
Parameter
Min
Typ
Max
Unit
V
Test Condition
Operation voltage range
Operating Current
2.5
3.3
25
5.5
5
mA
VDD=5V, T=125℃
Operating Temperature
-40
125
+2
Input Offset with calibration
mV
Type
corner,
temp=25,VCM=AVDD/2
Input Offset Average Drift
1
uV/
V
Output Swing
0.1
-1
VDD - 0.1
+1
PGA gain accuracy
Input Common Mode Range
DC Gain
%
0
VDD - 1.5
V
50
7
80
dB
MHz
°
Unity Gain Frequency
Phase Margin
8.2
VDD = 5V
50°
PSRR+
CMRR
49
69
90
90
dB
dB
VDD = 5V
VDD = 5V
Apr. 06, 2017
Page 124 of 131
Rev.1.00
Mini57
Slew Rate+
6.0
7.5
20
V/us
us
VDD=5V, RLoad=1.3K,
CLoad=100p
Wake Up Time
Note: Guaranteed by design, not test in production.
Apr. 06, 2017
Page 125 of 131
Rev.1.00
Mini57
8.5 Flash DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
1.65
-
Unit
V
Test Condition
TA =125℃
[2]
VFLA
Supply Voltage
Endurance
1.35
1.5
NENDUR
TRET
100,000
-
-
cycles[1]
year
ms
Data Retention
Sector Erase Time
Program Time
Read Current
Program Current
Erase Current
20
-
-
TERASE
TPROG
IDD1
5
-
-
7.5
4.5
4
us
-
3
-
mA
@33 MHz
IDD2
-
mA
IDD3
-
-
2
mA
Notes:
1. Number of program/erase cycles.
2. VFLA is source from chip LDO output voltage.
Guaranteed by design, not test in production.
Apr. 06, 2017
Page 126 of 131
Rev.1.00
Mini57
9 PACKAGE DIMENSIONS
9.1 28-Pin TSSOP (4.4x9.7x1.0 mm)
Apr. 06, 2017
Page 127 of 131
Rev.1.00
Mini57
9.2 20-Pin TSSOP (4.4x6.5x0.9 mm)
Apr. 06, 2017
Page 128 of 131
Rev.1.00
Mini57
9.3 33-pin QFN33 (4x4x0.8 mm)
Apr. 06, 2017
Page 129 of 131
Rev.1.00
Mini57
10 REVISION HISTORY
Date
Revision
Description
2017.04.06
1.00
Preliminary version.
Apr. 06, 2017
Page 130 of 131
Rev.1.00
Mini57
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Apr. 06, 2017
Page 131 of 131
Rev.1.00
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