ML51DC2AE [NUVOTON]
1T 8051 8-bit Microcontroller;
| 型号： | ML51DC2AE |
| 厂家： | 
NUVOTON |
| 描述： | 1T 8051 8-bit Microcontroller 微控制器 |
| 文件： | 总164页 (文件大小：3068K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML51/ML54/ML56
1T 8051
8-bit Microcontroller
NuMicro® Family
ML51/ML54/ML56 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Sep. 1, 2020
Page 1 of 164
Rev 2.00
ML51/ML54/ML56
TABLE OF CONTENTS
1
2
3
GENERAL DESCRIPTION ............................................................................10
FEATURES....................................................................................................11
PART INFORMATION ...................................................................................16
3.1 ML51/ML54/ML56 Series Package Type................................................................. 16
3.2 ML51/ML54/ML56 Series Selection Guide.............................................................. 17
3.2.1 ML51 Series ....................................................................................................................17
3.2.2 ML54 Series ....................................................................................................................20
3.2.3 ML56 Series ....................................................................................................................21
3.3 ML51/ML54/ML56 Series Selection Code............................................................... 22
4
PIN CONFIGURATION ..................................................................................23
4.1 Pin Configuration......................................................................................................... 23
4.1.1 ML51/ML54/ML56 Series Pin Diagram .......................................................................23
4.1.2 ML51/ML54/ML56 Series Multi Function Pin Diagram .............................................31
4.2 Pin Description............................................................................................................. 71
4.2.1 ML51/ML54/ML56 Series Pin Mapping.......................................................................71
4.2.2 ML51/ML54/ML56 Series Pin Functional Description...............................................73
BLOCK DIAGRAM.........................................................................................78
5
6
5.1 ML51/ML54/ML56 Series Full Function Block ........................................................ 78
FUNCTIONAL DESCRIPTION.......................................................................79
6.1 Memory Organization.................................................................................................. 79
6.2 System Manager ......................................................................................................... 80
6.3 Flash Memory Control ................................................................................................ 81
6.3.1 In-application-programming (IAP)................................................................................81
6.3.2 In-Circuit-Programming (ICP).......................................................................................81
6.3.3 On-Chip-Debugger (ICE)...............................................................................................81
6.4 GPIO Port Structure and Operation.......................................................................... 82
6.4.1 GPIO Mode .....................................................................................................................82
6.5 Timer.............................................................................................................................. 83
6.5.1 Overview..........................................................................................................................83
6.6 Watchdog Timer (WDT).............................................................................................. 84
6.7 Self Wake-up Timer (WKT)........................................................................................ 85
6.7.1 Overview..........................................................................................................................85
6.8 Pulse Width Modulated (PWM)................................................................................. 86
6.8.1 Overview..........................................................................................................................86
6.8.2 Features...........................................................................................................................86
6.9 Serial Port (UART0 & UART1) .................................................................................. 87
Sep. 1, 2020
Page 2 of 164
Rev 2.00
ML51/ML54/ML56
6.9.1 Overview..........................................................................................................................87
6.9.2 Features...........................................................................................................................87
6.10 Smart Card Interface (SC) ................................................................................... 88
6.10.1Overview..........................................................................................................................88
6.10.2Features...........................................................................................................................88
6.11 Serial Peripheral Interface (SPI) ......................................................................... 89
6.11.1Overview..........................................................................................................................89
6.11.2Features...........................................................................................................................89
6.12 Inter-Integrated Circuit (I2C)................................................................................. 90
6.12.1Overview..........................................................................................................................90
6.12.2Features...........................................................................................................................90
6.13 12-bit Analog-to-digital Converter (ADC) ........................................................... 91
6.13.1Overview..........................................................................................................................91
6.14 Voltage Reference (VREF)................................................................................... 92
6.15 Analog Comparator Controller (ACMP).............................................................. 93
6.15.1Overview..........................................................................................................................93
6.15.2Feature.............................................................................................................................93
6.16 PDMA Controller (PDMA)..................................................................................... 94
6.16.1Overview..........................................................................................................................94
6.16.2Feature.............................................................................................................................94
6.17 LCD Driver.............................................................................................................. 95
6.17.1Overview..........................................................................................................................95
6.17.2Features...........................................................................................................................95
6.18 Real Time Clock (RTC)......................................................................................... 96
6.18.1Overview..........................................................................................................................96
6.18.2Features...........................................................................................................................96
6.19 Touch Key (TK) ...................................................................................................... 97
6.19.1Overview..........................................................................................................................97
6.19.2Features...........................................................................................................................97
6.20 Auxiliary Features.................................................................................................. 98
6.20.1Dual DPTRs ....................................................................................................................98
6.20.296-Bit Unique Code (UID) ...........................................................................................102
6.21 Instruction Set ...................................................................................................... 103
6.21.1Instruction Set And Addressing Modes .....................................................................103
6.21.2Read-Modify-Write Instructions..................................................................................105
6.21.3Instruction Set...............................................................................................................105
APPLICATION CIRCUIT..............................................................................109
7
7.1 Power Supply Scheme ............................................................................................. 109
7.2 Peripheral Application Scheme ............................................................................... 110
Sep. 1, 2020
Page 3 of 164
Rev 2.00
ML51/ML54/ML56
8
ELECTRICAL CHARACTERISTICS............................................................111
8.1 General Operating Conditions................................................................................. 111
8.1.1 ML51 32KB/16KB Flash Series..................................................................................111
8.1.2 ML51 64KB Flash/ML54/ML56 Series ......................................................................111
8.2 DC Electrical Characteristics................................................................................... 112
8.2.1 Supply Current Characteristics...................................................................................112
8.2.2 On-Chip Peripheral Current Consumption................................................................120
8.2.3 Wakeup Time from Low-Power Modes .....................................................................122
8.2.4 I/O DC Characteristics.................................................................................................123
8.3 AC Electrical Characteristics ................................................................................... 125
8.3.1 24 MHz Internal High Speed RC Oscillator (HIRC).................................................125
8.3.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC) ................................................126
8.3.3 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
127
8.3.4 External 4~24 MHz High Speed Clock Input Signal Characteristics ....................129
8.3.5 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
130
8.3.6 I/O AC Characteristics .................................................................................................131
8.4 Analog Characteristics.............................................................................................. 132
8.4.1 Reset and Power Control Block Characteristics......................................................132
8.4.2 12-bit SAR ADC............................................................................................................133
8.4.3 Analog Comparator Controller (ACMP).....................................................................135
8.4.4 Internal Voltage Reference .........................................................................................136
8.4.5 Temperature Sensor ....................................................................................................137
8.4.6 LCD Controller ..............................................................................................................138
8.5 Flash DC Electrical Characteristics ........................................................................ 142
8.6 Absolute Maximum Ratings..................................................................................... 143
8.6.1 Voltage Characteristics................................................................................................143
8.6.2 Current Characteristics................................................................................................144
8.6.3 Thermal Characteristics...............................................................................................145
8.6.4 EMC Characteristics ....................................................................................................146
8.6.5 Package Moisture Sensitivity(MSL)...........................................................................148
8.6.6 Soldering Profile ...........................................................................................................149
9
PACKAGE DIMENSIONS............................................................................150
9.1 LQFP 64L-pin (7.0 x 7.0 x 1.4 mm) ........................................................................ 150
9.2 LQFP 48-pin (7.0 x 7.0 x 1.4 mm)........................................................................... 151
9.3 LQFP 44-pin (10 x 10 x 1.4mm............................................................................... 152
9.4 QFN 33-pin (4.0 x 4.0 x 0.8 mm) ............................................................................ 153
9.5 LQFP 32-pin (7.0 x 7.0 x 1.4 mm)........................................................................... 154
9.6 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm) ....................................................................... 155
Sep. 1, 2020
Page 4 of 164
Rev 2.00
ML51/ML54/ML56
9.7 SOP 28-pin (300mil).................................................................................................. 156
9.8 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) ...................................................................... 157
9.9 SOP 20-pin (300 mil) ................................................................................................ 158
9.10 QFN 20-pin ( 3.0 x 3.0 x 0.8 mm ) .................................................................... 159
9.11 TSSOP 14-pin (4.4 x 5.0 x 0.9 mm).................................................................. 160
9.12 MSOP 10-pin (3.0 x 3.0 x 0.85 mm)................................................................. 161
ABBREVIATIONS........................................................................................162
10.1 Abbreviations........................................................................................................ 162
REVISION HISTORY ...................................................................................163
10
11
Sep. 1, 2020
Page 5 of 164
Rev 2.00
ML51/ML54/ML56
LIST OF FIGURES
Figure 4.1-1 ML51SD1AE Pin Assignment.................................................................................... 23
Figure 4.1-2 ML54SD1AE / ML56SD1AE Pin Assignment............................................................ 24
Figure 4.1-3 ML51LD1AE Pin Assignment .................................................................................... 24
Figure 4.1-4 ML54LD1AE / ML56LD1AE Pin Assignment............................................................. 25
Figure 4.1-5 ML54MD1AE / ML56MD1AE Pin Assignment........................................................... 25
Figure 4.1-6 ML51TD1AE / ML51TC0AE / ML51TB9AE Pin Assignment..................................... 26
Figure 4.1-7 ML51PC0AE / ML51PB9AE Pin Assignment............................................................ 27
Figure 4.1-8 ML51EC0AE / ML51EB9AE Pin Assignment............................................................ 27
Figure 4.1-9 ML51UC0AE / ML51UB9AE Pin Assignment............................................................ 28
Figure 4.1-10 ML51FB9AE Pin Assignment .................................................................................. 28
Figure 4.1-11 ML51OB9AE Pin Assignment.................................................................................. 29
Figure 4.1-12 ML51XB9AE Pin Assignment.................................................................................. 29
Figure 4.1-13 ML51DB9AE Pin Assignment.................................................................................. 30
Figure 4.1-14 ML51BB9AE Pin Assignment.................................................................................. 30
Figure 4.1-15 ML51SD1AE Multi-Function Pin assignment .......................................................... 31
Figure 4.1-16 ML54SD1AE Multi-Function Pin assignment .......................................................... 34
Figure 4.1-17 ML56SD1AE Multi-Function Pin assignment .......................................................... 37
Figure 4.1-18 ML51LD1AE Multi-Function Pin assignment........................................................... 40
Figure 4.1-19 ML54LD1AE Multi-Function Pin assignment........................................................... 43
Figure 4.1-20 ML56LD1AE Multi-Function Pin assignment........................................................... 46
Figure 4.1-21 ML54MD1AE Multi-Function Pin assignment.......................................................... 49
Figure 4.1-22 ML56MD1AE Multi-Function Pin assignment.......................................................... 52
Figure 4.1-23 ML51TD1AE Multi-Function Pin assignment........................................................... 55
Figure 4.1-24 ML51TC0AE / ML51TB9AE Multi-Function Pin Assignment.................................. 57
Figure 4.1-25 ML51PC0AE / ML51PB9AE Multi-Function Pin Assignment .................................. 59
Figure 4.1-26 ML51EC0AE / ML51EB9AE Multi-Function Pin Assignment ................................. 61
Figure 4.1-27 ML51UC0AE / ML51UB9AE Multi Function Pin Assignment.................................. 63
Figure 4.1-28 ML51FB9AE Multi Function Pin Assignment........................................................... 65
Figure 4.1-29 ML51OB9AE Multi Function Pin Assignment.......................................................... 66
Figure 4.1-30 ML51XB9AE Multi Function Pin Assignment .......................................................... 67
Figure 4.1-31 ML51DB9AE Multi Function Pin Assignment .......................................................... 69
Figure 4.1-32 ML51BB9AE Pin Assignment.................................................................................. 70
Figure 5.1-1 Functional Block Diagram.......................................................................................... 78
Figure 6.2-1 Clock System Block Diagram .................................................................................... 80
Figure 7.1-1 NuMicro® ML51/ML54/ML56 Series Power supply circuit....................................... 109
Figure 7.2-1 NuMicro® ML51/ML54/ML56 Series Peripheral interface circuit ............................. 110
Sep. 1, 2020
Page 6 of 164
Rev 2.00
ML51/ML54/ML56
Figure 8.4-1 Typical Connection With Internal Voltage Reference.............................................. 136
Figure 8.6-1 Soldering Profile From J-STD-020C........................................................................ 149
Figure 9.1-1 LQFP 64L Package Dimension ............................................................................... 150
Figure 9.2-1 LQFP-48 Package Dimension................................................................................ 151
Figure 9.3-1 LFP44 Package Dimension.................................................................................... 152
Figure 9.4-1 QFN-33 Package Dimension.................................................................................. 153
Figure 9.5-1 LQFP-32 Package Dimension................................................................................. 154
Figure 9.6-1 TSSOP-28 Package Dimension .............................................................................. 155
Figure 9.7-1 SOP-28 Package Dimension.................................................................................. 156
Figure 9.8-1 TSSOP-20 Package Dimension .............................................................................. 157
Figure 9.9-1 SOP-20 Package Dimension................................................................................... 158
Figure 9.10-1 QFN-20 Package Dimension................................................................................. 159
Figure 9.11-1 TSSOP-14 Package Dimension ............................................................................ 160
Figure 9.12-1 MSOP-10 Package Dimension.............................................................................. 161
Sep. 1, 2020
Page 7 of 164
Rev 2.00
ML51/ML54/ML56
List of Tables
Table 6.4-1 Configuration for Different I/O Modes......................................................................... 82
Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars.......................................... 84
Table 6.21-1 Instruction Set And Addressing Modes .................................................................. 103
Table 6.21-2 Instructions Affect Flag Settings ............................................................................ 104
Table 6.21-3 Instruction Set........................................................................................................ 108
Table 8.1-1 ML51 32KB/16KB Flash Series General Operating Conditions ............................... 111
Table 8.1-2 ML56/ML54/ML51 64KB Flash Series General Operating Conditions ..................... 111
Table 8.2-1 ML51 32KB / 16KB Series Current Consumption In Normal Run Mode .................. 113
Table 8.2-2 ML51 32KB/16KB Flash Series Current Consumption In Low Power Run Mode.... 113
Table 8.2-3 ML51 32KB/16KB Flash Series Current Consumption In Idle Mode........................ 114
Table 8.2-4 ML51 32KB/16KB Flash Series Current Consumption In Low Power Idle Mode..... 114
Table 8.2-5 ML51 32KB/16KB Flash Series Chip Current Consumption in Power down mode . 115
Table 8.2-6 ML56/ML54/ML51 64KB Flash Series Current Consumption In Normal Run Mode 117
Table 8.2-7 ML56/ML54/ML51 64KB Flash Series Current Consumption In Low Power Run Mode
.............................................................................................................................................. 117
Table 8.2-8 ML56/ML54/ML51 64KB Flash Series Current Consumption In Idle Mode.............. 118
Table 8.2-9 ML56/ML54/ML51 64KB Flash Series Current consumption in Low Power Idle mode
.............................................................................................................................................. 118
Table 8.2-10 ML56/ML54/ML51 64KB Flash Series Series Chip Current Consumption In Power
Down Mode........................................................................................................................... 119
Table 8.2-11 Peripheral Current Consumption ............................................................................ 121
Table 8.2-12 Low-Power Mode Wakeup Timings........................................................................ 122
Table 8.2-13I/O Input Characteristics .......................................................................................... 123
Table 8.2-14 nRESET Input Characteristics................................................................................ 124
Table 8.3-1 24 MHz Internal High Speed RC Oscillator(HIRC) Characteristic............................ 125
Table 8.3-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics.......................... 126
Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator ........................................ 127
Table 8.3-4 Typical Crystal Application....................................................................................... 128
Table 8.3-5 External 4~24 MHz High Speed Clock Input Signal ................................................. 129
Table 8.3-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator Characteristics............... 130
Table 8.3-7 Typical 32.768 kHz Crystal Application Circuit ......................................................... 130
Table 8.3-8 I/O AC characteristics ............................................................................................... 131
Table 8.4-1 Reset And Power Control Unit.................................................................................. 132
Table 8.4-2 ADC Characteristics.................................................................................................. 133
Table 8.4-3 ACMP Characteristics............................................................................................... 135
Table 8.4-4 Voltage Reference Character ................................................................................... 136
Table 8.4-5 Temperature Sensor Character................................................................................ 137
Sep. 1, 2020
Page 8 of 164
Rev 2.00
ML51/ML54/ML56
Table 8.4-6 LCD Digital Characteristics....................................................................................... 139
Table 8.4-7 Current Consumption In Power Down Mode With LCD Voltage Source From Internal
Charge Pump........................................................................................................................ 140
Table 8.4-8 Current Consumption In Power Down Mode With LCD Voltage Source From AVDD140
Table 8.4-9 Current Consumption In Power Down Mode With LCD Voltage Source From External
VLCD pin............................................................................................................................... 141
Table 8.5-1 Flash Memory Characteristics .................................................................................. 142
Table 8.6-1 ML51 32KB/16KB Flash Series Voltage Characteristics.......................................... 143
Table 8.6-2 ML51 64KB Flash/ML54/ML56 Series Voltage Characteristics................................ 143
Table 8.6-3 Current Characteristics ............................................................................................. 144
Table 8.6-4 Thermal Characteristics............................................................................................ 145
Table 8.6-5 ML51 32KB/16KB Flash Series EMC Characteristics .............................................. 146
Table 8.6-6 ML51 64KB Flash/ML54/ML56 Series EMC Characteristics.................................... 147
Table 8.6-7 Package Moisture Sensitivity(MSL).......................................................................... 148
Table 8.6-8 Soldering Profile........................................................................................................ 149
Table 10.1-1 List of Abbreviations................................................................................................ 162
Sep. 1, 2020
Page 9 of 164
Rev 2.00
ML51/ML54/ML56
1 GENERAL DESCRIPTION
The NuMicro® ML51/ML54/ML56 series is a Flash embedded 1T 8051-based microcontroller. The
instruction set of the ML51 series is fully compatible with the standard 80C51 with enhanced
performance; This series is a three-to-one single microcontrollers, intergrated with up to 14 channels
of capacitive touch and LCD driver.
The ML51/ML54/ML56 series is 1T 8051 core based low-power microcontrollers running at less
80µA/MHz in normal run mode, and power down current is below 1uA. It Provides operating frequency
up to 24 MHz. 16KB and 32KB Flash of ML51 series voltage range supports 1.8V to 5.5V, and 64KB
Flash of ML51 series supports 1.8 to 3.6V voltage range.
The ML51/ML54/ML56 series microcontroller provides 3 power modes to reduce power consumption
－Low power run mode, Low power Idle mode, and Power-down mode. In Low power run mode, the
power consumption can be down to 15 uA at 38.4 kHz LIRC. In Low power idle mode, CPU
processing is suspended by holding the Program Counter. No program code is fetched and run in low
power idle mode if the power consumption does not exceed 13 uA. Power-down mode stops the
whole system clock for minimum power consumption with the leakage current less than 1 uA. The
system clock of the ML51 series can also be slowed down by software clock divider, which allows for
flexibility between execution performance and power consumption.
The ML51/ML54/ML56 series provides rich peripherals including 256 bytes of SRAM, 4 Kbytes of
auxiliary RAM (XRAM), up to 56 general purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit
Timer2 with three-channel input capture module, one Watchdog Timer (WDT), one Self Wake-up
Timer (WKT), one 16-bit auto-reload Timer3 for general purpose or baud rate generator, two UARTs
with frame error detection and automatic address recognition, two ISO7816 Smartcard interface, two
SPI, two I2C, 6 enhanced PWM output channels with dead zone control, 6 PWM output channels with
3 individual configurable period, two analog comparators, eight-channel shared pin interrupt for all I/O
ports, and one 12-bit ADC at 500 ksps. There are a total of 31 sources with 4-level-priority interrupts
capability.
All series contains up to 64 Kbytes Flash, called APROM designed for programming. Flash supports
In-Application-Programming (IAP) function, which supports on-chip firmware upgrade. Partial flash can
be configured as Data Flash programmed by IAP and read by IAP or MOVC instruction. The
ML51/ML54/ML56 series includes an additional configurable up to 4/3/2/1 Kbytes Flash area called
LDROM, in which the Boot Code normally resides for carrying out the In-System-Programming (ISP).
To facilitate mass production programming and verification, the Flash is allowed to be programmed
and read electronically by parallel Writer/Programmer or In-Circuit-Programming (ICP) with Nu-Link.
Once programmed and verified, the programmed code can be protected by the Flash lock mechanism
from being read out by external programming tool.
Through the high performance and low power features of ML51/ML54/ML56 series, this series benefits
for low-power, battery powered devices, general purpose, home appliances, and motor control
system.
Series
VDD Voltage
1.8 ~ 5.5 V
1.8 ~3.6 V
1.8 ~3.6 V
1.8 ~3.6 V
LCD Driver
Touch Key
ML51 32/16KB Flash Series
ML51 64KB Flash Series
ML54 Series
-
-
-
-
-
ML56 Series
Sep. 1, 2020
Page 10 of 164
Rev 2.00
ML51/ML54/ML56
2 FEATURES
Core and System
Fully static design 8-bit high performance 1T 8051-based
CMOS microcontroller.
Instruction set fully compatible with MCS-51.
4-priority-level interrupts capability.
Dual Data Pointers (DPTRs).
8051
Power on Reset (POR)
Brown-out Detector (BOD)
Low Voltage Reset (LVR)
POR with 1.55V threshold voltage level
7-level selection, with brown-out interrupt and reset option.
(4.4V / 3.7V / 3.0V / 2.7V / 2.4V / 2.0V / 1.8V)
LVR with 1.63V threshold voltage level
96-bit Unique ID (UID)
Security
128-bit Unique Customer ID (UCID)
128-bytes security protection memory SPROM
Memories
Up to 64 KBytes of APROM for User Code.
4/3/2/1 Kbytes of Flash for loader (LDROM) configure from
APROM for In-System-Programmable (ISP)
Flash Memory accumulated with pages of 128 Bytes from
APROM by In-Application-Programmable (IAP) means
whole APROM can be use as Data Flash
Flash
An additional 128 bytes security protection memory SPROM
Code lock for security by CONFIG
256 Bytes on-chip RAM.
SRAM
Additional 4 KBytes on-chip auxiliary RAM (XRAM)
accessed by MOVX instruction.
Three modes: peripheral-to-memory, memory-to-peripheral,
and memory-to-memory transfer.
Source address and destination address must be word
alignment in all modes.
PDMA:
Memory-to-memory mode: transfer length must be word
alignment.
Clocks
4~24 MHz High-speed external crystal oscillator (HXT) for
precise timing operation
External Clock Source
Sep. 1, 2020
Page 11 of 164
Rev 2.00
ML51/ML54/ML56
32.768 kHz High-speed external crystal oscillator (LXT) for
RTC operation
Default 24 MHz high-speed internal oscillator (HIRC)
trimmed to ±1% (accuracy at 25 °C, 3.3 V), ±2% in -
20~105°C.
Internal Clock Source
38.4 kHz low-speed internal oscillator (LIRC) calibrating to
±2% by software from high-speed internal oscillator
Timers
Two 16-bit Timers/Counters 0 and 1 compatible with
standard 8051.
One 16-bit Timer 2 with three-channel input capture module
and 9 input pin can be selected.
16-bit Timer
One 16-bit auto-reload Timer 3, which can be the baud rate
clock source of UARTs.
6-bit free running up counter for WDT time-out interval.
Selectable time-out interval is 1.66 ms ~ 3413.12 ms since
WDT_CLK = 38.4 kHz (LIRC).
Watchdog
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
16-bit free running up counter for time-out interval.
Clock sources from LIRC
Wake-up Timer
Able self Wake-up wake up from Power-down or Idle mode,
and auto reload count value.
Supports Interrupt
Up To 12 output pins can be selected
Supports maximum clock source frequency up to 24 MHz
Supports up to Three PWM modules, each module provides
6 output channels.
Supports independent mode for PWM output
Supports complementary mode for 3 complementary paired
PWM output channels
PWM
Dead-time insertion with 8-bit resolution
Supports 16-bit resolution PWM counter
Supports mask function and tri-state enable for each PWM
pin
Supports brake function
Supports trigger ADC on the following events
Supports real time counter and calendar counter for RTC
time and calendar check.
RTC
Supports alarm time and calendar settings
Sep. 1, 2020
Page 12 of 164
Rev 2.00
ML51/ML54/ML56
Supports alarm time and calendar mask enable settings.
Selectable 12-hour or 24-hour time scale setting.
Supports Leap Year indication setting.
Supports Day of the Week counter setting.
Frequency of RTC clock source compensate by
RTC_FREQADJ register.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period
interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1
second.
Supports RTC Time Tick and Alarm Match interrupt.
Supports chip wake-up from Idle or Power-down mode while
a RTC interrupt signal is generated.
Support clock source selectable from LXT or LIRC.
Analog Interfaces
Analog input voltage range: 0 ~ AVDD.
External or internal Voltage reference input selectable.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 16 single-end analog input channels
1 internal channels, they are band-gap voltage (VBG).
Maximum ADC peripheral clock frequency is 1 MHz.
Up to 500 KSPS sampling rate.
Analog-to-Digital Converter
(ADC)
Software Write 1 to ADCS bit to trig ADC start.
External pin (STADC) trigger
PWM trigger.
Communication Interfaces
Supports up to 2 UARTs: UART0, UART1
Supports 2 Smart Card configuration as UART function as
UART2 and UART3.
UART baud rate clock from HIRC or HXT.
Full-duplex asynchronous communications
Programmable 9th bit.
UART
TXD and RXD pins of UART0 exchangeable via software.
2 sets of I2C devices
Master/Slave mode
I2C
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
7-bit addressing mode
Sep. 1, 2020
Page 13 of 164
Rev 2.00
ML51/ML54/ML56
Standard mode (100 kbps) and Fast mode (400 kbps).
Supports 8-bit time-out counter requesting the I2C interrupt if
the I2C bus hangs up and timer-out counter overflows
Multiple address recognition (four slave addresses with
mask option)
Supports hold time programmable
2 sets of SPI devices
Supports Master or Slave mode operation
Supports MSB first or LSB first transfer sequence
Slave mode up to 12 Mhz
SPI
Two sets ISO 7816-3 device
ISO 7816-3
Supports ISO 7816-3 compliant T=0, T=1
Supports full-duplex UART mode.
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
Schmitt trigger input / TTL mode selectable.
Each I/O pin configured as interrupt source with edge/level
trigger setting
̅̅̅̅̅̅̅
̅̅̅̅̅̅̅
Standard interrupt pins INT0 and INT1.
GPIO
Supports high drive and high sink current I/O
I/O pin internal pull-up or pull-down resistor enabled in input
mode.
Maximum I/O Speed is 24 MHz
Enabling the pin interrupt function will also enable the wake-
up function
Supports 5V-tolerance function for
ML51 Series: ML51TD1AE/ML51LD1AE/ML51SD1AD
ML54 Series: ML54MD1AE/ML54LD1AE/ML54SD1AE
ML56 Series: ML56MD1AE/ML56LD1AEML56SD1AE
Support Internal resistor bias, capacitor bias
Support programmable internal VLCD charge pump mode
1/2, 1/3, 1/4 bias selectable
LCD Driver
Touch Key
4 COM x 32 SEG, 6 COM x 30 SEG, 8 COM x 28 SEG
Support 2.8V to 5.5V LCD operating voltage
Supports up to 14 touch key + 1 reference pin.
Sep. 1, 2020
Page 14 of 164
Rev 2.00
ML51/ML54/ML56
Programmable sensitivity levels for each channel.
Programmable scanning speed for different applications.
Supports effect when in power down mode.
Supports single key-scan and programmable periodic key-
scan.
Programmable interrupt options for key-scan complete
with/without threshold control.
ESD & EFT
HBM 8 kV for ML51 32KB/16KB Flash Series pass
ESD
HBM 7 kV for ML51 64KB Flash/ML54/ML56 Series pass
EFT
> ± 4.4 kV
150 mA for ML51 32KB/16KB Flash Series pass
Latch-up
200 mA for ML51 64KB Flash/ML54/ML56 Series pass
Sep. 1, 2020
Page 15 of 164
Rev 2.00
ML51/ML54/ML56
3 PART INFORMATION
3.1 ML51/ML54/ML56 Series Package Type
Package
ML51
ML54
ML56
ML51xB
ML51xC
ML51xD
ML54xD
ML56xD
MSOP10
TSSOP14
TSSOP20
SOP20
ML51BB9AE
ML51DB9AE
ML51FB9AE
ML51OB9AE
ML51XB9AE
ML51EB9AE
ML51UB9AE
ML51PB9AE
ML51TB9AE
QFN20(3x3)
TSSOP28
SOP28
ML51EC0AE
ML51UC0AE
ML51PC0AE
ML51TC0AE
LQFP32
QFN33(4x4)
LQFP44
ML51TD1AE
ML54MD1AE
ML54LD1AE
ML54SD1AE
ML56MD1AE
ML56LD1AE
ML56SD1AE
LQFP48
ML51LD1AE
ML51SD1AE
LQFP64
Sep. 1, 2020
Page 16 of 164
Rev 2.00
ML51/ML54/ML56
3.2 ML51/ML54/ML56 Series Selection Guide
3.2.1 ML51 Series
ML51 16KB Flash Series
ML51
Part Number
BB9AE
DB9AE
FB9AE
OB9AE
XB9AE
EB9AE
UB9AE
PB9AE
Flash (KB)
SRAM (KB)
16
1
16
1
16
1
16
1
16
1
16
1
16
2
16
2
ISP ROM (KB)
SPROM (bytes)
System Frequency ( MHz)
GPIO
4
4
4
4
4
4
4
4
128
24
7
128
24
11
4
128
24
16
4
128
24
16
4
128
24
17
4
128
24
24
4
128
24
24
4
128
24
28
16-bit Timer
4
4
PWM
5
6
6
6
6
6
6
6
Analog Comparator
Internal Voltage Reference
PDMA
-
-
-
-
-
-
2
2
-
-
-
-
-
-
Y
2
Y
2
2
2
2
2
2
2
RTC
-
-
-
-
-
-
-
-
LCD
ISO 7816-3
UART
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
SPI
-
1
1
1
1
1
1
1
I2C
1
2
2
2
2
2
2
2
8
12-bit SAR ADC
Package
2
3
6
6
6
8
8
MSOP10 TSSOP14 TSSOP20 SOP20
QFN20 TSSOP28 SOP28
LQFP32
Note:
1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
2. ISO 7816-3 configurable as standard UART function.
Sep. 1, 2020
Page 17 of 164
Rev 2.00
ML51/ML54/ML56
ML51 32KB Flash Series
ML51
Part Number
EC0AE
UC0AE
PC0AE
TC0AE
TC1AE
LC1AE
Flash (KB)
SRAM (KB)
32
2
32
32
32
32
32
2
2
2
2
2
ISP ROM (KB)
SPROM (bytes)
System Frequency ( MHz)
GPIO
4
4
4
4
4
4
128
24
24
4
128
128
128
128
128
24
24
24
24
24
24
28
28
28
43
16-bit Timer
4
4
4
4
4
PWM
6
6
6
6
6
6
Analog Comparator
Internal Voltage Reference
PDMA
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
RTC
-
-
-
-
-
-
LCD
ISO 7816-3
UART
-
-
-
-
-
-
1
1
1
1
2
2
2
2
2
2
2
2
SPI
2[3]
2
2[3]
2
2
2
2
2
I2C
2
8
2
8
2
8
2
9
12-bit SAR ADC
8
10
Package TSSOP28
SOP28
LQFP32
QFN33
QFN33
LQFP48
Note:
1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
2. ISO 7816-3 configurable as standard UART function.
3. SPI0 and SPI1 share with same SS pin in 28pin package.
Sep. 1, 2020
Page 18 of 164
Rev 2.00
ML51/ML54/ML56
ML51 64KB Flash Series
ML51
Part Number
TD1AE
LD1AE
SD1AE
Flash (KB)
SRAM (KB)
64
64
64
4
4
4
ISP ROM (KB)
SPROM (bytes)
System Frequency ( MHz)
GPIO
4
4
4
128
128
128
24
24
24
28
43
56
16-bit Timer
4
4
4
PWM
6+2+2+2
6+2+2+2
6+2+2+2
Analog Comparator
Internal Voltage Reference
PDMA
2
2
2
Y
Y
Y
4
4
4
RTC
Y
Y
Y
LCD
-
-
-
ISO 7816-3
2
2
2
UART
2
2
2
SPI
2
2
2
2
2
I2C
12-bit SAR ADC
Package
2
9
10
14
QFN33
LQFP48
LQFP64
Note:
1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
2. ISO 7816-3 configurable as standard UART function.
Sep. 1, 2020
Page 19 of 164
Rev 2.00
ML51/ML54/ML56
3.2.2
ML54 Series
ML54
Part Number
MD1AE
LD1AE
SD1AE
Flash (KB)
SRAM (KB)
64
64
64
4
4
4
ISP ROM (KB)
SPROM (bytes)
4
4
4
128
128
128
System Frequency ( MHz)
24
24
24
GPIO
16-bit Timer
38
42
55
4
4
4
PWM
6+2+2+2
6+2+2+2
6+2+2+2
Analog Comparator
Internal Voltage Reference
PDMA
2
2
2
Y
Y
Y
4
4
4
RTC
Y
8x17
6x19
4x21
2
Y
8x18
6x20
4x22
2
Y
8x28
6x30
4x32
2
LCD
ISO 7816-3
UART
2
2
2
SPI
2
2
2
I2C
2
2
2
12-bit SAR ADC
Package
10
10
14
LQFP44
LQFP48
LQFP64
Note:
1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
2. ISO 7816-3 configurable as standard UART function.
Sep. 1, 2020
Page 20 of 164
Rev 2.00
ML51/ML54/ML56
3.2.3
ML56 Series
ML56
Part Number
MD1AE
LD1AE
SD1AE
Flash (KB)
SRAM (KB)
64
64
64
4
4
4
ISP ROM (KB)
SPROM (bytes)
4
4
4
128
128
128
System Frequency ( MHz)
24
24
24
GPIO
16-bit Timer
38
42
55
4
4
4
PWM
6+2+2+2
6+2+2+2
6+2+2+2
Analog Comparator
Internal Voltage Reference
PDMA
2
2
2
Y
Y
Y
4
Y
4
Y
4
Y
RTC
8x17
6x19
4x21
6+1
2
8x18
6x20
4x22
9+1
2
8x28
6x30
4x32
14+1
2
LCD
Touch Key
ISO 7816-3
UART
2
2
2
SPI
2
2
2
I2C
2
2
2
12-bit SAR ADC
Package
10
10
14
LQFP44
LQFP48
LQFP64
Note:
1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
2. ISO 7816-3 configurable as standard UART function.
3.Touch key should define 1 key as reference pin.
Sep. 1, 2020
Page 21 of 164
Rev 2.00
ML51/ML54/ML56
3.3 ML51/ML54/ML56 Series Selection Code
ML
51
Line
F
B
9
A
E
Core
Package
Flash
SRAM
Reserve
Temperature
E:-40 ~ 105°C
1T 8051
51: Base
B: MSOP10 (3x3 mm)
D: TSSOP14 (4.4x5.0 mm)
E: TSSOP28 (4.4x9.7 mm)
F: TSSOP20 (4.4x6.5 mm)
L: LQFP48 (7x7 mm)
M: LQFP44(10x10 mm)
O: SOP20 (300 mil)
A: 8 KB
0: 2 KB
Low power 54: LCD
56: Touch
B: 16 KB
C: 32 KB
D: 64 KB
1: 4 KB
2: 8/12 KB
3: 16 KB
6: 32 KB
8: 64 KB
9: 1 KB
P: LQFP32 (7x7 mm)
S: LQFP64 (7x7 mm)
T: QFN33 (4x4 mm)
A: 96 KB
U: SOP28 (300 mil)
X: QFN20 (3x3mm)
Sep. 1, 2020
Page 22 of 164
Rev 2.00
ML51/ML54/ML56
4 PIN CONFIGURATION
4.1 Pin Configuration
Users can find pin configuaration informations in chapter 4 or by using NuTool - PinConfigure. The
NuTool - PinConfigure contains all Nuvoton NuMicro® Family chip series with all part number, and
helps users configure GPIO multi-function correctly and handily.
4.1.1
ML51/ML54/ML56 Series Pin Diagram
4.1.1.1 LQFP64 Package
Corresponding Part Number: ML51SD1AE/ ML54SD1AE / ML56SD1AE
ML51SD1AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
P4.6
VDD
nRESET
P5.6
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P3.6
VDD
P4.7
P3.3
P3.2
P3.1
P3.0
AVDD
VREF
AVSS
P6.7
P6.6
P6.5
P6.4
P2.7
LQFP64
VSS
P0.6
P0.7
P3.4
P3.5
P5.2
Figure 4.1-1 ML51SD1AE Pin Assignment
Sep. 1, 2020
Page 23 of 164
Rev 2.00
ML51/ML54/ML56
ML54SD1AE / ML56SD1AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
P4.6
VDD
P4.7
P3.3
P3.2
P3.1
P3.0
AVDD
VREF
AVSS
P6.7
P6.6
P6.5
P6.4
P2.7
nRESET
P5.6
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P3.6
VDD
VSS
P0.6
P0.7
P3.4
P3.5
P5.2
LQFP64
Figure 4.1-2 ML54SD1AE / ML56SD1AE Pin Assignment
4.1.1.2 LQFP48 Package
Corresponding Part Number: ML51LD1AE/ ML54LD1AE / ML56LD1AE
ML51LD1AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
P4.6
VDD
P4.7
P3.3
P3.2
P3.1
P3.0
VREF
AVSS
P2.7
P2.6
nRESET
P5.6
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P5.2
P5.3
LQFP48
Figure 4.1-3 ML51LD1AE Pin Assignment
Sep. 1, 2020
Page 24 of 164
Rev 2.00
ML51/ML54/ML56
ML54LD1AE / ML56LD1AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
P4.6
VDD
P4.7
P3.3
P3.2
P3.1
P3.0
VREF
AVSS
P2.7
P2.6
nRESET
P5.6
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P5.2
P5.3
LQFP48
Figure 4.1-4 ML54LD1AE / ML56LD1AE Pin Assignment
4.1.1.3 LQFP44 Package
Corresponding Part Number: ML54MD1AE / ML56MD1AE
ML54MD1AE / ML56MD1AE
34
22
21
20
19
18
17
16
15
14
13
12
VSS
P5.0
nRESET
P0.0
P0.1
P0.2
P0.3
P0.6
P0.7
P5.2
P5.3
P5.4
35
P4.6
36
VDD
37
P3.3
38
P3.2
39
P3.1
LQFP44
40
P3.0
41
VREF
42
AVSS
43
P2.7
44
P2.6
Figure 4.1-5 ML54MD1AE / ML56MD1AE Pin Assignment
Sep. 1, 2020
Page 25 of 164
Rev 2.00
ML51/ML54/ML56
4.1.1.4 QFN33 Package
Corresponding Part Number: ML51TD1AE / ML51TC0AE / ML51TB9AE
ML51TD1AE / ML51TC0AE / ML51TB9AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
P4.6
VDD
P3.3
P3.2
P3.1
P3.0
VREF
nRESET
P5.6
Top transparent view
P0.0
P0.1
QFN33
P0.2
P0.3
P5.2
33 VSS
P5.3
Figure 4.1-6 ML51TD1AE / ML51TC0AE / ML51TB9AE Pin Assignment
Sep. 1, 2020
Page 26 of 164
Rev 2.00
ML51/ML54/ML56
4.1.1.5 LQFP32 Package
Corresponding Part Number: ML51PC0AE / ML51PB9AE
ML51PC0AE / ML51PB9AE
25
16
15
14
13
12
11
10
9
VSS
nRESET
P5.6
26
P4.6
27
VDD
P0.0
28
P3.3
P0.1
LQFP32
29
P3.2
P0.2
30
P3.1
P0.3
31
P3.0
P5.2
32
VREF
P5.3
Figure 4.1-7 ML51PC0AE / ML51PB9AE Pin Assignment
4.1.1.6 TSSOP28 Package
Corresponding Part Number: ML51EC0AE / ML51EB9AE
ML51EC0AE / ML51EB9AE
1
28
27
26
25
24
P4.0
P1.4
2
P4.1
P1.5
3
P5.1
P1.6
4
P5.0
P1.7
5
nRESET
VSS
6
7
23 P0.0
22 P0.1
21 P0.2
P4.6
VDD
P3.2
P3.1
P3.0
VREF
P2.5
P2.4
P2.3
8
P0.3
P5.2
P5.3
P2.0
P2.1
P2.2
9
20
19
18
17
16
15
10
11
12
13
14
Figure 4.1-8 ML51EC0AE / ML51EB9AE Pin Assignment
Sep. 1, 2020
Page 27 of 164
Rev 2.00
ML51/ML54/ML56
4.1.1.7 SOP28 Package
Corresponding Part Number: ML51UC0AE / ML51UB9AE
ML51UC0AE / ML51UB9AE
1
28
27
26
25
24
P4.0
P1.4
2
P4.1
P1.5
3
P5.1
P1.6
4
P5.0
P1.7
5
nRESET
VSS
6
7
23 P0.0
22 P0.1
21 P0.2
P4.6
VDD
P3.2
P3.1
P3.0
VREF
P2.5
P2.4
P2.3
8
P0.3
P5.2
P5.3
P2.0
P2.1
P2.2
9
20
19
18
17
16
15
10
11
12
13
14
Figure 4.1-9 ML51UC0AE / ML51UB9AE Pin Assignment
4.1.1.8 TSSOP20 Package
Corresponding Part Number: ML51FB9AE
ML51FB9AE
1
20
19
18
VSS
P5.1
2
3
P4.6
VDD
P3.2
P3.1
P3.0
VREF
P2.5
P2.4
P2.3
P5.0
nRESET
4
17 P0.0
16 P0.1
15 P0.2
5
6
P0.3
P5.2
P5.3
P2.2
7
14
13
12
11
8
9
10
Figure 4.1-10 ML51FB9AE Pin Assignment
Sep. 1, 2020
Page 28 of 164
Rev 2.00
ML51/ML54/ML56
4.1.1.9 SOP20 Package
Corresponding Part Number: ML51OB9AE
ML51OB9AE
1
20
19
18
VSS
P5.1
2
3
P4.6
VDD
P3.2
P3.1
P3.0
VREF
P2.5
P2.4
P2.3
P5.0
nRESET
4
17 P0.0
16 P0.1
15 P0.2
5
6
P0.3
P5.2
P5.3
P2.2
7
14
13
12
11
8
9
10
Figure 4.1-11 ML51OB9AE Pin Assignment
4.1.1.10 QFN20 Package
Corresponding Part Number: ML51XB9AE
ML51XB9AE
15 14 13 12 11
nRESET
P0.0
VSS 16
10
9
17
18
19
20
P4.6
QFN20
8
P0.1
VDD
P3.1
P3.0
7
P0.2
6
NC
P0.3
1
2
3
4
5
Figure 4.1-12 ML51XB9AE Pin Assignment
Sep. 1, 2020
Page 29 of 164
Rev 2.00
ML51/ML54/ML56
4.1.1.11 TSSOP14 Package
Corresponding Part Number: ML51DB9AE
ML51DB9AE
1
14
13
12
11
10
9
VSS
P5.1
2
P4.6
P5.0
3
4
5
6
7
VDD
P3.1
P3.0
P2.5
P2.4
nRESET
P0.2
TSSOP14
P0.3
P5.2
8
P5.3
Figure 4.1-13 ML51DB9AE Pin Assignment
4.1.1.12 MSOP10 Package
Corresponding Part Number: ML51BB9AE
ML51BB9AE
1
10
9
P5.0
P5.1
2
nRESET
P0.0
VSS
3
8
MSOP10
P4.6
4
7
P0.1
VDD
5
6
P2.0
P2.3
Figure 4.1-14 ML51BB9AE Pin Assignment
Sep. 1, 2020
Page 30 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2
ML51/ML54/ML56 Series Multi Function Pin Diagram
4.1.2.1 LQFP64 Package
Corresponding Part Number: ML51SD1AE / ML54SD1AE / ML56SD1AE
ML51SD1AE Pin Function
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1
P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0
P3.6 / PWM0_CH5 / INT1
VDD
T1 / P4.7
PWM0_BRAKE / IC0 / PWM1_CH0 / SPI1_SS / P3.3
CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / ADC_CH10 / P3.0
LQFP64
AVDD
VREF
VDD
AVSS
VSS
I2C1_SCL / ADC_CH11 / P6.7
I2C1_SDA / ADC_CH12 / P6.6
UART0_TXD / ADC_CH13 / P6.5
UART0_RXD / ADC_CH14 / P6.4
ACMP0_O / PWM3_CH0 / UART1_TXD / ADC_CH15 / P2.7
P0.6 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
P0.7 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
P3.4 / PWM2_CH1 / T1
P3.5 / PWM2_CH0 / T0
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
Figure 4.1-15 ML51SD1AE Multi-Function Pin assignment
Pin ML51SD1AE Pin Function
1
2
3
4
P2.6 / UART1_RXD / PWM3_CH1 / ACMP1_O
P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
Sep. 1, 2020
Page 31 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML51SD1AE Pin Function
5
6
P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3
P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 /
PWM0_BRAKE
7
8
9
P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE
P1.3 / IC0
P1.2 / UART3_TXD / IC1
10 P1.1 / UART3_RXD / UART1_TXD / IC2
11 P1.0 / UART1_RXD / IC0
12 P3.7 / SPI1_MOSI
13 P5.7 / PWM0_BRAKE / PWM0_CH4 / CLKO
14 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC
15 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT
16 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
17 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
18 P3.5 / PWM2_CH0 / T0
19 P3.4 / PWM2_CH1 / T1
20 P0.7 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
21 P0.6 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
22 VSS
23 VDD
24 P3.6 / PWM0_CH5 / INT1
25 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0
26 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1
27 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
28 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
29 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
30 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
31 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
32 nRESET
33 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
34 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
35 P4.5 / UART2_TXD / I2C1_SCL / PWM1_CH0
36 P4.4 / UART2_RXD / I2C1_SDA / PWM1_CH1
Sep. 1, 2020
Page 32 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML51SD1AE Pin Function
37 P4.3 / PWM2_CH0
38 P4.2 / PWM2_CH1
39 P4.1 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O
40 P4.0 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1
41 P6.3 / SPI0_SS / UART0_TXD
42 P6.2 / UART3_TXD / SPI0_CLK / UART0_RXD
43 P6.1 / UART3_RXD / SPI0_MISO
44 P6.0 / SPI0_MOSI
45 P1.4 / I2C1_SCL
46 P1.5 / I2C1_SDA
47 P1.6 / UART0_TXD
48 P1.7 / UART0_RXD
49 VSS
50 P4.6 / PWM0_CH0 / T0 / CLKO / INT0
51 VDD
52 P4.7 / T1
53 P3.3 / SPI1_SS / PWM1_CH0 / IC0 / PWM0_BRAKE
54 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 /
IC2
55
56 P3.0 / ADC_CH10 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0
57 AVDD
58 VREF
59 AVSS
60 P6.7 / ADC_CH11 / I2C1_SCL
61 P6.6 / ADC_CH12 / I2C1_SDA
62 P6.5 / ADC_CH13 / UART0_TXD
63 P6.4 / ADC_CH14 / UART0_RXD
64 P2.7 / ADC_CH15 / UART1_TXD / PWM3_CH0 / ACMP0_O
Sep. 1, 2020
Page 33 of 164
Rev 2.00
ML51/ML54/ML56
ML54SD1AE Pin Function
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6
P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1
P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0
P3.6 / PWM0_CH5 / INT1
VDD
T1 / LCD_COM0 / LCD_SEG16 / P4.7
PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3
CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0
AVDD
LQFP64
VREF
VDD
AVSS
VSS
I2C1_SCL / LCD_SEG11 / ADC_CH11 / P6.7
P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
P3.4 / LCD_SEG2 / PWM2_CH1 / T1
I2C1_SDA / LCD_V1 / LCD_SEG10 / ADC_CH12 / P6.6
UART0_TXD / LCD_V2 / LCD_SEG9 / ADC_CH13 / P6.5
UART0_RXD / LCD_V3 / LCD_SEG8 / ADC_CH14 / P6.4
ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7
P3.5 / LCD_SEG3 / PWM2_CH0 / T0
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
Figure 4.1-16 ML54SD1AE Multi-Function Pin assignment
Pin ML54SD1AE Pin Function
1
2
3
4
P2.6 / LCD_SEG6 / UART1_RXD / PWM3_CH1 / ACMP1_O
P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / LCD_COM0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0
/ INT0
P2.4 / ADC_CH1 / ACMP0_N0 / LCD_COM1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / LCD_COM2 / UART1_TXD / PWM0_CH2 /
PWM0_BRAKE
Sep. 1, 2020
Page 34 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML54SD1AE Pin Function
5
6
P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / LCD_COM3 / UART1_RXD / PWM0_CH3
P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / LCD_SEG5 / UART2_TXD / I2C1_SCL / PWM0_CH4 /
PWM3_CH0 / PWM0_BRAKE
P2.0 / ADC_CH5 / ACMP0_N1 / LCD_SEG4 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 /
PWM0_BRAKE
7
8
9
P1.3 / IC0
P1.2 / LCD_DH2 / UART3_TXD / IC1
10 P1.1 / LCD_DH1 / UART3_RXD / UART1_TXD / IC2
11 P1.0 / UART1_RXD / IC0
12 VLCD
13 P5.7 / PWM0_BRAKE / PWM0_CH4 / CLKO
14 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC
15 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT
16 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
17 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
18 P3.5 / LCD_SEG3 / PWM2_CH0 / T0
19 P3.4 / LCD_SEG2 / PWM2_CH1 / T1
20 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
21 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
22 VSS
23 VDD
24 P3.6 / PWM0_CH5 / INT1
25 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0
26 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1
27 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
28 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
29 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
30 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
31 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
32 nRESET
33 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
34 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
35 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0
Sep. 1, 2020
Page 35 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML54SD1AE Pin Function
36 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / PWM1_CH1
37 P4.3 / LCD_SEG29 / LCD_COM6 / PWM2_CH0
38 P4.2 / LCD_SEG28 / LCD_COM7 / PWM2_CH1
39 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O
40 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1
41 P6.3 / LCD_SEG25 / SPI0_SS / UART0_TXD
42 P6.2 / LCD_SEG24 / UART3_TXD / SPI0_CLK / UART0_RXD
43 P6.1 / LCD_SEG23 / UART3_RXD / SPI0_MISO
44 P6.0 / LCD_SEG22 / SPI0_MOSI
45 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4
46 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5
47 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6
48 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7
49 VSS
50 P4.6 / LCD_SEG17 / PWM0_CH0 / T0 / CLKO / INT0
51 VDD
52 P4.7 / LCD_SEG16 / LCD_COM0 / T1
53 P3.3 / LCD_SEG15 / SPI1_SS / LCD_COM1 / PWM1_CH0 / IC0 / PWM0_BRAKE
54 P3.2 / ADC_CH7 / ACMP1_N1 / LCD_SEG14 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / LCD_SEG13 / SPI1_MISO / UART3_TXD / UART0_TXD /
PWM2_CH0 / IC2
55
56 P3.0 / ADC_CH10 / LCD_SEG12 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0
57 AVDD
58 VREF
59 AVSS
60 P6.7 / ADC_CH11 / LCD_SEG11 / I2C1_SCL
61 P6.6 / ADC_CH12 / LCD_SEG10 / LCD_V1 / I2C1_SDA
62 P6.5 / ADC_CH13 / LCD_SEG9 / LCD_V2 / UART0_TXD
63 P6.4 / ADC_CH14 / LCD_SEG8 / LCD_V3 / UART0_RXD
64 P2.7 / ADC_CH15 / LCD_SEG7 / UART1_TXD / PWM3_CH0 / ACMP0_O
Sep. 1, 2020
Page 36 of 164
Rev 2.00
ML51/ML54/ML56
ML56SD1AE Pin Function
VSS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
nRESET
INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6
P5.6 / TK0 / PWM0_BRAKE / PWM0_CH1 / CLKO
P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / TK4 / STADC / PWM0_CH2 / CLKO
P0.4 / UART0_RXD / I2C0_SDA / TK5 / PWM0_CH1
P0.5 / UART0_TXD / I2C0_SCL / TK6 / PWM0_CH0
P3.6 / TK7 / PWM0_CH5 / INT1
VDD
T1 / LCD_COM0 / LCD_SEG16 / P4.7
PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3
CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0
AVDD
LQFP64
VREF
VDD
AVSS
VSS
I2C1_SCL / LCD_SEG11 / ADC_CH11 / P6.7
P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
P3.4 / LCD_SEG2 / PWM2_CH1 / T1
I2C1_SDA / LCD_V1 / LCD_SEG10 / ADC_CH12 / P6.6
UART0_TXD / LCD_V2 / LCD_SEG9 / ADC_CH13 / P6.5
UART0_RXD / LCD_V3 / LCD_SEG8 / ADC_CH14 / P6.4
ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7
P3.5 / LCD_SEG3 / PWM2_CH0 / T0
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
Figure 4.1-17 ML56SD1AE Multi-Function Pin assignment
Pin ML56SD1AE Pin Function
1
2
3
4
5
6
P2.6/LCD_SEG6/UART1_RXD/PWM3_CH1/ACMP1_O
P2.5/ADC_CH0/ACMP0_P0/ACMP1_P0/LCD_COM0/I2C0_SCL/PWM0_CH0/UART2_TXD/T0/INT0
P2.4/ADC_CH1/ACMP0_N0/LCD_COM1/I2C0_SDA/PWM0_CH1/UART2_RXD/T1/INT1
P2.3/ADC_CH2/ACMP0_P1/ACMP1_P1/I2C1_SCL/LCD_COM2/UART1_TXD/PWM0_CH2/PWM0_BRAKE
P2.2/ADC_CH3/ACMP1_N0/I2C1_SDA/LCD_COM3/UART1_RXD/PWM0_CH3
P2.1/ADC_CH4/ACMP0_P2/ACMP1_P2/LCD_SEG5/UART2_TXD/I2C1_SCL/PWM0_CH4/PWM3_CH0/PWM0_BRAK
Sep. 1, 2020
Page 37 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML56SD1AE Pin Function
E
7
8
9
P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE
P1.3/IC0
P1.2/LCD_DH2/UART3_TXD/IC1
10 P1.1/LCD_DH1/UART3_RXD/UART1_TXD/IC2
11 P1.0/UART1_RXD/IC0
12 VLCD
13 P5.7/PWM0_BRAKE/PWM0_CH4/CLKO
14 P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC
15 P5.4/UART2_TXD/PWM0_CH1/X32_OUT
16 P5.3/UART0_TXD/I2C0_SCL/XT1_IN
17 P5.2/UART0_RXD/I2C0_SDA/XT1_OUT
18 P3.5/LCD_SEG3/PWM2_CH0/T0
19 P3.4/LCD_SEG2/PWM2_CH1/T1
20 P0.7/LCD_SEG1/UART0_TXD/I2C1_SCL/PWM3_CH0/INT1
21 P0.6/LCD_SEG0/UART0_RXD/I2C1_SDA/PWM3_CH1/INT0
22 VSS
23 VDD
24 P3.6/TK7/PWM0_CH5/INT1
25 P0.5/UART0_TXD/I2C0_SCL/TK6/PWM0_CH0
26 P0.4/UART0_RXD/I2C0_SDA/TK5/PWM0_CH1
27 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO
28 P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3
29 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4
30 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5
31 P5.6/TK0/PWM0_BRAKE/PWM0_CH1/CLKO
32 nRESET
33 P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
34 P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
35 P4.5/LCD_SEG31/LCD_COM4/UART2_TXD/I2C1_SCL/PWM1_CH0
36 P4.4/LCD_SEG30/LCD_COM5/UART2_RXD/I2C1_SDA/TK12/PWM1_CH1
37 P4.3/LCD_SEG29/LCD_COM6/TK13/PWM2_CH0
38 P4.2/LCD_SEG28/LCD_COM7/TK14/PWM2_CH1
39 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O
40 P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1
Sep. 1, 2020
Page 38 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML56SD1AE Pin Function
41 P6.3/LCD_SEG25/SPI0_SS/UART0_TXD/TK8
42 P6.2/LCD_SEG24/UART3_TXD/SPI0_CLK/UART0_RXD/TK9
43 P6.1/LCD_SEG23/UART3_RXD/SPI0_MISO/TK10
44 P6.0/LCD_SEG22/SPI0_MOSI/TK11
45 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4
46 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5
47 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6
48 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7
49 VSS
50 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0
51 VDD
52 P4.7/LCD_SEG16/LCD_COM0/T1
53 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE
54 P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO
55 P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2
56 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0
57 AVDD
58 VREF
59 AVSS
60 P6.7/ADC_CH11/LCD_SEG11/I2C1_SCL
61 P6.6/ADC_CH12/LCD_SEG10/LCD_V1/I2C1_SDA
62 P6.5/ADC_CH13/LCD_SEG9/LCD_V2/UART0_TXD
63 P6.4/ADC_CH14/LCD_SEG8/LCD_V3/UART0_RXD
64 P2.7/ADC_CH15/LCD_SEG7/UART1_TXD/PWM3_CH0/ACMP0_O
Sep. 1, 2020
Page 39 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.2 LQFP48 Package
Corresponding Part Number: ML51LD1AE
ML51LD1AE Pin Function
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
VDD
P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1
T1 / P4.7
PWM0_BRAKE / IC0 / PWM1_CH0 / SPI1_SS / P3.3
CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / ADC_CH10 / P3.0
VREF
LQFP48
P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0
P0.6 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
P0.7 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
AVSS
ACMP0_O / PWM3_CH0 / UART1_TXD / ADC_CH15 / P2.7
ACMP1_O / PWM3_CH1 / UART1_RXD / P2.6
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-18 ML51LD1AE Multi-Function Pin assignment
Pin ML51LD1AE Pin Function
1
2
3
4
P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3
Sep. 1, 2020
Page 40 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML51LD1AE Pin Function
P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 /
PWM0_BRAKE
5
6
7
8
9
P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE
P1.3 / IC0
P1.2 / UART3_TXD / IC1
P1.1 / UART3_RXD / UART1_TXD / IC2
10 P1.0 / UART1_RXD / IC0
11 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC
12 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT
13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
15 P0.7 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
16 P0.6 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
17 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0
18 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1
19 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
20 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
21 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
22 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
23 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
24 nRESET
25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 P4.5 / UART2_TXD / I2C1_SCL / PWM1_CH0
28 P4.4 / UART2_RXD / I2C1_SDA / PWM1_CH1
29 P4.3 / PWM2_CH0
30 P4.2 / PWM2_CH1
31 P4.1 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O
32 P4.0 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1
33 P1.4 / I2C1_SCL
34 P1.5 / I2C1_SDA
35 P1.6 / UART0_TXD
36 P1.7 / UART0_RXD
Sep. 1, 2020
Page 41 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML51LD1AE Pin Function
37 VSS
38 P4.6 / PWM0_CH0 / T0 / CLKO / INT0
39 VDD
40 P4.7 / T1
41 P3.3 / SPI1_SS / PWM1_CH0 / IC0 / PWM0_BRAKE
42 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 /
IC2
43
44 P3.0 / ADC_CH10 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0
45 VREF
46 AVSS
47 P2.7 / ADC_CH15 / UART1_TXD / PWM3_CH0 / ACMP0_O
48 P2.6 / UART1_RXD / PWM3_CH1 / ACMP1_O
Sep. 1, 2020
Page 42 of 164
Rev 2.00
ML51/ML54/ML56
ML54LD1AE Pin Function
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6
P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
VDD
T1 / LCD_COM0 / LCD_SEG16 / P4.7
P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1
PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3
CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0
VREF
LQFP48
P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0
P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
AVSS
ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7
ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-19 ML54LD1AE Multi-Function Pin assignment
Pin ML54LD1AE Pin Function
P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / LCD_COM0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0
/ INT0
1
2
3
P2.4 / ADC_CH1 / ACMP0_N0 / LCD_COM1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / LCD_COM2 / UART1_TXD / PWM0_CH2 /
PWM0_BRAKE
Sep. 1, 2020
Page 43 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML54LD1AE Pin Function
4
5
P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / LCD_COM3 / UART1_RXD / PWM0_CH3
P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / LCD_SEG5 / UART2_TXD / I2C1_SCL / PWM0_CH4 /
PWM3_CH0 / PWM0_BRAKE
P2.0 / ADC_CH5 / ACMP0_N1 / LCD_SEG4 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 /
PWM0_BRAKE
6
7
8
9
P1.3 / IC0
P1.2 / LCD_DH2 / UART3_TXD / IC1
P1.1 / LCD_DH1 / UART3_RXD / UART1_TXD / IC2
10 VLCD
11 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC
12 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT
13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
15 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
16 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
17 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0
18 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1
19 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
20 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
21 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
22 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
23 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
24 nRESET
25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0
28 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / PWM1_CH1
29 P4.3 / LCD_SEG29 / LCD_COM6 / PWM2_CH0
30 P4.2 / LCD_SEG28 / LCD_COM7 / PWM2_CH1
31 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O
32 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1
33 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4
34 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5
Sep. 1, 2020
Page 44 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML54LD1AE Pin Function
35 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6
36 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7
37 VSS
38 P4.6 / LCD_SEG17 / PWM0_CH0 / T0 / CLKO / INT0
39 VDD
40 P4.7 / LCD_SEG16 / LCD_COM0 / T1
41 P3.3 / LCD_SEG15 / SPI1_SS / LCD_COM1 / PWM1_CH0 / IC0 / PWM0_BRAKE
42 P3.2 / ADC_CH7 / ACMP1_N1 / LCD_SEG14 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / LCD_SEG13 / SPI1_MISO / UART3_TXD / UART0_TXD /
PWM2_CH0 / IC2
43
44 P3.0 / ADC_CH10 / LCD_SEG12 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0
45 VREF
46 AVSS
47 P2.7 / ADC_CH15 / LCD_SEG7 / UART1_TXD / PWM3_CH0 / ACMP0_O
48 P2.6 / LCD_SEG6 / UART1_RXD / PWM3_CH1 / ACMP1_O
Sep. 1, 2020
Page 45 of 164
Rev 2.00
ML51/ML54/ML56
ML56LD1AE Pin Function
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6
VDD
nRESET
P5.6 / TK0 / PWM0_BRAKE / PWM0_CH1 / CLKO
P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / TK4 / STADC / PWM0_CH2 / CLKO
P0.4 / UART0_RXD / I2C0_SDA / TK5 / PWM0_CH1
T1 / LCD_COM0 / LCD_SEG16 / P4.7
PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3
CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0
VREF
LQFP48
P0.5 / UART0_TXD / I2C0_SCL / TK6 / PWM0_CH0
P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
AVSS
ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7
ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-20 ML56LD1AE Multi-Function Pin assignment
Pin ML56LD1AE/ML56LC1AE Pin Function
1
2
3
4
P2.5/ADC_CH0/ACMP0_P0/ACMP1_P0/LCD_COM0/I2C0_SCL/PWM0_CH0/UART2_TXD/T0/INT0
P2.4/ADC_CH1/ACMP0_N0/LCD_COM1/I2C0_SDA/PWM0_CH1/UART2_RXD/T1/INT1
P2.3/ADC_CH2/ACMP0_P1/ACMP1_P1/I2C1_SCL/LCD_COM2/UART1_TXD/PWM0_CH2/PWM0_BRAKE
P2.2/ADC_CH3/ACMP1_N0/I2C1_SDA/LCD_COM3/UART1_RXD/PWM0_CH3
P2.1/ADC_CH4/ACMP0_P2/ACMP1_P2/LCD_SEG5/UART2_TXD/I2C1_SCL/PWM0_CH4/PWM3_CH0/PWM0_BRAK
E
5
Sep. 1, 2020
Page 46 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML56LD1AE/ML56LC1AE Pin Function
6
7
8
9
P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE
P1.3/IC0
P1.2/LCD_DH2/UART3_TXD/IC1
P1.1/LCD_DH1/UART3_RXD/UART1_TXD/IC2
10 VLCD
11 P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC
12 P5.4/UART2_TXD/PWM0_CH1/X32_OUT
13 P5.3/UART0_TXD/I2C0_SCL/XT1_IN
14 P5.2/UART0_RXD/I2C0_SDA/XT1_OUT
15 P0.7/LCD_SEG1/UART0_TXD/I2C1_SCL/PWM3_CH0/INT1
16 P0.6/LCD_SEG0/UART0_RXD/I2C1_SDA/PWM3_CH1/INT0
17 P0.5/UART0_TXD/I2C0_SCL/TK6/PWM0_CH0
18 P0.4/UART0_RXD/I2C0_SDA/TK5/PWM0_CH1
19 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO
20 P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3
21 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4
22 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5
23 P5.6/TK0/PWM0_BRAKE/PWM0_CH1/CLKO
24 nRESET
25 P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
26 P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
27 P4.5/LCD_SEG31/LCD_COM4/UART2_TXD/I2C1_SCL/PWM1_CH0
28 P4.4/LCD_SEG30/LCD_COM5/UART2_RXD/I2C1_SDA/TK12/PWM1_CH1
29 P4.3/LCD_SEG29/LCD_COM6/TK13/PWM2_CH0
30 P4.2/LCD_SEG28/LCD_COM7/TK14/PWM2_CH1
31 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O
32 P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1
33 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4
34 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5
35 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6
36 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7
37 VSS
38 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0
39 VDD
Sep. 1, 2020
Page 47 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML56LD1AE/ML56LC1AE Pin Function
40 P4.7/LCD_SEG16/LCD_COM0/T1
41 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE
42 P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO
43 P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2
44 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0
45 VREF
46 AVSS
47 P2.7/ADC_CH15/LCD_SEG7/UART1_TXD/PWM3_CH0/ACMP0_O
48 P2.6/LCD_SEG6/UART1_RXD/PWM3_CH1/ACMP1_O
Sep. 1, 2020
Page 48 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.3 LQFP44 Package
ML54MD1AE Pin Function
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
VSS
P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6
nRESET
VDD
PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3
CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0
VREF
P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / TK4 / STADC / PWM0_CH2 / CLKO
P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
LQFP44
AVSS
ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7
ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT
Figure 4.1-21 ML54MD1AE Multi-Function Pin assignment
Pin ML54MD1AE Pin Function
P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / LCD_COM0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0
/ INT0
1
2
3
P2.4 / ADC_CH1 / ACMP0_N0 / LCD_COM1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / LCD_COM2 / UART1_TXD / PWM0_CH2 /
PWM0_BRAKE
Sep. 1, 2020
Page 49 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML54MD1AE Pin Function
4
5
P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / LCD_COM3 / UART1_RXD / PWM0_CH3
P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / LCD_SEG5 / UART2_TXD / I2C1_SCL / PWM0_CH4 /
PWM3_CH0 / PWM0_BRAKE
P2.0 / ADC_CH5 / ACMP0_N1 / LCD_SEG4 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 /
PWM0_BRAKE
6
7
8
9
P1.3 / IC0
P1.2 / LCD_DH2 / UART3_TXD / IC1
P1.1 / LCD_DH1 / UART3_RXD / UART1_TXD / IC2
10 VLCD
11 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC
12 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT
13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
15 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
16 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
17 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
18 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
19 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
20 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
21 nRESET
22 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
23 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
24 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0
25 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / PWM1_CH1
26 P4.3 / LCD_SEG29 / LCD_COM6 / PWM2_CH0
27 P4.2 / LCD_SEG28 / LCD_COM7 / PWM2_CH1
28 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O
29 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1
30 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4
31 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5
32 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6
33 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7
34 VSS
Sep. 1, 2020
Page 50 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML54MD1AE Pin Function
35 P4.6 / LCD_SEG17 / PWM0_CH0 / T0 / CLKO / INT0
36 VDD
37 P3.3 / LCD_SEG15 / SPI1_SS / LCD_COM1 / PWM1_CH0 / IC0 / PWM0_BRAKE
38 P3.2 / ADC_CH7 / ACMP1_N1 / LCD_SEG14 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / LCD_SEG13 / SPI1_MISO / UART3_TXD / UART0_TXD /
PWM2_CH0 / IC2
39
40 P3.0 / ADC_CH10 / LCD_SEG12 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0
41 VREF
42 AVSS
43 P2.7 / ADC_CH15 / LCD_SEG7 / UART1_TXD / PWM3_CH0 / ACMP0_O
44 P2.6 / LCD_SEG6 / UART1_RXD / PWM3_CH1 / ACMP1_O
Sep. 1, 2020
Page 51 of 164
Rev 2.00
ML51/ML54/ML56
ML56MD1AE Pin Function
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
VSS
P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6
nRESET
VDD
PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3
CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0
VREF
P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / TK4 / STADC / PWM0_CH2 / CLKO
P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0
P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
LQFP44
AVSS
ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7
ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT
Figure 4.1-22 ML56MD1AE Multi-Function Pin assignment
Pin ML56MD1AE Pin Function
1
2
3
4
P2.5/ADC_CH0/ACMP0_P0/ACMP1_P0/LCD_COM0/I2C0_SCL/PWM0_CH0/UART2_TXD/T0/INT0
P2.4/ADC_CH1/ACMP0_N0/LCD_COM1/I2C0_SDA/PWM0_CH1/UART2_RXD/T1/INT1
P2.3/ADC_CH2/ACMP0_P1/ACMP1_P1/I2C1_SCL/LCD_COM2/UART1_TXD/PWM0_CH2/PWM0_BRAKE
P2.2/ADC_CH3/ACMP1_N0/I2C1_SDA/LCD_COM3/UART1_RXD/PWM0_CH3
P2.1/ADC_CH4/ACMP0_P2/ACMP1_P2/LCD_SEG5/UART2_TXD/I2C1_SCL/PWM0_CH4/PWM3_CH0/PWM0_BRAK
E
5
Sep. 1, 2020
Page 52 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML56MD1AE Pin Function
6
7
8
9
P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE
P1.3/IC0
P1.2/LCD_DH2/UART3_TXD/IC1
P1.1/LCD_DH1/UART3_RXD/UART1_TXD/IC2
10 VLCD
11 P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC
12 P5.4/UART2_TXD/PWM0_CH1/X32_OUT
13 P5.3/UART0_TXD/I2C0_SCL/XT1_IN
14 P5.2/UART0_RXD/I2C0_SDA/XT1_OUT
15 P0.7/LCD_SEG1/UART0_TXD/I2C1_SCL/PWM3_CH0/INT1
16 P0.6/LCD_SEG0/UART0_RXD/I2C1_SDA/PWM3_CH1/INT0
17 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO
18 P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3
19 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4
20 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5
21 nRESET
22 P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
23 P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
24 P4.5/LCD_SEG31/LCD_COM4/UART2_TXD/I2C1_SCL/PWM1_CH0
25 P4.4/LCD_SEG30/LCD_COM5/UART2_RXD/I2C1_SDA/TK12/PWM1_CH1
26 P4.3/LCD_SEG29/LCD_COM6/TK13/PWM2_CH0
27 P4.2/LCD_SEG28/LCD_COM7/TK14/PWM2_CH1
28 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O
29 P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1
30 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4
31 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5
32 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6
33 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7
34 VSS
35 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0
36 VDD
37 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE
38 P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO
39 P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2
Sep. 1, 2020
Page 53 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML56MD1AE Pin Function
40 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0
41 VREF
42 AVSS
43 P2.7/ADC_CH15/LCD_SEG7/UART1_TXD/PWM3_CH0/ACMP0_O
44 P2.6/LCD_SEG6/UART1_RXD/PWM3_CH1/ACMP1_O
Sep. 1, 2020
Page 54 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.4 QFN33 Package
ML51TD1AE Pin Function
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
VDD
nRESET
Top transparent view
P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
PWM0_BRAKE / IC0 / PWM1_CH0 / SPI1_SS / P3.3
CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / ADC_CH10 / P3.0
QFN33
33 VSS
VREF
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-23 ML51TD1AE Multi-Function Pin assignment
Pin ML56TD1AE Pin Function
1
2
3
4
P2.5/ADC_CH0/ACMP0_P0/ACMP1_P0/LCD_COM0/I2C0_SCL/PWM0_CH0/UART2_TXD/T0/INT0
P2.4/ADC_CH1/ACMP0_N0/LCD_COM1/I2C0_SDA/PWM0_CH1/UART2_RXD/T1/INT1
P2.3/ADC_CH2/ACMP0_P1/ACMP1_P1/I2C1_SCL/LCD_COM2/UART1_TXD/PWM0_CH2/PWM0_BRAKE
P2.2/ADC_CH3/ACMP1_N0/I2C1_SDA/LCD_COM3/UART1_RXD/PWM0_CH3
P2.1/ADC_CH4/ACMP0_P2/ACMP1_P2/LCD_SEG5/UART2_TXD/I2C1_SCL/PWM0_CH4/PWM3_CH0/PWM0_BRAK
E
5
6
P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE
Sep. 1, 2020
Page 55 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML56TD1AE Pin Function
7
8
9
P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC
P5.4/UART2_TXD/PWM0_CH1/X32_OUT
P5.3/UART0_TXD/I2C0_SCL/XT1_IN
10 P5.2/UART0_RXD/I2C0_SDA/XT1_OUT
11 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO
12 P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3
13 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4
14 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5
15 P5.6/TK0/PWM0_BRAKE/PWM0_CH1/CLKO
16 nRESET
17 P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
18 P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
19 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O
20 P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1
21 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4
22 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5
23 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6
24 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7
25 VSS
26 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0
27 VDD
28 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE
29 P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO
30 P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2
31 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0
32 VREF
33 VSS
Sep. 1, 2020
Page 56 of 164
Rev 2.00
ML51/ML54/ML56
ML51TC0AE / ML51TB9AE Pin Function
25
16
15
14
13
12
11
10
9
VSS
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
nRESET
Top transparent view
26
27
28
29
30
31
32
P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
VDD
P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
PWM0_BRAKE / IC0 / SPI1_SS / P3.3
CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / UART0_RXD / SPI1_MOSI / P3.0
AVDD
QFN33
33 VSS
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-24 ML51TC0AE / ML51TB9AE Multi-Function Pin Assignment
Pin ML51TC0AE / ML51TB9AE Pin Function
1
2
3
4
5
P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3
P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE
Sep. 1, 2020
Page 57 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML51TC0AE / ML51TB9AE Pin Function
6
7
8
9
P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE
P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC
P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
10 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
11 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
12 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
13 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4
14 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5
15 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
16 nRESET
17 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
18 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
19 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O
20 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1
21 P1.4 / I2C1_SCL
22 P1.5 / I2C1_SDA
23 P1.6 / UART0_TXD
24 P1.7 / UART0_RXD
25 VSS
26 P4.6 / PWM0_CH0 / T0 / CLKO / INT0
27 VDD
28 P3.3 / SPI1_SS / IC0 / PWM0_BRAKE
29 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO
30 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2
31 P3.0 / SPI1_MOSI / UART0_RXD / IC0
32 AVDD
33 VSS
Sep. 1, 2020
Page 58 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.5 LQFP32 Package
ML51PC0AE / ML51PB9AE Pin Function
25
VSS
16
15
14
13
12
11
10
9
nRESET
26
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
27
VDD
P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5
P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4
P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
28
PWM0_BRAKE / IC0 / SPI1_SS / P3.3
LQFP32
29
CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2
30
IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
31
IC0 / UART0_RXD / SPI1_MOSI / P3.0
32
AVDD
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-25 ML51PC0AE / ML51PB9AE Multi-Function Pin Assignment
Pin ML51PC0AE Pin Function
1
2
3
4
P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3
Sep. 1, 2020
Page 59 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML51PC0AE Pin Function
5
6
7
8
9
P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE
P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE
P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC
P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
10 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
11 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
12 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
13 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4
14 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5
15 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO
16 nRESET
17 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
18 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
19 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O
20 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1
21 P1.4 / I2C1_SCL
22 P1.5 / I2C1_SDA
23 P1.6 / UART0_TXD
24 P1.7 / UART0_RXD
25 VSS
26 P4.6 / PWM0_CH0 / T0 / CLKO / INT0
27 VDD
28 P3.3 / SPI1_SS / IC0 / PWM0_BRAKE
29 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO
30 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2
31 P3.0 / SPI1_MOSI / UART0_RXD / IC0
32 AVDD
Sep. 1, 2020
Page 60 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.6 TSSOP28 Package
ML51EC0AE / ML51EB9AE Pin Function
1
2
28
27
26
25
I2C1_SCL / P1.4
P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1
I2C1_SDA / P1.5
P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O
3
UART0_TXD / P1.6
P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
4
UART0_RXD / P1.7
VSS
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
5
24 nRESET
6
23 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5
22 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4
21 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
20 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
VDD
7
CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / UART0_RXD / SPI1_MOSI / P3.0
8
9
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
10
11
12
13
14
19
18
17
16
15
AVDD
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5
INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4
PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3
P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE
P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE
P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3
Figure 4.1-26 ML51EC0AE / ML51EB9AE Multi-Function Pin Assignment
Pin ML51EC0AE / ML51EB9AE Pin Function
1
2
3
4
5
6
7
8
9
P1.4 / I2C1_SCL
P1.5 / I2C1_SDA
P1.6 / UART0_TXD
P1.7 / UART0_RXD
VSS
P4.6 / PWM0_CH0 / T0 / CLKO / INT0
VDD
P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2
10 P3.0 / SPI1_MOSI / UART0_RXD / IC0
11 AVDD
12 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
13 P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
14 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
15 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3
16 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE
17 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE
18 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
19 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
20 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
21 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
Sep. 1, 2020
Page 61 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML51EC0AE / ML51EB9AE Pin Function
22 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4
23 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5
24 nRESET
25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O
28 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1
Sep. 1, 2020
Page 62 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.7 SOP28 Package
Corresponding Part Number: ML51UC0AE / ML51UB9AE
1
2
28
27
26
25
I2C1_SCL / P1.4
P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1
I2C1_SDA / P1.5
P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O
3
UART0_TXD / P1.6
P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
4
UART0_RXD / P1.7
VSS
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
5
24 nRESET
6
23 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5
22 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4
21 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
20 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
VDD
7
CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / UART0_RXD / SPI1_MOSI / P3.0
8
9
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
10
11
12
13
14
19
18
17
16
15
AVDD
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5
INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4
PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3
P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE
P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE
P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3
Figure 4.1-27 ML51UC0AE / ML51UB9AE Multi Function Pin Assignment
ML51UC0AE / ML51UB9AE Pin Function
Pin ML51UC0AE / ML51UB9AE Pin Function
1
2
3
4
5
6
7
8
9
P1.4 / I2C1_SCL
P1.5 / I2C1_SDA
P1.6 / UART0_TXD
P1.7 / UART0_RXD
VSS
P4.6 / PWM0_CH0 / T0 / CLKO / INT0
VDD
P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2
10 P3.0 / SPI1_MOSI / UART0_RXD / IC0
11 AVDD
12 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
13 P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
14 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
15 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3
16 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE
17 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE
18 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
19 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
20 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
Sep. 1, 2020
Page 63 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML51UC0AE / ML51UB9AE Pin Function
21 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
22 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4
23 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5
24 nRESET
25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O
28 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1
Sep. 1, 2020
Page 64 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.8 TSSOP20 Package
ML51FB9AE Pin Function
1
2
20
19
18
VSS
P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
VDD
P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
nRESET
3
CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / UART0_RXD / SPI1_MOSI / P3.0
4
17 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5
5
16 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4
6
15 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
14 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
AVDD
7
INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC_CH0 / P2.5
INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC_CH1 / P2.4
PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC_CH2 / P2.3
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
8
13
12
11
9
P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3
10
Figure 4.1-28 ML51FB9AE Multi Function Pin Assignment
Pin ML51FB9AE Pin Function
1
2
3
4
5
6
7
8
9
VSS
P4.6 / PWM0_CH0 / T0 / CLKO / INT0
VDD
P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2
P3.0 / SPI1_MOSI / UART0_RXD / IC0
AVDD
P2.5 / ADC_CH0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
P2.4 / ADC_CH1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
10 P2.3 / ADC_CH2 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
11 P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3
12 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
13 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
14 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
15 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
16 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4
17 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5
18 nRESET
19 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
20 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
Sep. 1, 2020
Page 65 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.9 SOP20 Package
ML51OB9AE Pin Function
1
2
20
19
18
VSS
P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
VDD
P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
nRESET
3
CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2
IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / UART0_RXD / SPI1_MOSI / P3.0
4
17 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5
5
16 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4
6
15 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
14 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
AVDD
7
INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC_CH0 / P2.5
INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC_CH1 / P2.4
PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC_CH2 / P2.3
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
8
13
12
11
9
P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3
10
Figure 4.1-29 ML51OB9AE Multi Function Pin Assignment
Pin ML51OB9AE Pin Function
1
2
3
4
5
6
7
8
9
VSS
P4.6 / PWM0_CH0 / T0 / CLKO / INT0
VDD
P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2
P3.0 / SPI1_MOSI / UART0_RXD / IC0
AVDD
P2.5 / ADC_CH0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
P2.4 / ADC_CH1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
10 P2.3 / ADC_CH2 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
11 P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3
12 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
13 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
14 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
15 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
16 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4
17 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5
18 nRESET
19 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
20 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
Sep. 1, 2020
Page 66 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.10 QFN20 Package
ML51XB9AE Pin Function
Top transparent view
16
17
18
19
20
10
9
VSS
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
VDD
nRESET
P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5
QFN
20
8
P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4
7
IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / UART0_RXD / SPI1_MOSI / P3.0
P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
N/C
6
Figure 4.1-30 ML51XB9AE Multi Function Pin Assignment
Pin ML51XB9AE Pin Function
1
2
3
4
5
6
7
8
P2.5 / ADC_CH0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
P2.4 / ADC_CH1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
P2.3 / ADC_CH2 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3
P2.1 / ADC_CH4 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE
P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4
Sep. 1, 2020
Page 67 of 164
Rev 2.00
ML51/ML54/ML56
Pin ML51XB9AE Pin Function
P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5
9
10 nRESET
11 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
12 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
13 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O
14 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1
15 P1.7 / UART0_RXD
16 VSS
17 P4.6 / PWM0_CH0 / T0 / CLKO / INT0
18 VDD
19 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2
20 P3.0 / SPI1_MOSI / UART0_RXD / IC0
Sep. 1, 2020
Page 68 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.11 TSSOP14 Package
ML51DB9AE Pin Function
1
2
3
4
5
6
7
14
13
12
11
10
9
VSS
P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
VDD
P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
nRESET
IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1
IC0 / UART0_RXD / SPI1_MOSI / P3.0
P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC_CH0 / P2.5
INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC_CH1 / P2.4
8
Figure 4.1-31 ML51DB9AE Multi Function Pin Assignment
Pin ML51DB9AE Pin Function
1
2
3
4
5
6
7
8
9
VSS
P4.6 / PWM0_CH0 / T0 / CLKO / INT0
VDD
P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2
P3.0 / SPI1_MOSI / UART0_RXD / IC0
P2.5 / ADC_CH0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0
P2.4 / ADC_CH1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1
P5.3 / UART0_TXD / I2C0_SCL / XT1_IN
P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT
10 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2
11 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
12 nRESET
13 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
14 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
Sep. 1, 2020
Page 69 of 164
Rev 2.00
ML51/ML54/ML56
4.1.2.12 MSOP10 Package
ML51BB9AE Pin Function
ICE_CLK / UART0_RXD / I2C1_SDA / UART1_RXD / P5.1
1
2
3
4
5
10
9
P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
VSS
INT0 / CLKO / T0 / PWM0_CH0 / P4.6
nRESET
8
P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5
P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4
P2.0 / ADC_CH5 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE
VDD
7
PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC_CH2 / P2.3
6
Figure 4.1-32 ML51BB9AE Pin Assignment
Pin ML51BB9AE Pin Function
1
2
3
4
5
6
7
8
9
P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
VSS
P4.6 / PWM0_CH0 / T0 / CLKO / INT0
VDD
P2.3 / ADC_CH2 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE
P2.0 / ADC_CH5 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE
P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4
P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5
nRESET
10 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
Sep. 1, 2020
Page 70 of 164
Rev 2.00
ML51/ML54/ML56
4.2 Pin Description
4.2.1
ML51/ML54/ML56 Series Pin Mapping
ML54/ML56
ML51
Pin Number
64
48
44
64
48
33/32
28
20
QFN20
14
10
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.3
P1.2
P1.1
P1.0
VLCD
P3.7
P5.7
P5.5
P5.4
P5.3
P5.2
P3.5
P3.4
P0.7
P0.6
1
2
48
1
2
3
4
5
6
7
8
9
44
1
2
3
4
5
6
7
8
9
1
2
48
1
1
2
3
4
5
6
12
13
14
15
16
17
8
9
1
2
3
4
5
6
7
3
3
2
4
4
3
10
11
5
6
5
5
4
6
6
5
7
7
6
8
8
7
9
9
8
10
11
12
10
11
9
10
10
10
12
13
14
15
16
17
18
19
20
21
13
14
15
16
17
18
19
20
21
11
12
13
14
11
12
13
14
11
12
13
14
7
8
9
18
19
12
13
8
9
10
15
16
15
16
15
16
VSS
VDD
22
23
22
23
33
P3.6
P0.5
24
25
26
27
28
29
30
31
32
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
17
18
19
20
21
22
23
24
P0.4
P0.3
17
18
19
20
11
12
13
14
15
16
20
21
22
23
14
15
16
17
6
7
8
9
10
11
P0.2
P0.1
7
8
P0.0
P5.6
nRESET
21
24
18
10
12
9
Sep. 1, 2020
Page 71 of 164
Rev 2.00
ML51/ML54/ML56
ML54/ML56
48
ML51
Pin Number
64
44
64
48
33/32
28
20
QFN20
14
10
P5.0
P5.1
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
P6.3
P6.2
P6.1
P6.0
P1.4
P1.5
P1.6
P1.7
VSS
P4.6
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
25
26
27
28
29
30
31
32
22
23
24
25
26
27
28
29
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
25
26
27
28
29
30
31
32
17
18
25
26
19
20
11
12
13
14
10
1
19
20
27
28
13
14
33
34
35
36
37
38
30
31
32
33
34
35
33
34
35
36
37
38
21
22
23
24
25
26
1
2
3
4
5
6
15
16
17
1
2
1
2
2
3
VDD
51
39
36
51
39
27
7
3
18
3
4
P4.7
P3.3
P3.2
P3.1
P3.0
52
53
54
55
56
40
41
42
43
44
52
53
54
55
56
40
41
42
43
44
37
38
39
40
28
29
30
31
8
9
4
5
6
19
20
4
5
10
AVDD
VREF
AVSS
57
58
59
39
45
46
36
41
42
57
58
59
39
45
46
27
32
7
11
7
16
P6.7
P6.6
P6.5
P6.4
P2.7
60
61
62
63
64
60
61
62
63
64
47
43
47
Sep. 1, 2020
Page 72 of 164
Rev 2.00
ML51/ML54/ML56
4.2.2
ML51/ML54/ML56 Series Pin Functional Description
As default all GPIO type is defined as input mode. User should setting the GPIO Mode by PxMx
register.
A: Analog suggest disable digial function O: output, I: input, I/O: bi-direction (Quasi)
Group
Pin Name
ACMP0_N0
Type
Description
Analog comparator 0 negative input 0 pin.
Analog comparator 0 negative input 1 pin.
Analog comparator 0 output pin.
Analog comparator 0 positive input 0 pin.
Analog comparator 0 positive input 1 pin.
Analog comparator 0 positive input 2 pin.
Analog comparator 0 positive input 3 pin.
Analog comparator 1 negative input 0 pin.
Analog comparator 1 negative input 1 pin.
Analog comparator 1 output pin.
Analog comparator 1 positive input 0 pin.
Analog comparator 1 positive input 1 pin.
Analog comparator 1 positive input 2 pin.
Analog comparator 1 positive input 3 pin.
ADC_ channel analog input.
A
ACMP0_N1
ACMP0_O
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_P3
ACMP1_N0
ACMP1_N1
ACMP1_O
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
ADC_CH0
ADC_CH1
ADC_CH2
ADC_CH3
ADC_CH4
ADC_CH5
ADC_CH6
ADC_CH7
ADC_CH10
ADC_CH11
ADC_CH12
ADC_CH13
ADC_CH14
ADC_CH15
CLKO
O
ACMP0
A
A
O
ACMP1
A
ADC_ channel analog input.
ADC_ channel analog input.
ADC_ channel analog input.
ADC_ channel analog input.
ADC_ channel analog input.
ADC_ channel analog input.
ADC
A
ADC_ channel analog input.
ADC_ channel analog input.
ADC_ channel analog input.
ADC_ channel analog input.
ADC_ channel analog input.
ADC_ channel analog input.
ADC_ channel analog input.
CLKO
I2C0
O
Clock Out
I2C0_SCL
I/O
I2C0 clock pin.
Sep. 1, 2020
Page 73 of 164
Rev 2.00
ML51/ML54/ML56
Group
Pin Name
I2C0_SDA
Type
I/O
Description
I2C0 data input/output pin.
I2C1 clock pin.
I2C1_SCL
I2C1_SDA
IC0
I/O
I2C1
I/O
I2C1 data input/output pin.
Input Capture channel 0
Input Capture channel 1
Input Capture channel 2
IC0
IC1
IC2
I/O
IC1
I/O
IC2
I/O
Serial wired debugger clock pin.
ICE_CLK
ICE_DAT
I
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_CLK pin
ICE
Serial wired debugger data pin.
O
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_DAT pin
INT0
INT1
INT0
I
External interrupt 0 input pin.
External interrupt 1 input pin.
LCD Common 0 output.
LCD Common 1 output.
LCD Common 2 output.
LCD Common 3 output.
LCD Common 4 output.
LCD Common 5 output.
LCD Common 6 output.
LCD Common 7 output.
LCD external capacitor pin of charge pump circuit.
LCD external capacitor pin of charge pump circuit.
LCD segment 0 output
INT1
I
LCD_COM0
LCD_COM1
LCD_COM2
LCD_COM3
LCD_COM4
LCD_COM5
LCD_COM6
LCD_COM7
LCD_DH1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD_DH2
LCD_SEG0
LCD_SEG1
LCD_SEG2
LCD_SEG3
LCD_SEG4
LCD_SEG5
LCD_SEG6
LCD_SEG7
LCD_SEG8
LCD_SEG9
LCD_SEG10
LCD_SEG11
LCD
LCD segment 1 output
LCD segment 2 output
LCD segment 3 output
LCD segment 4 output
LCD segment 5 output
LCD segment 6 output
LCD segment 7 output
LCD segment 8 output
LCD segment 9 output
LCD segment 10 output
LCD segment 11 output
Sep. 1, 2020
Page 74 of 164
Rev 2.00
ML51/ML54/ML56
Group
Pin Name
LCD_SEG12
Type
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Description
LCD segment 12 output
LCD segment 13 output
LCD segment 14 output
LCD segment 15 output
LCD segment 16 output
LCD segment 17 output
LCD segment 18 output
LCD segment 19 output
LCD segment 20 output
LCD segment 21 output
LCD segment 22 output
LCD segment 23 output
LCD segment 24 output
LCD segment 25 output
LCD segment 26 output
LCD segment 27 output
LCD segment 28 output
LCD segment 29 output
LCD segment 30 output
LCD segment 31 output
LCD_SEG13
LCD_SEG14
LCD_SEG15
LCD_SEG16
LCD_SEG17
LCD_SEG18
LCD_SEG19
LCD_SEG20
LCD_SEG21
LCD_SEG22
LCD_SEG23
LCD_SEG24
LCD_SEG25
LCD_SEG26
LCD_SEG27
LCD_SEG28
LCD_SEG29
LCD_SEG30
LCD_SEG31
LCD_V1
Input pin of the 1st most positive LCD level.
Input pin of the 2nd most positive LCD level.
Input pin of the 3rd most positive LCD level.
LCD_V2
I
LCD_V3
I
External reset input: active LOW, with an internal pull-up. Set this
pin low reset to initial state.
nRESET
nRESET
I
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF
capacitor on nRESET pin.
PWM0_BRAKE
PWM0_CH0
PWM0_CH1
PWM0_CH2
PWM0_CH3
PWM0_CH4
PWM0_CH5
PWM1_CH0
PWM1_CH1
I
PWM0 Brake input pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PWM0 channel 0 output/capture input.
PWM0 channel 1 output/capture input.
PWM0 channel 2 output/capture input.
PWM0 channel 3 output/capture input.
PWM0 channel 4 output/capture input.
PWM0 channel 5 output/capture input.
PWM1 channel 0 output/capture input.
PWM1 channel 1 output/capture input.
PWM0
PWM1
Sep. 1, 2020
Page 75 of 164
Rev 2.00
ML51/ML54/ML56
Group
Pin Name
PWM2_CH0
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
PWM2 channel 0 output/capture input.
PWM2 channel 1 output/capture input.
PWM3 channel 0 output/capture input.
PWM3 channel 1 output/capture input.
SPI0 serial clock pin.
PWM2
PWM2_CH1
PWM3_CH0
PWM3_CH1
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_SS
SPI1_CLK
SPI1_MISO
SPI1_MOSI
SPI1_SS
STADC
T0
PWM3
SPI0
SPI0 MISO (Master In, Slave Out) pin.
SPI0 MOSI (Master Out, Slave In) pin.
SPI0 slave select pin.
SPI1 serial clock pin.
SPI1 MISO (Master In, Slave Out) pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 slave select pin.
SPI1
STADC
T0
ADC external trigger input.
External count input to Timer/Counter 0 or its toggle output.
External count input to Timer/Counter 1 or its toggle output.
Touch Key 0.
I/O
I/O
A
T1
T1
TK0
TK1
A
Touch Key 1.
TK2
A
Touch Key 2.
TK3
A
Touch Key 3.
TK4
A
Touch Key 4.
TK5
A
Touch Key 5.
TK6
A
Touch Key 6.
TK
TK7
A
Touch Key 7.
TK8
A
Touch Key 8.
TK9
A
Touch Key 9.
TK10
A
Touch Key 10.
TK11
A
Touch Key 11.
TK12
A
Touch Key 12.
TK13
A
Touch Key 13.
TK14
A
Touch Key 14.
UART0_RXD
UART0_TXD
UART1_RXD
UART1_TXD
UART2_RXD
I
UART0 data receiver input pin.
UART0 data transmitter output pin.
UART1 data receiver input pin.
UART1 data transmitter output pin.
UART2 data receiver input pin.
UART0
O
I
UART1
UART2
O
I
Sep. 1, 2020
Page 76 of 164
Rev 2.00
ML51/ML54/ML56
Group
Pin Name
UART2_TXD
Type
Description
UART2 data transmitter output pin.
O
I
UART3_RXD
UART3_TXD
UART3 data receiver input pin.
UART3 data transmitter output pin.
ADC reference voltage input.
UART3
VREF
O
VREF
A
Note: This pin needs to be connected with a 1uF capacitor when
use internal voltage reference output.
X32_IN
I
External 32.768 kHz crystal input pin.
X32
XT1
X32_OUT
XT1_IN
O
I
External 32.768 kHz crystal output pin.
External 4~24 MHz (high speed) crystal input pin.
External 4~24 MHz (high speed) crystal output pin.
XT1_OUT
O
Sep. 1, 2020
Page 77 of 164
Rev 2.00
ML51/ML54/ML56
5 BLOCK DIAGRAM
5.1 ML51/ML54/ML56 Series Full Function Block
1T High
Performance
8051 Core
Power
Management
VDD
VSS
POR / LVR / BOD
T0
T1
Max. 64KB
APROM Flash
Memory
Access
Timer 0/1
Timer 2 with
Input Capture
3
ICAP0~2
Max. 4KB
LDROM Flash
Timer 3
Max. Bytes
Data Flash
(page: 128B)
Digital
Peripheral
Self Wake-up
Timer
256 bytes
Internal RAM
Watchdog Timer
UART0_TXD
UART0_RXD
UART1_TXD
UART1_RXD
UART2_TXD
UART2_RXD
UART3_TXD
UART3_RXD
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
4 Kbytes XRAM
(Auxiliary RAM)
Serial Ports
(UART 0/1)
Smart Card/
Series Ports
(UART 2/3)
PDMA with CRC
8
8
P0[7:0]
P0
P1
P2
P3
P4
P5
P6
I2C0/1
SPI0
SPI1
P1[7:0]
P2[7:0]
SPI0_MOSI
SPI0_MISO
SPI0_SS
SPI0_SCK
SPI1_MOSI
SPI1_MISO
8
GPIO
SPI1_SS
SPI1_SCK
8
8
P3[7:0]
P4[7:0]
6
PWM0CH0~5
PWM1/2/3CH0~1
FB0
6
PWM0/1/2/3
RTC
8
8
P5[7:0]
P6[7:0]
15
AIN0~7, 9~15
STADC
12-bit ADC
Analog
Peripheral
8
Any Port
GPIO Interrupt
Internal VREF
External VREF
INT0
INT1
External Interrupt
ACMP0_P
ACMP0_N
ACMP1_P
ACMP1_N
ACMP 0/1
LCD
4/6/8
15
COM
Touch key
32/30/28
TK0~14
SEG
System Clock
24 MHz Internal
RC Oscillator
(HIRC)
4-24 MHz
Oscillator Circuit
(HXT)
XIN
XOUT
System Clock
Source
Clock Divider
38.4 kHz Internal
RC Oscillator
(LIRC)
32768 Hz
Oscillator Circuit
(LXT)
X32IN
X32OUT
Figure 5.1-1 Functional Block Diagram
Sep. 1, 2020
Page 78 of 164
Rev 2.00
ML51/ML54/ML56
6 FUNCTIONAL DESCRIPTION
6.1 Memory Organization
A standard 80C51 based microcontroller divides the memory into two different sections, Program
Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the
Data Memory is used to store data or variations during the program execution.
The Data Memory occupies a separate address space from Program Memory. In ML51/ML54/ML56
Series, there are 256 bytes of internal scratch-pad RAM. For many applications those need more
internal RAM, the ML51/ML54/ML56 Series provides another on-chip 4 Kbytes of RAM, which is called
XRAM, accessed by MOVX instruction.
The whole embedded Flash, functioning as Program Memory, is divided into three blocks: Application
ROM (APROM) normally for User Code, Loader ROM (LDROM) normally for Boot Code, and CONFIG
bytes for hardware initialization. Actually, APROM and LDROM function in the same way but have
different size. Each block is accumulated page by page and the page size is 128 bytes. The Flash
control unit supports Erase, Program, and Read modes. The external writer tools though specific I/O
pins, In-Application-Programming (IAP), or In-System-Programming (ISP) can both perform these
modes.
Sep. 1, 2020
Page 79 of 164
Rev 2.00
ML51/ML54/ML56
6.2 System Manager
The ML51/ML54/ML56 Series has a wide variety of clock sources and selection features that allow it
to be used in a wide range of applications while maximizing performance and minimizing power
consumption. The ML51/ML54/ML56 Series provides five options of the system clock sources
including internal oscillator, crystal/resonator, or external clock from XIN pin via software. The
ML51/ML54/ML56 Series is embedded with two internal oscillators: one 38.4 kHz low-speed and one
24 MHz high-speed, which is factory trimmed to ±2% under all conditions. A clock divider CKDIV is
also available on ML51/ML54/ML56 Series for adjustment of the flexibility between power
consumption and operating performance.
32.768 kHz
Oscillating
Circuit
FLXT
X32OUT
X32IN
111
110
FHXT
4~24 MHz
Oscillating
Circuit
Flash
Memory
XOUT
XIN
10X
01X
00X
FECLK
Clock
Filter
Clock
Divider
FOSC
FSYS
CPU
FHIRC
24 MHz Internal
Oscillator[1]
CKDIV
Peripherals
CLO
OSC[2:0]
(CKSWT[2:0])
38.4 kHz
Internal
Oscillator
FLIRC
Watchdog
Timer
CLOEN
(CKCON.1)
Self
Wake-up
Timer
0
1
WKTCK
(WKCON.5)
[1] Default system clock source after power-on
Figure 6.2-1 Clock System Block Diagram
Sep. 1, 2020
Page 80 of 164
Rev 2.00
ML51/ML54/ML56
6.3
Flash Memory Control
6.3.1
In-application-programming (IAP)
Unlike RAM’s real-time operation, to update Flash data often takes long time. Furthermore, it is a quite
complex timing procedure to erase, program, or read Flash data. The ML51/ML54/ML56 Series
carried out the Flash operation with convenient mechanism to help user re-programming the Flash
content by In-Application-Programming (IAP). IAP is an in-circuit electrical erasure and programming
method through software.
After IAP enabling by setting IAPEN (CHPCON.0 with TA protected) and setting the enable bit in
IAPUEN that allows the target block to be updated, user can easily fill the 16-bit target address in
IAPAH and IAPAL, data in IAPFD, and command in IAPCN. Then the IAP is ready to begin by setting
a triggering bit IAPGO (IAPTRG.0). Note that IAPTRG is also TA protected. At this moment, the CPU
holds the Program Counter and the built-in IAP automation takes over to control the internal charge-
pump for high voltage and the detail signal timing. The erase and program time is internally controlled
disregard of the operating voltage and frequency. Nominally, a page-erase time is 5 ms and a byte-
program time is 23.5 μs. After IAP action completed, the Program Counter continues to run the
following instructions. The IAPGO bit will be automatically cleared. An IAP failure flag, IAPFF
(CHPCON.6), can be check whether the previous IAP operation was successful or not. Through this
progress, user can easily erase, program, and verify the Flash Memory by just taking care of pure
software.
6.3.2
In-Circuit-Programming (ICP)
The Flash Memory can be programmed by “In-Circuit-Programming” (ICP). If the product is just under
development or the end product needs firmware updating in the hand of an end customer, the
hardware programming mode will make repeated programming difficult and inconvenient. ICP method
makes it easy and possible without removing the microcontroller from the system. ICP mode also
allows customers to manufacture circuit boards with un-programmed devices. Programming can be
done after the assembly process allowing the device to be programmed with the most recent firmware
or a customized firmware.
̅̅̅̅̅̅
̅̅̅̅̅̅
There are three signal pins, RST, ICPDA, and ICPCK, involved in ICP function. RST is used to enter
or exit ICP mode. ICPDA is the data input and output pin. ICPCK is the clock input pin, which
synchronizes the data shifted in to or out from MCU under programming. User should leave these
three pins plus VDD and GND pins on the circuit board to make ICP possible.
Nuvoton provides ICP tool for ML51/ML54/ML56 Series, which enables user to easily perform ICP
through Nuvoton ICP programmer. The ICP programmer developed by Nuvoton has been optimized
according to the electric characteristics of MCU. It also satisfies the stability and efficiency during
production progress. For more details, please visit Nuvoton 8-bit Microcontroller website: Nuvoton
80C51 Microcontroller Technical Support.
6.3.3
On-Chip-Debugger (ICE)
The ML51/ML54/ML56 Series is embedded in an on-chip-debugger (OCD) providing developers with a
low cost method for debugging user code, which is available on each package. The OCD gives debug
capability of complete program flow control with eight hardware address breakpoints, single step, free
running, and non-intrusive commands for memory access. The OCD system does not occupy any
locations in the memory map and does not share any on-chip peripherals.
Sep. 1, 2020
Page 81 of 164
Rev 2.00
ML51/ML54/ML56
6.4 GPIO Port Structure and Operation
6.4.1 GPIO Mode
The ML51/ML54/ML56 Series has a maximum of 56 general purpose I/O pins which 40 bit-
addressable general I/O pins grouped as 5 ports, P0 to P4, and 16 general I/O pins grouped as P5
and P6. Each port has its port control register (Px register). The writing and reading of a port control
register have different meanings. A write to port control register sets the port output latch logic value,
where as a read gets the port pin logic state. These four modes are quasi-bidirectional (standard 8051
port structure), push-pull, input-only, and open-drain modes. Each port spends two special function
registers PxM1 and PxM2 to select the I/O mode of port Px. The list below illustrates how to select the
I/O mode of Px.n. Note that the default configuration of is input-only (high-impedance) after any reset.
PnM1.X[1]
PnM2.X[1]
I/O Type
0
0
1
0
1
0
1
Quasi-bidirectional
Push-pull
Input-only (high-impedance)
Open-drain
1
Note: N = 0~5, x = 0~7
Table 6.4-1 Configuration for Different I/O Modes
All I/O pins can be selected as TTL level inputs or Schmitt triggered inputs by selecting corresponding
bit in PxS register. Schmitt triggered input has better glitch suppression capability. All I/O pins also
have bit-controllable, slew rate select ability via software. The Register Description are PxSR. By
default, the slew rate is slow. If user would like to increase the I/O output speed, setting the
corresponding bit in PxSR, the slew rate is selected in a faster level.
Sep. 1, 2020
Page 82 of 164
Rev 2.00
ML51/ML54/ML56
6.5 Timer
6.5.1 Overview
ML51/ML54/ML56 Series provides following 16-bit Timer. Two 16-bit Timers/Counters 0 and 1
compatible with standard 8051. One 16-bit Timer 2 with three-channel input capture module and 9
input pin can be selected. One 16-bit auto-reload Timer 3, which can be the baud rate clock source of
UARTs.
Sep. 1, 2020
Page 83 of 164
Rev 2.00
ML51/ML54/ML56
6.6 Watchdog Timer (WDT)
The ML51/ML54/ML56 Series provides one Watchdog Timer (WDT). It can be configured as a time-
out reset timer to reset whole device. Once the device runs in an abnormal status or hangs up by
outward interference, a WDT reset recover the system. It provides a system monitor, which improves
the reliability of the system. Therefore, WDT is especially useful for system that is susceptible to noise,
power glitches, or electrostatic discharge. The WDT also can be configured as a general purpose
timer, of which the periodic interrupt serves as an event timer or a durational system supervisor in a
monitoring system, which is able to operate during Idle or Power-down mode. WDTEN[3:0]
(CONFIG4[7:4]) initialize the WDT to operate as a time-out reset timer or a general purpose timer.
1
The Watchdog time-out interval is determined by the formula
, where
× 64
F
LIRC × clockdividerscalar
FLIRC is the frequency of internal 38.4 kHz oscillator. The following table shows an example of the
Watchdog time-out interval with different pre-scales.
WDPS.3
WDPS.2
WDPS.1
WDPS.0
Clock Divider Scale
WDT Time-Out Timing[1]
1.66 ms
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1/1
1/4
6.64 ms
1/8
13.31 ms
1/16
26.62 ms
1/32
53.25 ms
1/64
106.66 ms
213.12 ms
426.64 ms
853.28ms
1/128
1/256
1/512
1/1024
1/2048
1/2048
1706.56ms
3413.12ms
3413.12ms
Others
Note: This is an approximate value since the deviation of LIRC.
Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars
Since the limitation of the maxima vaule of WDT timer delay. To wake up ML51/ML54/ML56 Series
from idle mode or power down mode suggest use WKT function see Chapter 6.7 .
The WDT is implemented with a set of divider that divides the low-speed internal oscillator clock
nominal 38.4 kHz. The divider output is selectable and determines the time-out interval. When the
time-out interval is fulfilled, it will wake the system up from Idle or Power-down mode and an interrupt
event will occur if WDT interrupt is enabled. If WDT is initialized as a time-out reset timer, a system
reset will occur after a period of delay if without any software action.
Sep. 1, 2020
Page 84 of 164
Rev 2.00
ML51/ML54/ML56
6.7 Self Wake-up Timer (WKT)
6.7.1 Overview
The ML51/ML54/ML56 Series has a dedicated Self Wake-up Timer (WKT), which serves for a periodic
wake-up timer in low power mode or for general purpose timer. WKT remains counting in Idle or
Power-down mode. When WKT is being used as a wake-up timer, a start of WKT can occur just prior
to entering a power management mode. WKT has two clock source, internal LIRC 38.4 kHz or LXT
32.768 kHz. Note that the system clock frequency must be twice over WKT clock. If WKT starts
counting, the selected clock source will remain active once the device enters Idle or Power-down
mode. Note that the selected clock source of WKT will not automatically enabled along with WKT
configuration. User should manually enable the selected clock source and waiting for stability to
ensure a proper operation.
The WKT is implemented simply as a 16-bit auto-reload, up-counting timer with pre-scale 1/1 to
1/2048 selected by WKPS[2:0] (WKCON[2:0]). User fills the reload value into RWK register to
determine its overflow rate. The RWK can reloadable when counter is count to overflow. The CWK
can read current count value. The WKTR (WKCON.3) can be set to start counting. When the counter
rolls over FFH, WKTF (WKCON.4) is set as 1 and a reload is generated and causes the contents of
the RWK register to be reloaded into the internal 8-bit counter. If EWKT (EIE1.2) is set as 1, WKT
interrupt service routine will be served.
Sep. 1, 2020
Page 85 of 164
Rev 2.00
ML51/ML54/ML56
6.8 Pulse Width Modulated (PWM)
6.8.1 Overview
The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can
used on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as a
simple digital to analog converter output through a low pass filter circuit.
The ML51/ML54/ML56 Series PWM0 is especially designed for motor control by providing three pairs,
maximum 16-bit resolution of PWM0 output with programmable period and duty. The architecture
makes user easy to drive the one-phase or three-phase brushless DC motor (BLDC), or three-phase
AC induction motor. Each of six PWM can be configured as one of independent mode, complementary
mode, or synchronous mode. If the complementary mode is used, a programmable dead-time
insertion is available to protect MOS turn-on simultaneously. The PWM waveform can be edge-aligned
or center-aligned with variable interrupt points.
The ML51/ML54/ML56 Series PWM1/2/3 provide individual configurable period and duty. maximum
16-bit resolution output. Each of two PWM1/2/3 can be configured as one of independent mode,
complementary mode, or synchronous mode.The PWM1/2/3 waveform can be edge-aligned or center-
aligned with variable interrupt points.
6.8.2
Features
Up To 12 output pins can be selected
Supports maximum clock source frequency up to 24 MHz
Supports up to Three PWM modules, each module provides 6 output channels.
Supports independent mode for PWM output
Supports complementary mode for 3 complementary paired PWM output channels
Dead-time insertion with 8-bit resolution
Supports 16-bit resolution PWM counter
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Supports trigger ADC on the following events
Sep. 1, 2020
Page 86 of 164
Rev 2.00
ML51/ML54/ML56
6.9 Serial Port (UART0 & UART1)
6.9.1 Overview
The ML51/ML54/ML56 Series includes two enhanced full duplex serial ports enhanced with automatic
address recognition and framing error detection. As control bits of these two serial ports are
implemented the same. Generally speaking, in the following contents, there will not be any reference
to serial port 1, but only to serial port 0.
Each serial port supports one synchronous communication mode, Mode 0, and three modes of full
duplex UART (Universal Asynchronous Receiver and Transmitter), Mode 1, 2, and 3. This means it
can transmit and receive simultaneously. The serial port is also receiving-buffered, meaning it can
commence reception of a second byte before a previously received byte has been read from the
register. The receiving and transmitting registers are both accessed at SBUF. Writing to SBUF loads
the transmitting register, and reading SBUF accesses a physically separate receiving register. There
are four operation modes in serial port. In all four modes, transmission initiates by any instruction that
uses SBUF as a destination register.
6.9.2
Features
Supports up to 2 UARTs: UART0, UART1
Supports 2 Smart Card configuration as UART function as UART2 and UART3.
UART baud rate clock from HIRC or HXT.
Full-duplex asynchronous communications
Programmable 9th bit.
TXD and RXD pins of UART0 exchangeable via software.
Sep. 1, 2020
Page 87 of 164
Rev 2.00
ML51/ML54/ML56
6.10 Smart Card Interface (SC)
6.10.1 Overview
The ML51/ML54/ML56 Series provides Smart Card Interface controller (SC controller) with
asynchronous protocal based on ISO/IEC 7816-3 standard. Software controls GPIO pins as the
smartcard reset function and card detection function. This controller also provides UART emulation for
high precision baud rate communication.
6.10.2 Features
ISO 7816-3 T = 0, T = 1 compliant
Programmable transmission clock frequency
Programmable extra guard time selection
Supports auto inverse convention function
Supports UART mode
Full duplex, asynchronous communications
Supports programmable baud rate generator for each channel
Programmable transmitting data delay time between the last stop bit leaving the TX-FIFO
and the de-assertion by setting SCnEGT register
Programmable even, odd or no parity bit generation and detection
Programmable stop bit, 1 or 2 stop bit generation
Sep. 1, 2020
Page 88 of 164
Rev 2.00
ML51/ML54/ML56
6.11 Serial Peripheral Interface (SPI)
6.11.1 Overview
The ML51/ML54/ML56 Series provides two Serial Peripheral Interface (SPI) block to support high-
speed serial communication. SPI is a full-duplex, high-speed, synchronous communication bus
between microcontrollers or other peripheral devices such as serial EEPROM, LCD driver, or D/A
converter. It provides either Master or Slave mode, high-speed rate up to FSYS/4, transfer complete and
write collision flag. For a multi-master system, SPI supports Master Mode Fault to protect a multi-
master conflict.
6.11.2 Features
2 sets of SPI devices
Supports Master or Slave mode operation
Supports MSB first or LSB first transfer sequence
Slave mode up to 12 Mhz
Sep. 1, 2020
Page 89 of 164
Rev 2.00
ML51/ML54/ML56
6.12 Inter-Integrated Circuit (I2C)
6.12.1 Overview
The ML51/ML54/ML56 Series provides two Inter-Integrated Circuit (I2C) bus to serves as an serial
interface between the microcontrollers and the I2C devices such as EEPROM, LCD module,
temperature sensor, and so on. The I2C bus used two wires design (a serial data line SDA and a serial
clock line SCL) to transfer information between devices.
The I2C bus uses bi-directional data transfer between masters and slaves. There is no central master
and the multi-master system is allowed by arbitration between simultaneously transmitting masters.
The serial clock synchronization allows devices with different bit rates to communicate via one serial
bus. The I2C bus supports four transfer modes including master transmitter, master receiver, slave
receiver, and slave transmitter. The I2C interface only supports 7-bit addressing mode. A special mode
General Call is also available. The I2C can meet both standard (up to 100kbps) and fast (up to 400k
bps) speeds.
6.12.2 Features
2 sets of I2C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
7-bit addressing mode
Standard mode (100 kbps) and Fast mode (400 kbps).
Supports 8-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out
counter overflows
Multiple address recognition (four slave addresses with mask option)
Supports hold time programmable
Sep. 1, 2020
Page 90 of 164
Rev 2.00
ML51/ML54/ML56
6.13 12-bit Analog-to-digital Converter (ADC)
6.13.1 Overview
The ML51/ML54/ML56 Series is embedded with a 12-bit SAR ADC. The ADC (analog-to-digital
converter) allows conversion of an analog input signal to a 12-bit binary representation of that signal.
The ML51/ML54/ML56 Series is selected as 8-channel inputs in single end mode. The internal band-
gap voltage 0.814 V also can be the internal ADC input. The analog input, multiplexed into one sample
and hold circuit, charges a sample and hold capacitor. The output of the sample and hold capacitor is
the input into the converter. The converter then generates a digital result of this analog level via
successive approximation and stores the result in the result registers. The ADC controller also
supports DMA (direct memory access) function for ADC continuous conversion and storage result
data into XRAM no need special enable PDMA module.
Sep. 1, 2020
Page 91 of 164
Rev 2.00
ML51/ML54/ML56
6.14 Voltage Reference (VREF)
The VREF pin is for analog multiplexer, such as ADC, ACMP. It default be used as an external
source(set ENVRF = 0). It also could be configurable as on-chip reference voltage generator (VREF_IN
)
by setting ENVRF = 1. The output voltage is selectable by setting VRFSEL[2:0]. The maximum load of
the VREF_IN must be less than 200 uA to AVSS. Set pre-load is to reduce stable time of VREF_IN. At first
enable VREF_IN and turn on pre-load at the same time, the minimum stable time of pre-load on the
VREF_IN must be greater than 3 ms. After the VREF_IN stable, user should be turn off pre-load to avoid
any interference on analog multiplexer. Pre-load is only for internal VREF use. For detailed electrical
characteristics
Sep. 1, 2020
Page 92 of 164
Rev 2.00
ML51/ML54/ML56
6.15 Analog Comparator Controller (ACMP)
6.15.1 Overview
The ML51/ML54/ML56 Series contains two comparators. The comparator output is logic 1 when
positive input is greater than negative input; otherwise, the output is 0. The comparator can be
configured to generate an interrupt when the comparator output value changes.
6.15.2 Feature
Analog input voltage range: 0 ~ AVDD(voltage of AVDD pin)
Supports hysteresis function
Supports wake-up function
Selectable input sources of negative input
Comparator ACMP0 supports
4 positive source
P2.5 (ACMPn_P0)
P2.3 (ACMPn_P1)
P2.1 (ACMPn_P2)
P3.1 (ACMPn_P3)
4 negative sources
P2.4 (ACMP0_N0)
Comparator Reference Voltage (CRV)
VBG (BANDGAP voltage)
P2.0 (ACMP0_N1)
Comparator ACMP1 supports
4 positive source
P2.5 (ACMPn_P0)
P2.3 (ACMPn_P1)
P2.1 (ACMPn_P2)
P3.1 (ACMPn_P3)
4 negative sources
P2.2 (ACMP1_N0)
Comparator Reference Voltage (CRV)
VBG (BANDGAP voltage)
P3.2 (ACMP1_N1)
Sep. 1, 2020
Page 93 of 164
Rev 2.00
ML51/ML54/ML56
6.16 PDMA Controller (PDMA)
6.16.1 Overview
The ML51/ML54/ML56 Series provides peripheral direct memory access (PDMA) controller. The
PDMA controller is used to provide high-speed data transfer between memory and peripherals or
between memory and memory. The PDMA controller can transfer data from one address to another
without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU
resources free for other applications.
6.16.2 Feature
Supports transfer data width of 8 bits
Supports software and SPI and SMC/UART request
Supports source and destination address increment size can be byte
Supports transfer done and half done interrupt
Supports using PDMA to write data to perform CRC operation
Sep. 1, 2020
Page 94 of 164
Rev 2.00
ML51/ML54/ML56
6.17 LCD Driver
6.17.1 Overview
The Liquid Crystal Displays (LCD) panel is widely used to meet the display need in applications. The
ML54/ML56 series is equipped with LCD driver that can directly drive the LCD panel with 4 COM x 32
SEG , 6 COM x 30 SEG or 8 COM x 28 SEG. Use the corresponding COM and SEM according to the
definition of multiple function pin. The LCD driver supports 1/4 duty, 1/6 duty, or 1/8 duty. The driving
voltage supports 1/2 bias, 1/3 bias or 1/4 bias with waveform type A or Type B. The source of LCD
clock is based on the choice of LIRC or LXT. The LCD display can keep display on or off during chip in
power-down mode. The LCD power supply VLCD source is selectable from internal charge pump,
external VLCD pin or analog power AVDD.
6.17.2 Features
1.8V to 5.5V LCD operating voltage.
Selectable LCD clock source from LIRC or LXT
1/2, 1/3, 1/4 bias selectable
Maximum 4 COM x 32 SEG, 6 COM x 30 SEG, 8 COM x 28 SEG
Supports buffer mode for high current driving
Support enhaced resistor mode for low power application
Support external VLCD source or AVDD as LCD voltage source.
Support programmable internal charge pump circuit for LCD voltage level is higher or lower than
VDD application.
Support blink function.
Suppot display on or off during chip in power down mode
Sep. 1, 2020
Page 95 of 164
Rev 2.00
ML51/ML54/ML56
6.18 Real Time Clock (RTC)
6.18.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers
programmable time tick and alarm match interrupts. The data format of time and calendar messages
are expressed in BCD format. A digital frequency compensation feature is available to compensate
external crystal oscillator frequency accuracy.
6.18.2 Features
Supports real time counter and calendar counter for RTC time and calendar check.
Supports alarm time and calendar settings
Supports alarm time and calendar mask enable settings.
Selectable 12-hour or 24-hour time scale setting.
Supports Leap Year indication setting.
Supports Day of the Week counter setting.
Frequency of RTC clock source compensate by RTCFREQADJ0/1 register.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm Match interrupt.
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated.
Sep. 1, 2020
Page 96 of 164
Rev 2.00
ML51/ML54/ML56
6.19 Touch Key (TK)
6.19.1 Overview
The capacitive touch key sensing controller supports several programmable sensitivity levels for
different applications to detect the finger touched or near the electrode covered by dielectric. It
supports total 15 keys with single scan or programmable periodic key scans, and system can be
waked up by any key for low power applications.
6.19.2 Features
Supports up to 14 touch keys + 1 reference
Supports any CLKO pin as shielding and any TK pin as reference.
Programmable sensitivity levels for each channel.
Programmable scanning speed for different applications.
Supports any touch key wake up for low power applications.
Supports single key scan and programmable periodic key scan.
Programmable interrupt options for key scan complete with/without threshold control.
Sep. 1, 2020
Page 97 of 164
Rev 2.00
ML51/ML54/ML56
6.20 Auxiliary Features
6.20.1 Dual DPTRs
The original 8051 contains one DPTR (data pointer) only. With single DPTR, it is difficult to move data
form one address to another with wasting code size and low performance. The ML51/ML54/ML56
Series provides two data pointers. Thus, software can load both a source and a destination address
when doing a block move. Once loading, the software simply switches between DPTR and DPTR1 by
the active data pointer selection DPS (AUXR0.0) bit.
An example of 64 bytes block move with dual DPTRs is illustrated below. By giving source and
destination addresses in data pointers and activating cyclic makes block RAM data move more simple
and efficient than only one DPTR. The INC AUXR0 instruction is the shortest (2 bytes) instruction to
accomplish DPTR toggling rather than ORL or ANL. For AUXR0.1 contains a hard-wired 0, it allows
toggling of the DPS bit by incrementing AUXR0 without interfering with other bits in the register.
MOV
MOV
INC
R0,#64
;number of bytes to move
;load destination address
;change active DPTR
DPTR,#D_Addr
AUXR0
MOV
DPTR,#S_Addr
;load source address
LOOP:
MOVX
INC
A,@DPTR
AUXR0
@DPTR,A
DPTR
AUXR0
DPTR
;read source data byte
;change DPTR to destination
;write data to destination
;next destination address
;change DPTR to source
;next source address
MOVX
INC
INC
INC
DJNZ
INC
R0,LOOP
AUXR0
;(optional) restore DPS
AUXR0 also contains a general purpose flag GF2 in its bit 3 that can be set or cleared by the user via
software.
Sep. 1, 2020
Page 98 of 164
Rev 2.00
ML51/ML54/ML56
DPL – Data Pointer Low Byte
Register
SFR Address
Reset Value
DPL
82H, All pages
0000_0000b
7
6
5
4
3
2
1
0
DPTR[7:0]
R/W
Bit
Name
Description
7:0
DPTR[7:0] Data Pointer Low Byte
This is the low byte of 16-bit data pointer. DPL combined with DPH serve as a 16-bit data
pointer DPTR to access indirect addressed RAM or Program Memory. DPS (AUXR0.0) bit
decides which data pointer, DPTR or DPTR1, is activated.
Sep. 1, 2020
Page 99 of 164
Rev 2.00
ML51/ML54/ML56
DPH – Data Pointer High Byte
Register
SFR Address
Reset Value
DPH
83H, All pages
0000_0000b
7
6
5
4
3
2
1
0
DPTR[15:8]
R/W
Bit
Name
Description
7:0
DPTR[15:8] Data Pointer High Byte
This is the high byte of 16-bit data pointer. DPH combined with DPL serve as a 16-bit data
pointer DPTR to access indirect addressed RAM or Program Memory. DPS (AUXR0.0) bit
decides which data pointer, DPTR or DPTR1, is activated.
Sep. 1, 2020
Page 100 of 164
Rev 2.00
ML51/ML54/ML56
AUXR0 – Auxiliary Register 0
Register
SFR Address
Reset Value
POR: 0000 0000b,
Software reset: 1U00 0000b,
nRESET pin: U100 0000b,
Hard fault: UU10 0000b
Others: UUU0 0000b
AUXR0
A2H , Page 0
7
6
5
4
3
2
-
1
0
0
SWRF
R/W
RSTPINF
R/W
HardF
R/W
HardFInt
GF2
R/W
DPS
R/W
R/W
-
R
Bit
Name
GF2
Description
3
General Purpose Flag 2
The general purpose flag that can be set or cleared by the user via software.
2
1
0
-
0
Reserved
Reserved This bit is always read as 0.
DPS
Data Pointer Select
0 = Data pointer 0 (DPTR) is active by default.
1 = Data pointer 1 (DPTR1) is active.
After DPS switches the activated data pointer, the previous inactivated data pointer remains
its original value unchanged.
Sep. 1, 2020
Page 101 of 164
Rev 2.00
ML51/ML54/ML56
6.20.2 96-Bit Unique Code (UID)
Before shipping out, each ML51/ML54/ML56 Series chip was factory pre-programmed with a 96-bit
width serial number, which is guaranteed to be unique for each piece of ML51/ML54/ML56 Series. The
serial number is called Unique Code or UID. The user can read the Unique Code only by IAP
command. More details please see Chapter 6.3 Flash Memory Control
In-application-programming (IAP).
IAPCN
IAPA[15:0]
IAP Mode
IAPFD[7:0]
{IAPAH, IAPAL}
IAPB [1:0]
FOEN
FCEN
FCTRL [3:0]
96-bit Unique Code read
XX
0
0
0100
0000H to 000BH
Data out
Sep. 1, 2020
Page 102 of 164
Rev 2.00
ML51/ML54/ML56
6.21 Instruction Set
6.21.1 Instruction Set And Addressing Modes
The ML51/ML54/ML56 Series executes all the instructions of the standard 80C51 family fully
compatible with MCS-51. However, the timing of each instruction is different for it uses high
performance 1T 8051 core. The architecture eliminates redundant bus states and implements parallel
execution of fetching, decode, and execution phases. The ML51/ML54/ML56 Series uses one clock
per machine-cycle. It leads to performance improvement of rate 8.1 (in terms of MIPS) with respect to
traditional 12T 80C51 device working at the same clock frequency. However, the real speed
improvement seen in any system will depend on the instruction mix.
All instructions are coded within an 8-bit field called an OPCODE. This single byte should be fetched
from Program Memory. The OPCODE is decoded by the CPU. It determines what action the CPU will
take and whether more operation data is needed from memory. If no other data is needed, then only
one byte was required. Thus the instruction is called a one byte instruction. In some cases, more data
is needed, which is two or three byte instructions.
Following lists all instructions for details. The note of the instruction set and addressing modes are
shown below.
Rn (N = 0~7)
Direct
Register R0 To R7 Of The Currently Selected Register Bank.
8-bit internal data location’s address. It could be an internal data RAM location (00H to 7FH) or an
SFR (80H to FFH).
@RI (I = 0, 1)
#data
8-bit internal data RAM location (00H to FFH) addressed indirectly through register R0 or R1.
8-bit constant included in the instruction.
#data16
Addr16
16-bit constant included in the instruction.
16-bit destination address. Used by LCALL and LJMP. A branch can be any-where within the
Program Memory address space.
Addr11
Rel
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K-Byte
page of Program Memory as the first byte of the following instruction.
Signed (2’s complement) 8-bit offset Byte. Used by SJMP and all conditional branches. The range is
-128 to +127 bytes relative to first byte of the following instruction.
Bit
Direct addressed bit in internal data RAM or SFR.
Table 6.21-1 Instruction Set And Addressing Modes
Sep. 1, 2020
Page 103 of 164
Rev 2.00
ML51/ML54/ML56
Instruction
ADD
CY
X[1]
X
OV
X
AC
X
Instruction
CLR C
CY
0
OV
AC
ADDC
SUBB
MUL
X
X
CPL C
X
X
X
X
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
CJNE
X
0
X
X
DIV
0
X
X
DA A
X
X
RRC A
RLC A
SETB C
X
X
X
X
1
Note: X indicates the modification depends on the result of the instruction.
Table 6.21-2 Instructions Affect Flag Settings
Sep. 1, 2020
Page 104 of 164
Rev 2.00
ML51/ML54/ML56
6.21.2 Read-Modify-Write Instructions
Instructions that read a byte from SFR or internal RAM, modify it, and rewrite it back, are called “Read-
Modify-Write” instructions. When the destination is an I/O port or a port bit, these instructions read the
internal output latch rather than the external pin state. This kind of instructions read the port SFR
value, modify it and write back to the port SFR. All “Read-Modify-Write” instructions are listed as
follows.
Instruction
ANL
Description
Logical AND. (ANL direct, A and ANL direct, #data)
Logical OR. (ORL direct, A and ORL direct, #data)
ORL
XRL
Logical exclusive OR. (XRL direct, A and XRL direct,
#data)
JBC
CPL
INC
DEC
DJNZ
MOV
CLR
SETB
Jump if bit = 1 and clear it. (JBC bit, rel)
Complement bit. (CPL bit)
Increment. (INC direct)
Decrement. (DEC direct)
Decrement and jump if not zero. (DJNZ direct, rel)
bit, C
Move carry to bit. (MOV bit, C)
bit Clear bit. (CLR bit)
bit Set bit. (SETB bit)
The last three seem not obviously “Read-Modify-Write” instructions but actually they are. They read
the entire port latch value, modify the changed bit, and then write the new value back to the port latch.
6.21.3 Instruction Set
ML51/ML54/ML56 Series
Instruction
OPCODE
Bytes
Clock Cycles
V.S. Tradition 80C51 Speed
Ratio
NOP
00
28~2F
25
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
3
4
2
2
3
4
2
2
3
4
2
12
6
4
3
6
6
4
3
6
6
4
3
6
ADD
A, Rn
ADD
A, direct
A, @Ri
A, #data
A, Rn
ADD
26, 27
24
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
38~3F
35
A, direct
A, @Ri
A, #data
A, Rn
36, 37
34
98~9F
95
A, direct
A, @Ri
A, #data
96, 97
94
Sep. 1, 2020
Page 105 of 164
Rev 2.00
ML51/ML54/ML56
ML51/ML54/ML56 Series
V.S. Tradition 80C51 Speed
Ratio
Instruction
OPCODE
Bytes
Clock Cycles
INC
A
04
08~0F
05
1
1
2
1
1
1
1
2
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
2
1
1
3
4
5
1
1
3
4
5
4
4
1
2
3
4
2
4
4
2
3
4
2
4
4
2
3
4
2
4
4
1
1
1
1
1
1
1
1
3
4
12
4
INC
Rn
INC
direct
@Ri
3
INC
06, 07
A3
2.4
24
12
4
INC
DPTR
A
DEC
DEC
DEC
DEC
MUL
DIV
14
Rn
18~1F
15
direct
@Ri
3
16, 17
A4
2.4
12
12
12
6
AB
AB
84
DA
A
D4
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A, Rn
A, direct
A, @Ri
A, #data
direct, A
direct, #data
A, Rn
A, direct
A, @Ri
A, #data
direct, A
direct, #data
A, Rn
A, direct
A, @Ri
A, #data
direct, A
direct, #data
A
58~5F
55
4
56, 57
54
3
6
52
3
53
6
48~4F
45
6
4
46, 47
44
3
6
42
3
43
6
68~6F
65
6
4
66, 67
64
3
6
62
3
63
6
E4
12
12
12
12
12
12
12
12
4
A
F4
A
23
RLC
RR
A
33
A
03
RRC
SWAP
MOV
MOV
MOV
A
13
A
C4
A, Rn
A, direct
A, @Ri
E8~EF
E5
E6, E7
3
Sep. 1, 2020
Page 106 of 164
Rev 2.00
ML51/ML54/ML56
ML51/ML54/ML56 Series
V.S. Tradition 80C51 Speed
Ratio
Instruction
OPCODE
Bytes
Clock Cycles
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A, #data
74
F8~FF
A8~AF
78~7F
F5
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
1
2
1
2
2
2
2
2
2
2
2
1
4
2
2
3
4
5
3
3
4
3
3
4
4
5
4
6
5
4
3
2
3
4
5
1
4
1
4
1
4
3
3
3
3
3
4
6
12
6
Rn, A
Rn, direct
Rn, #data
direct, A
6
6
direct, Rn
direct, direct
direct, @Ri
direct, #data
@Ri, A
88~8F
85
8
6
86, 87
75
4.8
8
F6, F7
A6, A7
76, 77
90
4
@Ri, direct
@Ri, #data
DPTR, #data16
6
6
8
MOVC A, @A+DPTR
MOVC A, @A+PC
93
6
83
6
MOVX
MOVX
MOVX
MOVX
PUSH
POP
A, @Ri[1]
A, @DPTR[1]
@Ri, A[1]
@DPTR, A[1]
direct
direct
A, Rn
A, direct
A, @Ri
A, @Ri
C
E2, E3
E0
4.8
6
F2, F3
F0
4
4.8
6
C0
D0
8
XCH
C8~CF
C5
6
XCH
4
XCH
C6, C7
D6, D7
C3
3
XCHD
CLR
2.4
12
3
CLR
bit
C2
SETB
SETB
CPL
C
D3
12
3
bit
D2
C
B3
12
3
CPL
bit
B2
ANL
C, bit
82
8
ANL
C, /bit
C, bit
B0
8
ORL
72
8
ORL
C, /bit
C, bit
A0
8
MOV
MOV
A2
4
bit, C
92
6
11, 31, 51, 71, 91, B1,
D1, F1[2]
ACALL addr11
2
4
6
LCALL addr16
RET
12
22
3
1
4
5
6
4.8
Sep. 1, 2020
Page 107 of 164
Rev 2.00
ML51/ML54/ML56
ML51/ML54/ML56 Series
V.S. Tradition 80C51 Speed
Ratio
Instruction
OPCODE
Bytes
Clock Cycles
RETI
32
1
2
5
3
4.8
8
AJMP
addr11
01, 21, 41, 61, 81, A1,
C1, E1[3]
LJMP
SJMP
JMP
JZ
addr16
rel
02
80
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
4
3
3
3
3
3
3
5
5
5
5
4
4
6
4
5
6
8
@A+DPTR
rel
73
8
60
8
JNZ
rel
70
8
JC
rel
40
8
JNC
JB
rel
50
8
bit, rel
20
4.8
4.8
4.8
4.8
6
JNB
bit, rel
30
JBC
bit, rel
10
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
Note:
A, direct, rel
A, #data, rel
Rn, #data, rel
@Ri, #data, rel
Rn, rel
B5
B4
B8~BF
B6, B7
D8~DF
D5
6
4
6
direct, rel
4.8
1. The ML51/ML54/ML56 Series does not have external memory bus. MOVX instructions are used to access internal XRAM.
2. The most three significant bits in the 11-bit address [A10:A8] decide the ACALL hex code. The code will be [A10, A9, A8, 1,
0, 0, 0, 1].
3. The most three significant bits in the 11-bit address [A10:A8] decide the AJMP hex code. The code will be [A10, A9, A8, 0,
0, 0, 0, 1].
Table 6.21-3 Instruction Set
Sep. 1, 2020
Page 108 of 164
Rev 2.00
ML51/ML54/ML56
7 APPLICATION CIRCUIT
7.1 Power Supply Scheme
EXT_PWR
For external VREF source from
VDD only
Way 1
Way 2
as close to VREF
as possible
L=30S
VREF
1uF
10uF+0.1uF
For internal VREF only
ML51
Series
as close to the
EXT_PWR as
possible
VDD
VSS
EXT_VSS
0.1uF*N
as close to VDD as possible
Figure 7.1-1 NuMicro® ML51/ML54/ML56 Series Power supply circuit
Sep. 1, 2020
Page 109 of 164
Rev 2.00
ML51/ML54/ML56
7.2 Peripheral Application Scheme
DVCC
DVCC
ICE / ICP
CS
SPI_SS
SPI_CLK
VDD
SPI
CLK
Device
Interface
SPI_MISO
SPI_MOSI
MISO
VSS
MOSI
100K 100K
VDD
100
100
ICE_CLK
VSS
DVCC
DVCC
4.7K
4.7K
XT1_IN
I2C
Device
20pF
CLK
DIO
VDD
VSS
I2C_SCL
I2C_SDA
4~24 MHz
crystal
20pF
XT1_OUT
X32_IN
ML51 Series
Crystal
RS 232 Transceiver
20pF
20pF
32.768 kHz
crystal
RIN
UART_RXD
UART_TXD
ROUT
TIN
UART
TOUT
X32_OUT
PC COM Port
DVCC
DH1
VLCD
10K
Source
0.1uF
1uF
nRST
DH2
Reset
10 uF
VLCD
Circuit
LCD
Note
1: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin.
2: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
3: It is suggest add 100ohm series resistor between ICE_DAT/ICE_CLK and writer pin to filter the disturb of noise on the circuit.
Figure 7.2-1 NuMicro® ML51/ML54/ML56 Series Peripheral interface circuit
Sep. 1, 2020
Page 110 of 164
Rev 2.00
ML51/ML54/ML56
8 ELECTRICAL CHARACTERISTICS
Please refer to the relative Datasheet for detailed information about the ML51/ML54/ML56 series
electrical characteristics.
8.1 General Operating Conditions
(VDD-VSS = 1.8 ~ 5.5V, TA = 25C, Fsys = 24 MHz unless otherwise specified.)
8.1.1
ML51 32KB/16KB Flash Series
Symbol
Parameter
Min
-40
1.8
Typ
Max
105
5.5
Unit
Test Conditions
TA
Temperature
-
℃
VDD
Operation voltage
-
V
[1]
AVDD
Analog operation voltage
VDD
Note:
1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3V between VDD and AVDD
can be tolerated during power-on and power-off operation .
2.Based on characterization, tested in production.
Table 8.1-1 ML51 32KB/16KB Flash Series General Operating Conditions
8.1.2
ML51 64KB Flash/ML54/ML56 Series
Symbol
Parameter
Temperature
Min
-40
1.8
Typ
Max
105
3.6
Unit
Test Conditions
TA
-
℃
VDD
Operation voltage
-
V
[1]
AVDD
Analog operation voltage
VDD
Note:
1.It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3V between VDD and
AVDD can be tolerated during power-on and power-off operation .
2.Based on characterization, tested in production.
Table 8.1-2 ML56/ML54/ML51 64KB Flash Series General Operating Conditions
Sep. 1, 2020
Page 111 of 164
Rev 2.00
ML51/ML54/ML56
8.2 DC Electrical Characteristics
8.2.1 Supply Current Characteristics
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
8.2.1.1 ML51 32KB/16KB Flash Series
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 1. 8V ~ 5.5 V and maximum ambient
temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise
specified.
VDD = AVDD
When the peripherals clock base is the system clock Fsys.
Program run “while (1);” in flash.
Normal Run Mode
Typ [6]
Max[6][7]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
24 MHz
2.40
2.64
2.87
2.90
(HIRC)[1]
24 MHz
2.52
1.56
0.91
0.22
0.24
3.50
3.62
2.26
1.30
0.37
0.40
2.97
2.04
1.33
0.29
0.30
3.78
4.11
2.74
1.74
0.57
0.58
3.10
2.13
1.39
0.32
0.32
3.86
4.24
2.83
1.81
0.59
0.60
3.16
2.20
1.43
0.35
0.35
3.89
4.31
2.92
1.83
0.61
0.62
(HXT) [2][5]
12 MHz
Normal run mode, executed
from Flash, all peripherals
disable
(HXT) [2][5]
4 MHz
(HXT) [2][5]
38.4 kHz
(LIRC)[3]
32.768 kHz
(LXT)[4]
IDD_RUN
mA
24 MHz
(HIRC)[1]
24 MHz
(HXT) [2][5]
12 MHz
Normal run mode, executed
from Flash, all peripherals
enable
(HXT) [2][5]
4 MHz
(HXT) [2][5]
38.4 kHz
(LIRC)[3]
32.768 kHz
(LXT)[4]
Notes:
1. This value base on HIRC enable, HXT disable, LIRC enable, LXT enable
2. This value base on HIRC disable, HXT enable, LIRC enable, LXT disable
3. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable
Sep. 1, 2020
Page 112 of 164
Rev 2.00
ML51/ML54/ML56
Typ [6]
= 25 °C
Max[6][7]
= 85 °C
Symbol
Conditions
Fsys
Unit
T
T
= 25 °C
T
T = 105 °C
A
A
A
A
4. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable
5. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values
6. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD enable.
7. Based on characterization, not tested in production unless otherwise specified.
Table 8.2-1 ML51 32KB / 16KB Series Current Consumption In Normal Run Mode
Low Power Run Mode
Typ [3]
Max[3][4]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
38.4 kHz
(LIRC)[1]
15
21
42
66
Low power run mode, executed
from Flash, all peripherals
disable
32.768 kHz
(LXT)[2]
19
23
44
67
IDD_LPRUN
µA
38.4 kHz
(LIRC)[1]
193
194
307
308
320
321
344
345
Low power run mode, executed
from Flash, all peripherals
enable
32.768 kHz
(LXT)[2]
Notes:
1. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable
2. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable
3. Based on characterization, not tested in production unless otherwise specified.
4. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD disable.
Table 8.2-2 ML51 32KB/16KB Flash Series Current Consumption In Low Power Run Mode
Idle Mode
Typ [6]
Max[6][7]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
24 MHz
1.43
1.58
1.62
1.64
(HIRC)[1]
24 MHz
1.52
1.07
0.76
0.20
0.22
2.46
2.55
1.91
1.44
1.10
0.30
0.32
2.72
3.04
2.00
1.50
1.15
0.32
0.34
2.78
3.15
2.05
1.56
1.19
0.35
0.36
2.80
3.19
(HXT) [2][5]
12 MHz
(HXT) [2][5]
Idle mode, all peripherals
disable
4 MHz
(HXT) [2][5]
IDD_IDLE
mA
38.4 kHz
(LIRC)[3]
32.768 kHz
(LXT)[4]
24 MHz
(HIRC)[1]
Idle mode, all peripherals
enable
24 MHz
(HXT) [2][5]
Sep. 1, 2020
Page 113 of 164
Rev 2.00
ML51/ML54/ML56
Typ [6]
Max[6][7]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
12 MHz
1.67
2.14
2.22
2.26
(HXT) [2][5]
4 MHz
1.08
0.37
0.38
1.51
0.57
0.59
1.57
0.60
0.61
1.60
0.61
0.62
(HXT) [2][5]
38.4 kHz
(LIRC)[3]
32.768 kHz
(LXT)[4]
Notes:
1. This value base on HIRC enable, HXT disable, LIRC enable, LXT enable
2. This value base on HIRC disable, HXT enable, LIRC enable, LXT disable
3. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable
4. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable
5. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values
6. Based on characterization, not tested in production unless otherwise specified.
7. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD enable.
Table 8.2-3 ML51 32KB/16KB Flash Series Current Consumption In Idle Mode
Low Power Idle Mode
Typ [3]
Max[3][4]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
38.4 kHz
(LIRC)[1]
13
19
40
63
Low power idle mode, executed
from Flash, all peripherals
disable
32.768 kHz
(LXT)[2]
15
20
41
65
IDD_LPIDLE
µA
38.4 kHz
(LIRC)[1]
173
174
304
306
317
319
341
342
Low power idle mode, executed
from Flash, all peripherals
enable
32.768 kHz
(LXT)[2]
Notes:
1. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable
2. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable
3. Based on characterization, not tested in production unless otherwise specified.
4. AVDD = VDD = 3.3V , LVR17 enabled, POR enable and BOD enable.
Table 8.2-4 ML51 32KB/16KB Flash Series Current Consumption In Low Power Idle Mode
Sep. 1, 2020
Page 114 of 164
Rev 2.00
ML51/ML54/ML56
Power Down Mode
Typ[1]
Max[2][3]
Symbol
Test Conditions
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
Power down mode, all peripherals disable@3.3V
Power down mode, all peripherals disable@5.5V
0.8
1.6
1.6[4]
2.5
18
25
34
50
Power down mode, LVR enable all other peripherals
disable
1.4
60
3.2
80
19
70
21
20
36
100
37
IDD_PD Power down mode, LVR enable BOD enable all
other peripherals disable
µA
Power down mode, WDT / WKT enable all use LIRC,
BOD disable
2.87
2.42
5.2
4.2
Power down mode, WDT use LIRC, WKT use LXT,
BOD disable
38
Notes:
1. AVDD = VDD = 3.3V unless otherwise specified, LVR17 enabled, POR disabled and BOD disabled.
2. Based on characterization, not tested in production unless otherwise specified.
3. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
4. Based on characterization, tested in production.
Table 8.2-5 ML51 32KB/16KB Flash Series Chip Current Consumption in Power down mode
Sep. 1, 2020
Page 115 of 164
Rev 2.00
ML51/ML54/ML56
8.2.1.2 ML51 64KB Flash/ML54/ML56 Series
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 1. 8V ~ 3.6 V and maximum ambient
temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise
specified.
VDD = AVDD
When the peripherals clock base is the system clock Fsys.
Program run “while (1);” in flash.
Normal Run Mode
Typ [6]
Max[6][7]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
24 MHz
2.86
3.67
3.92
4.15
(HIRC)[1]
12 MHz
1.98
0.91
2.94
2.08
0.96
0.23
0.25
4.50
2.8
2.37
1.14
3.76
2.47
1.2
2.6
1.2
2.89
1.32
4.23
2.98
1.48
0.39
0.42
4.89
3.98
1.75
5.89
3.69
1.83
0.72
0.73
(HIRC)[1]
1 MHz
(HIRC)[1]
24 MHz
4.02
2.7
Normal run mode, executed
from Flash, all peripherals
disable
(HXT) [2][5]
12 MHz
(HXT) [2][5]
1 MHz
1.3
(HXT) [2][5]
38.4 kHz
(LIRC)[3]
0.32
0.35
4.78
3.4
0.34
0.37
4.86
3.6
32.768 kHz
(LXT)[4]
IDD_RUN
mA
24 MHz
(HIRC)[1]
12 MHz
(HIRC)[1]
1 MHz
1.17
4.9
1.45
5.21
3.12
1.49
0.61
0.62
1.6
(HIRC)[1]
24 MHz
5.46
3.33
1.75
0.67
0.69
Normal run mode, executed
from Flash, all peripherals
enable
(HXT) [2][5]
12 MHz
2.67
1.21
0.41
0.42
(HXT) [2][5]
1 MHz
(HXT) [2][5]
38.4 kHz
(LIRC)[3]
32.768 kHz
(LXT)[4]
Notes:
1. This value base on HIRC enable, HXT disable, LIRC enable, LXT enable
Sep. 1, 2020
Page 116 of 164
Rev 2.00
ML51/ML54/ML56
Typ [6]
= 25 °C
Max[6][7]
= 85 °C
Symbol
Conditions
Fsys
Unit
T
T
= 25 °C
T
T = 105 °C
A
A
A
A
2. This value base on HIRC disable, HXT enable, LIRC enable, LXT disable
3. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable
4. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable
5. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values
6. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD enable.
7. Based on characterization, not tested in production unless otherwise specified.
Table 8.2-6 ML56/ML54/ML51 64KB Flash Series Current Consumption In Normal Run Mode
Low Power Run Mode
Typ [3]
Max[3][4]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
19
T
= 25 °C
29
T
= 85 °C
52
T
A
= 105 °C
83
A
A
A
38.4 kHz
(LIRC)[1]
Low power run mode, executed
from Flash, all peripherals
disable
32.768 kHz
(LXT)[2]
21
32
55
85
IDD_LPRUN
µA
38.4 kHz
(LIRC)[1]
223
230
314
326
327
339
351
362
Low power run mode, executed
from Flash, all peripherals
enable
32.768 kHz
(LXT)[2]
Notes:
1. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable
2. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable
3. Based on characterization, not tested in production unless otherwise specified.
4. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD disable.
Table 8.2-7 ML56/ML54/ML51 64KB Flash Series Current Consumption In Low Power Run Mode
Idle Mode
Typ [6]
Max[6][7]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
24 MHz
1.8
2.25
2.43
2.46
(HIRC)[1]
24 MHz
1.74
1.07
0.97
0.20
0.22
1.91
1.44
1.10
0.30
0.32
2.00
1.50
1.15
0.32
0.34
2.05
1.56
1.19
0.35
0.36
(HXT) [2][5]
12 MHz
(HXT) [2][5]
Idle mode, all peripherals
disable
IDD_IDLE
mA
4 MHz
(HXT) [2][5]
38.4 kHz
(LIRC)[3]
32.768 kHz
(LXT)[4]
Sep. 1, 2020
Page 117 of 164
Rev 2.00
ML51/ML54/ML56
Typ [6]
Max[6][7]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
24 MHz
2.46
2.72
2.78
2.80
(HIRC)[1]
24 MHz
2.55
1.67
1.08
0.37
0.38
3.04
2.14
1.51
0.57
0.59
3.15
2.22
1.57
0.60
0.61
3.19
2.26
1.60
0.61
0.62
(HXT) [2][5]
12 MHz
(HXT) [2][5]
Idle mode, all peripherals
enable
4 MHz
(HXT) [2][5]
38.4 kHz
(LIRC)[3]
32.768 kHz
(LXT)[4]
Notes:
1. This value base on HIRC enable, HXT disable, LIRC enable, LXT enable
2. This value base on HIRC disable, HXT enable, LIRC enable, LXT disable
3. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable
4. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable
5. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values
6. Based on characterization, not tested in production unless otherwise specified.
7. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD enable.
Table 8.2-8 ML56/ML54/ML51 64KB Flash Series Current Consumption In Idle Mode
Low Power Idle Mode
Typ [3]
Max[3][4]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
38.4 kHz
(LIRC)[1]
17
27
50
81
Low power idle mode, executed
from Flash, all peripherals
disable
32.768 kHz
(LXT)[2]
22
32
55
87
IDD_LPIDLE
µA
38.4 kHz
(LIRC)[1]
213
220
302
312
317
320
340
342
Low power idle mode, executed
from Flash, all peripherals
enable
32.768 kHz
(LXT)[2]
Notes:
5. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable
6. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable
7. Based on characterization, not tested in production unless otherwise specified.
8. AVDD = VDD = 3.3V , LVR17 enabled, POR enable and BOD enable.
Table 8.2-9 ML56/ML54/ML51 64KB Flash Series Current consumption in Low Power Idle mode
Power Down Mode
Typ[1]
Max[2][3]
Symbol
Test Conditions
Unit
TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C
Power down mode, all peripherals disable@3.3V
Power down mode, all peripherals disable@5.5V
1.2
1.7
1.6[4]
2.6
20
27
37
47
IDD_PD
µA
Sep. 1, 2020
Page 118 of 164
Rev 2.00
ML51/ML54/ML56
Typ[1]
Max[2][3]
Symbol
Test Conditions
Unit
TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C
Power down mode, LVR enable all other peripherals
disable
1.7
4.8
61
3.2
10
25
52
98
44
48
32
42
48
42
69
110
52
68
49
56
77
Power down mode, LVR enable, Low power BOD
enable all other peripherals disable
Power down mode, LVR enable BOD enable all
other peripherals disable
82
Power down mode, WDT / WKT enable all use LIRC,
BOD disable
3
6.4
7.2
5.9
6.8
7.3
Power down mode, WDT use LIRC, WKT use LXT,
BOD disable
3.5
2.9
3.4
3.9
Power-down mode, RTC use LIRC, BOD disable,
HIRC off / HXT off / LIRC on / LXT off
Power-down mode, RTC/TK use LIRC, BOD disable,
HIRC off / HXT off / LIRC on / LXT off
Power-down mode, RTC use LXT, BOD disable,
HIRC off / HXT off / LIRC off / LXT on
Notes:
1. AVDD = VDD = 3.3V unless otherwise specified, LVR17 enabled, POR disabled and BOD disabled.
2. Based on characterization, not tested in production unless otherwise specified.
3. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be considered.
4. Based on characterization, tested in production.
Table 8.2-10 ML56/ML54/ML51 64KB Flash Series Series Chip Current Consumption In Power Down
Mode
Sep. 1, 2020
Page 119 of 164
Rev 2.00
ML51/ML54/ML56
8.2.2
On-Chip Peripheral Current Consumption
The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.
All GPIO pins are set as output high of push pull mode without multi-function.
The system clock = 24 MHz.
The result value is calculated by measuring the difference of current consumption
between all peripherals clocked off and only one peripheral clocked on
[1]
Peripheral
IDD Base
IDD
Unit
ADC[2]
ACMP0[3]
ACMP1[3]
PWM0
309.2
1.0
1.1
152.3
40.2
44.2
SPI0
SPI1
UART0
UART1
I2C0
1
1
1
1
98.8
118.7
I2C1
SC0
67.8
0.2
PIN Interrupt
TIMER 0
TIMER 1
TIMER 2
TIMER 3
INT0
4.1
3.9
4.4
10
145
µA
0.3
0.3
0.4
0.7
INT1
WDT
WKT
PDMA0
PDMA1
PDMA2
PDMA3
CAPTURE0
CAPTURE1
CAPTURE2
RTC
0.5
0.5
0.5
0.5
0.5
0.3
0.5
13.4
145
1
LCD
23
Sep. 1, 2020
Page 120 of 164
Rev 2.00
ML51/ML54/ML56
[1]
Peripheral
IDD Base
IDD
Unit
Notes:
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part.
Table 8.2-11 Peripheral Current Consumption
Sep. 1, 2020
Page 121 of 164
Rev 2.00
ML51/ML54/ML56
8.2.3
Wakeup Time from Low-Power Modes
The wakeup times given in Table 8.2-12 Low-Power Mode Wakeup Timings is measured on a wakeup
phase with a 24 MHz HIRC oscillator.
Symbol
Parameter
Typ
5
Max
Unit
cycles
µs
tWU_IDLE
Wakeup from IDLE mode
6
Fsys = HIRC @5.5V
7
20
Fsys = HIRC @3.6V
10
20
µs
Fsys = HIRC @1.8V
13
20
µs
Fsys = HXT@24MHz @5.5V[3]
Fsys = HXT@24MHz @3.6V[3]
Fsys = HXT@24MHz @1.8V[3]
Fsys = LIRC
370
440
600
938
860
-
µs
Wakeup from Power
down mode
[1][2]
tWU_NPD
-
-
1500
-
µs
µs
µs
Fsys = LXT@32.768KHz[4]
Notes:
1. Based on test during characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
3. Value variable based on extnerl Crystal stable time.
4 Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values, LXT not disabled when
ML51/ML54/ML56 Series into Power down mode.
Table 8.2-12 Low-Power Mode Wakeup Timings
Sep. 1, 2020
Page 122 of 164
Rev 2.00
ML51/ML54/ML56
8.2.4
I/O DC Characteristics
8.2.4.1 PIN Input Characteristics
Symbol
Parameter
Input low voltage
Min
Typ
Max
Unit
Test Conditions
VIL
0
-
0.3*VDD
V
Input low voltage
(I/O with TTL input)
VIL1
VIH
VSS-0.3
-
-
0.2VDD-0.1
VDD+0.3
V
V
0.2VDD+0.9
Input high voltage
Input high voltage
VIH1
0.7*VDD
-
VDD
V
V
(I/O with Schmitt trigger input and
Xin)
Hysteresis voltage of schmitt
input
[1]
VHY
-
0.2*VDD
-
VSS < VIN < VDD
Open-drain or input only mode
,
-1
1
[2]
ILK
Input leakage current
A
VDD < VIN < 5.5 V,
Open-drain or input only mode
-1
1
VDD = 5.5 V, Quasi mode and Input
mode with pull up enable
40
40
40
40
40
40
-
-
-
-
-
-
60
60
70
60
60
70
kΩ
VDD = 3.3 V, Quasi mode and Input
mode with pull up enable
[1] [3]
RPU
Pull up resistor
VDD = 1.8 V, Quasi mode and Input
mode pull up enable
VDD = 5.5 V, Quasi mode and Input
mode with pull up enable
kΩ
VDD = 3.3 V, Quasi mode and Input
mode with pull up enable
[1] [3]
RPD
Pull down resistor
VDD = 1.8 V, Quasi mode and Input
mode pull up enable
Notes:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher than
the maximum value, if positive current is injected on adjacent pins
4. Test condition of VDD is base on the maximum value of VDD
Table 8.2-13I/O Input Characteristics
Sep. 1, 2020
Page 123 of 164
Rev 2.00
ML51/ML54/ML56
8.2.4.2 nRESET Input Characteristics
Symbol
VILR
Parameter
Min
Typ
Max
Unit
V
Test Conditions
Negative going threshold, nRESET
Positive going threshold, nRESET
-
0.7*VDD
45
-
0.3*VDD
VIHR
-
-
V
-
60
60
65
-
VDD = 5.5 V
[1]
-
-
RRST
Internal nRESET pull up resistor
nRESET input response time
45
KΩ VDD = 3.6 V
50
VDD = 1.8 V
-
1.5
-
Normal run and Idle mode
Power down mode
[1]
tFR
µs
10
25
Notes:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
Table 8.2-14 nRESET Input Characteristics
Sep. 1, 2020
Page 124 of 164
Rev 2.00
ML51/ML54/ML56
8.3
AC Electrical Characteristics
The maximum values are obtained for VDD = 1.8 V ~ 5.5 V and maximum ambient temperature (TA),
and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. VDD = AVDD.
8.3.1
24 MHz Internal High Speed RC Oscillator (HIRC)
The 24 MHz RC oscillator is calibrated in production.
Symbol.
Parameter
Operating voltage
Min
Typ
Max
Unit
Test Conditions
VDD
1.8
-
5.5
V
TA = 25 °C,
VDD = 5V
Oscillator frequnecy
23.76
-1[1]
24
-
24.24
1[1]
MHz
%
TA = 25 °C,
VDD = 3.3V
FHRC
TA = -20C ~ +105 °C,
Frequency drift over temperarure and
volatge
-2[2]
-
2[2]
%
VDD = 1.8 ~ 5.5V
TA = -40C ~ -20°C,
-5[2]
5[2]
550
5
%
µA
µs
VDD = 1.8 ~ 5.5V
[2]
IHRC
Operating current
Stable time
-
-
490
3
TA = -40C ~ +105 °C,
[3]
TS
VDD = 1.8 ~ 5.5V
Notes:
1.
2.
3.
Based on characterization, tested in production.
Guaranteed by characterization result, not tested in production.
Guaranteed by design.
Table 8.3-1 24 MHz Internal High Speed RC Oscillator(HIRC) Characteristic
Sep. 1, 2020
Page 125 of 164
Rev 2.00
ML51/ML54/ML56
8.3.2
38.4 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
Parameter
Operating voltage
Min
1.8
-
Typ
-
Max
5.5
-
Unit
V
Test Conditions
VDD
Oscillator frequnecy
38.4
kHz
TA = 25 °C,
VDD = 5V
-2[1]
-
-
2[1]
%
%
FLRC
Frequency drift over temperarure
and volatge
TA=-40~105°C
VDD=1.8V~5.5V
-10[2]
10[2]
Without software calibration
[2]
ILRC
Operating current
Stable time
-
-
0.85
500
1
-
µA
VDD = 3.3V
TA=-40~105°C
VDD=1.8V~5.5V
TS
μs
Notes:
1. Guaranteed by characterization, tested in production.
2. Guaranteed by characterization, not tested in production.
3. The 38.4 kHz low speed RC oscillator can be calibrated by user.
4. Guaranteed by design.
Table 8.3-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics
Sep. 1, 2020
Page 126 of 164
Rev 2.00
ML51/ML54/ML56
8.3.3
External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Operating voltage
Min[1]
Typ
-
Max[1]
Unit
V
Test Conditions[2]
1.8
5.5
-
Rf
Internal feedback resister
Oscillator frequency
-
4
-
500
-
kΩ
fHXT
24
180
300
500
650
975
-
MHz
80
4 MHz, Gain = L0
-
110
180
230
360
3500
950
700
450
400
-
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
4 MHz, Gain = L0
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
IHXT
Current consumption
-
µA
-
-
-
-
-
TS
Stable time [3]
Duty cycle
-
-
µs
%
-
-
-
-
DuHXT
40
60
Notes:
1.
2.
3.
Guaranteed by characterization, not tested in production.
L0 ~ L4 defined by SFR XLTCON[6:4] HXSG
Value variable based on extnerl Crystal stable time.
Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator
Typical Crystal Application Circuits
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 25 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing C1 and C2.
CRYSTAL
C1
C2
R1
4 MHz ~ 24 MHz
10 ~ 25 pF
10 ~ 25 pF
without
Sep. 1, 2020
Page 127 of 164
Rev 2.00
ML51/ML54/ML56
XT1_OUT
XT1_IN
R1
C1
C2
Table 8.3-4 Typical Crystal Application
Sep. 1, 2020
Page 128 of 164
Rev 2.00
ML51/ML54/ML56
8.3.4
External 4~24 MHz High Speed Clock Input Signal Characteristics
For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
Parameter
Min[1]
Typ
Max[1]
Unit
Test Conditions
External user clock source
frequency
fHXT_ext
4
-
24
MHz
tCHCX
tCLCX
tCLCH
Clock high time
Clock low time
8
8
-
-
-
-
ns
ns
Low (10%) to high level (90%)
rise time
Clock rise time
Clock fall time
-
-
-
-
10
10
ns
ns
High (90%) to low level (10%)
fall time
tCHCL
DuE_HXT
VIH
Duty cycle
40
0.7*VDD
VSS
-
-
-
60
VDD
%
V
Input high voltage
Input low voltage
VIL
0.3*VDD
V
External
clock source
XT1_IN
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Notes:
1. Guaranteed by characterization, not tested in production.
Table 8.3-5 External 4~24 MHz High Speed Clock Input Signal
Sep. 1, 2020
Page 129 of 164
Rev 2.00
ML51/ML54/ML56
8.3.5
External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in
order to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Min[1]
1.8
-40
-
Typ Max[1] Unit
Test Conditions[2]
Operation voltage
-
5.5
105
-
V
Temperature range
TLXT
Rf
-
6
C
Internal feedback resistor
Oscillator frequency
MΩ
kHz
FLXT
32.768
1.3
1.6
2
-
-
3.7
6
ESR=35 kΩ, Gain = L2
ESR=70 kΩ, Gain = L3
ILXT
Current consumption
A
TsLXT Stable time [3]
DuLXT Duty cycle
-
-
s
30
-
-
70
70
%
Rs
Equivalnet Series Resisotr(ESR)
35
kΩ Crystal @32.768 kHz
Notes:
1. Guaranteed by characterization, not tested in production.
2. L1 ~ L2 defined by SFR XLTCON[1:0] LXSG
3. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values, Value variable based on extnerl
Crystal stable time.
Table 8.3-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator Characteristics
Typical Crystal Application Circuits
CRYSTAL
C1
C2
R1
32.768 kHz, ESR < 70 KΩ
20 pF
20 pF
without
X32_OUT
X32_IN
R1
C1
C2
Table 8.3-7 Typical 32.768 kHz Crystal Application Circuit
Sep. 1, 2020
Page 130 of 164
Rev 2.00
ML51/ML54/ML56
8.3.6
I/O AC Characteristics
Symbol
Parameter
Typ.
4.6
2.9
6.6
4.3
8.5
8.0
4.0
2.1
4.9
3.0
9.5
5.4
5.6
3.4
8.1
5.1
15.1
9.6
4.8
2.1
6.4
3.0
12.7
5.4
Max[1]. Unit
Test Conditions[2]
CL = 30 pF, VDD >= 5.5 V
CL = 10 pF, VDD >= 5.5 V
CL = 30 pF, VDD >= 3.3 V
CL = 10 pF, VDD >= 3.3 V
CL = 30 pF, VDD >= 1.8 V
CL = 10 pF, VDD >= 1.8 V
CL = 30 pF, VDD >= 5.5 V
CL = 10 pF, VDD >= 5.5 V
CL = 30 pF, VDD >= 3.3 V
CL = 10 pF, VDD >= 3.3 V
CL = 30 pF, VDD >= 1.8 V
CL = 10 pF, VDD >= 1.8 V
CL = 30 pF, VDD >= 5.5 V
CL = 10 pF, VDD >= 5.5 V
CL = 30 pF, VDD >= 3.3 V
CL = 10 pF, VDD >= 3.3 V
CL = 30 pF, VDD >= 1.8 V
CL = 10 pF, VDD >= 1.8 V
CL = 30 pF, VDD >= 5.5 V
CL = 10 pF, VDD >= 5.5 V
CL = 30 pF, VDD >= 3.3 V
CL = 10 pF, VDD >= 3.3 V
CL = 30 pF, VDD >= 1.8 V
CL = 10 pF, VDD >= 1.8 V
CL = 30 pF, VDD >= 1.8 V
CL = 10 pF, VDD >= 1.8 V
5.1
3.3
8
Normal mode[4] output high (90%) to low level (10%)
falling time
tf(IO)out
tf(IO)out
tr(IO)out
ns
ns
ns
5
12.5
10.7
4.3
2.5
5.8
3.7
13.8
7.4
6.1
3.7
9.4
5.8
20.3
12.4
5.2
2.5
7.4
3.7
16.9
7.4
High slew rate mode [5] output high (90%) to low level
(10%) falling time
Normal mode[4] output low (10%) to high level (90%)
rising time
High slew rate mode [5] output low (10%) to high level
(90%) rising time
tr(IO)out
ns
[3]
fmax(IO)out
I/O maximum frequency
24
24
MHz
Notes:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
ꢅ
3. The maximum frequency is defined by
ꢃꢄ
ꢍꢄ.
ꢌ
ꢀꢁꢂ
ꢆꢄꢇꢄꢈꢉ ꢋꢉ
ꢊ
4. PxSR.n bit value = 0, Normal output slew rate
5. PxSR.n bit value = 1, high speed output slew rate
Table 8.3-8 I/O AC characteristics
Sep. 1, 2020
Page 131 of 164
Rev 2.00
ML51/ML54/ML56
8.4 Analog Characteristics
8.4.1 Reset and Power Control Block Characteristics
The maximum values are obtained for VDD = 1. 8V ~ 5.5 V and maximum ambient temperature (TA),
and the typical values for TA= 25 °C and VDD = 3.3 V.The parameters in below table are derived from
tests performed under ambient temperature unless otherwise specified.
Symbol
Parameter
POR Operating Current
LVR Operating Current
Min
Typ
60
Max
100
80
Unit
Test Conditions
AVDD = 5.5V
[1]
IPOR
-
-
µA
[1]
ILVR
30
AVDD = 5.5V
LVR Low Power Run Mode
Operating Current
0.5
1
AVDD = 5.5V
[1]
IBOD
BOD Operating Current
POR Reset Voltage
-
0.5
1.55
1.63
1.8
2
2.9
1.65
1.70
2
AVDD = 5.5V
VPOR
VLVR
VBOD
1.45
1.55
1.7
1.9
2.3
2.55
2.85
3.55
4.2
-
V
-
-
LVR Reset Voltage
BOD Brown-Out Detect Voltage
2.2
2.5
2.8
3.2
3.9
4.5
2
2.4
2.7
3
3.7
4.4
1
[1]
TLVR_SU
LVR Startup Time
LVR Respond Time
µs
-
-
-
[1]
TLVR_RE
-
15
20
LVR Low Power Run Mode
Respond Time
-
20
30
[1]
TBOD_SU
BOD Startup Time
BOD Respond Time
-
-
250
19
350
30
-
-
[1]
TBOD_RE
Notes:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
Table 8.4-1 Reset And Power Control Unit
Sep. 1, 2020
Page 132 of 164
Rev 2.00
ML51/ML54/ML56
8.4.2
12-bit SAR ADC
The maximum values are obtained for VDD = 1. 8V ~ 5.5 V and maximum ambient temperature (TA),
and the typical values for TA= 25 °C and VDD = 3.3 V.The parameters in below table are derived from
tests performed under ambient temperature unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
TA
Temperature
-40
-
105
℃
AV
AVDD
VREF
VIN
Analog Operating Voltage
Reference Voltage
1.8
1.8
0
-
-
-
VDD
AVDD
VREF
V
V
V
VDD
=
DD
AVDD − VREF < 1.2 V
ADC Channel Input Voltage
AVDD = VDD =VREF = 5 V
FADC = 500kHz
[1]
IADC
Operating Current (AVDD + VREF Current)
-
-
360
µA
Bit
NR
Resolution
12
-
[1]
FADC
ADC Conversion Rate
-
0.375
0.417
1
500
2.12
1.54
128
-
FADC ADC conversion rate
TSMP Sampling Time [2]
-
TSMP
Sampling Time [2]
-
TCONV
TEN
Conversion Time
-
1/FADC
Enable To Ready Time
Integral Non-Linearity Error
Differential Non-Linearity Error
Gain Error
20
-
μs
INL[1]
DNL[1]
-4
-
+4
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
-2
-
+4.5
+0.4
+2.5
+7
[1]
EG
-3.5
-2
-
[1]
EO
Offset Error
-
T
[1]
EA
Absolute Error
-7
Notes:
1.
2.
Guaranteed by characterization result, not tested in production.
4 * ADCAQT 6
ADC sampling time =.
, FADCAQT is defined in ADCDIV (ADCCON2[3:1]). As default FADCAQT = FSYS
F
ADCAQT
(ADCDIV=0),
3. Since the minima sampling time must over 370ns that means when FADCAQT = 24MHz, ADCAQT should be
defined as 1 at least. This value is defined by software.
Table 8.4-2 ADC Characteristics
Sep. 1, 2020
Page 133 of 164
Rev 2.00
ML51/ML54/ML56
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
Sep. 1, 2020
Page 134 of 164
Rev 2.00
ML51/ML54/ML56
8.4.3
Analog Comparator Controller (ACMP)
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the typical
values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
AVDD
TA
Parameter
Analog supply voltage
Temperature
Min
1.8
-40
Typ
Max
5.5
Unit
V
Test Conditions
VDD = AVDD
-
-
℃
105
IDD
Operating current
-
2
5
A
[2]
VCM
Input common mode voltage range
Differential input voltage sensitivity
Input offset voltage
Hysteresis window
0.35
1/2 AVDD AVDD -0.3
[2]
VDI
10
-
20
10
10
65
-
-
20
20
75
5
mV Hysteresis disable
[2]
Voffset
mV Hysteresis disable
[2]
Vhys
-
mV
dB
S
S
Av[1]
DC voltage Gain
45
-
[2]
Td
Propagation delay
[2]
TStable
Stable time
-
-
5
[2]
ACRV
CRV output voltage
Unit resistor value
-5
-
-
5
%
AVDD x (1/6+CRVCTL/24)
[2]
RCRV
4.5
-
kΩ
CRV output voltage settle
to ±5%
[2]
TSETUP_CRV
Stable time
-
-
-
2
-
µS
[2]
IDD_CRV
Operating current
2
A
Notes:
1. Guaranteed by design, not tested in production
2. Guaranteed by characteristic, not tested in production. unless otherwise specified.
Table 8.4-3 ACMP Characteristics
Sep. 1, 2020
Page 135 of 164
Rev 2.00
ML51/ML54/ML56
8.4.4
Internal Voltage Reference
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the
typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VREF_EXT
External Analog reference voltage
1.8
-
AVDD
AVDD >= 2.0 V, TA = 25°C
1.49
1.538
2.048
1.59
Internal analog reference voltage
VRFSEL[2:0] = 000 [2]
AVDD >= 2.4 V, TA = 25°C
Internal Analog reference voltage
VRFSEL[2:0] = 001[2]
2.018
2.078
Test in product.
AVDD >= 2.9 V, TA = 25°C
VREF_INT
Internal reference voltage
V
2.48
3.042
3.97
2.560
3.072
4.096
2.64
3.102
4.22
Internal analog reference voltage
VRFSEL[2:0] = 010 [2]
AVDD >= 3.4 V, TA = 25°C Internal
Analog reference voltage
VRFSEL[2:0] = 011[2]
Test in product.
AVDD >= 4.5 V, TA = 25°C
Internal analog reference voltage
VRFSEL[2:0] = 100 [2]
VBG
Band-gap voltage
Stable time
0.793
-
0.814
24
0.835
180
V
TA = -40°C ~105 °C, Test in product.
CL =1 uF, VREF initial=0, Preload is
enabled.
mS
Ts
CL =1 uF, VREF initial=5.5, Preload is
enabled.
-
2
2.6
mS
IVREF_INT
VREF_INT operating current
-
-
-
-
1
1
mA
mA
IVREF
_
LOAD
VREF_INT output loading current
Note:
1. Guaranteed by characterization, not tested in production
Table 8.4-4 Voltage Reference Character
VREF
1uF
Note: VREF_INT is only supported while package includes VREF pin with external capacitor.
Figure 8.4-1 Typical Connection With Internal Voltage Reference
Sep. 1, 2020
Page 136 of 164
Rev 2.00
ML51/ML54/ML56
8.4.5
Temperature Sensor
The maximum values are obtained for VDD = 1.8 ~ 5.5 V and maximum ambient temperature (TA), and
the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
[1]
VTEMP_OS
Tempereture sensor offset voltage
645
675
705
mV
[1]
TC
Temperature Coefficient
1.74
-
1.83
16
1.9
30
mV/℃
A
TJ = 25 ℃
[1]
ITEMP
Temperature sensor operating current
Note:
1. Guaranteed by characterization, not tested in production
2. VTEMP (mV) = TC (mV/°C) x Temperature (°C) + VTEMP_OS (mV)
Table 8.4-5 Temperature Sensor Character
Sep. 1, 2020
Page 137 of 164
Rev 2.00
ML51/ML54/ML56
8.4.6
LCD Controller
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical
values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
VDD
Parameter
Supply voltage
Min
1.8
1.8
0
Typ
Max
3.6
5.5
85
Unit
V
Test Conditions
-
-
VLCD
TA
LCD external pin voltage
Temperature
V
-
°C
0.1
µF Wihtout charge pump mode
With charge pump mode
VLCD pin external pin
capacitor[2]
CLCD
0.1
1
1
External charge-pump
capacitor[2]
The capacitor between DH1 and
DH2
CDH1-DH2
CVX
10
µF
V1/V2/V3 external capacitance
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N/A
5.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
VCP_SEL[5:0]=000000
VCP_SEL[5:0]=000101
VCP_SEL[5:0]=001010
VCP_SEL[5:0]=001110
VCP_SEL[5:0]=010011
VCP_SEL[5:0]=011000
VCP_SEL[5:0]=011101
5.2
5.0
4.8
4.6
4.4
4.2
LCD internal Charge Pump
Voltage Output Value
VLCDCP
V
VCP_SEL[5:0]=100010
4.0
VCP_SEL[5:0]=100111
VCP_SEL[5:0]=101100
VCP_SEL[5:0]=110000
VCP_SEL[5:0]=110101
VCP_SEL[5:0]=111010
VCP_SEL[5:0]=111111
3.8
3.6
3.4
3.2
3.0
2.8
V3/4
V2/4
V1/4
V2/3
V1/3
COM/SEG 3/4 VLCD (1/4 Bias)
COM/SEG 2/4 VLCD (1/4 Bias)
COM/SEG 2/4 VLCD (1/4 Bias)
COM/SEG 2/3 VLCD (1/3 Bias)
COM/SEG 1/3 VLCD (1/3 Bias)
3/4 VLCD
2/4 VLCD
1/4 VLCD
2/3 VLCD
1/3 VLCD
V
V
V
V
V
Resistor Mode total internal
Resistor Value
RR_MODE
240
6
-
-
KΩ
Resistor Enhance Mode total
internal Resistor Value
RRE_MODE
MΩ
VDD=1.8, VLCD=VCP=3.2, Buffer
Mode, all LCD display on
A
-
18
31
-
Supply current from VDD with built-
in charge pump and buffer mode
[3]
ILCD
VDD=1.8, VLCD=VCP=3.2, Resistor
Mode, all LCD display on
Sep. 1, 2020
Page 138 of 164
Rev 2.00
ML51/ML54/ML56
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD=1.8, VLCD=VCP=3.2, Resistor
Enhance Mode, all LCD display on
-
5.5
-
VDD=3.3, VLCD=VCP=5.4, Buffer
Mode, all LCD display on
-
-
-
24
1.8
7
-
-
-
VDD=1.8, VLCD=VCP=3.2, Buffer
Mode, all LCD display off
VDD=1.8, VLCD=3.3, Buffer Mode, all
LCD display on
VDD=1.8, VLCD=3.3, Resistor Mode,
all LCD display on
14
0.8
9.2
7
VDD=1.8, VLCD=3.3, Resistor
Enhance Mode, all LCD display on
Supply current from VLCD without
Bulit-In Charge Pump
[3]
IVLCD
A
VDD=1.8, VLCD=5.4, Buffer Mode, all
LCD display on
-
-
-
-
-
-
VDD=3.3, VLCD=3.3, Buffer Mode, all
LCD display on
VDD=1.8, VLCD=5.4, Buffer Mode, all
LCD display off
9
Notes:
1. All condition not special defined is guaranteed by design, not tested in production
2. CDH1-DH2 value should be 1/10 CLCD
3．LCD COM/SEG is set to clock source is LIRC, 1/8 duty, 1/4 bias, type B 64 Hz frame rate, all pixels active, waveform,
without LCD panel loading.
Table 8.4-6 LCD Digital Characteristics
LCD Voltage Source From Internal Charge Pump
Typ.
Unit
Resistor Enhance
Buffer Mode
Resistor Mode
Symbol Parameter
VDD
VLCD
Mode
0
25
85
0
25
85
0
25
85
℃
1.8V 3.2V
17
18
24
30
37
49
1.6
1.8
1.8
30
37
50
31
36
44
58
5
5.1
5.5
6.3
7
10
VDD Supply
Current in
Power Down
Mode with
LCD
On
3.2V
3.3V
20
22
22
24
29
31
5
39
52
1.6
2
6
7
6
6
5.4V
ILCDCPPD
LIRC,
VLCD
(LIRC)
1.8V 3.2V
1.6
1.8
1.8
17
1.6
1.6
1.8
1.8
5.5
6
1.6
2
5
source
internal
Charge
Pump
LCD
Off
3.2V
3.3V
2
5.7
5.7
25
5.7
5.7
37
45
59
5.7
5.7
11
16
17
µA
5.4V
2
2
2
1.8V 3.2V
18
22
24
32
40
52
6
VDD Supply
Current in
ILCDCPPD
Power Down LCD
3.2V
3.3V
21
30
6.5
7.5
Mode with
LXT,
On
(LXT)
5.4V
22
32
7
VLCD
Sep. 1, 2020
Page 139 of 164
Rev 2.00
ML51/ML54/ML56
Typ.
Resistor Mode
Unit
Resistor Enhance
Buffer Mode
Symbol Parameter
VDD
VLCD
Mode
0
25
85
0
25
85
0
25
85
℃
source
internal
Charge
Pump
1.8V 3.2V
1.6
1.6
5
1.6
1.8
1.8
1.6
5
1.6
1.6
2
5
LCD
Off
3.2V
3.3V
1.8
1.8
2
2
5.7
5.7
2
2
5.7
5.7
1.8
1.8
5.7
5.7
5.4V
2
Notes:
1. All condition not special defined is guaranteed by design, not tested in production
2. The values are obtained for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
3. LCD COM/SEG is set as 1/8 duty, 1/4 bias, type B 64 Hz frame rate, all pixels active, without LCD panel loading.
Table 8.4-7 Current Consumption In Power Down Mode With LCD Voltage Source From Internal
Charge Pump
LCD Voltage Source From AVDD
Typ.
Unit
Buffer Mode
25
Resistor Mode
Resistor Enhance
Mode
Symbol
Parameter
VLCD
0
85
0
25
85
0
25
85
℃
(AVDD
)
ILCDAVDDP
D(LIRC)
VDD Supply
Current in
Power Down
Mode with
LIRC,
LCD
On
1.8V
3.3V
1.8V
3.3V
1.8V
3.3V
1.8V
3.3V
6.2
9
6.8
9.5
6
13
15
11
9
16
9.2
16.4
8.3
13
21
2.1
2.6
1.2
1.6
2.7
3.2
1.2
1.6
2.4
3
6
7
LCD
Off
5.2
8
8
12
1.4
1.8
3
5
VLCD source
internal AVDD
8.5
7.5
10
6
13.5
5.2
14.2
9.6
16.8
8
14.6
10
19
6
µA
ILCDAVDDP
D(LXT)
VDD Supply
Current in
Power Down
Mode with
LXT,
LCD
On
6.6
9
12.1
19.2
12
4.8
5.8
5
6.2
14.5
8.3
3.5
1.4
1.8
LCD
Off
5.2
8
11
VLCD source
internal AVDD
8.5
13.5
14.2
14.6
19
6
Notes:
1. All condition not special defined is guaranteed by design, not tested in production
2. The values are obtained for TA= 25 °C unless otherwise specified.
3. LCD COM/SEG is set to 1/8 duty, 1/4 bias, 128 Hz frame rate, all pixels active, type B waveform, no LCD panel loading.
Table 8.4-8 Current Consumption In Power Down Mode With LCD Voltage Source From AVDD
Sep. 1, 2020
Page 140 of 164
Rev 2.00
ML51/ML54/ML56
LCD Voltage Source From External VLCD Pin
Typ.
Unit
Buffer Mode
Resistor Mode
Resistor Enhance
Mode
Symbol
Parameter
VLCD
0
25
85
0
25
85
0
25
85
℃
ILCDVLCDP
D(LIRC)
VLCD Supply
Current in
Power Down
Mode with
LIRC,
LCD
On
3.3
6.5
7
9
13.5
14
15
24
0.7
0.8
1.2
5.4V
3.3V
5.4V
3.3
8.6
6.5
8.3
6.5
8.6
6.5
8.3
9.2
7
11
8.5
11
9
22
14
23
14
23
14
23
14
23
1.2
0.5
0.9
0.7
1.2
0.5
0.9
1.2
0.6
1
2
1
LCD
Off
14.5
23.5
15
VLCD source
External
VLCD pin
9
22
2
µA
ILCDVLCDP
D(LXT)
Supply
LCD
On
7
13.5
22
0.8
1.2
0.6
1
1.2
2
Current in
Power Down
Mode with
LXT,
5.4V
3.3V
5.4V
9.2
7
11
8.5
11
24
LCD
Off
14
14.5
23.5
1
VLCD source
External
VLCD pin
9
22
2
Notes:
1. All condition not special defined is guaranteed by design, not tested in production
2. The values are obtained for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
3. LCD COM/SEG is set to 1/8 duty, 1/4 bias, 128 Hz frame rate, all pixels active, type B waveform, no LCD panel loading
Table 8.4-9 Current Consumption In Power Down Mode With LCD Voltage Source From External
VLCD pin
Sep. 1, 2020
Page 141 of 164
Rev 2.00
ML51/ML54/ML56
8.5 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
Symbol
Parameter
Supply voltage
Min
Typ
1.8
5
Max
Unit
Test Condition
[1]
VFLA
1.62
1.98
V
TERASE
TPROG
IDD1
Page erase time
Program time
Read current
-
-
-
-
-
-
-
-
-
-
ms
µs
10
4
TA = 25℃
mA
mA
mA
IDD2
Program current
Erase current
4
IDD3
12
NENDUR
Endurance
100,000
50
-
-
-
-
cycles[2]
year
TJ = -40℃~125℃
100 kcycle[3] TA = 55℃
100 kcycle[3] TA = 85℃
100 kcycle[3] TA = 105℃
-
-
-
TRET
Data retention
25
year
10
year
Notes:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles.
3. Guaranteed by design.
Table 8.5-1 Flash Memory Characteristics
Sep. 1, 2020
Page 142 of 164
Rev 2.00
ML51/ML54/ML56
8.6
Absolute Maximum Ratings
Volrage Stesses above the absolute maximum ratings may cause permanent damage to the device.
The limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
8.6.1
Voltage Characteristics
8.6.1.1 ML51 32KB/16KB Flash Series
Symbol
Description
Min
Max
6.5
50
Unit
V
[1]
VDD-VSS
ΔVDD
DC power supply
-0.3
Variations between different power pins
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
Input voltage on I/O
-
mV
mV
mV
mV
V
|VDD –AVDD
|
-
50
ΔVSS
-
50
|VSS - AVSS
|
-
50
VIN
VSS-0.3
6.5
Notes:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
Table 8.6-1 ML51 32KB/16KB Flash Series Voltage Characteristics
8.6.1.2 ML51 64KB Flash/ML54/ML56 Series
Symbol
Description
Min
Max
4.0
50
Unit
V
[1]
VDD-VSS
DC power supply
-0.3
ΔVDD
Variations between different power pins
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
Input voltage on I/O
-
mV
mV
mV
mV
V
|VDD –AVDD
|
-
50
ΔVSS
-
50
|VSS - AVSS
|
-
50
VIN
VSS-0.3
3.6
Notes:
2. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
Table 8.6-2 ML51 64KB Flash/ML54/ML56 Series Voltage Characteristics
Sep. 1, 2020
Page 143 of 164
Rev 2.00
ML51/ML54/ML56
8.6.2
Current Characteristics
Symbol
Description
Min
Max
150
150
22
Unit
[1]
ΣIDD
Maximum current into VDD
Maximum current out of VSS
-
-
-
-
-
-
-
-
ΣISS
Maximum current sunk by a I/O Pin
Maximum current sourced by a I/O Pin
Maximum current sunk by total I/O Pins[2]
Maximum current sourced by total I/O Pins[2]
Maximum injected current by a I/O Pin
Maximum injected current by total I/O Pins
10
IIO
mA
100
100
±5
[3]
IINJ(PIN)
[3]
ΣIINJ(PIN)
±25
Note:
1.
Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.
Table 8.6-3 Current Characteristics
Sep. 1, 2020
Page 144 of 164
Rev 2.00
ML51/ML54/ML56
8.6.3
Thermal Characteristics
The average junction temperature can be calculated by using the following equation:
T
T
+ (P
x
)
J
=
A
D
θJA
TA = ambient temperature (℃)
θJA = thermal resistance junction-ambient (℃/Watt)
P
D
= sum of internal and I/O power dissipation
Symbol
Description
Min
Typ
Max
Unit
T
A
-40
Operating ambient temperature
Operating junction temperature
Storage temperature
-
105
T
J
-40
-65
-
-
125
150
℃
T
ST
Thermal resistance junction-ambient
10-pin MSOP(3x3 mm)
℃/Watt
℃/Watt
℃/Watt
℃/Watt
℃/Watt
℃/Watt
℃/Watt
℃/Watt
℃/Watt
℃/Watt
℃/Watt
-
-
-
-
-
-
-
-
-
-
-
-
160
100
68
38
60
30
55
62
28
49
60
50
-
-
-
-
-
-
-
-
-
-
-
-
Thermal resistance junction-ambient
14-pin TSSOP( 4.4x5 mm)
Thermal resistance junction-ambient
20-pin QFN(3x3 mm)
Thermal resistance junction-ambient
20-pin TSSOP(4.4x6.5 mm)
Thermal resistance junction-ambient
20-pin SOP(300mil)
Thermal resistance junction-ambient
28-pin TSSOP(4.4x9.7 mm)
[1]
θJA
Thermal resistance junction-ambient
28-pin SOP(300 mil)
Thermal resistance junction-ambient
32-pin LQFP(7x7 mm)
Thermal resistance junction-ambient
33-pin QFN(4x4 mm)
Thermal resistance junction-ambient
44-pin LQFP(10x10 mm)
Thermal resistance junction-ambient
48-pin LQFP(7x7 mm)
Thermal resistance junction-ambient
64-pin LQFP(7x7 mm)
℃/Watt
Note:
1.
Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions
Table 8.6-4 Thermal Characteristics
Sep. 1, 2020
Page 145 of 164
Rev 2.00
ML51/ML54/ML56
8.6.4
EMC Characteristics
8.6.4.1 Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
8.6.4.2 Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
8.6.4.3 Electrical fast transients (EFT)
In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts
of narrow high-frequency transients on the power distribution system..
Inductive loads:
– Relays, switch contactors
– Heavy-duty motors when de-energized etc.
The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 by
International ElectrotechnicalCommission (IEC).
8.6.4.4 EMC Character Table
ML51 32KB/16KB Flash Series
Symbol
Description
Min
-8000
-1000
-150
Typ
Max
+8000
+1000
+150
Unit
[1]
VHBM
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[3] @VDD = 5.5V
Fast transient voltage burst
-
-
-
-
V
[2]
VCDM
LU[3]
mA
kV
[*4] [*5]
VEFT
-4.4
+4.4
Notes:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Table 8.6-5 ML51 32KB/16KB Flash Series EMC Characteristics
ML51 64KB Flash/ML54/ML56 Series
Symbol
Description
Min
-7000
-1000
-200
Typ
Max
+7000
+1000
+200
Unit
V
[1]
VHBM
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[3] @VDD = 3.6V
-
-
-
[2]
VCDM
LU[3]
mA
Sep. 1, 2020
Page 146 of 164
Rev 2.00
ML51/ML54/ML56
Symbol
Description
Fast transient voltage burst
Min
-4.4
Typ
Max
Unit
[*4] [*5]
VEFT
kV
-
+4.4
Notes:
1.
Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Table 8.6-6 ML51 64KB Flash/ML54/ML56 Series EMC Characteristics
Sep. 1, 2020
Page 147 of 164
Rev 2.00
ML51/ML54/ML56
8.6.5
Package Moisture Sensitivity(MSL)
The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing.
Pacakge
10-pin MSOP(3x3 mm) [1]
MSL
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
14-pin TSSOP( 4.4x5 mm) [1]
20-pin QFN(3x3 mm) [1]
20-pin TSSOP(4.4x6.5 mm) [1]
20-pin SOP(300mil) [1]
28-pin TSSOP(4.4x9.7 mm) [1]
28-pin SOP(300 mil) [1]
32-pin LQFP(7x7 mm) [1]
33-pin QFN(4x4 mm) [1]
44-pin LQFP(10x10 mm)
48-pin LQFP(7x7 mm) [1]
64-pin LQFP(7x7 mm) [1]
Note:
1. Determined according to IPC/JEDEC J-STD-020
Table 8.6-7 Package Moisture Sensitivity(MSL)
Sep. 1, 2020
Page 148 of 164
Rev 2.00
ML51/ML54/ML56
8.6.6
Soldering Profile
Figure 8.6-1 Soldering Profile From J-STD-020C
Porfile Feature
Pb Free Package
Average ramp-up rate (217℃ to peak)
Preheat temperature 150℃ ~200℃
Temperature maintained above 217℃
Time with 5℃ of actual peak temperature
Peak temperature range
3℃/sec. max
60 sec. to 120 sec.
60 sec. to 150 sec.
> 30 sec.
260℃
Ramp-down rate
6℃/sec ax.
8 min. max
Time 25℃ to peak temperature
Note:
1. Determined according to J-STD-020C
Table 8.6-8 Soldering Profile
Sep. 1, 2020
Page 149 of 164
Rev 2.00
ML51/ML54/ML56
9 PACKAGE DIMENSIONS
9.1 LQFP 64L-pin (7.0 x 7.0 x 1.4 mm)
Figure 9.1-1 LQFP 64L Package Dimension
Sep. 1, 2020
Page 150 of 164
Rev 2.00
ML51/ML54/ML56
9.2 LQFP 48-pin (7.0 x 7.0 x 1.4 mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
: Millimeters
Dimension in inch
Dimension in mm
Symbol
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
L
0.024 0.030
0.45
0.039
0.004
7
1
L
Y
0.10
7
0
0
0
Figure 9.2-1 LQFP-48 Package Dimension
Sep. 1, 2020
Page 151 of 164
Rev 2.00
ML51/ML54/ML56
9.3 LQFP 44-pin (10 x 10 x 1.4mm
Figure 9.3-1 LFP44 Package Dimension
Sep. 1, 2020
Page 152 of 164
Rev 2.00
ML51/ML54/ML56
9.4 QFN 33-pin (4.0 x 4.0 x 0.8 mm)
Figure 9.4-1 QFN-33 Package Dimension
Sep. 1, 2020
Page 153 of 164
Rev 2.00
ML51/ML54/ML56
9.5 LQFP 32-pin (7.0 x 7.0 x 1.4 mm)
Figure 9.5-1 LQFP-32 Package Dimension
Sep. 1, 2020
Page 154 of 164
Rev 2.00
ML51/ML54/ML56
9.6 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm)
Figure 9.6-1 TSSOP-28 Package Dimension
Sep. 1, 2020
Page 155 of 164
Rev 2.00
ML51/ML54/ML56
9.7 SOP 28-pin (300mil)
15
28
E
1
14
Control demensions are in milmeters .
E
Figure 9.7-1 SOP-28 Package Dimension
Sep. 1, 2020
Page 156 of 164
Rev 2.00
ML51/ML54/ML56
9.8 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm)
Figure 9.8-1 TSSOP-20 Package Dimension
Sep. 1, 2020
Page 157 of 164
Rev 2.00
ML51/ML54/ML56
9.9 SOP 20-pin (300 mil)
11
20
E
1
10
Control demensions are in milmeters .
E
Figure 9.9-1 SOP-20 Package Dimension
Sep. 1, 2020
Page 158 of 164
Rev 2.00
ML51/ML54/ML56
9.10 QFN 20-pin ( 3.0 x 3.0 x 0.8 mm )
Figure 9.10-1 QFN-20 Package Dimension
Sep. 1, 2020
Page 159 of 164
Rev 2.00
ML51/ML54/ML56
9.11 TSSOP 14-pin (4.4 x 5.0 x 0.9 mm)
Figure 9.11-1 TSSOP-14 Package Dimension
Sep. 1, 2020
Page 160 of 164
Rev 2.00
ML51/ML54/ML56
9.12 MSOP 10-pin (3.0 x 3.0 x 0.85 mm)
Figure 9.12-1 MSOP-10 Package Dimension
Sep. 1, 2020
Page 161 of 164
Rev 2.00
ML51/ML54/ML56
10 ABBREVIATIONS
10.1 Abbreviations
Acronym
ADC
BOD
GPIO
Fsys
HIRC
IAP
Description
Analog-to-Digital Converter
Brown-out Detection
General-Purpose Input/Output
Frequency of system clock
12 MHz Internal High Speed RC Oscillator
In Application Programming
In Circuit Programming
In System Programming
Liquid Crystal Displays
ICP
ISP
LCD
LDO
LIRC
LVR
Low Dropout Regulator
10 kHz internal low speed RC oscillator (LIRC)
Low Voltage $eset
PDMA
POR
PWM
RTC
SPI
Peripheral Direct Memory Access
Power On Reset
Pulse Width Modulation
Real Time Clock
Serial Peripheral Interface
Touch Key
TK
UART
UCID
WKT
WDT
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Wakeup Timer
Watchdog Timer
Table 10.1-1 List of Abbreviations
Sep. 1, 2020
Page 162 of 164
Rev 2.00
ML51/ML54/ML56
11 REVISION HISTORY
Date
Revision
Description
Initial release.
Section 3.1
2018.12.05
1.00
Added package type table.
Section 4.2.2 Added Multi-function summary table.
Section 6.2 Added ICP connect circuit.
Section 7.2.4 Modified ISR value.
2019.09.03
1.01
Section 7.3
Removed 32.768kHz external clock input and deviation figure.
Section 7.4.1 Modified POR/LVR/BOD operating current value.
Section 7.6.1 Modified DC power supply item.
Section 8.6
Modified TSSOP20 package dimension in title.
Section 37.6 Modified TSSOP20 package value.
Section 6.2 Added note in application circuit.
Section 7.4.2 Added RS and CIN value in table.
2020.03.11
1.02
Section 7.4.4 Added section 7.4.4. Moved internal voltage character table to
this section.
Chapter 8.1 Modified QFN33 package L value to 0.3.
Chapter 7.6.2 Modified Maximum current to 150mA
Chapter 7.6.4 Modified Pin current for latch-up value to 150mA .
Modified Fast transient voltage burst value to 4.4kV.
2020.06.29
2020.09.01
1.03
2.00
Chapter 7.4.2 Modified ADC conversion rate and sampling timing description.
Added ML51 64KB/ML54/ML56 Series description.
Sep. 1, 2020
Page 163 of 164
Rev 2.00
ML51/ML54/ML56
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Sep. 1, 2020
Page 164 of 164
Rev 2.00
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
©2020 ICPDF网 联系我们和版权申明