N79E8432 [NUVOTON]
Nuvoton 8051-based Microcontroller;
| 型号： | N79E8432 |
| 厂家： | 
NUVOTON |
| 描述： | Nuvoton 8051-based Microcontroller 微控制器 |
| 文件： | 总183页 (文件大小：3711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nuvoton 8051-based Microcontroller
N79E845
N79E844
N79E8432
Data Sheet
Version: A2.6
N79E845/844/8432 Data Sheet
Table of Contents
1
2
3
4
5
6
GENERAL DESCRIPTION...................................................................................................................................5
FEATURES............................................................................................................................................................6
PARTS INFORMATION LIST..............................................................................................................................8
BLOCK DIAGRAM...............................................................................................................................................9
PIN CONFIGURATION......................................................................................................................................10
MEMORY ORGANIZATION.............................................................................................................................13
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
APROM Flash memory...........................................................................................................................14
LDROM Flash Memory..........................................................................................................................14
CONFIG-bits...........................................................................................................................................14
On-chip Non-volatile Data Flash ............................................................................................................14
On-chip XRAM.......................................................................................................................................16
On-chip scratch-pad RAM and SFR .......................................................................................................16
Working Registers...................................................................................................................................17
Bit-addressable Locations .......................................................................................................................18
Stack........................................................................................................................................................18
7
8
9
SPECIAL FUNCTION REGISTER (SFR) ..........................................................................................................19
GENERAL 80C51 SYSTEM CONTROL............................................................................................................24
I/O PORT STRUCTURE AND OPERATION ....................................................................................................28
9.1
Quasi-Bidirectional Output Configuration..............................................................................................28
9.1.1 Read-Modify-Write ....................................................................................................................29
Open Drain Output Configuration...........................................................................................................30
Push-Pull Output Configuration..............................................................................................................30
Input Only Configuration........................................................................................................................31
9.2
9.3
9.4
10
TIMERS/COUNTERS .........................................................................................................................................34
10.1
Timers/Counters 0 and 1 .........................................................................................................................34
10.1.1 Mode 0 (13-bit Timer)..............................................................................................................38
10.1.2 Mode 1 (16-bit Timer)..............................................................................................................39
10.1.3 Mode 2 (8-bit Auto-Reload Timer) ..........................................................................................39
10.1.4 Mode 3 (Two Separate 8-bit Timers) .......................................................................................40
Timer/Counter 2......................................................................................................................................41
10.2.1 Input Capture Mode..................................................................................................................44
10.2.2 Auto-reload Mode ....................................................................................................................48
10.2.3 Compare Mode.........................................................................................................................48
10.2
11
12
WATCHDOG TIMER (WDT).............................................................................................................................50
11.1
11.2
11.3
Functional Description ............................................................................................................................50
Applications of Watchdog Timer Reset ..................................................................................................53
Applications of Watchdog Timer Interrupt .............................................................................................54
SERIAL PORT (UART).......................................................................................................................................56
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Mode 0 ....................................................................................................................................................58
Mode 1 ....................................................................................................................................................60
Mode 2 ....................................................................................................................................................62
Mode 3 ....................................................................................................................................................64
Baud Rates ..............................................................................................................................................66
Framing Error Detection .........................................................................................................................67
Multiprocessor Communication..............................................................................................................67
Automatic Address Recognition .............................................................................................................68
13
SERIAL PERIPHERAL INTERFACE (SPI).......................................................................................................71
13.1 Features ...................................................................................................................................................71
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13.2
13.3
13.4
Functional Description ............................................................................................................................71
SPI Control Registers..............................................................................................................................73
Operating Modes.....................................................................................................................................76
13.4.1 Master Mode.............................................................................................................................76
13.4.2 Slave Mode...............................................................................................................................77
Clock Formats and Data Transfer ...........................................................................................................77
Slave Select Pin Configuration................................................................................................................80
Mode Fault Detection..............................................................................................................................80
Write Collision Error...............................................................................................................................81
Overrun Error..........................................................................................................................................81
13.5
13.6
13.7
13.8
13.9
13.10 SPI Interrupts..........................................................................................................................................82
KEYBOARD INTERRUPT (KBI).......................................................................................................................84
ANALOG-TO-DIGITAL CONVERTER (ADC) ................................................................................................88
INTER-INTEGRATED CIRCUIT (I2C) ..............................................................................................................94
14
15
16
16.1
16.2
Features ...................................................................................................................................................94
Functional Description ............................................................................................................................94
16.2.1 START and STOP Conditions..................................................................................................95
16.2.2 7-bit Address with Data Format ...............................................................................................96
16.2.3 Acknowledge............................................................................................................................97
16.2.4 Arbitration ................................................................................................................................98
Control Registers of I2C ..........................................................................................................................99
Operation Modes...................................................................................................................................102
16.4.1 Master Transmitter Mode .......................................................................................................102
16.4.2 Master Receiver Mode............................................................................................................103
16.4.3 Slave Receiver Mode..............................................................................................................104
16.4.4 Slave Transmitter Mode .........................................................................................................105
16.4.5 General Call............................................................................................................................106
16.4.6 Miscellaneous States...............................................................................................................107
16.3
16.4
16.5
16.6
16.7
Typical Structure of I2C Interrupt Service Routine ...............................................................................108
I2C Time-out..........................................................................................................................................111
I2C Interrupts.........................................................................................................................................112
17
PULSE WIDTH MODULATED (PWM) ..........................................................................................................113
17.1
17.2
Features .................................................................................................................................................113
Functional Description ..........................................................................................................................113
18
19
TIMED ACCESS PROTECTION(TA)..............................................................................................................123
INTERRUPT SYSTEM......................................................................................................................................125
19.1
19.2
19.3
19.4
Interrupt Sources ...................................................................................................................................125
Priority Level Structure.........................................................................................................................127
Interrupt Response Time .......................................................................................................................131
SFR of Interrupt ....................................................................................................................................131
20
IN SYSTEM PROGRAMMING (ISP)...............................................................................................................137
20.1
20.2
20.3
20.4
20.5
ISP Procedure........................................................................................................................................137
ISP Command Table .............................................................................................................................141
Access Table of ISP Programming .......................................................................................................142
ISP User Guide......................................................................................................................................142
ISP Demo Code.....................................................................................................................................143
21
22
POWER MANAGEMENT.................................................................................................................................146
21.1
21.2
Idle Mode..............................................................................................................................................146
Power-down Mode................................................................................................................................147
CLOCK SYSTEM..............................................................................................................................................149
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N79E845/844/8432 Data Sheet
22.1
22.2
On-Chip RC Oscillator..........................................................................................................................151
Crystal/Resonator..................................................................................................................................151
23
24
POWER MONITORING....................................................................................................................................152
23.1
23.2
Power-on Detection...............................................................................................................................152
Brown-out Detection.............................................................................................................................152
RESET CONDITIONS.......................................................................................................................................155
24.1
24.2
24.3
24.4
24.5
24.6
24.7
Power-on Reset .....................................................................................................................................155
BOD Reset ............................................................................................................................................156
RST Pin Reset .......................................................................................................................................157
Watchdog Timer Reset..........................................................................................................................157
Software Reset ......................................................................................................................................158
Boot Selection.......................................................................................................................................159
Reset State.............................................................................................................................................160
25
CONFIG BITS (CONFIG) .................................................................................................................................162
25.1
25.2
25.3
25.4
CONFIG0..............................................................................................................................................162
CONFIG1 (N79E845 Only)..................................................................................................................163
CONFIG2..............................................................................................................................................164
CONFIG3..............................................................................................................................................165
26
27
28
INSTRUCTION SETS .......................................................................................................................................167
IN-CIRCUIT PROGRAM (ICP) ........................................................................................................................171
ELECTRICAL CHARACTERISTICS...............................................................................................................173
28.1
28.2
28.3
Absolute Maximum Ratings..................................................................................................................173
DC Electrical Characteristics ................................................................................................................173
AC Electrical Characteristics ................................................................................................................177
28.3.1 10-bits SAR-ADC Specification.............................................................................................177
28.3.2 4 ~ 24 MHz XTAL Specifications..........................................................................................178
28.3.3 Internal RC Oscillator Specifications － 22.1184 MHz/11.0592 MHz..................................178
28.3.4 Internal RC Oscillator Specifications － 10 kHz....................................................................179
29
30
APPLICATION CIRCUIT FOR EMC IMMUNITY .........................................................................................180
PACKAGE DIMENSIONS................................................................................................................................181
30.1
30.2
20-pin TSSOP - 4.4X6.5mm.................................................................................................................181
16-pin SOP - 150 mil ............................................................................................................................182
31
DOCUMENT REVISION HISTORY................................................................................................................183
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N79E845/844/8432 Data Sheet
1 General Description
The N79E845/844/8432 8-bit Turbo 51 (4T Mode) microcontroller is embedded with 16K[1]/8K/4K bytes Flash EPROM
which can be programmed through universal hardware writer, serial ICP (In Circuit Program) programmer, software ISP
function. The instruction sets of the N79E845/844/8432 is fully compatible with the standard 8052. The
N79E845/844/8432 contains 16K/8K/4K bytes Application Flash EPROM (APROM) memory, 4 Kbytes Data Flash
memory, and 2 Kbytes Load Flash EPROM (LDROM) memory; 256 bytes direct and indirect RAM, 256 bytes XRAM;
17 I/O with bit-addressable I/O ports; two 16-bit timers/counters; 7-channel multiplexed 10-bit A/D converter; 4-channel
10-bit PWM; three serial ports including a SPI, I2C and an enhanced full duplex serial port; 2-level BOD voltage detec-
tion/reset, and power-on reset (POR). The N79E845/844/8432 also supports internal RC oscillator at the nominal frequen-
cy of 22.1184 MHz. The accuracy of RC oscillator (22.1184 MHz) is trimmed as ±1% under the condition of room tem-
perature and VDD = 5V before shipping from by factory trimming mechanism, which peripherals are supported by 14
sources of four-level interrupt capability. To facilitate programming and verification, the Flash EPROM inside the
N79E845/844/8432 allows the program memory to be programmed and read electronically. Once the code is confirmed,
the user can protect the code for security.
The N79E845/844/8432 microcontroller, featuring wide operating voltage range, built-in rich analog and digital periph-
erals and non-volatile Flash memory, is widely suitable for general control and home appliances.
[1] For N79E845, Data Flash and APROM share 16 Kbytes space.
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2 Features
Core
Fully static design 8-bit Turbo 51 (4T) CMOS microcontroller
Instruction sets fully compatible with the MCS-51
Operating voltage range
VDD = 4.5V to 5.5V at FOSC up to 24MHz
V
V
DD = 3.0V to 5.5V at Internal RC 22.1184MHz
DD = 2.4V to 5.5V at FOSC = 4~12MHz or Internal RC 11.0592MHz
Operating temperature range
-40°C ~85°C
Clock Source
High-speed external oscillator:
Up to 24 MHz Crystal and resonator (enabled by CONFIG-bits)
Internal RC oscillator: 22.1184MHz/11.0592MHz (selectable by CONFIG-bits)
-
-
-
-
-
±1% at VDD = 5V and 25°C
±3% at VDD = 2.7V ~ 5.5V and 25°C
±5% at VDD = 2.7V ~ 5.5V and -10°C~+70°C
±8% at VDD = 2.7V ~ 5.5V and -40°C ~ 85°C
Flexible CPU clock source configurable by CONFIG-bits and software
8-bit Programmable CPU clock divider(DIVM)
On-chip Memory
100,000 erase/write cycles
N79E845: 16 Kbytes shared by APROM and Data Flash depending on CONFIG-bits definitions
N79E844: 8 Kbytes APROM, 4 Kbytes Data Flash
N79E8432: 4 Kbytes APROM, 4 Kbytes Data Flash
APROM, LDROM and Data Flash security protection
Flash page size as 128 bytes
256 bytes of on-chip direct/indirect RAM
256 bytes of XRAM, accessed by MOVX instruction
On-chip Flash programmed through
-
-
-
Parallel H/W Writer mode
Serial In-Circuit-Program mode (ICP)
Software Implemented ISP (In-System-Program)
I/O Ports
Maximum 17 I/O pins
All I/O pin besides P1.2 and P1.3 support 4 software configurable output modes
Software selectable TTL or Schmitt trigger input type per port
14 interrupt sources with four levels of priority
LED drive capability 38mA on P10, P11, P14, P16, P17
LED drive capability 20mA on port 0 and port 3
Timer/Counter
Two sets 16-bit Timers/Counters
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One 16-bit Timer with two channel of input captures
Watchdog Timer
Programmable Watchdog Timer
Clock source supported by internal 10kHz ±50% accuracy RC oscillator
Serial ports (UART, SPI, I2C)
One set of enhanced full duplex UART port with framing error detection and automatic address recognition.
One set SPI with master/slave capability.
One set I2C with master/slave capability
PWM
4 channels 10-bit PWM outputs with one brake/fault input
KBI
8-keypad interrupt inputs(KBI) with 8 falling/rising/both-edge detection pins selected by software
ADC
10-bit A/D converter
Up to 150 Ksps.(sample per second)
7 analog input channels
Brown-out Detector
2-level (3.8V/2.7V) BOD detector
Supports interrupt and reset options
POR (Power on Reset)
Threshold voltage levels as 2.0V
Built-in power management.
Idle mode
Power-down mode with optionally enabled WDT functions
Development Tools
Hardware writer
ICP programmer
ISP update APROM by UART port
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N79E845/844/8432 Data Sheet
3 Parts Information List
Table 3-1 Lead Free (RoHS) Parts Information List
PART NO.
APROM
LDROM
RAM
512B
512B
512B
DATA FLASH
PACKAGE
N79E845AWG
N79E844AWG
N79E8432ASG
16KB
8KB
4KB
2KB
2KB
2KB
Share APROM
4KB
TSSOP-20 Pin
TSSOP-20 Pin
SOP-16 Pin
4KB
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4 Block Diagram
P1.0
|
P1.7
Port 1
Latch
P0.0
|
P0.7
Port 1
Port 0
Latch
Port 0
ACC
B
T1 Register
T2 Register
DPTR
Interrupt
DPTR1
Timer Reg.
PC
Stack
Pointer
PSW
ALU
Input
Capture/
Timer 2
Timer
1
Incrementor
SFR & RAM
Address
Flash EPROM
ADC
Timer
0
Instruction
Decoder
&
256 bytes
RAM & SFR
I2C, SPI
KBI
UART
Sequencer
PWM
256 XRAM
P3.0
|
P3.1
Port 3
Latch
Port 3
On-Chip
RC
Oscillator
Bus & Lock
Controller
Oscillator
Power Control
&
Power Monitor
Reset Block
XTAL1
XTAL2
On-Chip
RC
Watchdog Timer
10 KHz
GND
VDD
RST
Figure 4–1 N79E845/844/8432 Function Block Diagram
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5 Pin Configuration
1
2
3
20
SPICLK, KB0, PWM3, P0.0
P0.1, ADC0, PWM0, KB1
P0.2, ADC1, BRAKE, KB2
P0.3, ADC2, KB3
19
18
17
16
15
14
13
12
11
ICPCLK, MOSI, PWM2, P1.7
ICPDATA, MISO, PWM1, P1.6
RST
P0.4, ADC3, KB4
4
5
VSS
XTAL1, P3.1
P0.5, ADC4, KB5
20 PIN
6
VDD
7
XTAL2, CLKOUT, P3.0
P0.6, ADC5, KB6
P0.7, ADC6 T1, KB7, IC1
P1.0, TXD
8
SS, STADC, INT1, P1.4
SDA, INT0, P1.3
9
10
P1.1, RXD
IC0, SCL, T0, P1.2
Figure 5–2 TSSOP/SOP 20- pin Assignment
1
2
3
16
15
14
13
12
11
10
9
KB0, PWM3, P0.0
ICPCLK, PWM2, P1.7
ICPDATA, PWM1, P1.6
RST
P0.1, ADC0, PWM0, KB1
P0.2, ADC1, BRAKE, KB2
P0.3, ADC2, KB3
P0.4, ADC3, KB4
VDD
4
5
6
7
8
16 PIN
VSS
XTAL1, P3.1
P1.0, TXD
XTAL2, CLKOUT, P3.0
SDA, INT0, P1.3
P1.1, RXD
P1.2, IC0, SCL, T0
Figure 5–3 SOP 16- pin Assignment
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Table 5–1 Pin Description
Pin number
Sym-
Alternate Function
Type
Description
SOP20
SOP16
1
2
3
TSSOP20
12
5
15
5
VDD
P
P
POWER SUPPLY: Supply voltage VDD for operation.
GROUND: Ground potential
VSS
RESET: Chip reset pin that is low active. Because reset pin has
internal pull-up resistor (about 200 KΩat VDD = 5V), this pin can-
not be floating. Reset pin should be connected to 100Ω pull-up
resistor and 10uF pull-low capacitor.
I
4
4
/RST
(ST)
PORT0: Port 0 has 4-type I/O port. Its multifunction pins are for PWM0,
PWM3, T1, BRAKE, SPICLK, ADC0~ADC6 and KB0~KB7.
1
16
15
14
13
-
1
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
PWM3
PWM0
BRAKE
KB0
SPICLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D
ADC0 ~ADC6: ADC channel input.
KB0 ~ KB7: Key Board Input
20
19
18
17
16
14
13
12
11
10
9
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
KB1
KB2
KB3
KB4
KB5
KB6
KB7
The PWM0 and PWM3 is PWM output channel.
T1: Timer 1 External Input
SPICLK: SPI-1 clock pin
-
-
T1
TXD
RXD
T0
IC1
PORT1: Port 1 has 4-type I/O port. Its multifunction pins are for TXD, RXD,
T0, /INT0, /INT1, SCL, SDA, STADC, ICPDAT, ICPCLK and /SS, MISO,
MOSI.
11
10
9
The TXD and RXD are UART port
The SCL and SDA are I2C function with open-drain port.
The ICPDAT and ICPCLK are ICP (In Circuit Programming) function pin.
The /SS, MISO, MOSI are SPI-1 function pins.
The PWM1 and PWM2 are PWM output channel
T0: Timer 0 External Input
SCL
SDA
IC0
8
/INT0
D
IC0/1: Input Capture pin
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Table 5–1 Pin Description
Pin number
Sym-
Alternate Function
Type
Description
SOP20
SOP16
1
2
3
TSSOP20
STADC: ADC trigger by external pin
-
8
3
2
7
P1.4
P1.6
P1.7
P3.0
/INT1
PWM1
PWM2
XTAL2
STADC
ICPDAT
ICPCLK
CLKOUT
/SS
I/O
I/O
I/O
I/O
3
2
7
MISO
MOSI
PORT3: Port 3 has 4-type I/O port. Its multifunction pins are for
XTAL1, XTAL2 and CLKOUT,
CLKOUT: Internal RC OSC/4 output pin.
XTAL2: This is the output pin from the internal inverting amplifier. It
emits the inverted signal of XTAL2.
6
6
P3.1
XTAL1
I/O
XTAL1: This is the output pin from the internal inverting amplifier. It
emits the inverted signal of XTAL1.
[1] I/O type description I: input, O: output, I/O: quasi bi-direction, D: open-drain, P: power pins, ST: Schmitt trigger.
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6 Memory Organization
The N79E845/844/8432 has embedded Flash EPROM including 16K/8K/4K bytes Application Program Flash memory
(APROM), fixed 4K bytes Data Flash (except the device with 16K APROM), fixed 2K bytes Load ROM Flash memory
(LDROM) and CONFIG-bits. The N79E845/844/8432 also provides 256 bytes of on-chip direct/indirect RAM and 256
bytes of XRAM accessed by MOVX instruction.
For the device of 16K-bytes APROM, the APROM block and Data Flash block comprise the 16K bytes embedded Flash.
The block size is CONFIG-bits/software configurable.
The N79E845/844/8432 is built with a CMOS page-erase. The page-erase operation erases all bytes within a page of 128
bytes.
00FFH
0FFH
Config-bits
LDROM
Data Flash
0000H
07FFH
128 bytes/page
256 Bytes
on-chip XRAM
Page n =128B
0000H
3FFFH
000H
XRAM accessed by MOVX
instruction
Data Flash
CHBDA
Or
SHBDA
FFH
Page 1 = 128B
SFR
Indirect
16K
Direct
RAM
Page 0 = 128B
Addressing
Addressing
Only
80H
7FH
Data Flash Memory Area
16K/8K/4K
Bytes
APROM
Direct
&
Indirect
RAM
16K: N79E845
8K: N79E844
4K: N79E8432
Addressing
00H
0000H
Direct/Indirect RAM
Accessed by MOV instruction
Program Memory Space
Flash Type
Data Memory Space
SRAM Type
Figure 6-1 N79E845/844/8432 Memory Map
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N79E845/844/8432 Data Sheet
6.1 APROM Flash memory
The N79E845/844/8432 has 16K/8K/4K Program Memory. All instructions are fetched for execution from this memory
area. The MOVC instruction can also read this memory region.
The user application program is located in APROM. When CPU boots from APROM (CHPCON.BS=0), CPU starts exe-
cuting the program from address 0000H. If the value of program counter (PC) is over the space of APROM, CPU will
execute NOP operand and program counter increases one by one until PC reaches 3FFFH then it wraparounds to address
0000H of APROM, the CPU executes the application program again.
6.2 LDROM Flash Memory
Each device of the N79E845/844/8432 is equipped with 2 Kbytes LDROM stored the ISP application program. User may
develop the ISP function in LDROM for updating application program or Data Flash. Similarly, APROM can also re-
program LDROM and Data Flash. The start address of LDROM is at 0000H corresponding to the physical address of the
Flash memory. However, when CPU runs in LDROM, CPU automatically re-vectors the LDROM start address to 0000H,
therefore user program regards the LDROM as an independent program memory, meanwhile, with all interrupt vectors
that CPU provides.
6.3 CONFIG-bits
There are several bytes of CONFIG-bits located CONFIG-bits block. The CONFIG-bits define the CPU initial setting
after power up or reset. Only hardware parallel writer or hardware ICP writer can erase/program CONFIG-bits. ISP pro-
gram in LDROM can also erase/program CONFIG-bits.
6.4 On-chip Non-volatile Data Flash
The N79E845/844/8432 additionally has non-volatile Data Flash, which is non-volatile so that it remains its content even
after the power is off. Therefore, in general application the user can write or read data which rules as parameters or con-
stants. By the software path, SP mode can erase, written, or read the Data Flash only . Of course, hardware with parallel
Programmer/Writer or ICP programmer can also access the Data Flash.
The Data Flash size is software adjustable in N79E845 (16KB) by updating the content of SHBDA. SHBDA[7:0] repre-
sents the high byte of 16-bit Data Flash start address and the low byte is hardware set to 00H. The value of SHBDA is
loaded from the content of CONFIG1 (CHBDA) after all resets. The application program can dynamically adjust the Data
Flash size by resetting SHBDA value. Once the Data Flash size is changed the APROM size is changed accordingly.
SHBDA has time access protection while a write to SHBDA is required. The Data Flash size will be 15.75k bytes and
there will is 256 bytes APROM.
The Data Flash size is fixed as 4 Kbytes from address 3000H through 3FFFH in N79E844/8432. SHBDA affects nothing.
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N79E845/844/8432 Data Sheet
The CONFIG bit DFEN (CONFIG0.0) should be programmed as 0 before accessing the Data Flash block. If DFEN re-
mains its un-programmed value 1, APROM will occupy whole 16K-bytes block in N79E845 DFEN.
N79E845
N79E844
N79E8432
0000H
3FFFH
3000H
3FFFH
Data Flash
(4KB)
Data Flash
(4KB)
Data Flash
3000H
Reserved
CHBDA
or
SHBDA
[1]
2000H
Reserved
APROM
APROM
(8KB)
1000H
0000H
APROM
(4KB)
0000H
0000H
[1] The address is [SHBDA, 00H] while DFEN (CONFIG0.0) is enabled.
Figure 6–2 N79E845/844/8432 Data Flash
SHBDA – SFR High Byte of Data Flash Starting Address (TA protected, N79E845 Only)
7
6
5
4
3
2
1
0
SHBDA[7:0] [1]
R/W
Address: 9CH Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
Description
7:0
SHBDA[7:0] SFR high byte of Data Flash starting address
This byte is valid only when DFEN (CONFIG0.0) being 0 condition. It is used to
dynamic adjust the starting address of the Data Flash when the application pro-
gram is executing.
[1] SHBDA is loaded from CONFIG1 after all resets.
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6.5 On-chip XRAM
The N79E845/844/8432 provides additional on-chip 256 bytes auxiliary RAM called XRAM to enlarge the RAM space. It
occupies the address space from 00H through FFH. The 256 bytes of XRAM are indirectly accessed by move external
instruction MOVX @DPTR or MOVX @Ri. (See the demo code below.) Note that the stack pointer may not be located in
any part of XRAM. Figure 6-1 shows the memory map for this product series.
XRAM demo code:
MOV
MOV
MOVX
R0,#23H
A,#5AH
@R0,A
;write #5AH to XRAM with address @23H
MOV
MOVX
R1,#23H
A,@R1
;read from XRAM with address @23H
MOV
MOV
DPTR,#0023H
A,#5BH
;write #5BH to XRAM with address @0023H
MOVX
@DPTR,A
MOV
MOVX
DPTR,#0023H
A,@DPTR
;read from XRAM with address @0023H
6.6 On-chip scratch-pad RAM and SFR
The N79E845/844/8432 provides the on-chip 256 bytes scratch pad RAM and Special Function Registers (SFRs) which
be accessed by software. The SFRs be accessed only by direct addressing, while the on-chip RAM be accessed by either
direct or indirect addressing.
FFH
SFR
Indirect
Direct
RAM
Addressing
Addressing
Only
80H
7FH
Direct
&
Indirect
RAM
Addressing
00H
Figure 6-3 256 bytes RAM and SFR
Since the scratch-pad RAM is only 256 byte it can be used only when data contents are small. There are several other spe-
cial purpose areas within the scratch-pad RAM, which are described as follows.
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FFH
FFH
Indirect Accessing RAM
80H
7FH
Direct or Indirect Accessing RAM
30H
2FH 7F
7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06
7D
75
6D
65
5D
55
4D
45
3D
35
2D
25
1D
15
0D
05
7C
74
6C
64
5C
54
4C
44
3C
34
2C
24
1C
14
0C
04
7B
73
6B
63
5B
53
4B
43
3B
33
2B
23
1B
13
0B
03
7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02
79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
2EH 77
2DH 6F
2CH 67
2BH 5F
2AH 57
29H 4F
28H 47
27H 3F
26H 37
25H 2F
24H 27
23H 1F
22H 17
21H 0F
20H 07
1FH
Register Bank 3
Register Bank 2
Register Bank 1
Register Bank 0
18H
17H
10H
0FH
08H
07H
00H
00H
Figure 6-4 Data Memory and Bit-addressable Region
6.7 Working Registers
There are four sets of working registers, each consisting of eight 8-bit registers, which are termed as Banks 0, 1, 2, and 3.
Individual registers within these banks can be directly accessed by separate instructions, which individual registers are
named as R0, R1, R2, R3, R4, R5, R6 and R7. However, at one time the N79E845/844/8432 can work with only one par-
ticular bank. The bank selection is done by setting RS1-RS0 bits in the PSW. The R0 and R1 registers are used to store the
address for indirect accessing.
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N79E845/844/8432 Data Sheet
6.8 Bit-addressable Locations
The Scratch-pad RAM area from location 20h to 2Fh is byte as well as bit-addressable. This means that a bit in this area
can be individually addressed. In addition, some of the SFRs are also bit-addressable. The instruction decoder is able to
distinguish a bit access from a byte access by the type of the instruction itself. In the SFR area, any existing SFR whose
address ends in 0 or 8 is bit-addressable.
6.9 Stack
The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP), which stores the address
of the top of the stack. Whenever a jump, call or interrupt is invoked the return address is placed on the stack. There is no
restriction as to where the stack can begin in the RAM. By default however, the Stack Pointer contains 07h at reset. The
user can then change this to any value desired. The SP will point to the last used value. Therefore, the SP will be incre-
mented and then address saved onto the stack. Conversely, while popping from the stack the contents will be read first,
and then the SP is decreased.
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N79E845/844/8432 Data Sheet
7 Special Function Register (SFR)
The N79E845/844/8432 uses Special Function Registers (SFRs) to control and monitor peripherals and their modes. The
SFRs reside in the register locations 80~FFH and are accessed by direct addressing only. Some of the SFRs are bit-
addressable. This is very useful in cases where user would like to modify a particular bit directly without changing other
bits. Those which are bit-addressable SFRs end their addresses as 0H or 8H. The N79E845/844/8432 contains all the
SFRs presenting in the standard 8051. However some additional SFRs are built in. Therefore, some of unused bytes in the
original 8051 have been given new functions. The SFRs are listed as follows.
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N79E845/844/8432 Data Sheet
Table 7–1 N79E845/844/8432 Special Function Registers (SFR) Mapping
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
ADCCON0
B
-
-
-
-
SPCR
KBLS0
-
-
SPSR
KBLS1
C0L
-
-
EIP
EIPH
FF
F7
-
KBIF
ADCH
PWM0L
PWM0H
RCOMP2L
-
SPDR
C2L
P0DIDS
C2H
EIE
KBIE
ADCCON1
PWMPL
PWMPH
T2MOD
I2ADDR
SADEN
P0M1
SADDR
-
-
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
ACC
WDCON0*
PSW
T2CON
I2CON
IP
C0H
C1L
C1H
PWM1L
PWM1H
RCOM2H
-
PWMCON0
-
PWM2L
PWM2H
TH2
PWM3L
PWM3H
-
PWMCON1
PWMCON2
-
TL2
-
-
-
TA
-
-
I2DAT
P1M2
-
I2STA
I2CLK
I2TOC
IPH
P3
P0M2
-
P1M1
WDCON1*
PMCR*
-
IE
-
ISPFD
ISPAL
-
ISPCN
ISPAH
CHPCON*
P3M2
-
-
AUXR1
-
ISPTRG*
SHBDA*
CAPCON2
TH0
-
SCON
P1
SBUF
-
-
DIVM
TH1
-
90
CAPCON0
TL0
CAPCON1
TL1
P3M1
CKCON
-
88
TCON
P0
TMOD
SP
8F
87
80
DPL
DPH
-
PCON
In Bold
bit-addressable
reserved
-
Note:
1.
The reserved SFR addresses should be kept in their own initial states. User should never change their values.
The SFRs in the column with dark borders are bit-addressable
2.
*
With TA-Protection. (Time Access Protection)
April 23 2014
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N79E845/844/8432 Data Sheet
Table 7–2 N79E845/844/8432 SFR Description and Reset Values
[1]
Symbol
Definition
Address
MSB
LSB
PI2
Reset Value
EIP
Interrupt Priority 1
FFH
PT2
PSPI
PPWM
PWDI
-
-
PKB
0000 0000B
(FF)
(FE)
(FD)
(FC)
(FB)
(FA)
(F9)
(F8)
ADCCON0
ADC control register 0
F8H
0000 0000B
ADC.1
ADC.0
ADCEX
ADCI
ADCS
AADR2
AADR1
AADR0
EIPH
Interrupt High Priority 1
F7H
F6H
PT2H
PSPIH
PPWMH
PWDIH
-
-
PKBH
PI2H
0000 0000B
0000 0000B
P0DIDS
Port 0 Digital Input Disable
P0DIDS[7:0]
Serial Peripheral Data
Register
SPDR
SPSR
SPCR
B
F5H
F4H
F3H
F0H
SPDR[7:0]
0000 0000B
0000 0000B
0000 0100B
Serial Peripheral Status
Register
SPIF
WCOL
SPIEN
SPIOVF
LSBFE
MODF DISMODF
-
-
-
Serial Peripheral Control
Register
SSOE
MSTR
CPOL
CPHA
SPR1
SPR0
(F7)
B.7
(F6)
B.6
(F5)
B.5
(F4)
B.4
(F3)
B.3
(F2)
B.2
(F1)
B.1
(F0)
B.0
B register
0000 0000B
C2H
C2L
Input Capture 2 High
Input Capture 2 Low
Keyboard level select 1
Keyboard level select 0
KBI Interrupt Flag
EEH
EDH
ECH
EBH
EAH
E9H
C2H[7:0]
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
C2L[7:0]
KBLS1[7:0]
KBLS0[7:0]
KBIF[7:0]
KBIE[7:0]
KBLS1
KBLS0
KBIF
KBIE
Keyboard Interrupt Enable
(EF)
ET2
(EE)
ESPI
(ED)
(EC)
EWDI
C1H[7:0]
(E7)
(E8)
(E9)
(E8)
EIE
Interrupt enable 1
E8H
0000 0000B
EPWM
ECPTF
EKB
EI2C
C1H
C1L
Input Capture 1 High
Input Capture 1 Low
Input Capture 0 High
Input Capture 0 Low
ADC converter result
ADC control register1
E7H
E6H
E5H
E4H
E2H
E1H
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
C1L[7:0]
C0H[7:0]
C0L[7:0]
C0H
C0L
ADCH
ADCCON1
ADC.9
ADC.8
-
ADC.7
-
ADC.6
ADC.5
-
ADC.4
-
ADC.3
ADC.2
ADCEN
-
RCCLK ADC0SEL
(E7)
(E6)
(E5)
(E4)
(E3)
(E2)
(E1)
(E0)
ACC
Accumulator
E0H
0000 0000B
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
PWMCON1
PWM3L
PWM control register 1
PWM 3 low bits register
PWM 2 low bits register
PWM control register 0
PWM 1 low bits register
PWM 0 low bits register
PWM counter low register
DFH
DEH
DDH
DCH
DBH
DAH
D9H
BKCH
BKPS
BPEN
BKEN
PWM3B
PWM2B
PWM1B
PWM0B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
PWM3.7 PWM3.6 PWM3.5 PWM3.4 PWM3.3 PWM3.2 PWM3.1 PWM3.0
PWM2.7 PWM2.6 PWM2.5 PWM2.4 PWM2.3 PWM2.2 PWM2.1 PWM2.0
PWM2L
PWMCON0
PWM1L
PWMRUN LOAD
CF
CLRPWM PWM3I
PWM2I
PWM1I
PWM0I
PWM1.7 PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 PWM1.0
PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0
PWMP0.7 PWMP0.6 PWMP0.5 PWMP0.4 PWMP0.3 PWMP0.2 PWMP0.1 PWMP0.0
PWM0L
PWMPL
Power-ON
C000 0000B
Watch reset
C0UU 1UUUB
Other reset
[4]
WDCON0
(DF)
(DE)
(DD)
(DC)
(DB)
(DA)
(D9)
(D8)
Watch-Dog control 0
D8H
[3]
WDTEN
WDCLR
WDTF
WIDPD
WDTRF
WPS2
WPS1
WPS0
C0UU UUUUB
PWMCON2
PWM3H
PWM2H
PWM1H
PWM0H
PWM control register 2
PWM 3 high bits register
PWM 2 high bits register
PWM 1 high bits register
PWM 0 high bits register
D7H
D6H
D5H
D3H
D2H
D1H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FP1
FP0
-
BKF
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
-
-
-
-
-
-
-
-
-
-
PWM3.9 PWM3.8
PWM2.9 PWM2.8
PWM1.9 PWM1.8
PWM0.9 PWM0.8
PWMP0.9 PWMP0.8
PWMPH PWM counter high register
(D7)
CY
(D6)
AC
(D5)
F0
(D4)
RS1
(D3)
RS0
(D2)
OV
(D1)
F1
(D0)
P
PSW
TH2
Program status word
Timer 2 MSB
D0H
CDH
0000 0000B
0000 0000B
TH2[7:0]
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N79E845/844/8432 Data Sheet
Table 7–2 N79E845/844/8432 SFR Description and Reset Values
[1]
Symbol
TL2
Definition
Timer 2 LSB
Address
CCH
MSB
LSB
Reset Value
0000 0000B
0000 0000B
0000 0000B
0000 0000B
TL2[7:0]
RCOMP2H
RCOMP2L
T2MOD
Timer 2 Reload MSB
Timer 2 Reload LSB
Timer 2 Mode
CBH
RCOMP2H[7:0]
RCOMPL2[7:0]
CAH
C9H
LDEN
T2DIV[2:0]
-
CAPCR COMPCR
LDTS[1:0]
(C8)
(CF)
TF2
(CA)
TR2
T2CON
Timer 2 Control
C8H
-
-
-
-
0000 0000B
CP/RL2
TA
Timed Access Protection
I2C address
C7H
C1H
1111 1111B
0000 0000B
I2ADDR
ADDR[7:1]
GC
(C7)
-
(C6)
(C5)
STA
(C4)
STO
(C3)
SI
(C2)
AA
(C1)
-
(C0)
-
I2CON
I2TOC
I2C Control register
C0H
BFH
0000 0000B
0000 0000B
I2CEN
I2C Time-out Counter
register
-
-
-
-
-
I2TOCEN
DIV
I2TOF
I2CLK
I2STA
I2DAT
SADEN
I2C Clock Rate
I2C Status Register
I2C Data Register
Slave address mask
BEH
BDH
BCH
B9H
I2CLK[7:0]
0000 0000B
1111 1000B
0000 0000B
0000 0000B
I2STA[7:3]
0
0
0
I2DAT[7:0]
SADEN[7:0]
(BF)
(BE)
(BD)
(BC)
(BB)
PT1
(BA)
PX1
(B9)
PT0
(B8)
PX0
IP
Interrupt priority
B8H
0000 0000B
PCAP
PADC
PBOD
PS
IPH
Interrupt high priority
Port 1 output mode 2
Port 1 output mode 1
Port 0 output mode 2
Port 0 output mode 1
B7H
B4H
B3H
B2H
B1H
PCAPH
P1M2.7
P1M1.7
PADCH
P1M2.6
P1M1.6
PBODH
PSH
PT1H
PX1H
P1M2.2
P1M1.2
PT0H
P1M2.1
P1M1.1
PX0H
P1M2.0
P1M1.0
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000b
P1M2
P1M1
P0M2
P0M1
-
-
P1M2.4
P1M1.4
P1M2.3
P1M1.3
P0M2[7:0]
P0M1[7:0]
(B0)
X2
(B1)
X1
P3
Port3
B0H
-
-
-
-
-
-
0000 0011B
CLKOUT
ISPCN
ISPFD
ISP Control Register
AFH
AEH
ISPA17
ISPA16
FOEN
FCEN
FCTRL3
FCTRL2
FCTRL1
FCTRL0
0011 0000B
0000 0000B
ISP Flash Data Register
ISPFD[7:0]
[4]
Watch-Dog control1
Slave address
ABH
A9H
-
-
-
-
-
-
-
EWRST
0000 0000B
00000000B
WDCON1
SADDR
SADDR[7:0]
(AF)
EA
(AE)
(AD)
(AC)
ES
(AB)
ET1
(AA)
EX1
(A9)
ET0
(A8)
EX0
IE
Interrupt enable
A8H
A7H
0000 0000B
0000 0000B
EADC
EBOD
ISP Flash Address High-
byte
ISPAH
ISPAL
ISPAH[7:0]
ISPAL[7:0]
ISP Flash Address Low-
byte
A6H
A4H
0000 0000B
0000 0000B
[4]
ISP Trigger Register
-
-
-
-
-
-
-
-
-
ISPGO
ISPTRG
Power-on
CC0C 100XB
BOR reset
UU0U 100XB
Other reset
[2][4]
Power Monitor Control
Register
A3H
BODEN
BOV
-
BORST
BOF
-
-
PMCR
UU0U 000XB
AUXR1
[4]
AUX function register
Chip Control
A2H
9FH
-
-
-
-
-
-
-
-
0
DPS
0000 0000B
Power-ON
0000 00C0B
Other reset
ISPF
(Read only)
[3]
SWRST
LDUE
ISPEN
CHPCON
BS
0000 00C0B
Power ON
[4] High-byte Data Flash Start
CCCC CCCCB
Other Reset
UUUU UUUUB
9CH
99H
SHBDA[7:0], SHBDA Initial by CHBDA
SHBDA
Address
SBUF
Serial buffer
SBUF.7
SBUF.6
SBUF.5
SBUF.4
SBUF.3
SBUF.2
SBUF.1
SBUF.0
0000 0000B
April 23 2014
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N79E845/844/8432 Data Sheet
Table 7–2 N79E845/844/8432 SFR Description and Reset Values
[1]
Symbol
Definition
Address
MSB
LSB
(98)
Reset Value
(9F)
(9E)
SM1
(9D)
SM2
(9C)
REN
(9B)
TB8
(9A)
RB8
(99)
TI
SCON
Serial control
98H
0000 0000B
SM0/FE
RI
P3M2
P3M1
Port 3 output mode 2
Port 3 output mode 1
97H
96H
95H
94H
93H
92H
-
-
-
-
-
-
ENCLK
T0OE
P3M2.1
P3M1.1
P3M2.0
P3M1.0
00000000B
00000000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
P3S
P1S
P0S
T1OE
DIVM
CPU Clock Divide Register
Input capture control 2
Input capture control 1
Input capture control 0
DIVM[7:0]
ENF0
CAPCON2
CAPCON1
CAPCON0
-
-
-
-
-
-
ENF1
-
-
-
-
-
CAP1LS1[2:0]
CAP1LS1[2:0]
CAPEN1 CAPEN0
-
CAPF1
CAPF0
(97)
P17
(96)
P16
(94)
(93)
P13
(92)
P12
(91)
P11
(90)
P10
P1
Port 1
90H
-
1111 1111B
P14
CKCON
TH1
Clock control
Timer high 1
Timer high 0
Timer low 1
Timer low 0
Timer mode
8EH
8DH
8CH
8BH
8AH
89H
-
-
-
T1M
T0M
-
-
-
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
TH1[7:0]
TH0
TH0[7:0]
TL1[7:0]
TL0[7:0]
TL1
TL0
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
(8F)
TF1
(8E)
TR1
(8D)
TF0
(8C)
TR0
(8B)
IE1
(8A)
IT1
(89)
IE0
(88)
IT0
TCON
PCON
Timer control
Power control
88H
87H
0000 0000B
Power-on
0001 0000B
Other reset
000u 0000B
SMOD
SMOD0
-
POF
GF1
GF0
PD
IDL
DPH
DPL
SP
Data pointer high
Data pointer low
Stack pointer
83H
82H
81H
DPH[7:0]
0000 0000B
0000 0000B
0000 0111B
DPL[7:0]
SP[7:0]
(87)
P07
(86)
P06
(85)
P05
(84)
P04
(83)
P03
(82)
P02
(81)
P01
(80)
P00
P0
Port 0
80H
1111 1111B
Note: Bits marked in "-" should be kept in their own initial states. User should never change their values.
Note:
[1.]
[2.]
( ) item means the bit address in bit-addressable SFRs.
BODEN, BOV and BORST are initialized by CONFIG2 at power-on reset, and keep unchanged at any other resets. If BODEN=1, BOF will be
automatically set by hardware at power-on reset, and keeps unchanged at any other resets.
[3.]
[4.]
[5.]
[6.]
Initialized by power-on reset. WDTEN=/CWDTEN; BS=/CBS;
With TA-Protection. (Time Access Protection)
Notation “C” means the bit is defined by CONFIG-bits; “U” means the bit is unchanged after any reset except power-on reset.
Reset value symbol description. 0: logic 0, 1: logic 1, U: unchanged, X:, C: initial by CONFIG.
April 23 2014
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N79E845/844/8432 Data Sheet
8 General 80C51 System Control
A or ACC – Accumulator (Bit-addressable)
7
ACC.7
R/W
6
5
4
3
2
1
0
ACC.6
R/W
ACC.5
R/W
ACC.4
R/W
ACC.3
R/W
ACC.2
R/W
ACC.1
R/W
ACC.0
R/W
Address: E0H
Reset value: 0000 0000B
Bit
7:0
Name
Description
ACC[7:0]
Accumulator.
The A or ACC register is the standard 8051 accumulator for arithmetic operation.
B – B Register (Bit-addressable)
7
B.7
R/W
6
B.6
R/W
5
B.5
R/W
4
B.4
R/W
3
B.3
R/W
2
B.2
R/W
1
B.1
R/W
0
B.0
R/W
Address: F0H
Reset value: 0000 0000B
Bit
7:0
Name
B[7:0]
Description
B Register
The B register is the other accumulator of the standard 8051. It is used mainly for MUL
and DIV operations.
SP – Stack Pointer
7
6
5
4
3
2
1
0
SP[7:0]
R/W
Address: 81H
Reset value: 0000 0111B
Bit
7:0
Name
Description
SP[7:0]
Stack Pointer
The Stack Pointer stores the scratch-pad RAM address where the stack begins. It is incre-
mented before data is stored during PUSH or CALL instructions. Note that the default
value of SP is 07H. It causes the stack to begin at location 08H.
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DPL – Data Pointer Low Byte
7
6
5
4
3
2
1
0
DPL[7:0]
R/W
Address: 82H
Reset value: 0000 0000B
Bit
7:0
Name
Description
DPL[7:0] Data Pointer Low Byte
This is the low byte of the standard 8051 16-bit data pointer. DPL combined with DPH
serve as 16-bit data pointer DPTR to address non-scratch-pad memory or Program
Memory.
DPH – Data Pointer High Byte
7
6
5
4
3
2
1
0
DPH[7:0]
R/W
Address: 83H
Reset value: 0000 0000B
Bit
7:0
Name
Description
DPH[7:0]
Data pointer high byte
This is the high byte of the standard 8051 16-bit data pointer. DPH combined with
DPL serve as 16-bit data pointer DPTR to address non-scratch-pad memory or
Program Memory.
PSW – Program Status Word (Bit-addressable)
7
CY
R/W
6
AC
R/W
5
F0
R/W
4
RS1
R/W
3
RS0
R/W
2
OV
R/W
1
F1
R/W
0
P
R
Address: D0H
Reset value: 0000 0000B
Bit
7
Name
CY
Description
Carry Flag
For a adding or subtracting operation, CY will be set when the previous operation
resulted in a carry-out from or a borrow-in to the Most Significant bit, otherwise
cleared. If the previous operation is MUL or DIV, CY is always 0.
CY is affected by DA A instruction which indicates that if the original BCD sum is
greater than 100. For a CJNE branch, CY will be set if the first unsigned integer
value is less than the second one. Otherwise, CY will be cleared.
6
AC
Auxiliary Carry
Set when the previous operation resulted in a carry-out from or a borrow-in to the
4th bit of the low order nibble, otherwise cleared.
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Bit
5
Name
F0
Description
User Flag 0
The general-purpose flag that can be set or cleared by the user.
Register Bank Selecting Bits
4
3
RS1
RS0
The two bits select one of four banks in which R0~R7 locate.
RS1 RS0
Register Bank
RAM Address
0
0
1
1
0
1
0
1
0
1
2
3
00~07H
08~0FH
10~17H
18~1FH
2
OV
Overflow Flag
OV is used for a signed character operands. For an ADD or ADDC instruction, OV
will be set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7
but not bit 6. Otherwise, OV is cleared. OV indicates a negative number produced
as the sum of two positive operands or a positive sum from two negative oper-
ands. For a SUBB, OV is set if a borrow is needed into bit6 but not into bit 7, or
into bit7 but not bit 6. Otherwise, OV is cleared. OV indicates a negative number
produced when a negative value is subtracted from a positive value or a positive
result when a positive number is subtracted from a negative number.
For a MUL, if the product is greater than 255 (00FFH), OV will be set. Otherwise,
it is cleared.
For a DIV, it is normally 0. However, if B had originally contained 00H, the values
returned in A and B will be undefined. Meanwhile, the OV will be set.
1
0
F1
P
User Flag 1
The general purpose flag that can be set or cleared by the user via software.
Parity Flag
Set to 1 to indicate an odd number of ones in the accumulator. Cleared for an
even number of ones. It performs even parity check.
Table 8–1 Instructions that Affect Flag Settings
Instruction
ADD
CY
X[1]
X
OV
X
AC
X
Instruction
CLR C
CY
0
OV
AC
ADDC
SUBB
MUL
X
X
CPL C
X
X
X
X
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
X
0
X
X
DIV
0
X
X
DA A
X
X
RRC A
X
X
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Instruction
RLC A
CY
X
OV
AC
Instruction
CY
OV
AC
CJNE
X
SETB C
1
[1] X indicates the modification is dependent on the result of the instruction
PCON – Power Control
7
SMOD
R/W
6
5
-
-
4
POF
R/W
3
GF1
R/W
2
GF0
R/W
1
PD
R/W
0
IDL
R/W
SMOD0
R/W
Address: 87H
Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
3
Name
GF1
Description
General Purpose Flag 1
The general purpose flag that can be set or cleared by the user.
General Purpose Flag 0
2
GF0
The general purpose flag that can be set or cleared by the user.
General 80C51 support one DPTR but the N79E845/844/8432 support two DPTRs by switching AUXR1.DPS. The set-
ting is as follows:
AUXR1 – AUX Function Resgister-1
7
-
6
-
5
-
4
-
3
-
2
-
1
0
0
DPS
-
-
-
-
-
-
R
R/W
Address: A2H
Reset value: 0000 0000B
Bit
Name
Description
0
DPS
Dual Data Pointer Selection
0 = Select DPTR of standard 8051.
1 = Select DPTR1
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9 I/O Port Structure and Operation
For N79E845/844/8432, there are four I/O ports － port 0, port 1, port2 and port 3. If using on-chip RC oscillator and
reset pin configurations, the N79E845/844/8432 can support up to 17 pins. All I/O pins besides P1.2 and P1.3 can be con-
figured to one of four types by software as shown in the following table.
Table 9–1 Setting Table for I/O Ports Structure
PxM1.y
PxM2.y
Port I/O Mode
Quasi-bidirectional
Push-Pull
0
0
1
0
1
0
1
Input Only (High Impedance)
Open Drain
1
Note: P1.2 and P1.3 are not effective in this table.
After reset, these pins are in quasi-bidirectional mode except P1.2 and P1.3 pins.
The P1.2 and P1.3 are dedicating open-drain pin for I2C interface after reset.
Each I/O port of the N79E845/844/8432 may be selected to use TTL level inputs or Schmitt inputs by P(n)S bit on P3M1
register; where n is 0, 1 or 3. When P(n)S is set to 1, Ports are selected Schmitt trigger inputs on Port(n).
The P3.0 (XTAL2) can be configured as clock output when used on-chip RC is clock source, and the frequency of clock
output is divided by 4 on on-chip RC clock.
9.1 Quasi-Bidirectional Output Configuration
The default port configuration for standard the N79E845/844/8432 I/O ports are the “Quasi-bidirectional” mode that is
common on the 80C51 and most of its derivatives. This type rules as both input and output. When the port outputs logic
high, it is weakly driven, allowing an external device to pull the pin low. When the pin is pulled low, it is driven strongly
and able to sink a large current. In the quasi bidirectional I/O structure, there are three pull-up transistors. Each of them
serves different purposes. One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port latch con-
tains logic 1. The “very weak” pull-up sources a very small current that will pull the pin high if it is left floating.
A second pull-up, called the “weak” pull-up, is turned on when the outside port pin itself is at logic 1 level. This pull-up
provides the primary source current for a quasi-bidirectional pin that is outputting 1. If a pin that has logic 1 on it is pulled
low by an external device, the “weak” pull-up turns off, and only the “very weak” pull-up remains on. To pull the pin low
under these conditions, the external device has to sink enough current (larger than ITL) to overcome the “weak” pull-up
and make the voltage on the port pin below its input threshold (lower than VIL).
The third pull-up is the “strong” pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional
port pin when the port latch changes from a logic 0 to logic 1. When this occurs, the strong pull-up turns on for two-
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peripheral-clock time to pull the port pin high quickly. Then it turns off and “weak: pull-up continues remaining the port
pin high. The quasi bidirectional port structure is shown below.
VDD
2-peripheral-
clock delay
P
N
P
P
Very
Weak
Strong
Weak
Port Pin
Port Latch
Input
Figure 9–1 Quasi Bi-direction I/O Structure
9.1.1
Read-Modify-Write
In the standard 8051 instruction set, user should watch out for one kind of instructions, read-modify-write instructions.
Instead of the normal instructions, the read-modify-write instructions read the internal port latch (Px in SFRs) rather than
the external port pin state. This kind of instructions read the port SFR value, modify it and write back to the port SFR.
Read-modify-write instructions are listed as follows.
Instruction
ANL
Description
Logical AND. (ANL Px,A and ANL Px,direct)
Logical OR. (ORL Px,A and ORL Px,direct)
Logical exclusive OR. (XRL Px,A and XRL Px,direct)
Jump if bit = 1 and clear it. (JBC Px.y,LABEL)
Complement bit. (CPL Px.y)
ORL
XRL
JBC
CPL
INC
Increment. (INC Px)
DEC
Decrement. (DEC Px)
DJNZ
MOV
Decrement and jump if not zero. (DJNZ Px,LABEL)
Px.y,C Move carry bit to Px.y.
CLR
Px.y
Px.y
Clear bit Px.y.
Set bit Px.y.
SETB
The last three seems not obviously read-modify-write instructions but actually they are. They read the entire port latch
value, modify the changed bit, and then write the new value back to the port latch.
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9.2 Open Drain Output Configuration
The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when
the port latch contains logic 0. To be used as a logic output, a port configured in this manner should have an external pull-
up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode. The open
drain port configuration is shown below.
Port Pin
Port Latch
Data
N
Input Data
Figure 9-2 Open Drain Output
9.3 Push-Pull Output Configuration
The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional
output modes, but provides a continuous strong pull-up when the port latch contains logic 1. The push-pull mode may be
used when more source current is needed from a port output. The push-pull port configuration is shown in Figure 9-2. The
two port pins that cannot be configured are P1.2 (SCL) and P1.3 (SDA). The port pins P1.2 and P1.3 are permanently con-
figured as open drain outputs. They may be used as inputs by writing ones to their respective port latches. Additionally,
port pins P3.0 and P3.1 are disabled for both input and output if one of the crystal oscillator options is chosen. Those op-
tions are described in the Oscillator section.
When port pins are driven high at reset, they are in quasi-bidirectional mode and therefore do not source large amounts of
current. Every output on the N79E845/844/8432 may potentially be used as a 38 mA sink LED drive output. However,
there is a maximum total output current for all ports which should not be exceeded.
All ports pins of the N79E845/844/8432 have slew rate controlled outputs. This is to limit noise generated by quickly
switching output signals. The slew rate is factory set to approximately 10 ns rise and fall times. The bits in the P3M1 reg-
ister that are not used to control configuration of P3.1 and P3.0 are used for other purposes, which bits can enable Schmitt
trigger inputs on each I/O port, enable toggle outputs from Timer 0 and Timer 1, and enable a clock output if either the
internal RC oscillator or external clock input is being used. The last two functions are described in the Timers/Counters
and Oscillator sections respectively. Each I/O port of the N79E845/844/8432 may be selected to use TTL level inputs or
Schmitt inputs with hysteresis. A single configuration bit determines this selection for the entire port.
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VDD
P
N
Port Pin
Port Latch
Data
Input Data
Figure 9-3 Push-Pull Output
9.4 Input Only Configuration
By setting this mode; the ports are only input mode. After setting this mode, the pin will be Hi-Impendence.
P0 – Port 0 (Bit-addressable)
7
P07
R/W
6
P06
R/W
5
P05
R/W
4
P04
R/W
3
P03
R/W
2
P02
R/W
1
P01
R/W
0
P00
R/W
Address: 80H
Reset value: 1111 1111B
Bit
7:0
Name
Description
P0[7:0]
Port 0.
Port 0 is an 8-bit quasi bidirectional I/O port.
P1 – Port 1 (Bit-addressable)
7
P17
R/W
6
P16
R/W
5
-
-
4
P14
R/W
3
P13
R/W
2
P12
R/W
1
P11
R/W
0
P10
R/W
Address: 90H
Reset value: 1111 1111B
Bit
7:0
Name
Description
P1[7:0]
Port 1
These pins are in quasi-bidirectional mode except P1.2 and P1.3 pins.
The P1.2 and P1.3 are dedicating open-drain pins for I2C interface after reset.
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P3 – Port 3 (Bit-addressable)
7
-
-
6
-
-
5
-
-
4
-
3
-
-
2
-
-
1
P31
R/W
0
P30
R/W
-
Address: B0H
Reset value: 0000 0011B
Bit
7:2
Name
-
Description
Reserved
1
0
P3.1
P3.0
X1 or I/O pin by alternative.
X2 or CLKOUT or I/O pin by alternative.
P0M1 – Port 0 Output Mode1
7
P0M1.7
R/W
6
5
4
3
2
1
0
P0M1.6
R/W
P0M1.5
R/W
P0M1.4
R/W
P0M1.3
R/W
P0M1.2
R/W
P0M1.1
R/W
P0M1.0
R/W
Address: B1H
Reset value: 0000 0000B
P0M2 – Port 0 Output Mode2
7
P0M2.7
R/W
6
5
4
3
2
1
0
P0M2.6
R/W
P0M2.5
R/W
P0M2.4
R/W
P0M2.3
R/W
P0M2.2
R/W
P0M2.1
R/W
P0M2.0
R/W
Address: B2H
Reset value: 0000 0000B
P1M1 – Port 1 Output Mode1
7
P1M1.7
R/W
6
5
-
-
4
3
2
1
0
P1M1.6
R/W
P1M1.4
R/W
P1M1.3
R/W
P1M1.2
R/W
P1M1.1
R/W
P1M1.0
R/W
Address: B3H
Reset value: 0000 0000B
P1M2 – Port 1 Output Mode2
7
P1M2.7
R/W
6
5
-
-
4
3
2
1
0
P1M2.6
R/W
P1M2.4
R/W
P1M2.3
R/W
P1M2.2
R/W
P1M2.1
R/W
P1M2.0
R/W
Address: B4H
Reset value: 0000 0000B
P3M1 – Port3 Output Mode1
7
P3S
R/W
6
-
-
5
P1S
R/W
4
P0S
R/W
3
2
1
0
T1OE
R/W
T0OE
R/W
P3M1.1
R/W
P3M1.0
R/W
Address: 96H
Reset value: 0000 0000B
Bit
7
Name
P3S
Description
Enable Schmitt trigger inputs on Port 3.
6
-
Reserved
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Bit
5
Name
P1S
Description
Enable Schmitt trigger inputs on Port 1.
Enable Schmitt trigger inputs on Port 0.
4
1
0
P0S
P3M1.1
P3M1.0
Control the output configuration of P3.1.
Control the output configuration of P3.0.
P3M2 – Port3 Output Mode2
7
-
-
6
-
-
5
-
-
4
-
3
-
-
2
1
0
ENCLK
R/W
P3M2.1
R/W
P3M2.0
R/W
-
Address: 97H
Reset value: 0000 0000B
Bit
7:3
Name
-
Description
Reserved
0
ENCLK
Clock Output to XTAL2 Pin (P3.0) Enable
If the clock is from internal RC, the frequency of P3.0 is internal RC/4 (22.1184MHz/4).
Refer to Table 9-1 Setting Table for I/O Port Structure
1
0
P3M2.1
P3M2.0
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10 Timers/Counters
The N79E845/844/8432 has three 16-bit programmable timers/counters.
10.1 Timers/Counters 0 and 1
Timer/Counter 0 and 1 in the N79E845/844/8432 is two 16-bit Timers/Counters. Each of them has two 8-bit registers that
form the 16 bit counting register. For Timer/Counter 0 they are TH0, the upper 8-bit register, and TL0, the lower 8-bit
register. Similar Timer/Counter 1 has two 8-bit registers, TH1 and TL1. TCON and TMOD can configure modes of Tim-
er/Counter 0 and 1.
They have additional timer 0 or timer 1 overflow toggle output enable feature as compare to conventional timers/counters.
This timer overflow toggle output can be configured to automatically toggle T0 or T1 pin output whenever a timer over-
flow occurs.
When configured as a “Timer”, the timer counts clock cycles. The timer clock can be programmed to be thought of as
1/12 of the clock system or 1/4 of the clock system. In the “Counter” mode, the register is incremented on the falling edge
of the external input pin, T0 in case of Timer 0, and T1 for Timer 1. The T0 and T1 inputs are sampled in every machine-
cycle at C4. If the sampled value is high in one machine-cycle and low in the next, then a valid high to low transition on
the pin is recognized and the count register is incremented. Since it takes two machine-cycles to recognize a negative tran-
sition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock frequency. In either the
“Timer” or “Counter” mode, the count register will be updated at C3. Therefore, in the “Timer” mode, the recognized
negative transition on pin T0 and T1 can cause the count register value to be updated only in the machine-cycle following
the one in which the negative edge was detected.
The “Timer” or “Counter” function is selected by the “ C/T ” bit in the TMOD Special Function Register. Each Tim-
er/Counter has one selection bit for its own; bit 2 of TMOD selects the function for Timer/Counter 0 and bit 6 of TMOD
selects the function for Timer/Counter 1. In addition each Timer/Counter can be set to operate in any one of four possible
modes. The mode selection is done by bits M0 and M1 in the TMOD SFR.
The N79E845/844/8432 can operate like the standard 8051/52 family, counting at the rate of 1/12 of the clock speed, or in
turbo mode, counting at the rate of 1/4 clock speed. The speed is controlled by the T0M and T1M bits in CKCON, and the
default value is zero, which uses the standard 8051/52 speed.
CKCON – Clock Control
7
-
6
-
5
-
4
T1M
3
T0M
2
-
1
-
0
-
-
-
-
R/W
R/W
-
-
-
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Address: 8EH
Reset value: 0000 0000B
Bit
7:5
4
Name
-
T1M
Description
Reserved
Timer 1 Clock Select:
0 = Timer 1 uses a divide by 12 clocks.
1 = Timer 1 uses a divide by 4 clocks.
3
T0M
-
Timer 0 Clock Select:
0 = Timer 0 uses a divide by 12 clocks.
1 = Timer 0 uses a divide by 4 clocks.
Reserved
2:0
TMOD – Timer 0 and 1 Mode
7
6
5
4
3
2
1
0
GATE
M1
M0
GATE
M1
M0
C/T
R/W
C/T
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: 89H
Reset value: 0000 0000B
Bit
7
Name
Description
GATE
Timer 1 Gate Control
0 = Timer 1 will clock when TR1 = 1 regardless of INT1 logic level.
1 = Timer 1 will clock only when TR1 = 1 and INT1 is logic 1.
Timer 1 Counter/Timer Selection
6
C/T
0 = Timer 1 is incremented by internal peripheral clocks.
1 = Timer 1 is incremented by the falling edge of the external pin T1.
Timer 1 Mode Select.
5
4
M1
M0
M1
M0
Timer 1 Mode
0
0
1
1
0
1
0
1
Mode 0: 8-bit Timer/Counter with 5-bit pre-scalar (TL1[4:0])
Mode 1: 16-bit Timer/Counter
Mode 2: 8-bit Timer/Counter with auto-reload from TH1
Mode 3: Timer 1 halted
3
2
GATE
Timer 0 Gate Control
0 = Timer 0 will clock when TR0 = 1 regardless of
logic level.
INT0
1 = Timer 0 will clock only when TR0 = 0 and
is logic 1.
INT0
Timer 0 Counter/Timer Selection
C/T
0 = Timer 0 is incremented by internal peripheral clocks.
1 = Timer 0 is incremented by the falling edge of the external pin T0.
Timer 0 mode select
1
M1
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Bit
0
Name
M0
Description
Timer 0 Mode
M1
M0
0
0
1
1
0
1
0
1
Mode 0: 8-bit Timer/Counter with 5-bit pre-scalar (TL0[4:0])
Mode 1: 16-bit Timer/Counter
Mode 2: 8-bit Timer/Counter with auto-reload from TH0
Mode 3: TL0 as a 8-bit Timer/Counter and TH0 as a 8-bit
Timer
TCON – Timer 0 and 1 Control (Bit-addressable)
7
TF1
R/W
6
TR1
R/W
5
TF0
R/W
4
TR0
R/W
3
IE1
R/W
2
IT1
R/W
1
IE0
R/W
0
IT0
R/W
Address: 88H
Reset value: 0000 0000B
Bit
7
Name
TF1
Description
Timer 1 Overflow Flag
This bit is set when Timer 1 overflows. It is automatically cleared by hardware
when the program executes the Timer 1 interrupt service routine. Software can
also set or clear this bit.
6
TR1
Timer 1 Run Control
0 = Timer 1 is halted. Clearing this bit will halt Timer 1 and the current count will
be preserved in TH1 and TL1.
1 = Timer 1 is enabled.
5
4
TF0
TR0
Timer 0 Overflow Flag
This bit is set when Timer 0 overflows. It is automatically cleared via hardware
when the program executes the Timer 0 interrupt service routine. Software can
also set or clear this bit.
Timer 0 Run Control
0 = Timer 0 is halted. Clearing this bit will halt Timer 0 and the current count will
be preserved in TH0 and TL0.
1 = Timer 0 is enabled.
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TL0 – Timer 0 Low Byte
7
6
5
4
3
2
1
0
TL0[7:0]
R/W
Address: 8AH
Reset value: 0000 0000B
Bit
7:0
Name
Description
TL0[7:0]
Timer 0 Low Byte
The TL0 register is the low byte of the 16-bit Timer 0.
TH0 – Timer 0 High Byte
7
6
5
4
3
2
1
0
TH0[7:0]
R/W
Address: 8CH
Reset value: 0000 0000B
Bit
7:0
Name
Description
TH0[7:0]
Timer 0 High Byte
The TH0 register is the high byte of the 16-bit Timer 0.
TL1 – Timer 1 Low Byte
7
6
5
4
3
2
1
0
TL1[7:0]
R/W
Address: 8BH
Reset value: 0000 0000B
Bit
7:0
Name
Description
TL1[7:0]
Timer 1 Low Byte
The TL1 register is the low byte of the 16-bit Timer 1.
TH1 – Timer 1 High Byte
7
6
5
4
3
2
1
0
TH1[7:0]
R/W
Address: 8DH
Reset value: 0000 0000B
Bit
7:0
Name
Description
TH1[7:0]
Timer 1 High Byte
The TH1 register is the high byte of the 16-bit Timer 1.
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P3M1 – Port3 Output Mode1
7
P3S
R/W
6
-
-
5
P1S
R/W
4
P0S
R/W
3
2
1
0
T1OE
R/W
T0OE
R/W
P3M1.1
R/W
P3M1.0
R/W
Address: 96H
Reset value: 0000 0000B
Bit
3
Name
T1OE
Description
P0.7 pin is toggled whenever Timer 1 overflows. The output frequency is therefore one
half of the Timer 1 overflow rate.
2
T0OE
P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is therefore one-
half of the Timer 0 overflow rate.
10.1.1 Mode 0 (13-bit Timer)
In Mode 0, the timers/counters act as a 8-bit counter with a 5-bit, divide by 32 pre-scale. In this mode we have 13-bit tim-
er/counter. The 13-bit counter consists of 8 bits of THx and 5 lower bits of TLx. The upper 3 bits of TLx are ignored.
The negative edge of the clock is increments count in the TLx register. When the fifth bit in TLx moves from 1 to 0, then
the count in the THx register is incremented. When the count in THx moves from FFh to 00h, then the overflow flag TFx
in TCON SFR is set. The counted input is enabled only if TRx is set and either GATE = 0 or INTx = 1. When C/T is set
to 0, then it will count clock cycles, and if C/T is set to 1, then it will count 1 to 0 transitions on T0 (P1.2) for timer 0 and
T1 (P0.7) for timer 1. When the 13-bit count reaches 1FFFh, the next count will cause it to rollover to 0000h. The timer
overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur.
T0M=CKCON.3
(T1M=CKCON.4)
1/4
1
0
C/T=TMOD.2
(C/T=TMOD.6)
0
TL0
(TL1)
FSYS
TF0
(TF1)
1/12
0
0
4
7
7
Interrupt
TFx
1
T0/T1
TR0/TR1
GATE
SFR
TH0
(TH1)
P1.2
(P0.7)
1
T0OE
PIN
P1.2
(P0.7)
INT0/INT1
(T1OE)
En
0
1
T0OE
(T1OE)
Figure 10–1 Timers/Counters 0 and 1 in Mode 0
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10.1.2 Mode 1 (16-bit Timer)
Mode 1 is similar to Mode 0 except that the counting registers are fully used as 16-bit counter. Rollover occurs when a
count moves FFFFH to 0000H. The Timer overflow flag TFx of the relevant Timer/Counter is set and an interrupt will
occurs if enabled.
T0M=CKCON.3
(T1M=CKCON.4)
1/4
1
0
C/T=TMOD.2
(C/T=TMOD.6)
0
TL0
(TL1)
FSYS
TF0
(TF1)
1/12
0
0
4
7
7
Interrupt
TFx
1
T0/T1
TR0/TR1
GATE
SFR
TH0
(TH1)
P1.2
(P0.7)
1
T0OE
PIN
P1.2
(P0.7)
INT0/INT1
(T1OE)
En
0
1
T0OE
(T1OE)
Figure 10–2 Timers/Counters 0 and 1 in Mode 1
10.1.3 Mode 2 (8-bit Auto-Reload Timer)
In Mode 2, the Timer/Counter is in auto-reload mode. In this mode, TLx acts as an 8-bit count register whereas THx holds
the reload value. When the TLx register overflows from FFH to 00H, the TFx bit in TCON is set and TLx is reloaded with
the contents of THx and the counting process continues from here. The reload operation leaves the contents of the THx
register unchanged. This feature is best suitable for UART baud rate generator for it runs without continuous software
intervention. Note that only Timer1 can be the baud rate source for UART. Counting is enabled by the TRx bit and proper
setting of GATE and INTx pins. The functions of GATE and INTx pins are just the same as Mode 0 and 1.
T0M=CKCON.3
(T1M=CKCON.4)
1/4
1
0
C/T=TMOD.2
(C/T=TMOD.6)
0
TL0
(TL1)
FSYS
TF0
(TF1)
1/12
0
0
7
7
Interrupt
TFx
1
T0/T1
TR0/TR1
GATE
P1.2
(P0.7)
TH0
(TH1)
INT0/INT1
T0OE
(T1OE)
Figure 10–3 Timer/Counter 0 and 1 in Mode 2
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10.1.4 Mode 3 (Two Separate 8-bit Timers)
Mode 3 has different operating methods for the two timers/counters. For timer/counter 1, mode 3 simply freezes the coun-
ter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count registers in this mode. The logic for
this mode is shown in the following figure. TL0 uses the Timer/Counter 0 control bits C/T , GATE, TR0, INT0 and
TF0. The TL0 can be used to count clock cycles (clock/12 or clock/4) or 1-to-0 transitions on pin T0 as determined by C/T
(TMOD.2). TH0 is forced as a clock cycle counter (clock/12 or clock/4) and takes over the use of TR1 and TF1 from
Timer/Counter 1. Mode 3 is used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still
be used in Modes 0, 1 and 2, but its flexibility is somewhat limited. While its basic functionality is maintained, it no long-
er has control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a timer/counter and retains
the use of GATE and INT1 pin. In this condition it can be turned on and off by switching it out of and into its own Mode
3. It can be also used as a baud rate generator for the serial port.
T0M=CKCON.3
(T1M=CKCON.4)
1/4
1
C/T=TMOD.2
FSYS
0
0
TL0
1/12
0
7
Interrupt
SFR
TF0
1
PIN
P1.2
T0=P1.2
TR0=TCON.4
GATE=TMOD.3
INT0=P1.3
P1.2
Toggle
(refer to mode 0)
T0OE
TH0
0
7
Interrupt
SFR
TF1
TR1=TCON.6
PIN
P0.7
P0.7
Toggle
(refer to mode 0)
T1OE
Figure 10–4 Timer/Counter 0 in Mode 3
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10.2 Timer/Counter 2
Timer 2 is 16-bit up counter cascaded with TH2, the upper 8 bits register, and TL2, the lower 8-bit register. Equipped with
RCOMP2H and RCOMP2L, Timer 2 can operate under compare mode and auto-reload mode. The additional 3-channel
input capture module makes Timer 2 detect and measure the width or period of input pulses. The results of 3 input cap-
tures are stores in C0H and C0L, C1H and C1L, C2H and C2L individually. The clock source of Timer 2 is from the clock
system pre-scaled by a clock divider with 8 different scales for wide field application. The clock is enabled when TR2
(T2CON.2) is 1, and disabled when TR2 is 0. The following registers are related to Timer 2 function.
T2CON – Timer 2 Control (Bit-addressable)
7
TF2
6
-
5
-
4
-
3
-
2
1
-
0
TR2
R/W
CP/RL2
R/W
R/W
-
-
-
-
-
Address: C8H
Reset value: 0000 0000B
Bit
Name
Description
7
TF2
Timer 2 Overflow Flag
This bit is set when Timer 2 overflows or a compare match occurs. If the Timer 2 interrupt
and the global interrupt are enable, setting this bit will make CPU execute Timer 2 interrupt
service routine. This bit is not automatically cleared via hardware and should be cleared via
software.
6:3
2
-
Reserved
TR2
Timer 2 Run Control
0 = Timer 2 is halted. Clearing this bit will halt Timer 2 and the current count will be
preserved in TH2 and TL2.
1 = Timer 2 is enabled.
1
0
-
Reserved
Timer 2 Capture or Reload Selection
CP/RL2
This bit selects whether Timer 2 functions in compare or auto-reload mode.
0 = Auto-reload on Timer 2 overflow or any input capture event.
1 = Compare mode of Timer 2.
T2MOD – Timer 2 Mode
7
LDEN
R/W
6
5
4
3
2
1
0
T2DIV[2:0]
R/W
CAPCR
R/W
COMPCR
R/W
LDTS[1:0]
R/W
R/W
R/W
R/W
Address: C9H
Reset value: 0000 0000B
Bit
Name
Description
7
LDEN
Auto-reload Enable.
0 = Disable reloading RCOMP2H and RCOMP2L to TH2 and TL2 on Timer 2
overflow or any input capture event.
1 = Enable reloading RCOMP2H and RCOMP2L to TH2 and TL2 on Timer 2
overflow or any input capture event.
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Bit
Name
Description
6:4
T2DIV[2:0] Timer 2 Clock Divider
000 = Timer 2 clock divider is 1/4.
001 = Timer 2 clock divider is 1/8.
010 = Timer 2 clock divider is 1/16.
011 = Timer 2 clock divider is 1/32.
100 = Timer 2 clock divider is 1/64.
101 = Timer 2 clock divider is 1/128.
110 = Timer 2 clock divider is 1/256.
111 = Timer 2 clock divider is 1/512.
3
2
CAPCR
Capture Auto-clear
This bit enables auto-clear Timer 2 value in TH2 and TL2 when a determined in-
put capture event occurs.
0 = Timer 2 continues counting when a capture event occurs.
1 = Timer 2 value is auto-cleared as 0000H when a capture event occurs.
COMPCR Compare Match Auto-clear.
This bit enables auto-clear Timer 2 value in TH2 and TL2 when a compare match
occurs.
0 = Timer 2 continues counting when a compare match occurs.
1 = Timer 2 value is auto-cleared as 0000H when a compare match occurs.
1:0
LDTS[1:0] Auto-reload Trigger Selection
These bits select the reload trigger event.
00 = Reload when Timer 2 overflows.
01 = Reload when input capture 0 event occurs.
10 = Reload when input capture 1 event occurs.
11 = Reload when input capture 2 event occurs.
RCOMP2L – Timer 2 Reload/Compare Low Byte
7
6
5
4
3
2
1
0
RCOMP2L[7:0]
R/W
Address: CAH
Reset value: 0000 0000B
Bit
Name
Description
7:0
RCOMP2L[7:0] Timer 2 Reload/Compare Low Byte
This register stores the low byte of compare value when Timer 2 is configured
in compare mode, It holds the low byte of the reload value when auto-reload
mode.
RCOMP2H – Timer 2 Reload/Compare High Byte
7
6
5
4
3
2
1
0
RCOMP2H[7:0]
R/W
Address: CBH
Reset value: 0000 0000B
Bit
Name
Description
7:0
RCOMP2H[7:0] Timer 2 Reload/Compare High Byte
This register stores the high byte of compare value when Timer 2 is config-
ured in compare mode. And it holds the high byte of the reload value when
auto-reload mode.
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TL2 – Timer 2 Low Byte
7
6
5
4
3
2
1
0
TL2[7:0]
R/W
Address: CCH
Reset value: 0000 0000B
Bit
Name
Description
7:0
TL2[7:0] Timer 2 Low Byte
The TL2 register is the low byte of the 16-bit Timer 2.
TH2 – Timer 2 High Byte
7
6
5
4
3
2
1
0
TH2[7:0]
R/W
Address: CDH
Reset value: 0000 0000B
Bit
Name
Description
7:0
TH2[7:0] Timer 2 high byte
The TH2 register is the high byte of the 16-bit Timer 2.
Timer/Counter 2 provides three operating mode which can be selected by control bits in T2CON and T2MOD as shown in
the table below. Note that the TH2 and TL2 are accessed separately. It is strongly recommended that user stop Timer 2
temporally for a reading from or writing to TH2 and TL2. The free-running reading or writing may cause unpredictable
situation.
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Table 10–1 Timer 2 Operating Modes
Timer 2 Mode
LDEN (T2MOD.7)
CP/RL2 (T2CON.0)
Input capture
Auto-reload
Compare
0
0
1
0
1
X
10.2.1 Input Capture Mode
The input capture module with Timer 2 implements the input capture mode. Timer 2 should be configured by clearing
CP/RL2 and LDEN bit to enter into input capture mode. The input capture module is configured through CAPCON0~2
registers. The input capture module supports 3-channel inputs (IC0 and IC1 pins) that share I/O pin P1.2 and P0.7. Each
input channel consists its own Schmitt trigger input. The noise filter for each channel is enabled via setting ENF0~1
(CAPCON2[5:4]). It filters input glitches smaller than 4 CPU clocks. Input capture 0~1 have independent edge detector
but share with unique Timer 2. The trigger edge is also configured individually by setting CAPCON1. It supports positive
edge capture, negative edge capture, or both edge captures. Each input capture channel has its own enabling bit
CAPEN0~1 (CAPCON0[5:4]).
While any input capture channel is enabled and the selected edge trigger occurs, the content of the free running Timer 2
counter, TH2 and TL2, will be captured, transferred, and stores into the capture registers CnH and CnL. The edge trigger-
ing also causes CAPFn (CAPCON0.n) is set by hardware. The interrupt will be also generated if ECPTF (EIE.2) and EA
bit are both set. For three input capture flags shares the same interrupt vector, the user should check CAPFn to confirm
which channel comes the input capture edge, which flags should be cleared by software.
The bit CAPCR (T2MOD.3) benefits the implement of period calculation. Setting CAPCR makes the hardware clear Tim-
er 2 as 0000H automatically after the value of TH2 and TL2 have been captured after an input capture edge event occurs.
It eliminates the routine software overhead of writing 16-bit counter or an arithmetic subtraction.
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C0L
C0H
CAPF0
[00]
[01]
[10]
Noise
Filter
IC0 (P1.2)
IC1 (P0.7)
ENF0
or
(CAPCON2.4)
CAPEN0
(CAPCON0.4)
CAP0LS[1:0]
(CAPCON1[1:0])
Input Capture 0 Module
Input Capture 1 Module
CAPF0 event
CAPF1 event
CAPCR
(T2MOD.3)
Clear Timer 2
Pre-scalar
1/4~1/512
FSYS
TL2
TH2
TF2
Timer 2 Interrupt
T2DIV[2:0]
TR2
(T2MOD[6:4])
(T2CON.2)
00
01
10
11
CAPF0 event
CAPF1 event
Reserved
LDEN
(T2MOD.7)
LDTS[1:0]
(T2MOD[1:0])
RCOMP2L RCOMP2H
Timer 2 Module
Figure 10–5 Timer 2 Input Capture and Auto-reload Mode Function Block
CAPCON0 – Input Capture Control 0
7
-
-
6
-
-
5
4
3
-
-
2
-
-
1
0
CAPEN1
R/W
CAPEN0
R/W
CAPF1
R/W
CAPF0
R/W
Address: 92H
Reset value: 0000 0000B
Bit
7:6
5
Name
Description
-
Reserved
CAPEN1 Input Capture 1 Enable
0 = Disable input capture channel 1.
1 = Enable input capture channel 1.
4
CAPEN0 Input Capture 0 Enable
0 = Disable input capture channel 0.
1 = Enable input capture channel 0.
3:2
1
-
Reserved
CAPF1 Input Capture 1 Flag
This bit is set by hardware if the determined edge of input capture 1 occurs. This bit
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Bit
Name
Description
should cleared by software.
CAPF0 Input Capture 0 Flag.
0
This bit is set by hardware if the determined edge of input capture 0 occurs. This bit
should cleared by software.
CAPCON1 – Input Capture Control 1
7
-
6
-
5
-
4
-
3
2
1
0
CAP1LS[1:0]
CAP0LS[1:0]
-
-
-
-
R/W
R/W
R/W
R/W
Address: 93H
Reset value: 0000 0000B
Bit
7:4
3:2
Name
Description
-
Reserved
CAP1LS[1:0] Input capture 1 Level Selection
00 = Falling edge.
01 = Rising edge.
10 = Either Rising or falling edge.
11 = Reserved
1:0
CAP0LS[1:0] Input Capture 0 Level Selection
00 = Falling edge.
01 = Rising edge.
10 = Either rising or falling edge.
11 = Reserved
CAPCON2 – Input Capture Control 2
7
-
-
6
-
-
5
4
3
-
-
2
-
-
1
-
-
0
-
-
ENF1
R/W
ENF0
R/W
Address: 94H
Reset value: 0000 0000B
Bit
7:6
5
Name
-
Description
Reserved
ENF1
Noise Filer on Input Capture 1 Enable
0 = Disable noise filter on input capture channel 1.
1 = Enable noise filter on input capture channel 1.
4
ENF0
-
Noise Filer on Input Capture 0 Enable
0 = Disable noise filter on input capture channel 0.
1 = Enable noise filter on input capture channel 0.
3:0
Reserved
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C0L – Capture 0 Low Byte
7
6
5
4
3
2
1
0
C0L[7:0]
R/W
Address: E4H
Reset value: 0000 0000B
Bit
Name
Description
7:0
C0L[7:0]
Input Capture 0 Result Low Byte
The C0L register is the low byte of the 16-bit result captured by input capture 0.
C0H – Capture 0 High Byte
7
6
5
4
3
2
1
0
C0H[7:0]
R/W
Address: E5H
Reset value: 0000 0000B
Bit
Name
Description
7:0
C0H[7:0] Input Capture 0 Result High Byte
The C0H register is the high byte of the 16-bit result captured by input capture 0.
C1L – Capture 1 Low Byte
7
6
5
4
3
2
1
0
C1L[7:0]
R/W
Address: E6H
Reset value: 0000 0000B
Bit
Name
Description
7:0
C1L[7:0]
Input Capture 1 Result Low Byte
The C1L register is the low byte of the 16-bit result captured by input capture 1.
C1H – Capture 1 High Byte
7
6
5
4
3
2
1
0
C1H[7:0]
R/W
Address: E7H
Reset value: 0000 0000B
Bit
Name
Description
7:0
C1H[7:0] Input Capture 1 Result High Byte
The C1H register is the high byte of the 16-bit result captured by input capture 1.
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C2L – Capture 2 Low Byte
7
6
5
4
3
2
1
0
C2L[7:0]
R/W
Address: EDH
Reset value: 0000 0000B
Bit
Name
Description
7:0
C2L[7:0]
Input Capture 2 Result Low Byte
The C2L register is the low byte of the 16-bit result captured by input capture 2.
C2H – Capture 2 High Byte
7
6
5
4
3
2
1
0
C2H[7:0]
R/W
Address: EEH
Reset value: 0000 0000B
Bit
Name
Description
7:0
C2H[7:0] Input Capture 2 Result High Byte
The C2H register is the high byte of the 16-bit result captured by input capture 2.
10.2.2 Auto-reload Mode
Timer 2 can be configured as auto-reload mode by clearing CP/RL2 and setting LDEN bit. In this mode RCOMP2H and
RCOMP2L registers stores the reload value. The contents in RCOMP2H and RCOM3L transfer into TH2 and TL2 once
the auto-reload event occurs. The event can be the Timer 2 overflow or one of the triggering event on any of enabled input
capture channel depending on the LDTS[1:0] (T2MOD[1:0]) selection.
Note that once CAPCR (T2MOD.3) is set, an input capture event only clears TH2 and TL2 without reloading RCOMP2H
and RCOMP2L contents.
10.2.3 Compare Mode
Timer 2 can be also configured simply as the compare mode by setting CP/RL2 . In this mode RCOMP2H and
RCOMP2L registers serve as the compare value registers. As Timer 2 up counting, TH2 and TL2 match RCOMP2H and
RCOMP2L, TF3 (T2CON.7) will be set by hardware to indicate a compare match event.
Setting COMPCR (T2MOD.2) makes the hardware to clear Timer 2 counter as 0000H automatically after a compare
match has occurred.
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COMPCR
(T2MOD.2)
Clear Timer 2
Pre-scalar
1/4~1/512
FSYS
TL2
TH2
T2DIV[2:0]
(T2MOD[6:4])
TR2
(T2CON.2)
TF2
Timer 2 Interrupt
=
RCOMP2L RCOMP2H
Timer 2 Module
Figure 10–6 Timer 2 Compare Mode Function Block
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11 Watchdog Timer (WDT)
The N79E845/844/8432 provides one Watchdog Counter to serve as a system monitor, which improve the reliability of
the system. Watchdog Timer is useful for systems that are susceptible to noise, power glitches, or electrostatic discharge.
The periodic interrupt of Watchdog Timer can also serve as an event timer or a durational system supervisor in a monitor-
ing system which generally operates in Idle or Power-Down mode. The Watchdog Timer is basic a setting of divider that
divides an internal low speed clock source. The divider output is selectable and determines the time-out interval. When the
time-out interval is fulfilled, it will wake the system up from Idle or Power-Down mode and an interrupt event will occur.
If Watchdog Timer reset is enabled, a system reset will occur after a period of delay if without any software response.
Pre-Scalar
WDT Counter
000
001
010
011
100
101
110
111
1/1
clock
1/2
6-bit Counter
1/8
clear
1/16
1/32
1/64
1/128
1/256
....
Fwck: WDT clock
Internal OSC
(10KHz)
Overflow
Checking
1: ON
0: OFF
overflow
EWDI
(EIE.4)
select
WDT interrupt
WPS2,WPS1,WPS0
WDTF
PD (PCON.1)
Delay 512 clock
(Internal 10KHz)
WIDPD
IDL (PCON.0)
WDT Reset
WCLR
(written '1' by software)
ENWDT
EWRST
WRF
Figure 11-1 Watchdog Timer
11.1 Functional Description
The Watchdog Timer should first be reset 00H by using WDCLR(WDCON0.6) to ensure that the timer starts from a
known state. After disable Watchdog Timer through clearing WDTEN (WDCON0.7) will also clear this counter. The
WDCLR bit is used to reset the Watchdog Timer. This bit is self-cleared thus the user doesn’t need to clear it. After writ-
ing 1 to WDCLR, the hardware will automatically clear it. After WDTEN set as 1, the Watchdog Timer starts counting.
The time-out interval is selected by the three bits WPS2, WPS1, and WPS0 (WDCON0[2:0]). When the selected time-out
occurs, the Watchdog Timer will set the interrupt flag WDTF (WDCON0.5). The Watchdog Timer interrupt enable bit
locates at EIE.4 register. If Watchdog Timer reset is enabled by writing logic 1 to EWRST (WDCON1.0) bit. An addi-
tional 512 clocks of the low speed internal RC delays to expect a counter clearing by setting WDCLR. If these is no
WDCLR setting during this 512-clock period, a reset will happen. Once a reset due to Watchdog Timer occurs, the
Watchdog Timer reset flag WDTRF (WDCON0.3) will be set. This bit keeps unchanged after any reset other than a pow-
er-on reset. The user may clear WDTRF via software. In general, software should restart the counter to put it into a known
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state by setting WDCLR. The Watchdog Timer also provides a WIDPD bit (WDCON0.4) to allow the Watchdog Timer
continuing running after the system enters into Idle or Power Down operating mode.
The hardware automatically clears WDT counter after entering into or being woken-up from Idle or Power-down mode. It
prevents unconscious system reset.
WDCON0 – Watchdog Timer Control (TA Protected)
7
6
WDCLR
w
5
4
3
2
1
0
WDTEN
R/W
WDTF
R/W
WIDPD
R/W
WDTRF
R/W
WPS2
R/W
WPS1
R/W
WPS0
R/W
Address: D8H Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
7
Name
Description
WDTEN
WDT Enable
WDTEN is initialized by inverted CWDTEN (CONFIG3, bit-7) at any other resets.
0 = Disable WDT at power-on reset.
1 = Enable WDT at power-on reset.
6
WDCLR
WDT Counter Clear
Writing “1” to clear the WDT counter to 0000H. Note that this bit is written-only and has
no need to be cleared by being written “0”.
5
WDTF
WDT Interrupt Flag
This bit will be set by hardware when WDT counter overflows.
WIDPD
4
WDT Running in Idle and Power-down Mode
This bit decides whether Watchdog Timer runs in Idle or Power-Down mode.
0 = WDT counter is halted while CPU is in Idle or Power-Down mode.
1 = WDT keeps running while CPU is in Idle or Power-Down mode.
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Bit
3
Name
Description
WDTRF
WDT Reset Flag
When the MCU resets itself, this bit is set by hardware. The bit should be cleared by soft-
ware.
If EWRST = 0, the interrupt flag WDTF won’t be set by hardware, and the MCU will
reset itself right away.
If EWRST = 1, the interrupt flag WDTF will be set by hardware and the MCU will jump
into WDT’s interrupt service routine if WDT interrupt is enabled, and the MCU won’t
reset itself until 512 CPU clocks elapse. In other words, in this condition, the user also
needs to clear the WDT counter (by writing ‘1’ to WDCLR bit) during this period of 512
CPU clocks, or the MCU will also reset itself when 512 CPU clocks elapse.
2:0
WPS[2:0]
WDT Pre-scalar Selection
Use these bits to select WDT time-out period.
64
The WDT time-out period is determined by the formula
, where
=
(Fwck ×Pr eScalar)
Fwck is the frequency of the WDT clock source. The following table shows an example of
WDT timeout period for different Fwck.
[1] WDTEN is initialized by reloading the inversed value of CWDTEN (CONFIG3.7) after all resets.
[2] WIDPD and WPS[2:0] are cleared after power-on reset and keep unchanged after any other resets.
[3] WDTRF will be cleared after power-on reset, be set after Watchdog Timer reset, and remains unchanged after any other resets.
WDCON1 – Watchdog Timer Control (TA Protected)
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
-
-
0
EWRST
R/W
Address: ABH
Reset value: 0000 0000B
Bit
0
Name
Description
EWRST
0 = Disable WDT Reset function.
1 = Enable WDT Reset function.
[1] EWRST is cleared after power-on reset and keeps unchanged after any other resets.
64
The Watchdog time-out interval is determined by the formula
. where Fwck is the frequency of inter-
=
(Fwck ×Pr eScalar)
nal 10 kHz RC. The following table shows an example of the Watchdog time-out interval under different FWCK and pre-
scalars.
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EIE – Extensive Interrupt Enable
7
ET2
R/W
6
5
4
3
-
-
2
1
0
ESPI
R/W
EPWM
R/W
EWDI
R/W
ECPTF
R/W
EKB
R/W
EI2C
R/W
Address: E8H
Reset value: 0000 0000B
Bit
Name
Description
4
EWDI
0 = Disable Watchdog Timer Interrupt.
1 = Enable Watchdog Timer Interrupt.
The Watchdog Timer time-out selection will result in different time-out values depending on the clock speed. The reset,
when enabled, will occur when 512 clocks after time-out has occurred.
Table 11-1 Time-out Values for the Watchdog Timer
WDT Interrupt time-out
Reset time-out
Number of
(WPS2,WPS1,WPS0)
Pre-Scalar
Number of
Time
Time
57.6ms
64ms
Clocks
Clocks
(0,0,0)
(0,0,1)
(0,1,0)
(0,1,1)
(1,0,0)
(1,0,1)
1/1
1/2
26
6.4ms
12.8ms
26+512
2x26
2x26+512
8x26+512
16x26+512
32x26+512
64x26+512
1/8
8x26
51.2ms
102.4ms
153.6ms
256ms
1/16
1/32
1/64
16x26
32x26
64x26
102.40ms
204.80ms
409.60ms
460.8ms
(1,1,0)
(1,1,1)
1/128
1/256
128x26
256x26
819.20ms
1.638s
128x26+512
256x26+512
870.4ms
1.6892s
11.2 Applications of Watchdog Timer Reset
The main application of the Watchdog Timer with time-out reset enabling is for the system monitor. This is important in
real-time control applications. In case of some power glitches or electro-magnetic interference, the processor may begin to
execute erroneous codes and operate in an unpredictable state. If this is left unchecked the entire system may crash. Using
the Watchdog Timer during software development will require the user to select ideal Watchdog reset locations for insert-
ing instructions to reset the Watchdog Timer. By inserting the instruction setting WDCLR, it will allow the code to run
without any Watchdog Timer reset. However If any erroneous code executes by any power of other interference, the in-
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structions to clear the Watchdog Timer counter will not be executed at the required instants. Thus the Watchdog Timer
reset will occur to reset the system start from an erroneously executing condition. The user should remember that
WDCON0 requires a timed access writing.
11.3 Applications of Watchdog Timer Interrupt
There is another application of the Watchdog Timer, which is used as a simple timer. The WDTF flag will be set while the
Watchdog Timer completes the selected time interval. The software polls the WDTF flag to detect a time-out and the
WDCLR allows software to restart the timer. The Watchdog Timer can be also used as a very long timer. Every time the
time-out occurs, an interrupt will occur if the individual interrupt EWDI (EIE.4) and global interrupt enable EA is set.
In some application of low power consumption, the CPU usually stays in Idle mode when nothing needs to be served to
save power consumption. After a while the CPU will be woken up to check if anything needs to be served at an interval of
programmed period implemented by Timer 0, 1 or 2. However, the current consumption of Idle mode still keeps at a
“mA” level. To further reducing the current consumption to “μA” level, the CPU should stay in Power-Down mode when
nothing needs to be served, and has the ability of waking up at a programmable interval. The N79E845/844/8432 is
equipped with this useful function. It provides a very low power internal RC 10 kHz. Along with the low power consump-
tion application, the Watchdog Timer needs to count under Idle and Power-Down mode and wake CPU up from Idle or
Power-Down mode. The demo code to accomplish this feature is shown below.
The demo code of Watchdog Timer waking CPU up from Power Down.
ORG
LJMP
0000H
START
ORG
0053H
LJMP
WDT_ISR
ORG
WDT_ISR:
CLR
0100H
EA
MOV
TA,#0AAH
MOV
TA,#55H
ORL
INC
WDCON0,#01000000B
ACC
;clear Watchdog Timer counter
MOV
SETB
P0,ACC
EA
CLR
EA
MOV
MOV
TA,#0AAH
TA,#55H
ANL
SETB
RETI
WDCON0,#11011111B
EA
;clear Watchdog Timer interrupt flag
START:
MOV
TA,#0AAH
MOV
TA,#55H
ORL
WDCON0,#01000000B
;clear Watchdog Timer counter
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MOV
MOV
ORL
TA,#0AAH
TA,#55H
WDCON0,#10000000B
;enable Watchdog Timer to run
Check_clear:
MOV
JB
A,WDCON0
ACC.6,Check_clear
MOV
MOV
ORL
MOV
MOV
ANL
SETB
MOV
MOV
SETB
TA,#0AAH
TA,#55H
WDCON0,#00000111B
TA,#0AAH
TA,#55H
WDCON1,#11111110B
EWDI
TA,#0AAH
TA,#55H
;choose interval length
;disable Watchdog Timer reset
;enable Watchdog Timer interrupt
WIDPD
SETB
EA
;********************************************************************
;Enter into Power-Down mode
;********************************************************************
LOOP:
ORL
LJMP
PCON,#02H
LOOP
END
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12 Serial Port (UART)
The N79E845/844/8432 includes one enhanced full duplex serial port with automatic address recognition and framing
error detection. The serial port supports three modes of full duplex UART (Universal Asynchronous Receiver and Trans-
mitter) in Mode 1, 2, and 3. This means it can transmit and receive simultaneously. The serial port is also receiving-
buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the
register. The receiving and transmitting registers are both accessed at SBUF. Writing to SBUF loads the transmitting reg-
ister, and reading SBUF accesses a physically separate receiving register. There are four operation modes in serial port. In
all four modes, transmission initiates by any instruction that uses SBUF as a destination register. Note that before serial
port function works, the port latch bits of RXD and TXD pins have to be set to 1.
SCON – Serial Port Control (Bit-addressable)
7
SM0/FE
R/W
6
SM1
R/W
5
SM2
R/W
4
REN
R/W
3
TB8
R/W
2
RB8
R/W
1
TI
R/W
0
RI
R/W
Address: 98H
Reset value: 0000 0000B
Bit
7
Name
SM0/FE
SM1
Description
Serial Port Mode Selection
6
SMOD0 (PCON.6) = 0:
See Table 12–1 Serial Port Mode Description for details.
SMOD0 (PCON.6) = 1:
SM0/FE bit is used as frame error (FE) status flag.
0 = Frame error (FE) does not occur.
1 = Frame error (FE) occurs and is detected.
5
SM2
Multiprocessor Communication Mode Enable
The function of this bit is dependent on the serial port mode.
Mode 0:
This bit select the baud rate between FSYS/12 and FSYS/4.
0 = The clock runs at FSYS/12 baud rate. It maintains standard 8051
compatibility.
1 = The clock runs at FSYS/4 baud rate for faster serial communication.
Mode 1:
This bit checks valid stop bit.
0 = Reception is always valid no matter the logic level of stop bit.
1 = Reception is valid only when the received stop bit is logic 1 and the
received data matches GIVEN or BROADCAST address.
Mode 2 or 3:
For multiprocessor communication.
0 = Reception is always valid no matter the logic level of the 9th bit.
1 = Reception is valid only when the received 9th bit is logic 1 and the
received data matches GIVEN or BROADCAST address.
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Bit
Name
Description
4
REN
Receiving Enable
0 = Serial port reception is disabled.
1 = Serial port reception is enabled in Mode 1,2, and 3. In Mode 0, clearing and
then setting REN initiates one-byte reception. After reception is complete, this
bit will not be cleared via hardware. The user should clear and set REN again
via software to triggering the next byte reception.
3
2
TB8
RB8
9th Transmitted Bit
This bit defines the state of the 9th transmission bit in serial port Mode 2 and 3. It
is not used in Mode0 and 1.
9th Received Bit
The bit identifies the logic level of the 9th received bit in Modes 2 and 3. In Mode
1, if SM2 0, RB8 is the logic level of the received stop bit. RB8 is not used in
Mode 0.
1
0
TI
RI
Transmission Interrupt Flag
This flag is set via hardware when a byte of data has been transmitted by the
UART after the 8th bit in Mode 0 or the last bit of data in other modes. When the
UART interrupt is enabled, setting this bit causes the CPU to execute the UART
interrupt service routine. This bit should be cleared manually via software.
Receiving Interrupt Flag
This flag is set via hardware when a 8-bit or 9-bit data has been received by the
UART after the 8th bit in Mode 0, after sampling the stop bit in Mode 1, or after
sampling the 9th bit in Mode 2 and 3. SM2 bit has restriction for exception. When
the UART interrupt is enabled, setting this bit causes the CPU to execute to the
UART interrupt service routine. This bit should be cleared manually via software.
Table 12–1 Serial Port Mode Description
Frame
Bits
Mode SM0 SM1
Description
Baud Rate
0
1
2
3
0
0
1
1
0
1
0
1
Synchronous
Asynchronous
Asynchronous
Asynchronous
8
FSYS divided by 12 or by 4[1]
10
11
11
Timer 1 overflow rate divided by 32 or divided by 16[2]
FSYS divided by 64 or 32[2]
Timer 1 overflow rate divided by 32 or divided by 16[2]
[1] While SM2 (SCON.5) is logic 1.
[2] While SMOD (PCON.7) is logic 1.
PCON – Power Control
7
SMOD
R/W
6
5
-
-
4
POF
R/W
3
GF1
R/W
2
GF0
R/W
1
PD
R/W
0
IDL
R/W
SMOD0
R/W
Address: 87H
Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
Description
7
SMOD
Serial Port Double Baud Rate Enable
Setting this bit doubles the serial port baud rate in UART mode 2 and mode 1 or 3
only if Timer 1 overflow is used as the baud rate source. See Table 12–1 Serial Port
Mode Description for details.
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Bit
Name
Description
6
SMOD0
Framing Error Detection Enable
0 = Framing error detection is disabled. SM0/FE (SCON.7) bit is used as SM0 as
standard 80C51 function.
1 = Framing error detection is enabled. SM0/FE bit is used as frame error (FE)
status flag.
SBUF – Serial Data Buffer
7
6
5
4
3
2
1
0
SBUF[7:0]
R/W
Address: 99H
Reset value: 0000 0000B
Bit
Name
Description
7:0
SBUF[7:0]
Serial Data Buffer
This byte actually consists two separate registers. One is the receiving resister, and
the other is the transmitting buffer. When data is moved to SBUF, it goes to the
transmitting buffer and is shifted for serial transmission. When data is moved
from SBUF, it comes from the receiving buffer.
The transmission is initiated through moving a byte to SBUF.
12.1 Mode 0
Mode 0 provides synchronous communication with external devices. Serial data enters and exits through RXD pin. TXD
outputs the shift clock. 8 bits are transmitted or received. Mode 0 therefore provides half-duplex communication because
the transmitting or receiving data is via the same data line RXD. The baud rate is enhanced to be selected as FSYS/12 if
SM2 (SCON.5) is 0 or as FSYS/4 if SM2 is 1. Note that whenever transmitting or receiving, the serial clock is always gen-
erated by the microcontroller. Thus any device on the serial port in Mode 0 should accept the microcontroller as the Mas-
ter. Figure 12–1 shows a simplified functional diagram of the serial port in Mode 0 and associated timing.
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Figure 12–1 Serial Port Mode 0 Function Block
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As shown there is one bidirectional data line (RXD) and one shift clock line (TXD). The shift clock is used to shift data in
or out of the serial port controller bit by bit for a serial communication. Data bits enter or exit LSB first. The band rate is
equal to the shift clock frequency.
Transmission is initiated by any instruction writes to SBUF. The control block will then shift out the clock and begin to
transfer data until all 8 bits are complete. Then the transmitted flag TI (SCON.1) will be set 1 to indicate one byte trans-
mitting complete.
Reception is initiated by clearing and then setting REN (SCON.4) while RI (SCON..0) is 0. This condition tells the serial
port controller that there is data to be shifted in. This process will continue until 8 bits have been received. Then the re-
ceived flag RI will be set as 1. Note that REN will not be cleared via hardware. The user should first clear RI, clear REN
and then set REN again via software to triggering the next byte reception.
12.2 Mode 1
Mode 1 supports asynchronous, full duplex serial communication. The asynchronous mode is commonly used for com-
munication with PCs, modems or other similar interfaces. In Mode 1, 10 bits are transmitted (through TXD) or received
(through RXD) including a start bit (logic 0), 8 data bits (LSB first) and a stop bit (logic 1). The baud rate is determined
by the Timer 1. SMOD (PCON.7) setting 1 makes the baud rate double while Timer 1 is selected as the clock source. Fig-
ure 12–2 shows a simplified functional diagram of the serial port in Mode 1 and associated timings for transmitting and
receiving.
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Figure 12–3 Serial Port Mode 1 Function Block and Timing Diagram
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Transmission is initiated by any writing instructions to SBUF. Transmission takes place on TXD pin. First the start bit
comes out, the 8-bit data follows to be shifted out and then ends with a stop bit. After the stop bit appears, TI (SCON.1)
will be set to indicate one byte transmission complete. All bits are shifted out depending on the rate determined by the
baud rate generator.
Once the baud rate generator is activated and REN (SCON.4) is 1, the reception can begin at any time. Reception is initi-
ated by a detected 1-to-0 transition at RXD. Data will be sampled and shifted in at the selected baud rate. In the midst of
the stop bit, certain conditions should be met to LOAD SBUF with the received data:
1. RI (SCON.0) = 0, and
2. Either SM2 (SCON.5) = 0, or the received stop bit = 1 while SM2 = 1.
If these conditions are met, the SBUF will be loaded with the received data, the RB8 (SCON.2) with stop bit, and RI will
be set. If these conditions fail, there will be no data loaded and RI will remain 0. After above receiving progress, the serial
control will look forward another 1-0 transition on RXD pin to start next data reception.
12.3 Mode 2
Mode 2 supports asynchronous, full duplex serial communication. Different from Mode1, there are 11 bits to be transmit-
ted or received. They are a start bit (logic 0), 8 data bits (LSB first), a programmable 9th bit TB8 or RB8 bit and a stop bit
(logic 1). The most common use of 9th bit is to put the parity bit in it. The baud rate is fixed as 1/32 or 1/64 the clock sys-
tem frequency depending on SMOD bit. Figure 12–4 shows a simplified functional diagram of the serial port in Mode 2
and associated timings for transmitting and receiving.
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Figure 12–4 Serial Port Mode 2 Function Block and Timing Diagram
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Transmission is initiated by any writing instructions to SBUF. Transmission takes place on TXD pin. First the start bit
comes out, the 8-bit data and bit TB8 (SCON.3) follows to be shifted out and then ends with a stop bit. After the stop bit
appears, TI will be set to indicate the transmission complete.
While REN is set, the reception is allowed at any time. A falling edge of a start bit on RXD will initiate the reception pro-
gress. Data will be sampled and shifted in at the selected baud rate. In the midst of the 9th bit, certain conditions should be
met to LOAD SBUF with the received data:
1. RI (SCON.0) = 0, and
2. Either SM2(SCON.5) = 0, or the received 9th bit = 1 while SM2 = 1.
If these conditions are met, the SBUF will be loaded with the received data, the RB8(SCON.2) with TB8 bit and RI will
be set. If these conditions fail, there will be no data loaded and RI will remain 0. After above receiving progress, the serial
control will look forward another 1-0 transition on RXD pin to start next data reception.
12.4 Mode 3
Mode 3 has the same operation as Mode 2, except its baud rate clock source. As shown is Figure 12–5, Mode 3 uses Tim-
er 1 overflow as its baud rate clock.
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Figure 12–5 Serial Port Mode 3 Function Block
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12.5 Baud Rates
Table 12–2 UART Baud Rate Formulas
UART Mode
Baud Rate Clock Source
Baud Rate
FSYS / 4 [1]
or
FSYS /12
2SMOD
0
2
Oscillator
Oscillator
×FSYS
64
2SMOD
32
2SMOD
32
FSYS
256 − TH1
FSYS
256 − TH1
Timer/Counter 1 overflow[2]
[3]
1 or 3
×
or
×
12×
4×
[1] While SM2 (SCON.5) is set as logic 1.
[2] Timer 1 is configured as a timer in auto-reload mode (Mode 2).
[3] While T1M (CKCON.4) is set as logic 1.
Note that in using Timer 1 as the baud rate generator, the interrupt should be disabled. The Timer itself can be configured
for either “Timer” or “Counter” operation. And Timer 1 can be in any of its 3 running modes. In the most typical applica-
tions, it is configured for “Timer” operation, in the auto-reload mode (Mode2). If Timer 1 is used as the baud rate genera-
tor, the reloaded value is stored in TH1. Therefore the baud rate is determined by TH1 value.
Table 12–3 lists various commonly used baud rates and how they can be obtained from Timer 1. In this mode, Timer 1
operates with divided-by-12 pre-scale, as an auto-reload Timer with SMOD (PCON.7) is 0. If SMOD is 1, the baud rate
will be doubled.
Table 12–3 Timer 1 Generated Commonly Used Baud Rates
TH1 reload value
Oscillator Frequency (MHz)
Baud Rate
57600
38400
19200
9600
11.0592
14.7456
18.432
22.1184
FFh
FFh
FEh
FCh
F8h
F0h
E0h
80h
FDh
FAh
F4h
E8h
D0h
40h
FDh
FAh
F4h
E8h
A0h
FBh
F6h
ECh
D8h
60h
4800
2400
1200
300
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12.6 Framing Error Detection
Framing error detection is provided for asynchronous modes. (Mode 1, 2 and 3.) The framing error occurs when a valid
stop bit is not detected due to the bus noise or contention. The UART can detect a framing error and notify the software.
The framing error bit, FE, is located in SCON.7. This bit normally serves as SM0. While the framing error detection ena-
ble bit SMOD0 (PCON.6) is set 1, it serves as FE flag. Actually SM0 and FE locate in different registers.
The FE bit will be set 1 via hardware while a framing error occurs. It should be cleared via software. Note that SMOD0
should be 1 while reading or writing to FE. If FE is set, any of the following frames received without any error will not
clear the FE flag. The clearing has to be done via software.
12.7 Multiprocessor Communication
The communication feature of the N79E845/844/8432 enables a Master device send a multiple frame serial message to a
Slave device in a multi-slave configuration. It does this without interrupting other slave devices that may be on the same
serial line. UART mode 2 or 3 mode can use this feature only. After 9 data bits are received. The 9th bit value is written to
RB8 (SCON.2). The user can enable this function by setting SM2 (SCON.5) as logic 1 so that when the stop bit is re-
ceived, the serial interrupt will be generated only if RB8 is 1. When the SM2 bit is 1, serial data frames that are received
with the 9th bit as 0 do not generate an interrupt. In this case, the 9th bit simply separates the address from the serial data.
When the Master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out an ad-
dress byte to identify the target slave. Note that in this case, an address byte differs from a data byte: In an address byte,
the 9th bit is 1 and in a data byte, it is 0. The address byte interrupts all slaves so that each slave can examine the received
byte and see if it is being addressed. The addressed slave then clears its SM2 bit and prepares to receive incoming data
bytes. The SM2 bits of slaves that were not addressed remain set, and they continue operating normally while ignoring the
incoming data bytes.
Follow the steps below to configure multiprocessor communications:
1. Set all devices (Masters and Slaves) to UART mode 2 or 3.
2. Write the SM2 bit of all the Slave devices to 1.
3. The Master device's transmission protocol is:
– First byte: the address, identifying the target slave device, (9th bit = 1).
– Next bytes: data, (9th bit = 0).
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4. When the target Slave receives the first byte, all of the Slaves are interrupted because the 9th data bit is 1. The targeted
Slave compares the address byte to its own address and then clears its SM2 bit to receiving incoming data. The other
slaves continue operating normally.
5. After all data bytes have been received, set SM2 back to 1 to wait for next address.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. For mode 1 reception, if
SM2 is 1, the receiving interrupt will not be issue unless a valid stop bit is received.
12.8 Automatic Address Recognition
The automatic address recognition is a feature which enhances the multiprocessor communication feature by allowing the
UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature
saves a great deal of software overhead by eliminating the need for the software to examine every serial address which
passes by the serial port. Only when the serial port recognizes its own address, the receiver sets RI bit to request an inter-
rupt. The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled.
(SM2 is set.)
If desired, the user may enable the automatic address recognition feature in Mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. RI is set only when the received command frame address matches the device’s ad-
dress and is terminated by a valid stop bit.
Using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by
invoking the “Given” slave address or addresses. All of the slaves may be contacted by using the “Broadcast” address.
Two SFRs are used to define the slave address, SADDR, and the slave address mask, SADEN. SADEN is used to define
which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can be logically ANDed with
the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the “Given”
address allows multiple slaves to be recognized while excluding others.
SADDR – Slave Address
7
6
5
4
3
2
1
0
SADDR[7:0]
R/W
Address: A9H
Reset value: 0000 0000B
Bit
Name
Description
7:0
SADDR[7:0] Slave Address.
This byte specifies the microcontroller’s own slave address for UART multipro-
cessor communication.
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SADEN – Slave Address Mask
7
6
5
4
3
2
1
0
SADEN[7:0]
R/W
Address: B9H
Reset value: 0000 0000B
Bit
Name
Description
7:0
SADEN[7:0] Slave Address Mask.
This byte is a mask byte that contains “don’t-care” bits (defined by zeros) to form
the device’s given address. The don’t-care bits provide the flexibility to address one or
more Slaves at a time.
The following examples will help to show the versatility of this scheme.
Example 1, slave 0:
SADDR = 11000000b
SADEN = 11111101b
Given = 110000X0b
Example 2, slave 1:
SADDR = 11000000b
SADEN = 11111110b
Given = 1100000Xb
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0
requires 0 in bit 0 and it ignores bit 1. Slave 1 requires 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would
be 1100 0010B since slave 1 requires 0 in bit 1. A unique address for slave 1 would be 11000001b since 1 in bit 0 will
exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0
(for slave 1). Thus, both could be addressed with 11000000b.
In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:
Example 1, slave 0:
SADDR = 11000000b
SADEN = 11111001b
Given = 11000XX0b
Example 2, slave 1:
SADDR = 11100000b
SADEN = 11111010b
Given = 11100X0Xb
Example 3, slave 2:
SADDR = 11000000b
SADEN = 11111100b
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Given = 110000XXb
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0
and it can be uniquely addressed by 11100110b. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by
11100101b. Slave 2 requires that bit 2 = 0 and its unique address is 11100011b. To select Slaves 0 and 1 and exclude
Slave 2 use address 11100100b, since it is necessary to make bit 2 = 1 to exclude slave 2. The “Broadcast” address for
each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as “don’t care”. In
most cases, interpreting the “don’t care” as ones, the broadcast address will be FFH.
On reset, SADDR and SADEN are initialized to 00H. This produces a “Given” address of all “don’t care” as well as a
“Broadcast” address of all XXXXXXXXb (all “don’t care” bits). This effectively disables the automatic addressing mode
and allows the microcontroller to use standard UART drivers which do not make use of this feature.
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13 Serial Peripheral Interface (SPI)
13.1 Features
The N79E845/844/8432 exists a Serial Peripheral Interface (SPI) block to support high-speed serial communication. SPI
is a full-duplex, high-speed, synchronous communication bus between MCUs or other peripheral devices such as serial
EEPROM, LCD driver, or D/A converter. It provides either Master or Slave mode, high-speed rate up to FSYS/16 for Mas-
ter mode and FSYS/4 for Slave mode, transfer complete and write collision flag. For a multi-master system, SPI supports
Master Mode Fault to protect a multi-master conflict.
13.2 Functional Description
FSYS
S
Divider
/16, /32, /64, /128
MISO
MOSI
M
M
S
MSB
LSB
8-bit Shift Register
Read Data Buffer
Select
CLOCK
SPCLK
SS
Clock Logic
MSTR
SPIEN
SPI Status Control Logic
SPI Status Register
SPI Control Register
SPI Interrupt
Request
Internal
Data Bus
Figure 13–1 SPI Block Diagram
Figure 13–1 shows SPI block diagram and provides an overview of SPI architecture in this device. The main blocks of SPI
are the SPI control register logic, SPI status logic, clock rate control logic, and pin control logic. For a serial data transfer
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or receiving, The SPI block exists a shift register and a read data buffer. It is single buffered in the transmit direction and
double buffered in the receiving direction. Transmit data cannot be written to the shifter until the previous transfer is com-
plete. Receiving logic consists of parallel read data buffer so the shift register is free to accept a second data, as the first
received data will be transferred to the read data buffer.
The four pins of SPI interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SPCLK), and
Slave Select ( SS ). The MOSI pin is used to transfer a 8-bit data in series from the Master to the Slave. Therefore, MOSI
is an output pin for Master device and a input for Slave. Respectively, the MISO is used to receive a serial data from the
Slave to the Master.
The SPCLK pin is the clock output in Master mode, but is the clock input in Slave mode. The shift clock is used to syn-
chronize the data movement both in and out of the devices through their MOSI and MISO pins. The shift clock is driven
by the Master mode device for eight clock cycles which exchanges one byte data on the serial lines. For the shift clock is
always produced out of the Master device, the system should never exist more than one device in Master mode for avoid-
ing device conflict. It is strongly recommended that the Schmitt trigger input buffer be enabled.
Each Slave peripheral is selected by one Slave Select pin ( SS ). The signal should stay low for any Slave access. When
SS is driven high, the Slave device will be inactivated. If the system is multi-slave, there should be only one Slave de-
vice selected at the same time. In the Master mode MCU, the SS pin does not function and it can be configured as a gen-
eral purpose I/O. However, SS can be used as Master Mode Fault detection (see Section 13.7“Mode Fault Detection”)
via software setting if multi-master environment exists. The N79E845/844/8432 also provide auto-activating function to
toggle SS between each byte-transfer.
Master/Slave
MCU1
Master/Slave
MCU2
MISO
MOSI
SPCLK
SS
MISO
MOSI
SPCLK
SS
0
1
3
0
1
3
I/O
PORT
I/O
PORT
Slave device 1
Slave device 2
Slave device 3
Figure 13–2 SPI Multi-master, Multi-slave Interconnection
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Figure 13–2 shows a typical interconnection of SPI devices. The bus generally connects devices together through three
signal wires, MOSI to MOSI, MISO to MISO, and SPCLK to SPCLK. The Master devices select the individual Slave
devices by using four pins of a parallel port to control the four SS pins. MCU1 and MCU2 play either Master or Slave
mode. The SS should be configured as Master Mode Fault detection to avoid multi-master conflict.
MOSI
MISO
MOSI
MISO
SPI shift register
SPI shift register
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SPCLK SPCLK
SPI clock
generator
SS
SS
*
Master MCU
* SS configuration follows DISMODF and SSOE bits.
Slave MCU
VSS
Figure 13–3 SPI Single-master, Single-slave Interconnection
Figure 13–3 shows the simplest SPI system interconnection, single-master and signal-slave. During a transfer, the Master
shifts data out to the Slave via MOSI line. While simultaneously, the Master shifts data in from the Slave via MISO line.
The two shift registers in the Master MCU and the Slave MCU can be considered as one 16-bit circular shift register.
Therefore, while a transfer data pushed from Master into Slave, the data in Slave will be also pulled in Master device re-
spectively. The transfer effectively exchanges the data which was in the SPI shift registers of the two MCUs.
By default, SPI data is transferred MSB first. If the LSBFE (SPCR.5) is set, SPI data shifts LSB first. This bit does not
affect the position of the MSB and LSB in the data register. Note that all following Description and figures are under the
condition of LSBFE logic 0. MSB is transmitted and received first.
13.3 SPI Control Registers
There are three SPI registers to support its operations, they are SPI control register (SPCR), SPI status register (SPSR),
and SPI data register (SPDR), which registers provide control, status, data storage functions, and clock rate selection. The
following registers relate to SPI function.
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SPCR – Serial Peripheral Control Register
7
SSOE
R/W
6
5
4
3
2
1
0
SPIEN
R/W
LSBFE
R/W
MSTR
R/W
CPOL
R/W
CPHA
R/W
SPR1
R/W
SPR0
R/W
Address: F3H
Reset value: 0000 0000B
Bit
7
Name
SSOE
Description
Slave Select Output Enable
This bit is used in combination with the DISMODF (SPSR.3) bit to determine the
feature of SS pin. This bit takes effect only under MSTR = 1 and DISMODF = 1
condition.
0 = SS functions as a general purpose I/O pin.
1 = SS automatically goes low for each transmission when selecting external
Slave device and goes high during each idle state to de-select the Slave device.
6
5
4
SPIEN
LSBFE
MSTR
SPI Enable
0 = Disable SPI function.
1 = Enable SPI function.
LSB First Enable
0 = The SPI data is transferred MSB first.
1 = The SPI data is transferred LSB first.
Master Mode Enable
This bit switches the SPI operating between Master and Slave modes.
0 = The SPI is configured as Slave mode.
1 = The SPI is configured as Master mode.
SPI Clock Polarity Selection
3
CPOL
CPOL bit determines the idle state level of the SPI clock. Refer to Figure 13–4
SPI Clock Format
0 = SPI clock is low in idle state.
1 = SPI clock is high in idle state.
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Bit
2
Name
Description
CPHA
SPI clock phase select
CPHA bit determines the data sampling edge of the SPI clock. See Figure 13–4
SPI Clock Format.
0 = The data is sampled on the first edge of the SPI clock.
1 = The data is sampled on the second edge of the SPI clock.
SPI Clock Rate Selection
1
0
SPR1
SPR0
The two bits select four grades of SPI clock divider.
SPR1
SPR0 Divider SPI clock rate
0
0
1
1
0
1
0
1
16
32
64
1.25M bit/s
625k bit/s
312k bit/s
156k bit/s
128
The clock rates above are illustrated under FSYS = 20 MHz condition.
Table 13–1 Slave Select Pin Configuration
DISMODF
SSOE
Master Mode (MSTR = 1)
SS input for Mode Fault
General purpose I/O
Slave Mode (MSTR = 0)
0
x
1
1
0
1
SS Input for Slave select
Automatic SS output
SPSR – Serial Peripheral Status Register
7
SPIF
R/W
6
5
4
3
2
-
-
1
-
-
0
-
-
WCOL
R/W
SPIOVF
R/W
MODF
R/W
DISMODF
R/W
Address: F4H
Reset value: 0000 0000B
Bit
Name
Description
SPI Complete Flag
7
SPIF
This bit is set to logic 1 via hardware while an SPI data transfer is complete or an
receiving data has been moved into the SPI read buffer. If ESPI (EIE .6) and EA
are enabled, an SPI interrupt will be required. This bit should be cleared via soft-
ware. Attempting to write to SPDR is inhibited if SPIF is set.
Write Collision Error Flag
6
WCOL
This bit indicates a write collision event. Once a write collision event occurs, this
bit will be set. It should be cleared via software.
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Bit
Name
SPIOVF
Description
SPI Overrun Error Flag
5
4
This bit indicates an overrun event. Once an overrun event occurs, this bit will be
set. If ESPI and EA are enabled, an SPI interrupt will be required. This bit should
be cleared via software.
Mode Fault Error Flag
MODF
This bit indicates a Mode Fault error event. If SS pin is configured as Mode
Fault input (MSTR = 1 and DISMODF = 0) and SS is pulled low by external de-
vices, a Mode Fault error occurs. Instantly MODF will be set as logic 1. If ESPI
and EA are enabled, an SPI interrupt will be required. This bit should be cleared
via software.
Mode Fault Error Detection Disable
3
DISMODF
This bit is used in combination with the SSOE (SPCR.7) bit to determine the fea-
ture of SS pin. DISMODF affects only in Master mode (MSTR = 1).
0 = Mode Fault detection is not disabled. SS serves as input pin for Mode Fault
detection disregard of SSOE.
1 = Mode Fault detection is disabled. The feature of SS follows SSOE bit.
Reserved
2:0
-
SPDR – Serial Peripheral Data Register
7
6
5
4
3
2
1
0
SPDR[7:0]
R/W
Address: F5H
Reset value: 0000 0000B
Bit
Name
SPDR[7:0]
Description
Serial Peripheral Data
7:0
This byte is used for transmitting or receiving data on SPI bus. A write of this byte
is a write to the shift register. A read of this byte is actually a read of the read da-
ta buffer. In Master mode, a write to this register initiates transmission and recep-
tion of a byte simultaneously.
13.4 Operating Modes
13.4.1
Master Mode
The SPI can operate in Master mode while MSTR (SPCR.4) is set as 1. Only one Master SPI device can initiate transmis-
sions. A transmission always begins by Master through writing to SPDR. The byte written to SPDR begins shifting out on
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MOSI pin under the control of SPCLK. Simultaneously, another byte shifts in from the Slave on the MISO pin. After 8-bit
data transfer complete, SPIF (SPSR.7) will automatically set via hardware to indicate one byte data transfer complete. At
the same time, the data received from the Slave is also transferred in SPDR. The user can clear SPIF and read data out of
SPDR.
13.4.2
Slave Mode
When MSTR is 0, the SPI operates in Slave mode. The SPCLK pin becomes input and it will be clocked by another Mas-
ter SPI device. The SS pin be becomes input. The Master device cannot exchange data with the Slave device until the
SS pin of the Slave device is externally pulled low. Before data transmissions occurs, the SS of the Slave device should
be pulled and remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. If the SS
is force to high at the middle of transmission, the transmission will be aborted and the rest bits of the receiving shifter
buffer will be high and goes into idle state.
In Slave mode, data flows from the Master to the Slave on MOSI pin and flows from the Slave to the Master on MISO
pin. The data enters the shift register under the control of the SPCLK from the Master device. After one byte is received in
the shift register, it is immediately moved into the read data buffer and the SPIF bit is set. A read of the SPDR is actually a
read of the read data buffer. To prevent an overrun and the loss of the byte that caused by the overrun, the Slave should
read SPDR out and the first SPIF should be cleared before a second transfer of data from the Master device comes in the
read data buffer.
13.5 Clock Formats and Data Transfer
To accommodate a wide variety of synchronous serial peripherals, the SPI has a clock polarity bit CPOL (SPCR.3) and a
clock phase bit CPHA (SPCR.2). Figure 13–4 SPI Clock Format shows that CPOL and CPHA compose four different
clock formats. The CPOL bit denotes the SPCLK line level in ISP idle state. The CPHA bit defines the edge on which the
MOSI and MISO lines are sampled. The CPOL and CPHA should be identical for the Master and Slave devices on the
same system. Communicating in different data formats with one another will result in undetermined results.
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Clock Phase (CPHA)
CPHA = 0
CPHA = 1
sample
sample
sample
sample
Figure 13–4 SPI Clock Format
In SPI, a Master device always initiates the transfer. If SPI is selected as Master mode (MSTR = 1) and enabled (SPIEN =
1), writing to the SPI data register (SPDR) by the Master device starts the SPI clock and data transfer. After shifting one
byte out and receiving one byte in, the SPI clock stops and SPIF (SPSR.7) in both Master and Slave are set. If SPI inter-
rupt enable bit ESPI (EIE.6) is set 1 and global interrupt is enabled (EA = 1), the interrupt service routine (ISR) of SPI
will be executed.
Concerning the Slave mode, the SS signal needs to be taken care. As shown in Figure 13–4 SPI Clock Format, when
CPHA = 0, the first SPCLK edge is the sampling strobe of MSB (for an example of LSBFE = 0, MSB first). Therefore,
the Slave should shift its MSB data before the first SPCLK edge. The falling edge of SS is used for preparing the MSB
on MISO line. The SS pin therefore should toggle high and then low between each successive serial byte. Furthermore, if
the slave writes data to the SPI data register (SPDR) while SS is low, a write collision error occurs.
When CPHA = 1, the sampling edge thus locates on the second edge of SPCLK clock. The Slave uses the first SPCLK
clock to shift MSB out rather than the SS falling edge. Therefore, the SS line can remain low between successive trans-
fers. This format may be preferred in systems having single fixed Master and single fixed Slave. The SS line of the
unique Slave device can be tied to VSS as long as only CPHA = 1 clock mode is used.
Note: The SPI should be configured before it is enabled (SPIEN = 1), or a change of LSBFE, MSTR, CPOL, CPHA
and SPR[1:0] will abort a transmission in progress and force the SPI system into idle state. Prior to any configuration
bit changed, SPIEN should be disabled first.
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SPCLK Cycles
1
2
3
4
5
6
7
8
SPCLK Cycles
SPCLK (CPOL=0)
SPCLK (CPOL=1)
Transfer Progress[1]
(internal signal)
MOSI
MISO
MSB
MSB
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
Input to Slave SS
SS output of Master[2]
SPIF (Master)
SPIF (Slave)
[1] Transfer progress starts by a writing SPDR of Master MCU.
[2] SS automatic output affects when MSTR = DISMODF = SSOE = 1.
Figure 13–5 SPI Clock and Data Format with CPHA = 0
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SPCLK Cycles
1
2
3
4
5
6
7
8
SPCLK Cycles
SPCLK (CPOL=0)
SPCLK (CPOL=1)
Transfer Progress[1]
(internal signal)
MOSI
MISO
MSB
MSB
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
[3]
[4]
Input to Slave SS
SS output of Master[2]
SPIF (Master)
SPIF (Slave)
[1] Transfer progress starts by a writing SPDR of Master MCU.
[2] SS automatic output affects when DISMODF = SSOE = MSTR = 1.
[3] If SS of Slave is low, the MISO will be the LSB of previous data. Otherwise, MISO will be high.
[4] While SS stays low, the LSB will last its state. Once SS is released to high, MISO will switch to high level.
Figure 13–6 SPI Clock and Data Format with CPHA = 1
13.6 Slave Select Pin Configuration
The N79E845/844/8432 SPI provides a flexible SS pin feature for different system requirements. When the SPI operates
as a Slave, SS pin always rules as Slave select input. When the Master mode is enabled, SS has three different func-
tions according to DISMODF (SPSR.3) and SSOE (SPCR.7). By default, DISMODF is 0. It means that the Mode Fault
detection activates. SS is configured as a input pin to check if the Mode Fault appears. On the contrary, if DISMODF is
1, Mode Fault is inactivated and the SSOE bit takes over to control the function of the SS pin. While SSOE is 1, it means
the Slave select signal will generate automatically to select a Slave device. The SS as output pin of the Master usually
connects with the SS input pin of the Slave device. The SS output automatically goes low for each transmission when
selecting external Slave device and goes high during each idle state to de-select the Slave device. While SSOE is 0 and
DISMODF is 1, SS is no more used by the SPI and reverts to be a general purpose I/O pin.
13.7 Mode Fault Detection
The Mode Fault detection is useful in a system where more than one SPI devices might become Masters at the same time.
It may induce data contention. A Mode Fault error occurs once the SS is pulled low by others. It indicates that some oth-
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er SPI device is trying to address this Master as if it is a Slave. Instantly the MSTR and SPIEN control bits in the SPCR
are cleared via hardware to disable SPI, Mode Fault flag MODF (SPSR.4) is set and an interrupt is generated if ESPI
(EIE .6) and EA are enabled.
13.8 Write Collision Error
The SPI is signal buffered in the transfer direction and double buffered in the receiving direction. New data for transmis-
sion cannot be written to the shift register until the previous transaction is complete. Write collision occurs while an at-
tempt was made to write data to the SPDR while a transfer was in progress. SPDR is not double buffered in the transmit
direction. Any writing to SPDR cause data to be written directly into the SPI shift register. Once a write collision error is
generated, WCOL (SPSR.6) will be set as 1 via hardware to indicate a write collision. In this case, the current transferring
data continues its transmission. However the new data that caused the collision will be lost. Although the SPI logic can
detect write collisions in both Master and Slave modes, a write collision is normally a Slave error because a Slave has no
indicator when a Master initiates a transfer. During the receive of Slave, a write to SPDAT causes a write collision under
Slave mode. WCOL flag needs to be cleared via software.
13.9 Overrun Error
For receiving data, the SPI is double buffered in the receiving direction. The received data is transferred into a parallel
read data buffer so the shifter is free to accept a second serial byte. However, the received data should be read from SPDR
before the next data has been completely shifted in. As long as the first byte is read out of the read data buffer and SPIF is
cleared before the next byte is ready to be transferred, no overrun error condition occurs. Otherwise the overrun error oc-
curs. In this condition, the second byte data will not be successfully received into the read data register and the previous
data will remains. If overrun occur, SPIOVF (SPSR.5) will be set via hardware. This will also require an interrupt if ena-
bled. Figure 13–7 SPI Overrun Waveform shows the relationship between the data receiving and the overrun error.
Data[n] Receiving Begins
Data[n+1] Receiving Begins
Data[n+2] Receiveing Begins
Shift Register
SPIF
Shifting Data[n] in
Shifting Data[n+1] in
Shifting Data[n+2] in
[1]
[3]
[4]
Read Data Buffer
SPIOVF
Data[n]
Data[n]
Data[n+2]
[2]
[3]
[1] When Data[n] is received, the SPIF will be set.
[2] If SPIF is not clear before Data[n+1] progress done, the SPIOVF will
be set. Data[n] will be kept in read data buffer but Data [n+1] will be lost.
[3] SPIF and SPIOVF must be cleared by software.
[4] When Data[n+2] is received, the SPIF will be set again.
Figure 13–7 SPI Overrun Waveform
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13.10 SPI Interrupts
Three SPI status flags, SPIF, MODF, and SPIOVF, can generate an SPI event interrupt requests. All of them locate in
SPSR. SPIF will be set after completion of data transfer with external device or a new data have been received and copied
to SPDR. MODF becomes set to indicate a low level on SS causing the Mode Fault state. SPIOVF denotes a receiving
overrun error. If SPI interrupt mask is enabled via setting ESPI (EIE.6) and EA is 1, CPU will executes the SPI interrupt
service routine once any of the three flags is set. The user needs to check flags to determine what event caused the inter-
rupt, which the flags are software cleared.
SPIF
SPIOVF
SPI Interrupt
Request
SS
Mode
Fault
Detection
MODF
ESPI
(EIE.6)
EA
MSTR
DISMODF
Figure 13–8 SPI Interrupt Request
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ORG
LJMP
0000H
START
ORG
004BH
LJMP
SPI_ISR
ORG
0100H
SPI_ISR:
ANL
SPSR,#7FH
reti
START:
ANL
ANL
ORL
ORL
ANL
SETB
SETB
ORL
SPCR,#0DFH
SPCR,#0F7H
SPCR,#04H
SPCR,#10H
SPCR,#0FCH
ESPI
;MSB first
;The SPI clock is low in idle mode
;The data is sample on the second edge of SPI clock
;SPI in Master mode
;SPI clock = Fosc/16
;Enable SPI interrupt
EA
SPCR,#40H
;Enable SPI function
MOV
ORL
SPDR,#90H
PCON,#01H
;Send 0x90 to Slave
;Enter idle mode
SJMP
END
$
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14 Keyboard Interrupt (KBI)
The N79E845/844/8432 provides the 8 keyboard interrupt function to detect keypad status which key is acted, and allow a
single interrupt to be generated when any key is pressed on a keyboard or keypad connected to specific pins of the
N79E845/844/8432, as shown in the following figure. This interrupt may be used to wake up the CPU from Idle or Power-
down mode, after chip is in Power-down or Idle mode.
Keyboard function is supported through by Port 0. It can allow any or all pins of Port 0 to be enabled to cause this inter-
rupt. Port pins are enabled by the setting of bits of KBI0 ~ KBI7 in the KBI register, as shown in the following figure. The
Keyboard Interrupt Flag, KBIF[7:0] in the KBIF(EAH), is set when any enabled pin is triggered while the KBI interrupt
function is active, an interrupt will be generated if it has been enabled. The KBIF[7:0] bit is set by hardware and should be
cleared by software. To determine which key was pressed, the KBI will allow the interrupt service routine to poll port 0.
KBI supports four triggered conditions － low level, falling edge, rising edge and either rising or falling edge detection.
The triggered condition of each port pin is individually controlled by two bits KBLS1(ECH).x and KBLS0(EBH).x where
x is 0 to 7. After Trigger occurs and two machines pass, KBIF assert.
KBI is generally used to detect an edge transient from peripheral devices like keyboard or keypad. During idle state, the
system prefers to enter Power-Down mode to minimize power consumption and waits for event trigger. The
N79E845/844/8432 supports KBI interrupt waking up MCU from Power down. Note that if KBI is selected as any of edge
trigger mode, restrictions should be followed to make Power down woken up valid. For a falling edge waking up, pin state
should be high at the moment of entering Power-Down mode. Respectively, pin state should be low for a rising edge wak-
ing up.
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Low-level/
edge detect
P0.7
P0.6
KBIF.7
KBIF.6
KBI.7
Low-level/
edge detect
KBI.6
Low-level/
edge detect
P0.5
KBIF.5
KBIF.4
KBIF.3
KBIF.2
KBIF.1
KBI.5
Low-level/
edge detect
P0.4
P0.3
KBI Interrupt
Request
KBI.4
Low-level/
edge detect
EIE.EKB
[KBIS1.x, KBIS0.x]
KBI.3
Low-level/
edge detect
P0.2
P0.1
P0.0
[00]
[01]
[10]
[11]
KBI.2
Low-level/
edge detect
KBI.1
P0.x
Low-level/
edge detect
or
X=0~7
KBIF.0
KBI.0
Low-
level
KBI Low-leve/Edge detect selection
Figure 14-1 Keyboard Interrupt Detection
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Table 14–1 Configuration for Different KBI Level Selection
KBLS1.n
KBLS0.n
KBI Channel n Type
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Either falling or rising edge
Low level
KBIE – Keyboard Interrupt Enable Register
7
KBIE.7
R/W
6
5
4
3
2
1
0
KBIE.6
R/W
KBIE.5
R/W
KBIE.4
R/W
KBIE.3
R/W
KBIE.3
R/W
KBIE.1
R/W
KBIE.0
R/W
Address: E9H
Reset value: 0000 0000B
Bit
7:0
Name
KBIE
Description
Keyboard Interrupt
Enable P0[7:0] as a cause of a Keyboard interrupt.
KBIF – Keyboard Interface Flags
7
6
5
4
3
2
1
0
KBIF[7:0]
R (level)
R/W (edge)
Address: EAH
Reset value: 0000 0000B
Bit
Name
Description
7:0
KBIFn
Keyboard Interface Channel n Flag
If any edge trigger mode of KBI is selected, this flag will be set by hardware if KBI
channel n (P0.n) detects a type defined edge. This flag should be cleared by soft-
ware.
If the low level trigger mode of KBI is selected, this flag follows the inverse of the
input signal’s logic level on KBI channel n (P0.n)l. Software cannot control it.
KBLS0 – Keyboard Level Select 0[1]
7
6
5
4
3
2
1
0
KBLS0[7:0]
R/W
Address: EBH
Reset value: 0000 0000B
Bit
Name
Description
7:0
KBLS0[7:0]
Keyboard Level Select 0
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KBLS1 – Keyboard Level Select 1[1]
7
6
5
4
3
2
1
0
KBLS1[7:0]
R/W
Address: ECH
Reset value: 0000 0000B
Bit
Name
Description
7:0
KBLS1[7:0]
Keyboard Level Select 1
[1] KBLS1 and KBLS0 is used in combination to determine the input type of each channel of KBI (on P0). Refer to Table 14–1 Configuration
for Different KBI Level Select.
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15 Analog-To-Digital Converter (ADC)
The ADC contains a DAC which converts the contents of a successive approximation register to a voltage (VDAC) which
is compared to the analog input voltage (Vin). The output of the comparator is fed to the successive approximation control
logic which controls the successive approximation register. A conversion is initiated by setting ADCS in the ADCCON0
register. ADCS can be set by software only or by either hardware or software.
Note that when the ADC function is disabled, all ADC related SFR bits will be unavailable and will not effect any other
CPU functions. The power of ADC block is approached to zero.
The software only start mode is selected when control bit ADCCON0.5 (ADCEX) =0. A conversion is then started by
setting control bit ADCCON0.3 (ADCS) The hardware or software start mode is selected when ADCCON0.5 (ADCEX)
=1, and a conversion may be started by setting ADCCON0.3 as above or by applying a rising edge to external pin
STADC. When a conversion is started by applying a rising edge, a low level should be applied to STADC for at least one
machine-cycle followed by a high level for at least one machine-cycle.
The low-to-high transition of STADC is recognized at the end of a machine-cycle, and the conversion commences at the
beginning of the next cycle. When a conversion is initiated by software, the conversion starts at the beginning of the ma-
chine-cycle which follows the instruction that sets ADCS. ADCS is actually implemented with tpw flip-flops: a command
flip-flop which is affected by set operations, and a status flag which is accessed during read operations.
The next two machine-cycles are used to initiate the converter. At the end of the first cycle, the ADCS status flag is set
end a value of “1” will be returned if the ADCS flag is read while the conversion is in progress. Sampling of the analog
input commences at the end of the second cycle.
During the next eight machine-cycles, the voltage at the previously selected pin of port 0 is sampled, and this input volt-
age should be stable to obtain a useful sample. In any event, the input voltage slew rate should be less than 10V/ms to
prevent an undefined result.
The successive approximation control logic first sets the most significant bit and clears all other bits in the successive ap-
proximation register (10 0000 0000b). The output of the DAC (50% full scale) is compared to the input voltage Vin. If the
input voltage is greater than VDAC, the bit remains set; otherwise if is cleared.
The successive approximation control logic now sets the next most significant bit (11 0000 0000b or 01 0000 0000b, de-
pending on the previous result), and the VDAC is compared to Vin again. If the input voltage is greater than VDAC, the bit
remains set; otherwise it is cleared. This process is repeated until all ten bits have been tested, at which stage the result of
the conversion is held in the successive approximation register. The conversion takes four machine-cycles per bit.
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The end of the 10-bit conversion is flagged by control bit ADCCON0.4 (ADCI). The upper 8 bits of the result are held in
special function register ADCH, and the two remaining bits are held in ADCCON0.7 (ADC.1) and ADCCON0.6
(ADC.0). The user may ignore the two least significant bits in ADCCON0 and use the ADC as an 8-bit converter (8 upper
bits in ADCH). In any event, the total actual conversion time is 35 machine-cycles. ADC will be set and the ADCS status
flag will be reset 35 cycles after the ADCS is set.
Control bits ADCCON0.0 ~ ADCCON0.2 are used to control an analog multiplexer which selects one of 8 analog chan-
nels. An ADC conversion in progress is unaffected by an external or software ADC start. The result of a completed con-
version remains unaffected provided ADCI = logic 1; a new ADC conversion already in progress is aborted when entering
Idle or Power-down mode. The result of a completed conversion (ADCI = logic 1) remains unaffected when entering Idle
mode.
When ADCCON0.5 (ADCEX) is set by external pin to start ADC conversion, after the N79E845/844/8432 entry Idle
mode, P1.4 can start ADC conversion at least ONE machine-cycle.
MSB
Start
Successive
Approximation
Register
Successive
Approximation
Control Logic
DAC
Ready
(Stop)
LSB
Comparator
-
V
DAC
Vin
+
Figure 15-1 Successive Approximation ADC
The ADC circuit has its own supply pins (AVDD and AVSS) and one pins (Vref+) connected to each end of the DAC’s
resistance-ladder that the AVDD and Vref+ are connected to VDD and AVSS is connected to VSS. The ladder has 1023
equally spaced taps, separated by a resistance of “R”. The first tap is located 0.5×R above AVSS, and the last tap is located
0.5×R below Vref+. This gives a total ladder resistance of 1024×R. This structure ensures that the DAC is monotonic and
results in a symmetrical quantization error.
For input voltages between AVSS and [(Vref+) + ½ LSB], the 10-bit result of an A/D conversion will be 0000000000B =
000H. For input voltages between [(Vref+) – 3/2 LSB] and Vref+, the result of a conversion will be 1111111111B =
3FFH. Avref+ and AVSS may be between AVDD + 0.2V and AVSS – 0.2 V. Avref+ should be positive with respect to
AVSS, and the input voltage (Vin) should be between Avref+ and AVSS.
The result can always be calculated according to the following formula:
Vin
Vin
Result = 1024 ×
or Result = 1024 ×
AVref +
VDD
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VDD
ADC Conversion Block
ADC0(P0.1)
0
1
ADC1(P0.2)
ADC2(P0.3)
ADC3(P0.4)
ADC4(P0.5)
ADC5(P0.6)
ADC6(P0.7)
Band-gap(1.3V)
Analog
Input
Multiplexer
Vref+
AVDD
ADC.[9:0]
ADC0SEL(ADCCON1.0)
AADR[2:0]
ADCI[3]
(ADCCON0.4)
ADCCON0[2:0]
ADCS[1]
0
1
(ADCCON0.3)
10-bits
ADC Block
ADCS[2]
P1.4
ADCEN
(ADCCON1.7)
ADCEX
(ADCCON0.5)
CPU clk
FSYS/4
0
ADCCLK
AVSS
VSS
RC osc
RC22MHz/4
or RC11MHz/2
1
RCCLK(ADCCON1.1)
Note: [1]. Write to ADCS to start ADC convertion
[2]. Read from ADCS to monitor ADC convertion finished or not.
[3]. Read from ADCI to monitor ADC convertion finished or not.
Figure 15-2 ADC Block Diagram
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ADCCON0 – ADC Control Register 0
7
ADC.1
R/W
6
5
4
3
2
1
0
ADC.0
R/W
ADCEX
R/W
ADCI
R/W
ADCS
R/W
AADR2
R/W
AADR1
R/W
AADR0
R/W
Address: F8H
Reset value: 0000 0000B
Bit
7
Name
Description
ADC.1
ADC conversion result.
ADC conversion result.
6
ADC.0
5
ADCEX
0 = Disable external start of conversion by P1.4.
1 = Enable external start of conversion by P1.4. The STADC signal at least 1 machine-
cycle.
4
3
ADCI
ADCS
0 = The ADC is not busy.
1 = The ADC conversion result is ready to be read. An interrupt is invoked if it is ena-
bled. It can
not set by software.
ADC Start and Status: Set this bit to start an A/D conversion. It may be also set by
STADC if ADCEX is 1. This signal remains high while the ADC is busy and is reset
right after ADCI is set.
Notes:
It is recommended to clear ADCI before ADCS is set. However, if ADCI is cleared and
ADCS is set at the same time, a new A/D conversion may start on the same channel.
Software clearing of ADCS will abort conversion in progress.
ADC cannot start a new conversion while ADCS or ADCI is high.
2
1
0
AADR2
AADR1
AADR0
ADC input select.
ADC input select.
ADC input select.
ADCI
ADCS
ADC Status
0
0
1
1
0
1
0
1
ADC not busy; A conversion can be started.
ADC busy; Start of a new conversion is blocked
Conversion completed; the start of a new conversion requires ADCI = 0
Conversion completed; the start of a new conversion requires ADCI = 0
If ADC is cleared by software while ADCS is set at the same time, a new A/D conversion with the same channel number
may be started. However, it is recommended to reset ADCI before ADCS is set.
ADDR2, AADR1, AADR0: ADC Analog Input Channel select bits:
These bits can only be changed when ADCI and ADCS are both zero.
AADR2
AADR1
AADR0
Selected Analog Channel
ADC0 (P0.1)
0
0
0
0
0
1
0
1
0
ADC1 (P0.2)
ADC2 (P0.3)
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0
1
1
1
1
0
0
1
1
0
1
0
ADC3 (P0.4)
ADC4 (P0.5)
ADC5 (P0.6)
ADC6 (P0.7)
ADCH – ADC Converter Result Register
7
ADC.9
R/W
6
5
4
3
2
1
0
ADC.8
R/W
ADC.7
R/W
ADC.6
R/W
ADC.5
R/W
ADC.4
R/W
ADC.3
R/W
ADC.2
R/W
Address: E2H
Reset value: 0000 0000B
Bit
Name
ADCH
Description
7:0
ADC conversion result bits [9:2].
ADCCON1 – ADC Control Register
7
ADCEN
R/W
6
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
0
RCCLK
R/W
ADC0SEL
R/W
Address: E1H
Reset value: 0000 0000B
Bit
Name
Description
7
ADCEN
0 = Disable ADC circuit.
1 = Enable ADC circuit.
6:2
1
-
Reserved
RCCLK
0 = The FSYS/4 clock is used as ADC clock.
1 = The internal RC/2 clock is used as ADC clock.
0
ADC0SEL
0 = Select ADC channel 0 as input.
1 = Select Band-gap (~1.3V) as input.
P0DIDS – Port0 Digital Input Disable
7
6
5
4
3
2
1
0
P0DIDS[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: F6H
Reset value: 0000 0000B
Bit
Name
P0DIDS.x
Description
1 = Disable digital function for each Port0.
7:0
0 = Enable digital function for each Port0.
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The demo code of ADC channel 0 with clock source = Fsys/4 is as follows:
ORG
LJMP
0000H
START
ORG
CLR
005BH
ADCI
;ADC Interrupt Service Routine
;Clear ADC flag
reti
START:
ORL
ORL
ANL
ANL
ANL
SETB
SETB
ORL
P0DIDS,#02H
P0M1,#02H
P0M2,#0FDH
ADCCON0,#0F8H
ADCCON1,#0FDH
EADC
; Disable digital function for P0.1
; ADC0(P0.1) is input-only mode
;ADC0(P0.1) as ADC Channel
;The FSYS/4 clock is used as ADC clock.
;Enable ADC Interrupt
EA
ADCCON1,#80H
;Enable ADC Function
Convert_LOOP:
SETB
ORL
MOV
ADCS
PCON,#01H
P0,ADCH
;Trigger ADC
;Enter idle mode
;Converted Data put in P0 and P1
MOV
P1,ADCL
SJMP
Convert_LOOP
END
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16
Inter-Integrated Circuit (I2C)
16.1 Features
The Inter-Integrated Circuit (I2C) bus serves as a serial interface between the microcontroller and the I2C devices such as
EEPROM, LCD module, and so on. The I2C bus used two wires design (a serial data line SDA and a serial clock line
SCL) to transfer information between devices.
The I2C bus uses bidirectional data transfer between masters and slaves. There is no central master and the multi-master
system is allowed by arbitration between simultaneously transmitting masters. The serial clock synchronization allows
devices with different bit rates to communicate via one serial bus. The I2C bus supports four transfer modes including
master transmitter mode, master receiver mode, slave receiver mode, and slave transmitter mode. The I2C interface only
supports 7-bit addressing mode and General Call can be accepted. The I2C can meet both standard (up to 100kbps) and
fast (up to 400kbps) speeds.
16.2 Functional Description
For the bidirectional transfer operation, the SDA and SCL pins should be connected to open-drain pads. This implements
a wired-AND function which is essential to the operation of the interface. A low level on a I2C bus line is generated when
one or more I2C devices output a “0”. A high level is generated when all I2C devices output “1”, allowing the pull-up re-
sistors to pull the line high.
In the N79E845/844/8432, the user should set output latches of P1.2 and P1.3. as logic 1 before enabling the I2C function
by setting I2CEN (I2CON.6). The P1.2 and P1.3 are configured as the open-drain I/O once the I2C function is enabled.
The P1M2 and P1M1 will be also re-configured. The Schmitt trigger input buffer is strongly recommended to be enabled
by setting P1S for improved glitch suppression.
Vdd
RUP
RUP
SDA
SCL
SDA SCL
SDA SCL
SDA SCL
N79E84x
Other MCU
Slave Device
Figure 16–1 I2C Bus Interconnection
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The I2C is considered free when both lines are high. Meanwhile, any device which can operate as a master can occupy the
bus and generate one transfer after generating a START condition. The bus now is considered busy before the transfer
ends by sending a STOP condition. The master generates all of the serial clock pulses and the START and STOP condi-
tion. However if there is no START condition on the bus, all devices serve as not addressed slave. The hardware looks for
its own slave address or a General Call address. (The General Call address detection may be enabled or disabled by GC
(I2ADDR.0).) If the matched address is received, an interrupt is requested.
Every transaction on the I2C bus is 9 bits long, consisting of 8 data bits (MSB first) and a single acknowledge bit. The
number of bytes per transfer (defined as the time between a valid START and STOP condition) is unrestricted but each
byte has to be followed by an acknowledge bit. The master device generates 8 clock pulse to send the 8-bit data. After the
8th falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an
acknowledge value on the 9th clock pulse. After 9th clock pulse, the data receiving device can hold SCL line stretched low
if next receiving is not prepared ready. It forces the next byte transaction suspended. The data transaction continues when
the receiver releases the SCL line.
SDA
MSB
1
LSB
8
ACK
9
SCL
2
START
STOP
condition
condition
Figure 16–2 I2C Bus Protocol
16.2.1
START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transfer, START (S) and STOP (P) conditions. A
START condition is defined as a high-to-low transition on the SDA line while SCL line is high. The STOP condition is
defined as a low-to-high transition on the SDA line while SCL line is high. A START or a STOP condition is always gen-
erated by the master and I2C bus is considered busy after a START condition and free after a STOP condition. After issu-
ing the STOP condition successful, the original master device will release the control authority and turn back as a not ad-
dressed slave. Consequently, the original addressed slave will become a not addressed slave. The I2C bus is free and lis-
tens to next START condition of next transfer.
A data transfer is always terminated by a STOP condition generated by the master. However, if a master still wishes to
communicate on the bus, it can generate a repeated START (Sr) condition and address the pervious or another slave with-
out first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.
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SDA
SCL
Repeated
STOP
START
START
STOP
START
Figure 16–3 START, Repeated START, and STOP Conditions
16.2.2
7-bit Address with Data Format
Following the START condition is generated, one byte of special data should be transmitted by the master. It includes a 7-
bit long slave address (SLA) following by an 8th bit, which is a data direction bit (R/W), to address the target slave device
and determine the direction of data flow. If R/W bit is 0, it indicates that the master will write information to a selected
slave, and if this bit is 1, it indicates that the master will read information from the slave. An address packet consisting of
a slave address and a read (R) or a write (W) bit is called SLA+R or SLA+W, respectively. A transmission basically con-
sists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. After the specified slave is
addressed by SLA+R/W, the second and following 8-bit data bytes issue by the master or the slave devices according to
the R/W bit configuration.
There is an exception called “General Call” address which can address all devices by giving the first byte of data all 0. A
General Call is used when a master wishes to transmit the same message to several slaves in the system. When this ad-
dress is used, other devices may respond with an acknowledge or ignore it according to individual software configuration.
If a device response the General Call, it operates as like in the slave-receiver mode.
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SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
ADDRESS W/R
ACK
DATA
ACK
DATA
ACK
P
Figure 16–4 Data Format of an I2C Transfer
During the data transaction period, the data on the SDA line should be stable during the high period of the clock, and the
data line can only change when SCL is low.
16.2.3
Acknowledge
The 9th SCL pulse for any transferred byte is dedicated as an Acknowledge (ACK). It allows receiving devices (which can
be the master or slave) to respond back to the transmitter (which can be also the master or slave) by pulling the SDA line
low. The acknowledge-related clock pulse is generated by the master. The transmitter should release control of SDA line
during the acknowledge clock pulse. The ACK is an active-low signal, pulling the SDA line low during the clock pulse
high duty, indicates to the transmitter that the device has received the transmitted data. Commonly, a receiver which has
been addressed is requested to generate an ACK after each byte has been received. When a slave receiver does not
acknowledge (NACK) the slave address, the SDA line should be left high by the slave so that the mater can generate a
STOP or a repeated START condition.
If a slave-receiver does acknowledge the slave address, it switches itself to not addressed slave mode and cannot receive
any more data bytes. This slave leaves the SDA line high. The master should generate a STOP or a repeated START con-
dition.
If a master-receiver is involved in a transfer, because the master controls the number of bytes in the transfer, it should sig-
nal the end of data to the slave-transmitter by not generating an acknowledge on the last byte. The slave-transmitter then
switches to not addressed mode and release the SDA line to allow the master to generate a STOP or a repeated START
condition.
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SDA output by transmitter
SDA output by receiver
SDA = 0, acknowledge (ACK)
SDA = 1, not acknowledge (NACK)
SCL from master
1
2
8
9
Clock pulse for
acknowledge bit
START
condition
Figure 16–5 Acknowledge Bit
16.2.4
Arbitration
A master may start a transfer only if the bus is free. It is possible for two or more masters to generate a START condition.
In these situations, an arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of
the competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low) switches off its data
output stage because the level on the bus does not match its own level. The arbitration lost master switches to the not ad-
dressed slave immediately to detect its own slave address in the same serial transfer whether it is being addressed by the
winning master. It also releases SDA line to high level for not affecting the data transfer initiated by the winning master.
However, the arbitration lost master continues SCL line to generate the clock pulses until the end of the byte in which it
loses the arbitration. If the address matches the losing master’s own slave address, it switches to the addressed-slave
mode.
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from
the SDA line does not match the value the master had output, it has lost the arbitration. Note that a master can only lose
arbitration when it outputs a high SDA value while another master outputs a low value. Arbitration will continue until
only one master remains, and this may take many bits. If several masters are trying to address the same slave, arbitration
will continue into the data packet.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if both masters are trying to
address the same device, arbitration continues on to the comparison of data bits or acknowledge bit.
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DATA 1 from master 1
DATA 2 from master 2
SDA line
Master 1 loses arbitration for DATA 1 ≠ SDA
It immediately switches to not addressed slave
and outputs high level
SCL line
START
condition
Figure 16–6 Arbitration Procedure of Two Masters
Since the control of I2C bus is decided solely by the address or master code and data sent by competing masters, there is
no central master, nor any order of priority on the bus.
Slaves are not involved in the arbitration procedure.
16.3 Control Registers of I2C
There are five control registers to interface the I2C bus. They are I2CON, I2STA, I2DAT, I2ADDR, I2CLK, and I2TMR,
which registers provide protocol control, status, data transmit and receive functions, clock rate configuration, and timeout
notification. The following registers relate to I2C function.
I2CON – I2C Control
7
-
-
6
5
STA
R/W
4
STO
R/W
3
SI
R/W
2
AA
R/W
1
-
-
0
-
-
I2CEN
R/W
Address: C0H
Reset value: 0000 0000B
Bit
7
Name
-
Description
Reserved
I2C Bus Enable
6
I2CEN
0 = I2C bus is disabled.
1 = I2C bus is enabled.
Before enabling the I2C, Px.x and Px.x port latches should be set to logic 1. Once the I2C
bus is enabled, SDA pin (Px.x) and SCL pin (Px.x) will be automatically switched to
the open-drain mode. PxM2 and PxM1 registers will be also re-configured accord-
ingly.
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Bit
Name
STA
Description
5
START Flag
When STA is set, the I2C generates a START condition if the bus is free. If the bus
is busy, the I2C waits for a STOP condition and generates a START condition fol-
lowing.
If STA is set while the I2C is already in Master mode and one or more bytes have been
transmitted or received, the I2C generates a repeated START condition.
Note that STA can be set anytime even in a slave mode, but STA is not hardware automati-
cally cleared after START or repeated START condition has been detected. The user should
take care of it by clearing STA manually.
4
STO
STOP Flag
When STO is set if the I2C is in Master mode, a STOP condition is transmitted to the bus.
STO is automatically cleared by hardware once the STOP condition has been detected on
the bus.
The STO flag setting is also used to recover the I2C device from the bus error state (I2STA
as 00H). In this case, no STOP condition is transmitted to the I2C bus.
If the STA and STO bits are both set and the device is original in Master mode, the I2C bus
will generate a STOP condition and immediately follow a START condition. If the device
is in slave mode, STA and STO simultaneous setting should be avoid from issuing illegal
I2C frames.
3
SI
Serial Interrupt Flag
The SI flag is set by hardware when one of 25 possible I2C status (besides F8H sta-
tus) is entered. After SI is set, the software should read I2STA register to determine which
step has been passed and take actions for next step.
SI is cleared by software. Before the SI is cleared, the low period of SCL line is
stretched. The transaction is suspended. It is useful for the slave device to deal
with previous data bytes until ready for receiving the next byte.
The serial transaction is suspended until SI is cleared by software. After SI is
cleared, I2C bus will continue to generate START or repeated START condition, STOP
condition, 8-bit data, or so on depending on the software configuration of controlling byte
or bits. Therefore the user should take care of it by preparing suitable setting of registers
before SI is software cleared.
2
AA
Acknowledge Assert Flag
If the AA flag is set, an ACK (low level on SDA) will be returned during the
acknowledge clock pulse of the SCL line while the I2C device is a receiver which can
be a master, an addressed slave, an own-address-matching slave, or a Genera-Call accepta-
ble slave.
If the AA flag is cleared, a NACK (high level on SDA) will be returned during the
acknowledge clock pulse of the SCL line while the I2C device is a receiver which can
be a master, an addressed slave. A device with its own AA flag cleared will ignore its own
salve address and the General Call. Consequently, SI will note be asserted and no interrupt
is requested.
Note that if an addressed slave does not return an ACK under slave receiver mode or not
receive an ACK under slave transmitter mode, the slave device will become a not addressed
slave. It cannot receive any data until its AA flag is set and a master addresses it again.
There is a special case of I2STA value C8H occurs under slave transmitter mode. Before
the slave device transmit the last data byte to the master, AA flag can be cleared as 0. Then
after the last data byte transmitted, the slave device will actively switch to not addressed
slave mode of disconnecting with the master. The further reading of the master will be all
FFH.
1:0
-
Reserved
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I2STA – I2C Status
7
6
5
I2STA[7:3]
R
4
3
2
0
R
1
0
R
0
0
R
Address: BDH
Reset value: 1111 1000B
Bit
Name
Description
I2C Status Code
7:3
I2STA[7:3]
The most five bits of I2STA contains the status code. There are 26 possible sta-
tus codes. When I2STA is F8H, no relevant state information is available and SI
flag keeps 0. All other 25 status codes correspond to the I2C states. When each of
the status is entered, SI will be set as logic 1 and a interrupt is requested.
2:0
-
Reserved
The least three bits of I2STA are always read as 0.
I2DAT – I2C Data
7
6
5
4
3
2
1
0
I2DAT[7:0]
R/W
Address: BCH
Reset value: 0000 0000B
Bit
Name
Description
I2C Data
7:0
I2DAT[7:0]
I2DAT contains a byte of the I2C data to be transmitted or a byte which has just re-
ceived. Data in I2DAT remains as long as SI is logic 1. The result of reading or writing
I2DAT during I2C transceiving progress is unpredicted.
While data in I2DAT is shifted out, data on the bus is simultaneously being shifted
in to update I2DAT. I2DAT always shows the last byte that presented on the I2C
bus. Thus the event of lost arbitration, the original value of I2DAT changes after the trans-
action.
I2ADDR – I2C Own Slave Address
7
6
5
4
3
2
1
0
I2ADDR[7:1]
R/W
GC
R/W
Address: C1H
Reset value: 0000 0000B
Bit
Name
Description
I2C device’s own Slave Address
In Master mode:
7:1
I2ADDR[7:1]
These bits have no effect.
In Slave mode:
The 7 bits define the slave address of this I2C device by the user. The master should
address this I2C device by sending the same address in the first byte data after a START or
a repeated START condition. If the AA flag is set, this I2C device will acknowledge the
master after receiving its own address and become an addressed slave. Otherwise, the ad-
dressing from the master will be ignored.
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Bit
Name
GC
Description
0
General Call Bit
In Master mode:
This bit has no effect.
In Slave mode:
0 = General Call is always ignored.
1 = General Call is recognized if AA flag is 1; otherwise, it is ignored if AA is 0.
I2CLK – I2C Clock
7
6
5
4
3
2
1
0
I2CLK[7:0]
R/W
Address: BEH
Reset value: 0000 1110B
Bit
Name
Description
I2C Clock Setting
7:0
I2CLK[7:0]
In Master mode:
This register determines the clock rate of I2C bus when the device is in Master mode. The
clock rate follows the formula below.
FPHERI
F
I2C
=
1+I2CLK
The default value will make the clock rate of I2C bus 400kbps if the clock system 24 MHz
with DIVM 1/4 mode is used.
Note that the I2CLK value of 00H and 01H are not valid. This is an implement limi-
tation.
In Slave mode:
This byte has no effect. In slave mode, the I2C device will automatically synchronize
with any given clock rate up to 400kps.
16.4 Operation Modes
In I2C protocol definition, there are four operating modes including master transmitter, master receiver, slave receive, and
slave transmitter. There is also a special mode called General Call. Its operation is similar to master transmitter mode.
16.4.1
Master Transmitter Mode
In Master Transmitter mode, several bytes of data are transmitted to a slave receiver. The master should prepare by setting
desired clock rate in I2CLK and enabling I2C bus by writing I2CEN (I2CON.6) as logic 1. The master transmitter mode
may now be entered by setting STA (I2CON.5) bit as 1. The hardware will test the bus and generate a START condition
as soon as the bus becomes free. After a START condition is successfully produced, the SI flag (I2CON.3) will be set and
the status code in I2STA show 08H. The progress is continued by loading I2DAT with the target slave address and the
data direction bit “write” (SLA+W). The SI bit should then be cleared to commence SLA+W transaction.
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After the SLA+W byte has been transmitted and an acknowledge (ACK) has been returned by the addressed slave device,
the SI flag is set again and I2STA is read as 18H. The appropriate action to be taken follows the user defined communica-
tion protocol by sending data continuously. After all data is transmitted, the master can send a STOP condition by setting
STO (I2CON.4) and then clearing SI to terminate the transmission. A repeated START condition can be also generated
without sending STOP condition to immediately initial another transmission.
(STA,STO,SI,AA) = (1,0,0,X)
A START will be transmitted
08H
A START has been transmitted
(STA,STO,SI,AA) = (X,0,0,X)
I2DAT = SLA+W
(STA,STO,SI,AA) = (X,0,0,1)
I2DAT = SLA+W
SLA+W will be transmitted
SLA+W will be transmitted
MT
68H or 78H
18H
Arbitration lost and addressed
as slave receiver
SLA+W has been transmitted
ACK has been received
OR
ACK has been transmitted
OR
20H
B0H
SLA+W has been transmitted
NACK has been received
Arbitration lost and addressed
as slave transmitter
ACK has been transmitted
to corresponding
slave mode
(STA,STO,SI,AA)=(0,0,0,X)
I2DAT = Data Byte
Data byte will be transmitted
(STA,STO,SI,AA)=(1,0,0,X)
A repeated START will be
transmitted
(STA,STO,SI,AA)=(0,1,0,X)
A STOP will be transmitted
(STA,STO,SI,AA)=(1,1,0,X)
A STOP followed by a
START will be transmitted
A STOP has been
transmitted
A STOP has been
transmitted
28H
10H
Data byte has been transmitted
A repeated START has
been transmitted
ACK has been received
or
30H
Data byte has been transmitted
NACK has been received
38H
Arbitration lost in
SLA+W or Data byte
(STA,STO,SI,AA) =(0,0,0,X)
I2DAT = SLA+R
SLA+R will be transmitted
(STA,STO,SI,AA)=(0,0,0,X)
Not addressed slave
will be entered
(STA,STO,SI,AA)=(1,0,0,X)
A START will be transmitted
when the bus becomes free
MR
to master receiver
Figure 16–7 Flow and Status of Master Transmitter Mode
16.4.2
Master Receiver Mode
In the master receiver mode, several bytes of data are received from a slave transmitter. The transaction is initialized just
as the master transmitter mode. Following the START condition, I2DAT should be loaded with the target slave address
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and the data direction bit “read” (SLA+R). After the SLA+R byte is transmitted and an acknowledge bit has been re-
turned, the SI flag is set again and I2STA is read as 40H. SI flag then should be cleared to receive data from the slave
transmitter. If AA flag (I2CON.3) is set, the master receiver will acknowledge the slave transmitter. If AA is cleared, the
master receiver will not acknowledge the slave and release the slave transmitter as a not addressed slave. After that, the
master can generate a STOP condition or a repeated START condition to terminate the transmission or initial another one.
(STA,STO,SI,AA) = (1,0,0,X)
A START will be transmitted
08H
A START has been transmitted
(STA,STO,SI,AA) = (X,0,0,1)
I2DAT = SLA+R
(STA,STO,SI,AA) = (X,0,0,X)
I2DAT = SLA+R
SLA+R will be transmitted
SLA+R will be transmitted
MR
68H or 78H
40H
Arbitration lost and addressed
as slave receiver
SLA+R has been transmitted
ACK has been received
OR
ACK has been transmitted
OR
48H
B0H
SLA+R has been transmitted
NACK has been received
Arbitration lost and addressed
as slave transmitter
ACK has been transmitted
to corresponding
slave mode
(STA,STO,SI,AA)=(0,0,0,0)
Data byte will be received
NACK will be transmitted
(STA,STO,SI,AA)=(0,0,0,1)
Data byte will be received
ACK will be transmitted
(STA,STO,SI,AA)=(1,0,0,X)
A repeated START will be
transmitted
(STA,STO,SI,AA)=(0,1,0,X)
A STOP will be transmitted
(STA,STO,SI,AA)=(1,1,0,X)
A STOP followed by a
START will be transmitted
A STOP has been
transmitted
A STOP has been
transmitted
58H
50H
10H
Data byte has been received
NACK has been transmitted
I2DAT = Data Byte
Data byte has been received
ACK has been transmitted
I2DAT = Data Byte
A repeated START has
been transmitted
38H
Arbitration lost in
SLA+W or NACK bit
(STA,STO,SI,AA) =(0,0,0,X)
I2DAT = SLA+W
SLA+W will be transmitted
(STA,STO,SI,AA)=(0,0,0,X)
Not addressed slave
will be entered
(STA,STO,SI,AA)=(1,0,0,X)
A START will be transmitted
when the bus becomes free
MT
to master transmitter
Figure 16–8 Flow and Status of Master Receiver Mode
16.4.3
Slave Receiver Mode
In Slave Receiver mode, several bytes of data are received form a master transmitter. Before a transmission is com-
menced, I2ADDR should be loaded with the address to which the device will respond when addressed by a master. I2CLK
does not affect in slave mode. The AA bit should be set to enable acknowledging its own slave address or General Call.
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After the initialization above, the I2C wait until it is addressed by its own address with the data direction bit “write”
(SLA+W) or by General Call addressing. The slave receiver mode may also be entered if arbitration is lost.
After the slave is addressed by SLA+W, it should clear its SI flag to receive the data from the master transmitter. If the
AA bit is 0 during a transaction, the slave will return a non-acknowledge after the next received data byte. The slave will
be become not addressed and isolate with the master. It cannot receive any byte of data with I2DAT remaining the previ-
ous byte of data which is just received.
(STA,STO,SI,AA) = (0,0,0,1)
If own SLA+W is received,
ACK will be transmitted
60H
Own SLA+W has been received
ACK has been transmitted
I2DAT = own SLA+W
OR
68H
Arbitration lost and own SLA+W
has been received
ACK has been transmitted
I2DAT = own SLA+W
(STA,STO,SI,AA)=(X,0,0,1)
Data byte will be received
ACK will be transmitted
(STA,STO,SI,AA)=(X,0,0,0)
Data byte will be received
NACK will be transmitted
80H
88H
Data byte has been received
ACK has been transmitted
I2DAT = Data Byte
Data byte has been received
NACK has been transmitted
I2DAT = Data Byte
A0H
A STOP or repeated
START has been received
(STA,STO,SI,AA)=(0,0,0,1)
Not addressed slave will be
entered; own SLA will be
recognized; General Call will
be recognized if GC = 1
(STA,STO,SI,AA)=(1,0,0,0)
Not addressed slave will be
entered; no recognition of own
SLA or General Call;
A START will be transmitted
when the bus becomes free
(STA,STO,SI,AA)=(1,0,0,1)
Not addressed slave will be
entered; own SLA will be
recognized; General Call will
be recognized if GC = 1;
(STA,STO,SI,AA)=(0,0,0,0)
Not addressed slave
will be entered; no recognition
of own SLA or General Call
A START will be transmitted
when the bus becomes free
Figure 16–9 Flow and Status of Slave Receiver Mode
16.4.4
Slave Transmitter Mode
In Slave Transmitter mode, several bytes of data are transmitted to a master receiver. After I2ADDR and I2CON values
are given, the I2C wait until it is addressed by its own address with the data direction bit “read” (SLA+R). The slave
transmitter mode may also be entered if arbitration is lost.
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After the slave is addressed by SLA+W, it should clear its SI flag to transmit the data to the master transmitter. Normally
the master receiver will return an acknowledge after every byte of data is transmitted by the slave. If the acknowledge is
not received, it will transmit all “1” data if it continues the transaction. It becomes a not addressed slave. If the AA flag is
cleared during a transaction, the slave transmit the last byte of data. The next transmitting data will be all “1” and the slave
becomes not addressed.
(STA,STO,SI,AA) = (0,0,0,1)
If own SLA+R is received,
ACK will be transmitted
A8H
Own SLA+R has been received
ACK has been transmitted
I2DAT = own SLA+R
OR
B0H
Arbitration lost and own SLA+R
has been received
ACK has been transmitted
I2DAT = own SLA+R
(STA,STO,SI,AA)=(X,0,0,1)
I2DAT = Data Byte
Data byte will be transmitted
ACK will be received
(STA,STO,SI,AA)=(X,0,0,X)
I2DAT = Data Byte
Data byte will be transmitted
NACK will be received
(STA,STO,SI,AA)=(X,0,0,0)
I2DAT = Last Data Byte
Data byte will be transmitted
ACK will be received
B8H
C0H
C8H
Data byte has been transmitted
ACK has been received
Data byte has been transmitted
NACK has been received
Last Data byte has been transmitted
ACK has been received
A0H
A STOP or repeated
START has been received
(STA,STO,SI,AA)=(0,0,0,1)
(STA,STO,SI,AA)=(1,0,0,0)
(STA,STO,SI,AA)=(1,0,0,1)
Not addressed slave will be
entered; own SLA will be
recognized; General Call will
be recognized if GC = 1;
(STA,STO,SI,AA)=(0,0,0,0)
Not addressed slave
will be entered; no recognition
of own SLA or General Call
Not addressed slave will be
entered; own SLA will be
recognized; General Call will
be recognized if GC = 1
Not addressed slave will be
entered; no recognition of own
SLA or General Call;
A START will be transmitted
when the bus becomes free
A START will be transmitted
when the bus becomes free
Figure 16–10 Flow and Status of Slave Transmitter Mode
16.4.5
General Call
The General Call is a special condition of slave receiver mode by sending all “0” data in slave address with data direction
bit. The slave addressed by a General Call has different status codes in I2STA with normal slave receiver mode. The Gen-
eral Call may be also produced if arbitration is lost.
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(STA,STO,SI,AA) = (0,0,0,1)
If General Call is received,
ACK will be transmitted
70H
General Call has been received
ACK has been transmitted
I2DAT = 00H
OR
78H
Arbitration lost and General Call
has been received
ACK has been transmitted
I2DAT = 00H
(STA,STO,SI,AA)=(X,0,0,1)
(STA,STO,SI,AA)=(X,0,0,0)
Data byte will be received
ACK will be transmitted
Data byte will be received
NACK will be transmitted
90H
98H
Data byte has been received
ACK has been transmitted
I2DAT = Data Byte
Data byte has been received
NACK has been transmitted
I2DAT = Data Byte
A0H
A STOP or repeated
START has been received
(STA,STO,SI,AA)=(0,0,0,1)
Not addressed slave will be
entered; own SLA will be
recognized; General Call will
be recognized if GC = 1
(STA,STO,SI,AA)=(1,0,0,0)
Not addressed slave will be
entered; no recognition of own
SLA or General Call;
A START will be transmitted
when the bus becomes free
(STA,STO,SI,AA)=(1,0,0,1)
Not addressed slave will be
entered; own SLA will be
recognized; General Call will
be recognized if GC = 1;
(STA,STO,SI,AA)=(0,0,0,0)
Not addressed slave
will be entered; no recognition
of own SLA or General Call
A START will be transmitted
when the bus becomes free
Figure 16–11. Flow and Status of General Call Mode
16.4.6
Miscellaneous States
There are two I2STA status codes that do not correspond to the 24 defined states, which are mentioned in previous sec-
tions, which are F8H and 00H states.
The first status code F8H indicates that no relevant information is available during each transaction. Meanwhile, the SI
flag is 0 and no I2C interrupt is required.
The other status code 00H means a bus error has occurred during a transaction. A bus error is caused by a START or
STOP condition appearing temporarily at an illegal position such as the second through eighth bits in an address byte or a
data byte including the acknowledge bit. When a bus error occurs, the SI flag is set immediately. When a bus error is de-
tected on the I2C bus, the operating device immediately switches to the not addressed salve mode, release SDA and SCL
lines, sets the SI flag, and loads I2STA 00H. To recover from a bus error, the STO bit should be set as logic 1 and SI
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should be cleared. After that, STO is cleared by hardware and release the I2C bus without issuing a real STOP condition
waveform.
There is a special case if a START or a repeated START condition is not successfully generated for I2C bus is obstructed
by a low level on SDA line e.g. a slave device out of bit synchronization, the problem can be solved by transmitting addi-
tional clock pulses on the SCL line. The I2C hardware transmits additional clock pulses when the STA bit is set, but no
START condition can be generated because the SDA line is pulled low. When the SDA line is eventually released, a nor-
mal START condition is transmitted, state 08H is entered, and the serial transaction continues. If a repeated START con-
dition is transmitted while SDA is obstructed low, the I2C hardware also performs the same action as above. In this case,
state 08H is entered instead of 10H after a successful START condition is transmitted. Note that the software is not in-
volved in solving these bus problems.
16.5 Typical Structure of I2C Interrupt Service Routine
The following software example in C language for KEIL C51 compiler shows the typical structure of the I2C interrupt
service routine including the 26 state service routines and may be used as a base for user applications. User can follow or
modify it for their own application. If one or more of the five modes are not used, the associated state service routines may
be removed, but care should be taken that a deleted routine can never be invoked.
void I2C_ISR (void) interrupt 6
{
switch (I2STA)
{
//===============================================
//Bus Error, always put in ISR for noise handling
//===============================================
case 0x00:
STO = 1;
/*00H, bus error occurs*/
//recover from bus error
break;
//===========
//Master Mode
//===========
case 0x08:
/*08H, a START transmitted*/
//STA bit should be cleared by software
//LOAD SLA+W/R
STA = 0;
I2DAT = SLA_ADDR1;
break;
case 0x10:
/*10H, a repeated START transmitted*/
STA = 0;
I2DAT = SLA_ADDR2;
break;
//=======================
//Master Transmitter Mode
//=======================
case 0x18:
/*18H, SLA+W transmitted, ACK received*/
//LOAD DATA
I2DAT = NEXT_SEND_DATA1;
break;
case 0x20:
/*20H, SLA+W transmitted, NACK received*/
//transmit STOP
STO = 1;
AA = 1;
//ready for ACK own SLA+W/R
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break;
case 0x28:
/*28H, DATA transmitted, ACK received*/
//if continuing to send DATA
if (Conti_TX_Data)
I2DAT = NEXT_SEND_DATA2;
else
//if no DATA to be sent
{
STO = 1;
AA = 1;
}
break;
case 0x30:
/*30H, DATA transmitted, NACK received*/
STO = 1;
AA = 1;
break;
//===========
//Master Mode
//===========
case 0x38:
/*38H, arbitration lost*/
STA = 1;
//retry to transmit START if bus free
break;
//====================
//Master Receiver Mode
//====================
case 0x40:
/*40H, SLA+R transmitted, ACK received*/
//ACK next received DATA
AA = 1;
break;
case 0x48:
/*48H, SLA+R transmitted, NACK received*/
STO = 1;
AA = 1;
break;
case 0x50:
/*50H, DATA received, ACK transmitted*/
//store received DATA
DATA_RECEIVED1 = I2DAT;
if (To_RX_Last_Data1)
AA = 0;
else
//if last DATA will be received
//not ACK next received DATA
//if continuing receiving DATA
AA = 1;
break;
case 0x58:
/*58H, DATA received, NACK transmitted*/
DATA_RECEIVED_LAST1 = I2DAT;
STO = 1;
AA = 1;
break;
//====================================
//Slave Receiver and General Call Mode
//====================================
case 0x60:
AA = 1;
break;
case 0x68:
/*60H, own SLA+W received, ACK returned*/
/*68H, arbitration lost in SLA+W/R
own SLA+W received, ACK returned */
//not ACK next received DATA after
//arbitration lost
AA = 0;
STA = 1;
break;
//retry to transmit START if bus free
case 0x70:
//70H, General Call received, ACK returned
AA = 1;
break;
case 0x78:
/*78H, arbitration lost in SLA+W/R
General Call received, ACK returned*/
AA = 0;
STA = 1;
break;
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case 0x80:
DATA_RECEIVED2 = I2DAT;
/*80H, previous own SLA+W, DATA received,
ACK returned*/
if (To_RX_Last_Data2)
AA = 0;
else
AA = 1;
break;
case 0x88:
/*88H, previous own SLA+W, DATA received,
NACK returned, not addressed SLAVE mode
entered*/
DATA_RECEIVED_LAST2 = I2DAT;
AA = 1;
//wait for ACK next Master addressing
break;
case 0x90:
/*90H, previous General Call, DATA received,
ACK returned*/
DATA_RECEIVED3 = I2DAT;
if (To_RX_Last_Data3)
AA = 0;
else
AA = 1;
break;
case 0x98:
/*98H, previous General Call, DATA received,
NACK returned, not addressed SLAVE mode
entered*/
DATA_RECEIVED_LAST3 = I2DAT;
AA = 1;
break;
//==========
//Slave Mode
//==========
case 0xA0:
/*A0H, STOP or repeated START received while
still addressed SLAVE mode*/
AA = 1;
break;
//======================
//Slave Transmitter Mode
//======================
case 0xA8:
/*A8H, own SLA+R received, ACK returned*/
I2DAT = NEXT_SEND_DATA3;
AA = 1;
//when AA is “1”, not last data to be
//transmitted
break;
case 0xB0:
/*B0H, arbitration lost in SLA+W/R
own SLA+R received, ACK returned */
I2DAT = DUMMY_DATA;
AA = 0;
//when AA is “0”, last data to be
//transmitted
STA = 1;
break;
//retry to transmit START if bus free
case 0xB8:
/*B8H, previous own SLA+R, DATA transmitted,
ACK received*/
I2DAT = NEXT_SEND_DATA4;
if (To_TX_Last_Data)
AA = 0;
//if last DATA will be transmitted
else
AA = 1;
break;
case 0xC0:
/*C0H, previous own SLA+R, DATA transmitted,
NACK received, not addressed SLAVE mode
entered*/
AA = 1;
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break;
case 0xC8:
/*C8H, previous own SLA+R, last DATA trans-
mitted, ACK received, not addressed SLAVE
mode entered*/
AA = 1;
break;
}//end of switch (I2STA)
SI = 0;
while(STO);
//SI should be the last step of I2C ISR
//wait for STOP transmitted or bus error
//free, STO is cleared by hardware
}//end of I2C_ISR
16.6 I2C Time-out
There is 14-bit time-out counter which can be used to deal with the I2C bus hang-up. If the time-out counter is enabled,
the counter starts up counting until it overflows. Meanwhile TIF will be set by hardware and requests I2C interrupt. When
time-out counter is enabled, setting flag SI to high will reset counter and restart counting up after SI is cleared. If the I2C
bus hangs up, it causes the SI flag not set for a period. The 14-bit time-out counter will overflow and require the interrupt
service.
FSYS
0
1
14-bit I2C Time-out Counter
I2TF
1/4
Clear Counter
DIV
I2CEN
I2TMREN
SI
Figure 16–12 I2C Time-out Count
I2TOC – I2C Time-out Counter
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
1
DIV
R/W
0
I2TOCEN
R/W
I2TOF
R/W
Address: BFH
Reset value: 0000 0000B
Bit
7:3
2
Name
Description
-
Reserved
I2C Time-out Counter Enable
I2TOCEN
0 = The I2C time-out counter is disabled.
1 = The I2C time-out counter is enabled.
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Bit
Name
DIV
Description
I2C time-out Counter Clock Divider
1
0
0 = The divider of I2C time-out counter is 1/1 of FSYS
1 = The divider of I2C time-out counter is 1/4 of FSYS
.
.
I2C Time-out Counter Overflow Flag
I2TOF
I2TOF flag is set by hardware if 14-bit I2C time-out counter overflows. I2TOF flag is
cleared by software.
16.7 I2C Interrupts
There are two I2C flags, SI and I2TOF. Both of them can generate an I2C event interrupt requests. If I2C interrupt mask is
enabled via setting EI2C (EIE.0) and EA is 1, CPU will executes the I2C interrupt service routine once any of the two
flags is set. The user needs to check flags to determine what event caused the interrupt. Both of I2C flags are cleared by
software.
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17 Pulse Width Modulated (PWM)
17.1 Features
PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can used on motor driving,
fan control, backlight brightness tuning, LED light dimming, or simulating as a simple digital to analog converter output
through a low pass filter circuit. The N79E845/844/8432 provides four channels, maximum 10-bit PWM output.
17.2 Functional Description
The N79E845/844/8432 contains four Pulse Width Modulated (PWM) channels which generate pulses of programmable
length and interval. The output for PWM0 is on P0.1, PWM1 on P1.6, PWM2 on P1.7 and PWM3 on P0.0. After chip
reset the internal output of the each PWM channel is a “1”. In this case before the pin will reflect the state of the internal
PWM output a “1” should be written to each port bit that serves as a PWM output. A block diagram is shown in Figure
17-1. The interval between successive outputs is controlled by 10–bit down counter which uses configurable internal
clock pre-scalar as its input. The PWM counter clock has the frequency as the clock source FPWM = FSYS/Pre-scalar. When
the counter reaches underflow it is reloaded with a user selectable value. This mechanism allows the user to set the PWM
frequency at any integer sub–multiple of the microcontroller clock frequency. The repetition frequency of the PWM is
given by:
FPWM
PWMn
PWM frequency =
, PWM active level duty =
.
1+PWMP
1+PWMP
where PWMP is contained in PWMPH and PWMPL as described in the following.
PWMPL – PWM Counter Low Bits Register
7
6
5
4
3
2
1
0
PWMP.7
PWMP.6
PWMP.5
PWMP.4
PWMP.3
PWMP.2
PWMP.1
PWMP.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: D9H
Reset value: 0000 0000B
Bit
Name
Description
7:0
PWMPL
PWM Counter Bits Register bit[7:0].
PWMPH – PWM Counter High Bits Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWMP.9
PWMP.8
-
-
-
-
-
-
R/W
R/W
Address: D1H
Reset value: 0000 0000B
Bit
Name
Description
7:2
-
Reserved
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Bit
Name
Description
1:0
PWMPH
PWM Counter Bits Register bit[9:8].
The user should follow the initialization steps below to start generating the PWM signal output. In the first step by setting
CLRPWM (PWMCON0.4), it ensures the 10-bit down counter a determined value. After setting all period and duty regis-
ters, PWMRUN (PWMCON0.7) can be set as logic 1 to trigger the 10-bit down counter running. In the beginning the
PWM output remains high until the counter value is less than the value in duty control registers of PWMnH and PWMnL.
At this point the PWM output goes low until the next underflow. When the 10-bit down counter underflows, PWMP buff-
er register will be reloaded in 10-bit down counter. It continues PWM signal output by repeating this routine.
The hardware for all period and duty control registers is double buffered designed. Therefore the PWMP and PWMn reg-
isters can be written to at any time, but the period and duty cycle of PWM will not updated immediately until the Load
(PWMCON0.6) is set and previous period is complete. This allows updating the PWM period and duty glitch less opera-
tion.
PWM0L – PWM 0 Low Register
7
6
5
4
3
2
1
0
PWM0.7
PWM0.6
PWM0.5
PWM0.4
PWM0.3
PWM0.2
PWM0.1
PWM0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: DAH
Reset value: 0000 0000B
Bit
Name
Description
7:0
PWM0L
PWM 0 Low Bits Register bit[7:0].
PWM0H – PWM 0 High Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM0.9
PWM0.8
-
-
-
-
-
-
R/W
R/W
Address: D2H
Reset value: 0000 0000B
Bit
7:2
1:0
Name
-
Description
Reserved
PWM0H
PWM 0 High Bits Register bit[9:8].
PWM1L – PWM 1 Low Register
7
6
5
4
3
PWM1.3
2
1
0
PWM1.7
PWM1.6
PWM1.5
PWM1.4
PWM1.2
PWM1.1
PWM1.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: DBH
Reset value: 0000 0000B
Bit
Name
Description
7:0
PWM1L
PWM 0 Low Bits Register bit[7:0].
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PWM1H – PWM 1 High Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM1.9
PWM1.8
-
-
-
-
-
-
R/W
R/W
Address: D3H
Reset value: 0000 0000B
Bit
7:2
1:0
Name
-
Description
Reserved
PWM1H
PWM 1 High Bits Register bit[9:8].
PWM2L – PWM 2 Low Register
7
6
5
4
3
PWM2.3
2
1
0
PWM2.7
PWM2.6
PWM2.5
PWM2.4
PWM2.2
PWM2.1
PWM2.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: DDH
Reset value: 0000 0000B
Bit
Name
Description
7:0
PWM2L
PWM 2 Low Bits Register bit[7:0].
PWM2H – PWM 2 High Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM2.9
PWM2.8
-
-
-
-
-
-
R/W
R/W
Address: D5H
Reset value: 0000 0000B
Bit
7:2
1:0
Name
-
Description
Reserved
PWM2H
PWM 2 High Bits Register bit[9:8].
PWM3L – PWM 3 Low Register
7
6
5
4
3
2
1
0
PWM3.7
PWM3.6
PWM3.5
PWM3.4
PWM3.3
PWM3.2
PWM3.1
PWM3.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: DEH
Reset value: 0000 0000B
Bit
Name
Description
7:0
PWM3L
PWM 0 Low Bits Register bit[7:0].
PWM3H – PWM 3 High Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM3.9
PWM3.8
-
-
-
-
-
-
R/W
R/W
Address: D6H
Reset value: 0000 0000B
Bit
Name
Description
7:2
-
Reserved
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Bit
Name
Description
1:0
PWM3H
PWM 3 High Bits Register bit[9:8].
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Figure 17-1 PWM Block Diagram
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A compare value greater than the counter reloaded value is in the PWM output being permanently low. In addition there
are two special cases. A compare value of all zeroes, 000H, causes the output to remain permanently high. A compare
value of all ones, 3FFH, results in the PWM output remaining permanently low. Again the compare value is loaded into a
Compare register. The transfer from this holding register to the actual Compare register is under program control. The
register assignments are shown below where the number immediately following “PWMn” identifies the PWM output.
Therefore, the PWM0 controls the width of PWM0, PWM1 the width of PWM1 etc.
The overall functioning of the PWM module is controlled by the contents of the PWMCON0 register. The operation of
most of the control bits is straightforward. For example, there is an invert bit for each output which causes results in the
output to have the opposite value compared to its non-inverted output. The transfer of the data from the Counter and
Compare registers to the control registers is controlled by the PWMCON0.6 (LOAD) while PWMCON0.7 (PWMRUN)
allows the PWM to be either in the run or idle state. The user can monitor when underflow causes the transfer to occur by
monitoring the Transfer bit PWCON1.6 (Load) or PWMCON0.5 (CF flag). Note that CF does not assert interrupt. When
the transfer takes place the PWM logic automatically resets those bits by the next clock cycle.
A loading of new period and duty by setting Load should be ensured complete by monitoring it and waiting for a hardware
automatic clearing Load bit. Any updating of PWM control registers during Load bit as logic 1 will cause unpredictable
output.
PWMCON0 – PWM Control Register 0
7
6
5
4
3
2
1
0
PWMRUN
Load
CF
CLRPWM
PWM3I
PWM2I
PWM1I
PWM0I
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: DCH
Reset value: 0000 0000B
Bit
Name
Description
7
PWMRUN 0 = PWM is not running.
1 = PWM counter is running.
6
Load
0 = The registers value of PWMP and Comparators are never loaded to counter and Com-
parator registers.
1 = The PWMP register will be LOAD value to counter register after counter underflow,
and hardware will clear by next clock cycle.
5
CF
10-bit counter overflow flag:
0 = 10-bit counter down count is not underflow.
1 = 10-bit counter down count is underflow.
4
3
CLRPWM 1 = Clear 10-bit PWM counter to 000H.
PWM3I 0 = PWM3 output is non-inverted.
1 = PWM3 output is inverted.
2
PWM2I 0 = PWM2 output is non-inverted.
1 = PWM2 output is inverted.
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Bit
Name
Description
1
0
PWM1I 0 = PWM1 output is non-inverted.
1 = PWM1 output is inverted.
PWM0I 0 = PWM0 output is non-inverted.
1 = PWM0 output is inverted.
The fact that the transfer from the Counter and PWMn register to the working registers(10-bit Counter and Compare regis-
ter) only occurs when there is an underflow in the counter results in the need for the user’s program to observe the follow-
ing precautions. If PWMCON0 is written with Load set without Run being enabled the transfer will never take place. Thus
if a subsequent write sets Run without Load the compare and counter values will not be those expected. If Load and Run
are set, and prior to underflow there is a subsequent LOAD of PWMCON0 which sets Run but not Load, the LOAD will
never take place. Again the compare and counter values that existed prior to the update attempt will be used.
As outlined above the Load bit can be polled to determine when the LOAD occurs. Unless there is a compelling reason to
do otherwise, it is recommended that both PWMRUN (PWMCON0.7), and Load (PWMCON0.6) be set when
PWMCON0 is written.
When the PWMRUN bit, PWMCON0.7 is cleared the PWM outputs take on the state they had just prior to the bit being
cleared. In general, this state is not known. To place the outputs in a known state when PWMRUN is cleared the Compare
registers can be written to either the “always 1” or “always 0” so the output will have the output desired when the counter
is halted. After this PWMCON0 should be written with the Load and Run bits are enabled. After this is done PWMCON0
to polled to find that the Load or CF flag has taken place. Once the LOAD has occurred the Run bit in PWMCON0 can be
cleared. The outputs will retain the state they had just prior to the Run being cleared. If the Brake pin (see discussion be-
low in section concerning the operation of PWMCON1) is not used to control the brake function, the “Brake when not
running” function can be used to cause the outputs to have a given state when the PWM is halted. This approach should be
used only in time critical situations when there is not sufficient time to use the approach outlined above since going from
the Brake state to run without causing an undefined state on the outputs is not straightforward. A discussion on this topic
is included in the PWMCON1 section.
PWMCON1 – PWM Control Register 1
7
6
5
4
3
2
1
0
BKCH
BKPS
BPEN
BKEN
PWM3B
PWM2B
PWM1B
PWM0B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: DFH
Reset value: 0000 0000B
Bit
7
Name
BKCH
BKPS
Description
See the following table (when BKEN is set).
0 = Brake is asserted if P0.2 is low.
6
1 = Brake is asserted if P0.2 is high
5
BPEN
See the following table (when BKEN is set).
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Bit
Name
BKEN
Description
4
3
2
1
0
0 = Brake is never asserted.
1 = Brake is enabled, and see the following table.
PWM3B 0 = PWM3 output is low, when Brake is asserted.
1 = PWM3 output is high, when Brake is asserted.
PWM2B 0 = PWM2 output is low, when Brake is asserted.
1 = PWM2 output is high, when Brake is asserted.
PWM1B 0 = PWM1 output is low, when Brake is asserted.
1 = PWM1 output is high, when Brake is asserted.
PWM0B 0 = PWM0 output is low, when Brake is asserted.
1 = PWM0 output is high, when Brake is asserted.
Brake Condition Table
BPEN BKCH
BREAK CONDITION
0
0
1
1
0
1
0
1
Brake on (software brake and keeping brake)
On, when PWM is not running (PWMRUN=0), the PWM output condition is follow PWMNB setting.
Off, when PWM is running (PWMRUN=1).
Brake on, when break pin asserted, no PWM output, the bit of PWMRUN will be cleared and BKF flag
will be set. The PWM output condition is follow PWMNB setting.
No active.
PWMCON2 – PWM Control Register 2
7
-
6
-
5
-
4
-
3
FP1
2
FP0
1
-
0
BKF
-
-
-
-
R/W
R/W
-
R/W
Address: D7H
Reset value: 0000 0000B
Bit
7:4
3:2
Name
Description
-
Reserved
FP[1:0] Select PWM frequency pre-scalar select bits. The clock source of pre-scalar, Fpwm is in
phase with FSYS if PWMRUN=1.
FP[1:0]
00
Fpwm
FSYS (Default)
FSYS /2
01
10
FSYS /4
11
FSYS /16
1
-
Reserved
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Bit
Name
BKF
Description
0
External Brake Pin Flag
0 = PWM is not brake.
1 = PWM is brake by external brake pin. It will be cleared by software.
The Brake function, which is controlled by the contents of the PWMCON1 register, is somewhat unique. In general when
Brake is asserted the four PWM outputs are forced to a user selected state, namely the state selected by PWMCON1 bits 0
to 3. As shown in the description of the operation of the PWMCON1 register if PWMCON1.4 is a “1” brake is asserted
under the control PWMCON1.7, BKCH, and PWMCON1.5, BPEN. As shown if both are a “0” Brake is asserted. If
PWMCON1.7 is a “1” brake is asserted when the run bit, PWMCON0.7, is a “0.” If PWMCON1.6 is a “1” brake is as-
serted when the Brake Pin, P0.2, has the same polarity as PWMCON1.6. When brake is asserted in response to this pin the
RUN bit, PWMCON0.7, is automatically cleared and BKF(PWMCON2.0) flag will be set. The combination of both
PWMCON1.7 and PWMCON1.5 being a “1” is not allowed.
Since the Brake Pin being asserted will automatically clear the Run bit of PWMCON0.7and BKF(PWMCON2.0) flag will
be set, the user program can poll this bit or enable PWM’s brake interrupt to determine when the Brake Pin causes a brake
to occur. The other method for detecting a brake caused by the Brake Pin would be to tie the Brake Pin to one of the ex-
ternal interrupt pins. This latter approach is needed if the Brake signal can be of insufficient length to ensure that it can be
captured by a polling routine. When, after being asserted, the condition causing the brake is removed, the PWM outputs
go to whatever state that had immediately prior to the brake. This means that to go from brake being asserted to having the
PWM run without going through an indeterminate state care should be taken. If the Brake Pin causes brake to be asserted
the following prototype code will allow the PWM to go from brake to run smoothly by software polling BKF flag or ena-
ble PWM’s interrupt.
Note that if a narrow pulse on the Brake Pin causes brake to be asserted, it may not be possible to go through the above
code before the end of the pulse. In this case, in addition to the code shown, an external latch on the Brake Pin may be
required to ensure that there is a smooth transition in going from brake to run.
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PWM demo code is as follows:
ORG
0H
SJMP
ORG
START
100H
START:
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
PWMPH,#0
PWMPL,#0FFH
PWM0H,#0
PWM0L,#080H
PWM1H,#0
PWM1L,#0A0H
PWM2H,#0
PWM2L,#0C0H
PWM3H,#0
PWM3L,#0F0H
;PWM Frequency = Fsys/(1+PWMP)
;If Fsys=20MHz, PWM Frequency=78.1kHz
;PWM0(P0.1) duty = PWM0/(1+PWMP)
;PWM1(P1.6) duty = PWM1/(1+PWMP)
;PWM2(P1.7) duty = PWM2/(1+PWMP)
;PWM3(P0.0) duty = PWM3/(1+PWMP)
;Start PWM
ORL
MOV
PWMCON0,#0D0H
PWMCON1,#30H
;PWM will be stopped when P0.2 is low level.
;PWM output condition is follow PWMNB setting.
;In this case, PWM0B=PWM1B=PWM2B=PWM3B=0
END
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18 Timed Access Protection(TA)
The N79E845/844/8432 has several features like the Watchdog Timer, the ISP function, Boot select control, etc. are cru-
cial to proper operation of the system. If leaving these control registers unprotected, errant code may write undetermined
value into them, it results in incorrect operation and loss of control. To prevent this risk, the N79E845/844/8432 has a
protection scheme which limits the write access to critical SFRs. This protection scheme is done using a timed access. The
following registers are related to TA process.
TA – Timed Access
7
6
5
4
3
2
1
0
TA[7:0]
W
Address: C7H
Reset value: 1111 1111B
Bit
Name
TA[7:0]
Description
Timed Access
7:0
The timed access register controls the access to protected SFRs. To access pro-
tected bits, the user should first write AAH to the TA and immediately followed by
a write of 55H to TA. After the two steps, a writing permission window is opened
for three machine-cycles during which the user may write to protected SFRs.
In timed access method, the bits, which are protected, have a timed write enable window. A write is successful only if this
window is active, otherwise the write will be discarded. When the software writes AAH to TA, a counter is started. This
counter waits for three machine-cycles looking for a write of 55H to TA. If the second write of 55H occurs within three
machine-cycles of the first write of AAH, then the timed access window is opened. It remains open for three machine-
cycles during which the user may write to the protected bits. After three machine-cycles, this window automatically clos-
es. Once the window closes, the procedure should be repeated to access the other protected bits. Not that the TA protected
SFRs are required timed access for writing. However, the reading is not protected. The user may read TA protected SFR
without giving AAH and 55H to TA. The suggestion code for opening the timed access window is shown below.
(CLR
MOV
MOV
EA)
TA, #0AAH
TA, #55H
;if any interrupt is enabled, disable temporarily
(Instruction that writes a TA protected register)
(SETB EA) ;resume interrupts enabled
The writes of AAH and 55H should occur within 3 machine-cycles of each other. Interrupts should be disabled during this
procedure to avoid delay between these two writes. If the is no interrupt enabled, the CLR EA and SETB EA instructions
can be left out. Once the timed access window closes, the procedure should be repeated to access the other protected bits.
Examples of timed assessing are shown to illustrate correct or incorrect writing processes.
Example 1,
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(CLR
MOV
MOV
ORL
EA)
;if any interrupt is enabled, disable temporarily
;2 machine-cycles.
;2 machine-cycles.
TA,#0AAH
TA,#55H
CHPCON,#data
;2 machine-cycles.
(SETB EA)
;resume interrupts enabled
Example 2,
(CLR
EA)
TA,#0AAH
TA,#55H
;if any interrupt is enabled, disable temporarily
;2 machine-cycles.
;2 machine-cycles.
;1 machine-cycle.
;1 machine-cycle.
MOV
MOV
NOP
NOP
ANL
ISPTRG,#data
;2 machine-cycles.
(SETB EA)
;resume interrupts enabled
Example 3,
(CLR
EA)
TA,#0AAH
;if any interrupt is enabled, disable temporarily
;2 machine-cycles.
;1 machine-cycle.
;2 machine-cycles.
;2 machine-cycles.
MOV
NOP
MOV
MOV
ORL
TA,#55H
WDCON0,#data1
PMCR,#data2
;2 machine-cycles.
(SETB EA)
;resume interrupts enabled
Example 4,
(CLR
EA)
TA,#0AAH
;if any interrupt is enabled, disable temporarily
;2 machine-cycles.
;1 machine-cycle.
;1 machine-cycle.
;2 machine-cycles.
MOV
NOP
NOP
MOV
ANL
TA,#55H
WDCON0,#data
;2 machine-cycles.
(SETB EA)
;resume interrupts enabled
In the first example, the writing to the protected bits is done before the three machine-cycle window closes. In example 2,
however, the writing to ISPTRG does not complete during the window opening, there will be no change of the value of
ISPTRG. In example 3, the WDCON0 is successful written but the PMCR access is out of the three machine-cycle win-
dow. Therefore PMCR value will not change either. In Example 4, the second write 55H to TA completes after three ma-
chine-cycles of the first write TA of AAH, therefore the timed access window in not opened at all, and the write to the
protected bit fails.
In the N79E845/844/8432, the TA protected SFRs include PMCR(A3H), CHPCON (9FH), ISPTRG (A4H), SHBDA
(9CH), WDCON0 (D8H), and WDCON1 (ABH).
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19 Interrupt System
The N79E845/844/8432 has four priority level of interrupts structure with 14 interrupt sources. Each of the interrupt
sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can be globally ena-
bled or disabled.
19.1 Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending on bits IT0 and IT1.
The bits IE0 and IE1 in the TCON register are the flags which are checked to generate the interrupt. In the edge triggered
mode, the INTx inputs are sampled in every machine-cycle. If the sample is high in one cycle and low in the next, then a
high to low transition is detected and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt.
Since the external interrupts are sampled every machine-cycle, they have to be held high or low for at least one complete
machine-cycle. The IEx flag is automatically cleared when the service routine is called. If the level triggered mode is se-
lected, then the requesting source has to hold the pin low till the interrupt is serviced. The IEx flag will not be cleared by
the hardware on entering the service routine. If the interrupt continues to be held low even after the service routine is
completed, then the processor may acknowledge another interrupt request from the same source.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags, which flags are set by the overflow in the Timer 0
and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when the timer interrupt is serviced.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the timeout
count is reached, the Watchdog Timer interrupt flag WDTRF (WDCON0.3) is set. If the interrupt is
enabled by the enable bit EIE.4, then an interrupt will occur.
The Serial block can generate interrupt on reception or transmission. There are two interrupt sources from the Serial
block, which are obtained by the RI and TI bits in the SCON SFR, which bits are not automatically cleared by the hard-
ware, and the user will have to clear these bits using software.
I2C will generate an interrupt due to a new SIO state present in I2STA register, if both EA and ES bits (in IE register) are
both enabled.
SPI asserts interrupt flag, SPIF, upon completion of data transfer with an external device. If SPI interrupt is enabled (ESPI
at EIE.6), a serial peripheral interrupt is generated. SPIF flag is software clear, by writing 0. MODF and SPIOVF will
also generate interrupt if occur. They share the same vector address as SPIF.
The ADC can generate interrupt after finished ADC converter. There is one interrupt source, which is obtained by the
ADCI bit in the ADCCON0 SFR. This bit is not automatically cleared by the hardware, and the user will have to clear this
bit using software.
PWM brake interrupt flag BKF is generated if P0.2 (Brake pin) detects a high (BKPS=1) or low (BKPS=0) at port pin. At
this moment, BKF (PWMCON2.0) is set by hardware and it should be cleared by software. PWM period interrupt flag CF
is set by hardware when its’ 10-bit down counter underflow and is only cleared by software. BKF is set the PWM inter-
rupt is requested If PWM interrupt is enabled (EPWM=1).
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Keyboard interrupt is generated when any of the keypad connected to P0 pins detects a low-level or edge changed at port
pin. Each keypad interrupt can be individually enabled or disabled. The KBI flag (KBIF[7:0]) should be cleared by soft-
ware.
POR detect can cause POF flag, BOF, to be asserted if power voltage drop below BOD voltage level. Interrupt will occur
if EBOD (IE.5) and global interrupt enable (EA) are set.
All the bits that generate interrupts can be set or reset by software, and thereby software initiated interrupts can be gener-
ated. Each of the individual interrupts can be enabled or disabled by setting or clearing a bit in the IE SFR. IE also has a
global enable/disable bit EA, in which can be cleared to disable all the interrupts.
IE0
EX0
IE1
EX1
BOF
EBOD
KBIF[7:0]
EKB
Wakeup
(If in Power Down)
WDTF
WDTEN
TF0
ET0
ADCI
Interrupt
To CPU
EADC
TF1
ET1
EA
CPTF0
CPTF1
RI+TI
ES
ECPTF
TF2
ET2
SI
I2TOF
EI2C
BKF
EPWM
SPIF
MODF
SPIOVF
ESPI
Figure 19-1 Interrupt Flag Block Diagram
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19.2 Priority Level Structure
There are four priority levels for the interrupts, highest, high, low and lowest. The interrupt sources can be individually set
to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. How-
ever there exists a pre-defined hierarchy amongst the interrupts themselves. This hierarchy comes into play when the in-
terrupt controller has to resolve simultaneous requests having the same priority level. This hierarchy is defined as shown
in Table 19-3, the interrupts are numbered starting from the highest priority to the lowest.
The interrupt flags are sampled every machine-cycle. In the same machine-cycle, the sampled interrupts are polled and
their priority is resolved. If certain conditions are met then the hardware will execute an internally generated LCALL in-
struction which will vector the process to the appropriate interrupt vector address. The conditions for generating the
LCALL include
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine-cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IE, EIE, IP, IPH, EIP or IPH1 registers and is not a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is repeated every ma-
chine-cycle, with the interrupts sampled in the same machine-cycle. If an interrupt flag is active in one cycle but not re-
sponded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. This means that
active interrupts are not remembered; every polling cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate service routine. This
may or may not clear the flag which caused the interrupt. In case of Timer interrupts, the TF0 or TF1 flags are cleared by
hardware whenever the processor vectors to the appropriate timer service routine. In case of external interrupt, INT0 and
INT1, the flags are cleared only if they are edge triggered. In case of Serial interrupts, the flags are not cleared by hard-
ware. In the case of Timer 2 interrupt, the flags are not cleared by hardware. The hardware LCALL behaves exactly like
the software LCALL instruction. This instruction saves the Program Counter contents onto the Stack, but does not save
the Program Status Word PSW. The PC is reloaded with the vector address of that interrupt which caused the LCALL,
which address of vector for the different sources are as follows
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Table 19-1 Vector Locations for Interrupt Sources
Vector Address
0003h
Source
Vector Address
Source
External Interrupt 0
External Interrupt 1
Serial Port
Timer 0 Overflow
Timer 1 Overflow
000Bh
001Bh
002Bh
003Bh
004Bh
005Bh
0013h
Timer 2
Overflow/Match
0023h
I2C Interrupt
KBI Interrupt
SPI Interrupt
ADC Interrupt
0033h
BOD Interrupt
Watchdog Timer
Capture
0043h
0053h
0063h
PWM brake Interrupt
0073h
The vector table is not evenly spaced; this is to accommodate future expansions to the device family.
Table 19-2 Four-level Interrupt Priority
Priority bits
Interrupt Priority Level
IPXH
IPX
0
0
0
1
1
Level 0 (Lowest priority)
Level 1
1
0
Level 2
1
Level 3 (highest priority)
Execution continues from the vectored address till an RETI instruction is executed. On execution of the RETI instruction
the processor pops the Stack and loads the PC with the contents at the top of the stack. The user should watch out for the
status of the stack is restored to whatever after the hardware LCALL, if the execution is to return to the interrupted pro-
gram. The processor does not notice anything if the stack contents are modified and will proceed with execution from the
address put back into PC. Note that a RET instruction would perform exactly the same process as a RETI instruction, but
it would not inform the Interrupt Controller that the interrupt service routine is completed, and would leave the controller
still thinking that the service routine is underway.
The N79E845/844/8432 uses a four-priority level interrupt structure. This allows great flexibility in controlling the han-
dling of the N79E845/844/8432 many interrupt sources. The N79E845/844/8432 supports up to 14 interrupt sources.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IE or EIE. The IE
register also contains a global disable bit, EA, which disables all interrupts at once.
Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the IP,
IPH, EIP, and EIPH registers. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but
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not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any
other interrupt source. So, if two requests of different priority levels are received simultaneously, the request of higher
priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is
serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve simultaneous re-
quests of the same priority level.
The following table summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration
ranking, and whether each interrupt may wake up the CPU from Power-down mode.
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Table 19-3 Summary of interrupt sources
Interrupt
Flag Bit(s)
Vector
Address
Interrupt
Enable Bit(s)
Flag cleared
by
Interrupt
Priority
Arbitration
Ranking
Power-down
Wake-up
Description
External Interrupt 0
BOD Detect
Hardware,
Software
1
IE0
BOF
WDTF
TF0
0003H
0043H
0053H
000BH
0033H
005BH
0013H
003BH
001BH
0023H
0073H
004BH
002Bh
0063H
EX0 (IE0.0)
EBOD (IE.5)
EWDI (EIE.4)
ET0 (IE.1)
IPH.0, IP.0
IPH.5, IP.5
Yes
Yes
Yes
No
(highest)
Software
Software
2
3
EIPH.4,
EIP.4
Watchdog Timer
Timer 0 Interrupt
I2C Interrupt
Hardware,
Software
IPH.1, IP.1
4
SI
I2TOF
EIPH.0,
EIP.0
EI2C (EIE.0)
EADC (IE.6)
EX1 (IE.2)
Software
Software
5
No
ADC Converter
External Interrupt 1
KBI Interrupt
ADCI
IE1
IPH.6, IP.6
IPH.2, IP.2
6
Yes(1)
Yes
Yes
No
Hardware,
Software
7
EIPH.1,
EIP.1
KBIF[7:0]
TF1
EKB (EIE.1)
ET1 (IE.3)
Software
8
Hardware,
Software
Timer 1 Interrupt
Serial Port Tx and Rx
PWM Interrupt
SPI
IPH.3, IP.3
IPH.4, IP.4
9
TI & RI
BKF
ES (IE.4)
Software
Software
Software
Software
Software
10
11
12
13
No
EIPH.5,
EIP.5
EPWM (EIE.5)
ESPI (EIE.6)
ET2 (EIE.7)
ECPTF (EIE.2)
No
SPIF +
MODF +
SPIOVF
EIPH.6,
EIP.6
No
Timer 2
Overflow/Match
EIPH.7,
EIP.7
TF2
No
IPH.7,
IP.7
14
(lowest)
Capture
CAPF0-1
No
[1] The ADC Converter can wake up “Power-down mode” when its clock source is from internal RC.
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19.3 Interrupt Response Time
The response time for each interrupt source depends on several factors, such as the nature of the interrupt and the instruc-
tion underway. In the case of external interrupts INT0 to RI+TI, they are sampled at C3 of every machine-cycle and then
their corresponding interrupt flags IEx will be set or reset. The Timer 0 and 1 overflow flags are set at C3 of the machine-
cycle in which overflow has occurred, which flag values are polled only in the next machine-cycle. If a request is active
and all three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes four machine-
cycles to be completed. Thus there is a minimum time of five machine-cycles between the interrupt flag being set and the
interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or equal priority is be-
ing serviced, the interrupt latency time is obviously dependent on the nature of the service routine currently being execut-
ed. If the polling cycle is not the last machine-cycle of the instruction being executed, an additional delay is introduced.
The maximum response time (if no other interrupt is in service) occurs if the N79E845/844/8432 performs a write to IE,
EIE, IP, IPH, EIP or EIPH and then executes a MUL or DIV instruction. From the time an interrupt source is activated,
the longest reaction time is 12 machine-cycles. This includes 1 machine-cycle to detect the interrupt, 3 machine-cycles to
complete the IE, EIE, IP, IPH, EIP or EIPH access, 5 machine-cycles to complete the MUL or DIV instruction and 4 ma-
chine-cycles to complete the hardware LCALL to the interrupt vector location.
Thus in a single-interrupt system the interrupt response time will always be more than 5 machine-cycles and not more than
12 machine-cycles. The maximum latency of 12 machine-cycle is 48 clock cycles. Note that in the standard 8051 the max-
imum latency is 8 machine-cycles which equals 96 machine-cycles. This is a 50% reduction in terms of clock periods.
19.4 SFR of Interrupt
The SFRs associated with these interrupts are listed below.
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IE – Interrupt Enable (Bit-addressable)
7
EA
R/W
6
5
4
ES
R/W
3
ET1
R/W
2
EX1
R/W
1
ET0
R/W
0
EX0
R/W
EADC
R/W
EBOD
R/W
Address: A8H
Reset value: 0000 0000B
Bit
Name
Description
Enable All Interrupt
7
EA
This bit globally enables/disables all interrupts. It overrides the individual interrupt
mask settings.
0 = Disable all interrupt sources.
1 = Enable each interrupt depending on its individual mask setting. Individual in-
terrupts will occur if enabled.
6
5
4
EADC
EBOD
ES
Enable ADC Interrupt
Enable BOD Interrupt
Enable Serial Port (UART) Interrupt
0 = Disable all UART interrupts.
1 = Enable interrupt generated by TI (SCON.1) or RI (SCON.0).
Enable Timer 1 Interrupt
3
2
ET1
EX1
0 = Disable Timer 1 interrupt
1 = Enable interrupt generated by TF1 (TCON.7).
Enable External interrupt 1
0 = Disable external interrupt 1.
1 = Enable interrupt generated by INT1 pin (P1.4).
Enable Timer 0 Interrupt
1
0
ET0
EX0
0 = Disable Timer 0 interrupt
1 = Enable interrupt generated by TF0 (TCON.5).
Enable External Interrupt 0
0 = Disable external interrupt 0.
1 = Enable interrupt generated by INT0 pin (P1.3).
EIE – Extensive Interrupt Enable
7
6
5
4
3
2
1
0
ET2
ESPI
EPWM
EWDI
-
ECPTF
EKB
EI2C
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R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
Address: E8H
Reset value: 0000 0000B
Bit
Name
Description
7
ET2
0 = Disable Timer 2 Interrupt.
1 = Enable Timer 2 Interrupt.
6
ESPI
SPI interrupt enable:
0 = Disable SPI Interrupt.
1 = Enable SPI Interrupt.
5
4
EPWM
EWDI
0 = Disable PWM Interrupt when external brake pin was braked.
1 = Enable PWM Interrupt when external brake pin was braked.
0 = Disable Watchdog Timer Interrupt.
1 = Enable Watchdog Timer Interrupt.
Reserved
3
2
-
0 = Disable capture interrupts.
1 = Enable capture interrupts.
0 = Disable Keypad Interrupt.
1 = Enable Keypad Interrupt.
0 = Disable I2C Interrupt.
ECPTF
1
0
EKB
EI2C
1 = Enable I2C Interrupt.
IP – Interrupt Priority-0 Register
7
PCAP
R/W
6
5
4
PS
R/W
3
PT1
R/W
2
PX1
R/W
1
PT0
R/W
0
PX0
R/W
PADC
R/W
PBOD
R/W
Address: B8H
Reset value: 0000 0000B
Bit
Name
Description
7
PCAP
1 = Set interrupt high priority of Capture 0/1/2 as highest priority level.
6
5
PADC
PBOD
1 = Set interrupt priority of ADC as higher priority level.
1 = Set interrupt priority of BOD Detector as higher priority level.
1 = Set interrupt priority of Serial port 0 as higher priority level.
1 = Set interrupt priority of Timer 1 as higher priority level.
4
3
PS
PT1
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Bit
Name
Description
2
1
0
PX1
1 = Set interrupt priority of External interrupt 1 as higher priority level.
PT0
PX0
1 = Set interrupt priority of Timer 0 as higher priority level.
1 = Set interrupt priority of External interrupt 0 as higher priority level.
IPH – Interrupt High Priority Register
7
6
5
4
3
2
1
0
PCAPH
PADCH
PBODH
PSH
PT1H
PX1H
PT0H
PX0H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: B7H
Reset value: 0000 0000B
Bit
Name
Description
7
PCAPH
1 = Set interrupt high priority of Capture 0/1/2 as highest priority level.
6
5
4
3
2
1
0
1 = Set interrupt high priority of ADC as the highest priority level.
PADCH
PBODH
PSH
1 = Set interrupt high priority of BOD Detector as the highest priority level.
1 = Set interrupt high priority of Serial port 0 as the highest priority level.
1 = Ro set interrupt high priority of Timer 1 as the highest priority level.
1 = Set interrupt high priority of External interrupt 1 as the highest priority level.
1 = Set interrupt high priority of Timer 0 as the highest priority level.
1 = Set interrupt high priority of External interrupt 0 as the highest priority level.
PT1H
PX1H
PT0H
PX0H
EIP – Interrupt Priority-1 Register
7
PT2
6
5
4
3
-
2
-
1
PKB
0
PI2
PSPI
PPWM
PWDI
R/W
R/W
R/W
R/W
-
R/W
R/W
-
Address: FFH
Reset value: 0000 0000B
Bit
Name
Description
7
1 = Set interrupt priority of Timer 2 as higher priority level.
1 = Set interrupt priority of SPI as higher priority level.
1 = Set interrupt priority of PWM’s brake as higher priority level.
1 = Set interrupt priority of Watchdog as higher priority level.
Reserved
PT2
6
5
PSPI
PPWM
4
PWDI
-
3:2
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Bit
Name
Description
1
0
PKB
1 = Set interrupt priority of Keypad as higher priority level.
PI2
1 = Set interrupt priority of I2C as higher priority level.
EIPH – Interrupt High Priority-1 Register
7
6
5
4
3
-
2
-
1
0
PT2H
PSPIH
PPWMH
PWDIH
PKBH
PI2H
R/W
R/W
R/W
R/W
-
R/W
R/W
-
Address: F7H
Reset value: 0000 0000B
Bit
Name
Description
7
1 = Set interrupt high priority of Timer 2 as the highest priority level.
PT2H
6
5
1 = Set interrupt high priority of SPI as the highest priority level.
PSPIH
PPWMH
PWDIH
-
1 = Set interrupt high priority of PWM’s external brake pin as the highest priority level.
1 = Set interrupt high priority of Watchdog as the highest priority level.
Reserved
4
3:2
1
1 = Set interrupt high priority of Keypad as the highest priority level.
1 = Set interrupt high priority of I2C as the highest priority level.
PKBH
PI2H
0
TCON – Timer 0 and 1 Control (Bit-addressable)
7
TF1
R/W
6
TR1
R/W
5
TF0
R/W
4
TR0
R/W
3
IE1
R/W
2
IT1
R/W
1
IE0
R/W
0
IT0
R/W
Address: 88H
Reset value: 0000 0000B
Bit
Name
Description
External Interrupt 1 Edge Flag
3
IE1
This flag is set via hardware when an edge/level of type defined by IT1 is detect-
ed. If IT1 = 1, this bit will remain set until it is cleared via software or at the begin-
ning of the External Interrupt 1 service routine. If IT1 = 0, this flag is the inverse of
the INT1 input signal's logic level.
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Bit
Name
Description
External Interrupt 1 Type Selection
2
IT1
This bit selects whether the INT1 pin will detect falling edge or low level triggered
interrupts.
0 = INT1 is low level triggered.
1 = INT1 is falling edge triggered.
1
IE0
External Interrupt 0 Edge Flag
This flag is set via hardware when an edge/level of type defined by IT0 is detect-
ed. If IT0 = 1, this bit will remain set until cleared via software or at the beginning
of the External Interrupt 0 service routine. If IT0 = 0, this flag is the inverse of the
INT0 input signal's logic level.
0
IT0
External Interrupt 0 Type Selection
This bit selects whether the INT0 pin will detect falling edge or low level triggered
interrupts.
0 = INT0 is low level triggered.
1 = INT0 is falling edge triggered.
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20 In System Programming (ISP)
The internal Program Memory and on-chip Data Flash support both hardware programming and in system programming
(ISP). Hardware programming mode uses gang-writers to reduce programming costs and time to market while the prod-
ucts enter into the mass production state. However, if the product is just under development or the end product needs
firmware updating in the hand of an end user, the hardware programming mode will make repeated programming difficult
and inconvenient. ISP method makes it easy and possible. The N79E845/844/8432 supports ISP mode allowing a device
to be reprogrammed under software control. The capability to update the application firmware makes VDD = 3.0V ~ 5.5V
of applications.
ISP is performed without removing the microcontroller from the system. The most common method to perform ISP is via
UART along with the firmware in LDROM. General speaking, PC transfers the new APROM code through serial port.
Then LDROM firmware receives it and re-programs into APROM through ISP commands. Nuvoton provides ISP firm-
ware, please visit Nuvoton 8-bit Microcontroller website below and select “Nuvoton ISP-ICP Programmer”.
http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx?tp_GUID=670aaf31-5d5c-45d3-8a9e-
040e148d55cf
20.1 ISP Procedure
Unlike RAM’s real-time operation, to update flash data often takes long time. Furthermore, it is a quite complex timing
procedure to erase, program, or read flash data. Fortunately, the N79E845/844/8432 carried out the flash operation with
convenient mechanism to help the user update the flash content. After ISP enabled by setting ISPEN (CHPCON.0 with
TA protected), the user can easily fill the 16-bit target address in ISPAH and ISPAL, data in ISPFD and command in
ISPCN. Then the ISP is ready to begin by setting a triggering bit ISPGO (ISPTRG.0). Note that ISPTRG is also TA pro-
tected. At this moment, the CPU holds the Program Counter and the built-in ISP automation takes over to control the in-
ternal charge-pump for high voltage and the detail signal timing. After ISP action completed, the Program Counter contin-
ues to run the following instructions. The ISPGO bit will be automatically cleared. The user may repeat steps above for
next ISP action if necessary. Through this progress, the user can easily erase, program, and verify the embedded flash by
just watching out for the pure software.
The following registers are related to ISP processing.
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CHPCON – Chip Control (TA Protected)
7
SWRST
w
6
ISPF
r
5
4
-
-
3
-
-
2
-
-
1
BS
R/W
0
LDUEN
R/W
ISPEN
R/W
Address: 9FH Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
Description
ISP Fault Flag (Read Only)
6
ISPF
The hardware will set this bit when any of the following condition is met:
1. The accessing area is illegal, such as,
(a) Erasing or programming APROM itself when APROM code runs.
(b) Erasing or programming LDROM when APROM code runs but LDUEN is 0.
(c) Erasing, programming, or reading CONFIG bytes when APROM code runs.
(d) Erasing or programming LDROM itself when LDROM code runs.
(e) Accessing oversize.
2. The ISP operating runs from internal Program Memory into external one.
This bit should be cleared via software.
5
LDUEN
Updating LDROM Enable
0 = LDROM is inhibited to be erased or programmed when APROM code runs.
LDROM remains read-only.
1 = LDROM is allowed to be fully accessed when APROM code runs.
4:2
-
Reserved
Boot Selection
There are different meanings of writing to or reading from this bit.
Writing
It defines from which block MCU boots after all resets.
0 = The next rebooting will be from APROM.
1 = The next rebooting will be from LDROM.
Reading
1
BS
It indicates from which block MCU booted after previous reset.
0 = The previous rebooting is from APROM.
1 = The previous rebooting is from LDROM.
ISP Enable
0
ISPEN
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Bit
Name
Description
0 = Enable ISP function.
1 = Disable ISP function.
To enable ISP function will start the internal 22.1184 MHz RC oscillator for timing
control. To clear ISPEN should always be the last instruction after ISP operation
to stop internal RC for reducing power consumption.
ISPCN – ISP Control
7
ISPA17
R/W
6
5
4
3
2
1
0
ISPA16
R/W
FOEN
R/W
FCEN
R/W
FCTRL.3
R/W
FCTRL.2
R/W
FCTRL.1
R/W
FCTRL.0
R/W
Address: AFH
Reset value: 0011 0000B
Bit
7:6
Name
Description
ISPA[17:16] ISP Control
This byte is for ISP controlling command to decide ISP destinations and actions.
5
4
FOEN
FCEN
3:0
FCTRL[3:0]
ISPAH – ISP Address High Byte
7
6
5
4
3
2
1
0
ISPA[15:8]
R/W
Address: A7H
Reset value: 0000 0000B
Bit
7:0
Name
Description
ISPA[15:8] ISP address High Byte
ISPAH contains address ISPA[15:8] for ISP operations.
ISPAL – ISP Address Low Byte
7
6
5
4
3
2
1
0
ISPA[7:0]
R/W
Address: A6H
Reset value: 0000 0000B
Bit
Name
ISPA[7:0]
Description
ISP Address Low Byte
7:0
ISPAL contains address ISPA[7:0] for ISP operations.
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ISPFD – ISP Flash Data
7
6
5
4
3
2
1
0
ISPFD[7:0]
R/W
Address: AEH
Reset value: 0000 0000B
Bit
Name
Description
7:0
ISPFD[7:0] ISP Flash Data
This byte contains flash data which is read from or is going to be written to the flash
memory. The user should write data into ISPFD for program mode before triggering ISP
processing and read data from ISPFD for read/verify mode after ISP processing is fin-
ished.
ISPTRG – ISP Trigger (TA Protected)
7
-
-
6
-
-
5
-
-
4
-
3
-
-
2
-
-
1
-
-
0
ISPGO
W
-
Address: A4H
Reset value: 0000 0000B
Bit
Name
ISPGO
Description
ISP Begin
0
ISP begins by setting this bit as logic 1. After this instruction, the CPU holds the
Program Counter (PC) and the ISP hardware automation takes over to control
the progress. After ISP action completed, the Program Counter continues to run
the following instructions. The ISPGO bit will be automatically cleared and al-
ways read as logic 0.
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20.2 ISP Command Table
ISPCN
FOEN
ISPAH, ISPAL
ISPFD
ISP Command
A[15:0]
D[7:0]
A17, A16
FCEN
FCTRL[3:0]
Data out
D[7:0]=DAH
Read Company ID
x, x[1]
0
1
1
0
1
1
0
1
1
0
0
1011
x[1]
Address in
A[15:0]
FLASH Page Erase
0, 0
0, 0
0, 0
0, 1
0, 1
0, 1
1, 1
1, 1
1, 1
0
0
0
0
0
0
0
0
0
0010
0001
0000
0010
0001
0000
0010
0001
0000
x[1]
APROM
Address in
A[15:0]
Data in
D[7:0]
&
FLASH Program
FLASH Read
Data Flash
Address in
A[15:0]
Data out
D[7:0]
Address in
A[15:0]
FLASH Page Erase
FLASH Program
FLASH Read
x[1]
Address in
A[15:0]
Data in
D[7:0]
LDROM
Address in
A[15:0]
Data out
D[7:0]
Address in
A[15:0]=0000H
CONFIG[2] Page Erase
x[1]
Address in
A[15:0]
Data in
D[7:0]
CONFIG[2] Program
CONFIG[2] Read
Address in
A[15:0]
Data out
D[7:0]
Note:
[1] ‘x’ means ‘don’t care’.
[2] The ‘CONFIG’ means the MCU hardware configuration.
[3] Each page has 128 bytes. So, the address for Page Erase should be 0000, 0080H, 0100H, 0180H, 0200H, .., which is incremented by 0080H.
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20.3 Access Table of ISP Programming
UNLOCK
ISP Code Residence
LOCK
Destination
ISP Code Residence
APROM
[1]
LDROM
APROM
[1]
LDROM
APROM
LDROM
Data Flash
CONFIGs
ID (read)
[2]
[2]
Block color
Comment
Fully accessing
Read only
Accessing inhibit
[1]
[2]
LDUE should be 1, or it will be read only.
New CONFIG functions after POR, WDT, Reset pin or
software reset
Note:
I.
CONFIG full accessing by LDROM while LOCK.
II.
III.
Inhibit APROM jump to LDROM or LDROM jump to APROM.
MCU run in APROM cannot read CONFIGs.
20.4 ISP User Guide
ISP facilitates the updating flash contents in a convenient way; however, the user should follow some restricted laws in
order that the ISP operates correctly. Without noticing warnings will possible cause undetermined results even serious
damages of devices. Be attention of these notices. Furthermore, this paragraph will also support useful suggestions during
ISP procedures.
(1) If no more ISP operation needs, the user should clear ISPEN (CHPCON.0) to zero. It will make the system void to
trigger ISP unaware. Furthermore, ISP requires internal 22.1184MHZ RC oscillator running. If the external clock source
is chosen, disabling ISP will stop internal 22.1184MHz RC for saving power consumption. Note that a write to ISPEN is
TA protected.
(2) CONFIG bytes can be ISP fully accessed only when loader code executing in LDROM. New CONFIG bytes other
than CBS bit activate after all resets. New CBS bit activates after resets other than software reset.
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(3) When the LOCK bit (CONFIG0.1) is activated, ISP reading, writing, or erasing can still be valid.
(4) ISP works under VDD = 3.0V ~ 5.5V.
(5) APROM and LDROM can read itself through ISP method.
Note: If the user would like to develop ISP program, always erase and program CONFIG bytes at the last step for data
security.
20.5 ISP Demo Code
Common Subroutine for ISP
Enable_ISP:
MOV
CLR
MOV
MOV
ORL
SETB
CALL
RET
ISPCN,#00110000b
EA
TA,#0AAH
TA,#55H
CHPCON,#00000001b
EA
;select “Standby” mode
;if any interrupt is enabled, disable temporarily
;CHPCON is TA-Protection
;
;ISPEN=1, enable ISP function
Trigger_ISP
;
Disable_ISP:
MOV
CALL
CLR
MOV
MOV
ANL
SETB
RET
ISPCN,#00110000b
Trigger_ISP
EA
TA,#0AAH
TA,#55H
;select “Standby” mode
;
;if any interrupt is enabled, disable temporarily
;CHPCON is TA-Protection
;
CHPCON,#11111110b
EA
;ISPEN=0, disable ISP function
Trigger_ISP:
CLR
MOV
MOV
MOV
SETB
RET
EA
TA,#0AAH
TA,#55H
ISPTRG,#00000001b
EA
;if any interrupt is enabled, disable temporarily
;ISPTRG is TA-Protection
;
;write ‘1’ to bit ISPGO to trigger an ISP processing
Read Company ID
CALL
MOV
CALL
MOV
Enable_ISP
ISPCN,#00001011b
Trigger_ISP
A,ISPFD
;select “Read Company ID” mode
;now, ISPFD contains Company ID (should be DAH), move to ACC for
;further use
CALL
Disable_ISP
Read Device ID
CALL
Enable_ISP
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MOV
MOV
MOV
CALL
MOV
MOV
MOV
CALL
MOV
CALL
ISPCN,#00001100b
ISPAH,#00H
ISPAL,#00H
Trigger_ISP
A,ISPFD
ISPAH,#00H
ISPAL,#01H
Trigger_ISP
A,ISPFD
;select “Read Device ID” mode
;fill address with 0000H for low-byte DID
;
;now, ISPFD contains low-byte DID, move to ACC for further use
;fill address with 0001H for high-byte DID
;
;now, ISPFD contains high-byte DID, move to ACC for further use
Disable_ISP
FLASH Page Erase (target address in APROM/Data Flash/LDROM area)
CALL
MOV
Enable_ISP
ISPCN,#00100010b
;select “FLASH Page Erase” mode, (A17,A16)=(0,0) for APROM/Data
;Flash/LDROM
MOV
MOV
CALL
CALL
ISPAH,#??H
ISPAL,#??H
Trigger_ISP
Disable_ISP
;fill page address
FLASH Program (target address in APROM/Data Flash/LDROM area)
CALL
MOV
Enable_ISP
ISPCN,#00100001b
;select “FLASH Program” mode, (A17,A16)=(0,0) for APROM/Data
;Flash/LDROM
MOV
MOV
MOV
CALL
CALL
ISPAH,#??H
ISPAL,#??H
ISPFD,#??H
Trigger_ISP
Disable_ISP
;fill byte address
;fill data to be programmed
FLASH Read (target address in APROM/Data Flash/LDROM area)
CALL
MOV
Enable_ISP
ISPCN,#00000000b
;select “FLASH Read” mode, (A17,A16)=(0,0) for APROM/Data
;Flash/LDROM
MOV
MOV
CALL
MOV
ISPAH,#??H
ISPAL,#??H
Trigger_ISP
A,ISPFD
;fill byte address
;now, ISPFD contains the Flash data, move to ACC for further use
CALL
Disable_ISP
CONFIG Page Erase (target address in CONFIG area)
CALL
MOV
MOV
Enable_ISP
ISPCN,#11100010b
ISPAH,#00H
;select “CONFIG Page Erase” mode, (A17,A16)=(1,1) for CONFIG
;fill page address #0000H, because there is only one page
MOV
ISPAL,#00H
CALL
CALL
Trigger_ISP
Disable_ISP
CONFIG Program (target address in CONFIG area)
CALL
MOV
MOV
Enable_ISP
ISPCN,#11100001b
ISPAH,#00H
;select “CONFIG Program” mode, (A17,A16)=(1,1) for CONFIG
;fill byte address, 0000H/0001H/0002H/0003H for CONFIG0/1/2/3,
;respectively
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MOV
MOV
CALL
ISPAL,#??H
ISPFD,#??H
Trigger_ISP
;fill data to be programmed
CALL
Disable_ISP
CONFIG Read (target address in CONFIG area)
CALL
MOV
MOV
Enable_ISP
ISPCN,#11000000b
ISPAH,#00H
;select “CONFIG Read” mode, (A17,A16)=(1,1) for CONFIG
; fill byte address, 0000H/0001H/0002H/0003H for CONFIG0/1/2/3,
;respectively
MOV
CALL
MOV
ISPAL,#??H
Trigger_ISP
A,ISPFD
;now, ISPFD contains the CONFIG data, move to ACC for further
;use
CALL
Disable_ISP
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21 Power Management
The N79E845/844/8432 has several features that help the user to control the power consumption of the device. The power
saved features have Power-down mode and Idle mode operations. For a stable current consumption, user should watch out
for the states of P0 pins.
In system power saving modes, user should specifically watch out for the Watchdog Timer. The hardware will clear WDT
counter automatically after entering into or being woken-up from Idle or Power-down mode. It prevents unconscious sys-
tem reset.
PCON – Power Control
7
6
5
-
-
4
POF
R/W
3
GF1
R/W
2
GF0
R/W
1
PD
R/W
0
IDL
R/W
SMOD
R/W
SMOD0
R/W
Address: 87H Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
Description
Power-down Mode
1
PD
Setting this bit puts MCU into Power-down mode. Under this mode, both CPU and
peripheral clocks stop and Program Counter (PC) suspends. It provides the lowest
power consumption. After CPU is woken up from Power Down, this bit will be au-
tomatically cleared via hardware and the program continue executing the interrupt
service routine (ISR) of the very interrupt source that woke the system up before.
After return from the ISR, the device continues execution at the instruction which fol-
lows the instruction that put the system into Power-down mode.
Note: If IDL bit and PD bit are set simultaneously, the MCU will enter into Power-
down mode. Then it does not go to Idle mode after exiting Power Down.
0
IDL
Idle Mode
Setting this bit puts MCU into Idle mode. Under this mode, the CPU clock stops
and Program Counter (PC) suspends. After CPU is woken up from Idle, this bit will
be automatically cleared via hardware and the program continue executing the
ISR of the very interrupt source that woke the system up before. After return from
the ISR, the device continues execution at the instruction which follows the in-
struction that put the system into Idle mode.
21.1 Idle Mode
Idle mode suspends CPU processing by holding the Program Counter. No program code are fetched and run in Idle mode.
This forces the CPU state to be frozen. The Program Counter (PC), the Stack Pointer (SP), the Program Status Word
(PSW), the Accumulator (ACC), and the other registers hold their contents during Idle mode. The port pins hold the logi-
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cal states they had at the time Idle was activated. Generally it saves considerable power of typical half of the full operating
power.
Since the clock provided for peripheral function logic circuit like timer or serial port still remain in Idle mode, the CPU
can be released from the Idle mode using any of the interrupt sources if enabled. The user can put the device into Idle
mode by writing 1 to the bit IDL (PCON.0). The instruction that sets the IDL bit is the last instruction that will be execut-
ed before the device goes into Idle mode.
The Idle mode can be terminated in two ways. First, any interrupt if enabled will cause an exit. This will automatically
clear the IDL bit, terminate the Idle mode, and the interrupt service routine (ISR) will be executed. After using the RETI
instruction to jump out of the ISR, execution of the program will be the one following the instruction which put the CPU
into Idle mode. The second way to terminate the Idle mode is with any reset other than software reset.
21.2 Power-down Mode
Power-down mode is the lowest power state that N79E845/844/8432 can enter. It remain the power consumption as
a ”μA” level. This is achieved by stopping the clock system no matter internal RC clock or external crystal. Both of CPU
and peripheral functions like Timers or UART are frozen. Flash memory stops. All activity is completely stopped and the
power consumption is reduced to the lowest possible value. The device can be put into Power-down mode by writing 1 to
bit PD (PCON.1). The instruction that does this action will be the last instruction to be executed before the device goes
into Power-down mode. In Power-down mode, RAM maintains its content. The port pins output the values held by their
respective.
There are two ways to exit N79E845/844/8432 from Power-down mode. The first is with all resets except software reset.
BOD reset will also wake up CPU from Power-down mode. Make sure that BOD detection is enabled before the system
enters into Power-down. However, for a principle of least power consumption, it is uncommon to enable BOD detection in
Power-down mode, which is not a recommended application. Of course, the RST pin reset and power-on reset will remove
the Power Down status. After RST pin reset or power-on reset, the CPU is initialized and starts executing program code
from the beginning.
The N79E845/844/8432 can be woken up from Power-down mode by forcing an external interrupt pin activated, provid-
ing the corresponding interrupt enabled and the global enable EA bit (IE.7) is set. If these conditions are met, the trigger
on the external pin will asynchronously restart the clock system. Then device executes the interrupt service routine (ISR)
for the corresponding external interrupt. After the ISR is completed, the program execution returns to the instruction after
the one that puts the device into Power-down mode and continues.
BOD, Watchdog and KBI interrupt are other sources to wake up CPU from Power Down. As mentioned before the user
will endure the current of BOD detection circuit. Using KBI interrupt to wake up CPU from Power Down has a re-
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striction: The KBI pin keeps low (high) before CPU enters Power Down. Then only rising (falling) edge of KBI Interrupt
can wake up CPU from Power Down.
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22 Clock System
The N79E845/844/8432 provides three options of the clock system source that is configured by FOSC (CONFIG3.1~0). It
switches the clock system from crystal/resonator, on-chip RC oscillator, or external clock from XTAL1 pin. The
N79E845/844/8432 is embedded with an on-chip RC oscillator of 22.1184 MHz/11.0592 MHz selected by CONFIG set-
ting, factory trimmed to ± 1% under the condition of room temperature and VDD=5V. If the external clock source is from
the crystal, the frequency supports from 4 MHz to 24 MHz.
KBI
Flash
XTAL2
Oscillating
0x
Circuit
XTAL1
Turbo 8051
CPU
Clock
Filter
Clock
Divider
FOSC
FSYS
10
11
FIHRC
1/2
1
0
Internal RC
Oscillator
(22.1184MHz)
CKF
(CONFIG3.4)
Timers
DIVM
FOSC[1:0]
(CONFIG3[1:0])
Serial Port
(UART)
OSCFS
(CONFIG3.3)
Internal RC
Oscillator
(~10kHz)
FILRC
Watchdog
Timer
I2C
PWM
ADC
Figure 22–1 Clock System Block Diagram
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CONFIG3
7
CWDTEN
R/W
6
-
-
5
-
-
4
CKF
R/W
3
2
-
-
1
0
OSCFS
R/W
FOSC1
R/W
FOSC0
R/W
Uprogrammed value: 1111 1111B
Bit
Name
Description
Clock Filter Enable
4
CKF
1 = Enable clock filter. It increases noise immunity and EMC capacity.
0 = Disable clock filter.
3
OSCFS
Internal RC Oscillator Frequency Selection
1 = Select 22.1184 MHz as the clock system if internal RC oscillator mode is used.
It bypasses the divided-by-2 path of internal oscillator to select 22.1184 MHz
output as the clock system source.
0 = Select 11.0592 MHz as the clock system if internal RC oscillator mode is used.
The internal RC divided-by-2 path is selected. The internal oscillator is equiva-
lent to 11.0592 MHz output used as the clock system.
2
-
Reserved
1:0
FOSC1
FOSC0
Oscillator Select Bit
For chip clock source selection, refer to the following table.
(FOSC1, FOSC0)
(1, 1)
Chip Clock Source
Internal RC oscillator
(1, 0)
Reserved
(0, 1)
(0, 0)
External crystal, 4 MHz ~ 24 MHz
DIVM – Clock Divider Register
7
6
5
4
3
2
1
0
DIVM[7:0]
R/W
Address: 95H
Reset value: 0000 0000B
Bit
Name
Description
7:0
DIVM[7:0]
Clock Dvider
The clock system frequency FSYS follows the equation below according to DIVM
value.
FSYS = FOSC, while DIVM = 00H.
1
FSYS
=
FOSC, while DIVM = 01H ~ FFH.
×
2(DIVM+1)
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22.1 On-Chip RC Oscillator
The on-chip RC oscillator is enabled while FOSC (CONFIG3.1~0) is 1. Setting OSCFS (CONFIG3.3) logic 1 will switch
to a divided-by-2 path.
22.2 Crystal/Resonator
The crystal/resonator is selected as the system clock while FOSC[1:0] keep programmed as [0:1]. XTAL1 and XTAL2 are
the input and output, respectively, of an internal inverting amplifier. A crystal or resonator can be used by connecting be-
tween XTAL1 and XTAL2 pins. The crystal or resonator frequency from 4MHz up to 24MHz is allowed. CKF
(CONFIG3.4) is the control bit of clock filter circuit of XTAL1 input pin.
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23 Power Monitoring
To prevent incorrect execution during power up and power drop, the N79E845/844/8432 provides three power monitor
functions, power-on detection and BOD detection.
23.1 Power-on Detection
The power-on detection function is designed for detecting power up after power voltage reaches to a level where system
can work. After power-on detected, the POF (PCON.4) will be set 1 to indicate a cold reset, a power-on reset complete.
The POF flag can be cleared via software.
23.2 Brown-out Detection
The other power monitoring function, BOD detection circuit is for monitoring the VDD level during execution. There are
two programmable BOD trigger levels available for wide voltage applications. The two nominal levels are 2.7V and 3.8V
selected via setting CBOV in CONFIG2. When VDD drops to the selected BOD trigger level (VBOD), the BOD detection
logic will either reset the CPU or request a BOD interrupt. The user may determine BOD reset or interrupt enable accord-
ing to different application systems.
The BOD detection will request the interrupt while VDD drops below VBOD while BORST (PMCR.4) is 0. In this case,
BOF (PMCR.3) will set as 1. After the user clears this flag whereas VDD remains below VBOD, BOF will not set again.
BOF just acknowledge the user a power drop occurs. The BOF will set 1 after VDD goes higher than VBOD to indicate a
power resuming. VBOD has a hysteresis of 20~200mV.
CONFIG2
7
6
5
-
-
4
3
-
-
2
-
-
1
-
-
0
-
-
CBODEN
R/W
CBOV
R/W
CBORST
R/W
Unprogrammed value: 1111 1111B
Bit Name
Description
7
CBODEN
CONFIG BOD Detection Enable
1 = Disable BOD detection.
0 = Enable BOD detection.
BODEN is initialized by inverted CBODEN (CONFIG2, bit-7) at any resets.
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Bit Name
Description
CONFIG BOD Voltage Selection
6
CBOV
This bit select one of two BOD voltage level.
CONFIG-bits SFR
BOD voltage
CBOV
BOV
1
0
0
1
Enable BOD= 2.7V
Enable BOD= 3.8V
5
4
-
Reserved
CBORST
CONFIG BOD Reset Enable
This bit decides if a BOD reset is caused after a BOD event.
1 = Enable BOD reset when VDD drops below VBOD or VDD rises above VBOD
.
0 = Disable BOD reset when VDD drops below VBOD. Chip will assert BOF when
VDD drops below VBOD or VDD rises above VBOD
.
PMCR – Power Monitoring Control (TA Protected)
7
6
BOV
5
-
-
4
3
BOF
R/W
2
-
1
-
0
-
BODEN
BORST
R/W
R/W
R/W
-
-
-
Address: A3H Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
BODEN
Description
7
BOD-detect Function Control
BODEN is initialized by inverted CBODEN (CONFIG2, bit-7) at any resets.
1 = Enable BOD detection.
0 = Disable BOD detection.
6
BOV
BOD Voltage Select Bits
BOD are initialized at reset with the value of bits CBOV in CONFIG3-bits
BOD Voltage Select bits:
CONFIG-bits SFR
BOD Voltage
CBOV
BOV
1
0
0
1
Enable BOD= 2.7V
Enable BOD= 3.8V
5
-
Reserved
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Bit
Name
BORST
Description
BOD Reset Enable
4
This bit decides if a BOD reset is caused after a BOD event.
0 = Disable BOD reset when VDD drops below VBOD or VDD rises above VBOD. Chip
will assert BOF when VDD drops below VBOD.
1 = Enable BOD reset when VDD drops below VBOD or VDD rises above VBOD
.
3
2
BOF
BOD Flag
This flag will be set as logic 1 via hardware after a VDD dropping below or rising
above VBOD event occurs. If both EBOD (IE.5) and EA (IE.7) are set, a BOD inter-
rupt requirement will be generated. This bit should be cleared via software.
-
-
-
It should be set to logic 0.
Reserved
1
0
Reserved
Note: If BOF is 1 after chip reset, it is strongly recommended to initialize the user program by clearing BOF.
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24 Reset Conditions
The N79E845/844/8432 has several options to place device in reset condition. In general, most SFRs go to their reset val-
ue irrespective of the reset condition, but there are several reset source indication flags whose state depends on the source
of reset. There are 5 ways of putting the device into reset state. They are power-on reset, RST pin reset, software reset,
Watchdog Timer reset, and BOD reset.
24.1 Power-on Reset
The N79E845/844/8432 incorporates an internal voltage reference. During a power-on process of rising power supply
voltage VDD, this voltage reference will hold the CPU in power-on reset mode when VDD is lower than the voltage refer-
ence threshold. This design makes CPU not access program flash while the VDD is not adequate performing the flash read-
ing. If an undetermined operating code is read from the program flash and executed, this will put CPU and even the whole
system in to an erroneous state. After a while, VDD rises above the reference threshold where the system can work, the
selected oscillator will start and then program code will be executed from 0000H. At the same time, a power-on flag POF
(PCON.4) will be set 1 to indicate a cold reset, a power-on reset complete. Note that the contents of internal RAM will be
undetermined after a power-on. It is recommended that user give initial values for the RAM block. P1.6, P1.7, P1.0 and
P1.1 are forced to Quasi-bi-direction type when chip is in reset state.
It is recommended that the POF be cleared to 0 via software to check if a cold reset or warm reset performed after the next
reset occurs. If a cold reset caused by power off and on, POF will be set 1 again. If the reset is a warm reset caused by
other reset sources, POF will remain 0. The user may take a different course to check other reset flags and deal with the
warm reset event.
PCON – Power Control
7
6
5
-
-
4
POF
R/W
3
GF1
R/W
2
GF0
R/W
1
PD
R/W
0
IDL
R/W
SMOD
R/W
SMOD0
R/W
Address: 87H Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
Description
Power-on Reset Flag
4
POF
This bit will be set as 1 after a power-on reset. It indicates a cold reset, a power-
on reset complete. This bit remains its value after any other resets. This flag is
recommended to be cleared via software.
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24.2 BOD Reset
BOD detection circuit is for monitoring the VDD level during execution. When VDD drops to the selected BOD trigger level
(VBOD) or VDD rises over VBOD , the BOD detection logic will reset the CPU if BORST (PMCR.4) setting 1.
PMCR – Power Monitoring Control (TA Protected)
7
6
BOV
R/W
5
-
-
4
3
BOF
R/W
2
-
1
-
0
-
BODEN
R/W
BORST
R/W
-
-
-
Address: A3H Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
BODEN
Description
7
BOD-detect Function Control
BODEN is initialized by inverted CBODEN (CONFIG2, bit-7) at any resets.
1 = Enable BOD detection.
0 = Disable BOD detection.
6
BOV
BOD Voltage Select Bits
BOD are initialized at reset with the value of bits CBOV in CONFIG3-bits
BOD Voltage Select bits:
CONFIG-bits
SFR
BOV
0
BOD Voltage
CBOV
1
0
Enable BOD= 2.7V
Enable BOD= 3.8V
1
5
4
-
Reserved
BOD Reset Enable
BORST
This bit decides if a BOD reset is caused after a BOD event.
0 = Disable BOD reset when VDD drops below VBOD or VDD rises above VBOD. Chip will
assert BOF when VDD drops below VBOD.
1 = Enable BOD reset when VDD drops below VBOD or VDD rises above VBOD
.
3
2
BOF
BOD Flag
This flag will be set as logic 1 via hardware after a VDD dropping below or rising
above VBOD event occurs. If both EBOD (IE.5) and EA (IE.7) are set, a BOD inter-
rupt requirement will be generated. This bit should be cleared via software.
-
-
-
It should be set to logic 0.
Reserved
1
0
Reserved
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24.3 RST Pin Reset
The hardware reset input is RST pin which is the input with a Schmitt trigger. A hardware reset is accomplished by hold-
ing the RST pin low for at least two machine-cycles to ensure detection of a valid hardware reset signal. The reset circuit-
ry then synchronously applies the internal reset signal. Thus the reset is a synchronous operation and requires the clock to
be running to cause an external reset.
Once the device is in reset condition, it will remain so as long as RST pin is 1. After the RST low is removed, the CPU
will exit the reset state with in two machine-cycles and begin code executing from address 0000H. There is no flag associ-
ated with the RST pin reset condition. However since the other reset sources have flags, the external reset can be consid-
ered as the default reset if those reset flags are cleared.
If a RST pin reset applies while CPU is in Power-down mode, the way to trigger a hardware reset is slightly different.
Since the Power-down mode stops clock system, the reset signal will asynchronously cause the clock system resuming.
After the clock system is stable, CPU will enter into the reset state, then exit and start to execute program code from ad-
dress 0000H.
Note: Because reset pin has internal pull-up resistor (about 200KΩ at VDD = 5V), this pin cannot be floating. Reset
pin should be connected to a 100Ω pull-up resistor and a 10uF pull-low capacitor.
24.4 Watchdog Timer Reset
The Watchdog Timer is a free running timer with programmable time-out intervals. The user can clear the Watchdog
Timer at any time, causing it to restart the count. When the selected time-out occurs, the Watchdog Timer will reset the
system directly. The reset condition is maintained via hardware for two machine-cycles. After the reset is removed the
device will begin execution from 0000H.
Once a reset due to Watchdog Timer occurs the Watchdog Timer reset flag WDTRF (WDCON0.3) will be set. This bit
keeps unchanged after any reset other than a power-on reset. The user may clear WDTRF via software.
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WDCON0 – Watchdog Timer Control (TA Protected)
7
6
WDCLR
W
5
WDTF
-
4
3
2
1
0
WDTEN
R/W
WIDPD
R/W
WDTRF
R/W
WPS2
R/W
WPS1
R/W
WPS0
R/W
Address: D8H Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
WDTRF
Description
3
WDT Reset Flag
When the MCU resets itself, this bit is set by hardware. The bit should be cleared by soft-
ware.
If EWRST=0, the interrupt flag WDTRF won’t be set by hardware, and the MCU will
reset itself right away.
If EWRST=1, the interrupt flag WDTRF will be set by hardware and the MCU will jump
into WDT’s interrupt service
routine if WDT interrupt is enabled, and the MCU won’t reset itself until 512 CPU clocks
elapse. In other words, in this condition, the user also needs to clear the WDT counter (by
writing ‘1’ to WDCLR bit) during this period of 512 CPU clocks, or the MCU will also
reset itself when 512 CPU clocks elapse.
WDCON1 – Watchdog Timer Control (TA Protected)
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
-
-
0
EWRST
R/W
Address: ABH
Reset value: 0000 0000B
Bit
Name
EWRST
Description
0
0 = Disable WDT Reset function.
1 = Enable WDT Reset function.
24.5 Software Reset
N79E845/844/8432 are enhanced with a software reset. This allows the program code to reset the whole system in soft-
ware approach. It is quite useful in the end of an ISP progress. For example, if an LDROM updating APROM ISP finishes
and the code in APROM is correctly updated, a software reset can be asserted to reboot CPU from the APROM to check
the result of the updated APROM program code immediately. Writing 1 to SWRST (CHPCON.7) will trigger a software
reset. Note that this bit is timed access protection. See demo code below.
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CHPCON – Chip Control (TA Protected)
7
SWRST
W
6
5
4
-
-
3
-
-
2
-
-
1
BS
R/W
0
ISPF
R/W
LDUEN
R/W
ISPEN
R/W
Address: 9FH Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
SWRST
Description
Software Reset
7
Setting this bit as logic 1 will cause a software reset. It will automatically be
cleared via hardware after reset in finished.
The software demo code is listed below.
CLR EA
;If any interrupt is enabled, disable temporarily
MOV TA,#0AAh
MOV TA,#55h
ANL CHPCON,#0FDh
MOV TA,#0AAh
MOV TA,#55h
ORL CHPCON,#80h
;TA protection.
;
;BS = 0, reset to APROM.
;Software reset
24.6 Boot Selection
CONFIG0.7
CBS
CHPCON.1
BS
Load
Watchdog Timer reset
Reset and boot from APROM
Reset and boot from LDROM
BS = 0
BS = 1
Software reset
Brownout reset
Power-on reset
RST-pin reset
Figure 24–1 Boot Selection Diagram
The N79E845/844/8432 provides user a flexible boot selection for variant application. The SFR bit BS in CHPCON.1
determines CPU booting from APROM or LDROM after any source of reset. If reset occurs and BS is 0, CPU will reboot
from APPROM. Else, the CPU will reboot from LDROM.
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CONFIG0
7
CBS
R/W
6
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
0
LOCK
R/W
DFEN
R/W
Unprogrammed value: 1111 1111B
Bit
Name
Description
CONFIG Boot Selection
7
CBS
This bit defines from which block MCU boots after all resets except software reset.
1 = MCU will boot from APROM after all resets except software reset.
0 = MCU will boot from LDROM after all resets except software reset.
CHPCON – Chip Control (TA Protected)
7
SWRST
W
6
5
4
-
3
-
-
2
-
-
1
0
ISPF
R/W
LDUEN
R/W
BS[1]
R/W
ISPEN
R/W
-
Address: 9FH Reset value: see Table 7–2 N79E845/844/8432 SFR Description and Reset Values
Bit
Name
Description
Boot Selection
1
BS
There are different meanings of writing to or reading from this bit.
Writing:
It defines from which block MCU boots after all resets.
0 = The next rebooting will be from APROM.
1 = The next rebooting will be from LDROM.
Reading:
It indicates from which block MCU booted after previous reset.
0 = The previous rebooting is from APROM.
1 = The previous rebooting is from LDROM.
[1] Note that this bit is initialized by being loaded from the inverted value of CBS bit in CONFIG0.7 at all resets except software reset. It
keeps unchanged after software reset.
Note: After the CPU is released from all reset state, the hardware will always check the BS bit instead of the CBS bit to
determine from APROM or LDROM that the device reboots.
24.7 Reset State
The reset state does not affect the on-chip RAM. The data in the RAM will be preserved during the reset. Note that the
RAM contents may be lost if the VDD falls below approximately 1.2V. This is the minimum voltage level required for
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RAM data retention. Therefore, after the power-on reset the RAM contents will be indeterminate. During a power fail
condition. If the power falls below the data retention minimum voltage, the RAM contents will also lose.
After a reset, most of SFRs go to their initial values except bits which are affected by different reset events. See the notes
of Table 7–2 N79E845/844/8432 SFR Description and Reset Values. for the initial state of all SFRs. Some special func-
tion registers initial value depends on different reset sources. Refer to Table 24- for details. The Program Counter is forced
to 0000H and held as long as the reset condition is applied. Note that the Stack Pointer is also reset to 07H, therefore the
stack contents may be effectively lost during the reset event even though the RAM contents are not altered.
After a reset, interrupts and Timers are disabled. The Watchdog Timer is disabled if the reset source was a power-on reset.
The I/O port SFRs have FFH written into them which puts the port pins in a high state.
Table 24-2 Initial State of SFR Caused by Different Resets
With Time
Watchdog
Reset
BOD
Reset
Software/ External
Reset
Power-on Reset
Access
Protection
C000 0000B
b7(ENWDT)=
/CENWDT(CONFIG3.7)
C0Uu 1UUUB
C0UU UUUUB
WDCON0 (D8H)
Y
0000 0000B
WDCON1 (ABH)
ISPTRG (A4H)
Y
Y
XXXX XXX0B
CXCC 10XXB
b[7:4]=CONFIG2
UXUU U0XXB
UXUU 10XXB
PMCR (A3H)
Y
0000 00C0B
b1(BS)=/CBS
000X XUU0B
CHPCON (9FH)
SHBDA (9CH)
Y
Y
CONFIG1
0001 000b
Unchanged
00uu 0000b
00uu 0000b
00uu 0000b
PCON (87H)
N
(software/External
reset)
Note: The writes of AAH and 55H should occur within 3 machine-cycles of each other. Interrupts should be
disabled during this procedure to avoid delay between the two writes.
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25 CONFIG Bits (CONFIG)
The N79E845/844/8432 has several hardware configuration bytes, called CONFIG bits, which are used to configure the
hardware options such as the security bits, clock system source, and so on, which hardware options can be re-configured
through the Programmer/Writer or ISP modes. The N79E845/844/8432 has four CONFIG bits those are CONFIG0~3.
Several functions which are defined by certain CONFIG bits are also available to be re-configured by certain SFR bits.
Therefore, there is a need to LOAD such CONFIG bits into respective SFR bits. Such loading will occurs after resets.
(Software reset will reload all CONFIG bits except CBS bit in CONFIG0.7) These SFR bits can be continuously con-
trolled via user’s software. Other resets will remain the values in these SFR bits unchanged.
Note: CONFIG bits marked as "-" should always keep unprogrammed.
25.1 CONFIG0
7
CBS
R/W
6
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
0
LOCK
R/W
DFEN
R/W
Unprogrammed value: 1111 1111B
Bit
7
Name
CBS
Description
CONFIG Boot Selection
This bit defines from which block MCU boots after all resets except software re-
set.
1 = MCU will boot from APROM after all resets except software reset.
0 = MCU will boot from LDROM after all resets except software reset.
6:2
1
-
Reserved
LOCK
Chip Lock Enable
1 = Chip is unlocked. All of APROM, LDROM, and Data Flash are not locked.
Their contents can be read out through a parallel Programmer/Writer.
0 = Chip is locked. APROM, LDROM, and Data Flash are locked. Their contents
read through parallel Programmer/Writer will become FFH.
Note that CONFIG bytes are always unlocked and can be read. Hence, once the chip is
locked, the CONFIG bytes cannot be erased or programmed individually. The only way
to disable chip lock is to use the whole chip erase mode. However, all data within
APROM, LDROM, Data Flash, and other CONFIG bits will be erased when this proce-
dure is executed.
If the chip is locked, it does not alter the ISP function.
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Bit
0
Name
Description
Data Flash Enable (N79E845 Only)
DFEN
1 = There is no Data Flash space. The APROM size is 16 Kbytes.
0 = Data Flash exists. The Data Flash and APROM share 16 Kbytes depending
on SHBDA settings.
7
6
-
5
-
4
-
3
-
2
-
1
0
CONFIG0
CHPCON
CBS
LOCK
DFEN
7
6
5
4
3
2
1
0
SWRST
ISPF
LDUE
-
-
-
BS
ISPEN
Figure 25–1 CONFIG0 Reset Reloading Except Software Reset
25.2 CONFIG1 (N79E845 Only)
7
6
5
4
3
2
1
0
CHBDA[7:0][1]
R/W
Unprogrammed value: 1111 1111B
Bit
7:0
Name
Description
CHBDA[7:0] CONFIG High Byte of Data Flash Starting Address
This byte is valid only when DFEN (CONFIG0.0) is 0. It is used to determine
the starting address of the Data Flash.
Note: There will be no APROM if setting CHBDA 00H. CPU will execute codes in minimum size(256B) of internal Program Memory.
7
6
5
4
3
2
1
0
CONFIG1
CHBDA[7:0]
7
6
5
4
3
2
1
0
SHBDA
SHBDA[7:0]
Figure 25–2 CONFIG1 Reset Reloading
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25.3 CONFIG2
7
6
5
-
-
4
3
-
-
2
-
-
1
-
-
0
-
-
CBODEN
R/W
CBOV
R/W
CBORST
R/W
Unprogrammed value: 1111 1111B
Bit Name
Description
7
CBODEN
CONFIG BOD Detection Enable
1 = Disable BOD detection.
0 = Enable BOD detection.
BODEN is initialized by inverted CBODEN (CONFIG2, bit-7) at any resets.
CONFIG BOD Voltage Selection
6
CBOV
This bit selects one of two BOD voltage level.
CONFIG-bits
SFR
BOV
0
BOD Voltage
CBOV
1
0
Enable BOD= 2.7V
Enable BOD= 3.8V
1
5
4
-
Reserved
CBORST
CONFIG BOD Reset Enable
This bit decides if a BOD reset is caused after a BOD event.
1 = Enable BOD reset when VDD drops below VBOD or VDD rises above VBOD.
0 = Disable BOD reset when VDD drops below VBOD or VDD rises above VBOD
Reserved
.
3:0
-
7
6
5
-
4
3
-
2
-
1
-
0
-
CONFIG2
CBODEN
CBOV
CBORST
7
6
5
-
4
3
2
-
1
-
0
-
PMCR
BODEN
BOV
BORST
BOF
Figure 25–3 CONFIG2 Reset Reloading
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25.4 CONFIG3
7
6
-
-
5
-
-
4
CKF
R/W
3
2
-
-
1
0
CWDTEN
R/W
OSCFS
R/W
FOSC1
R/W
FOSC0
R/W
Unprogrammed value: 1111 1111B
Bit
Name
Description
7
CWDTEN
CONFIG Watchdog Timer Enable
1 = Disable Watchdog Timer after all resets.
0 = Enable Watchdog Timer after all resets.
WDTEN is initialized by inverted CWDTEN (CONFIG3, bit-7) at any other resets.
6
5
4
-
-
Reserved
Reserved
CKF
Clock Filter Enable
1 = Enable clock filter. It increases noise immunity and EMC capacity.
0 = Disable clock filter.
3
OSCFS
Internal RC Oscillator Frequency Selection
1 = Select 22.1184 MHz as the clock system if internal RC oscillator mode is used.
It bypasses the divided-by-2 path of internal oscillator to select 22.1184MHz
output as the clock system source.
0 = Select 11.0592 MHz as the clock system if internal RC oscillator mode is used.
The internal RC divided-by-2 path is selected. The internal oscillator is equiva-
lent to 11.0592 MHz output used as the clock system.
2
1
0
-
Reserved
FOSC1
FOSC0
Oscillator Select Bit
Chip Clock Source Selection (See the Following Table)
(FOSC1, FOSC0)
(1, 1)
Chip Clock Source
Internal RC oscillator
(1, 0)
Reserved
(0, 0)
(0, 1)
External crystal, 4 MHz ~ 24 MHz
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7
6
5
4
3
2
1
0
CONFIG3
WDCON0
CWDTEN
-
-
CKF
OSCFS
-
FOSC1
FOSC0
7
6
5
4
3
2
1
0
WDTEN
WDCLR
WDTF
WIDPD
WDTRF
WPS2
WPS1
WPS0
Figure 25–4 CONFIG3 Reset Reloading
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N79E845/844/8432 Data Sheet
26 Instruction Sets
The N79E845/844/8432 executes all the instructions of the standard 8051 family. All instructions are coded within an 8-
bit field called an OPCODE. This single byte should be fetched from Program Memory. The OPCODE is decoded by the
CPU. It determines what action the microcontroller will take and whether more operation data is needed from memory. If
no other data is needed, then only one byte was required. Thus the instruction is called a one byte instruction. In some
cases, more data is needed, which will be two or three byte instructions.
Table 26–1 lists all instructions in details. The note of the instruction sets and addressing modes are shown below.
Rn (n = 0~7)
@Ri (i = 0, 1)
Register R0~R7 of the currently selected Register Bank.
Direct 8-bit internal data location’s address. This could be an internal data RAM lo-
cation (0~127) or a SFR (e.g. I/O port, control register, status register, etc.)
(128~255).
8-bit internal data RAM location (0~255) addressed indirectly through regis-
ter R0 or R1.
#data
8-bit constant included in the instruction.
16-bit constant included in the instruction.
#data16
addr16
16-bit destination address. Used by LCALL and LJMP. A branch can be any
within the 16 Kbytes Program Memory address space.
addr11
11-bit destination address. Used by ACALL and AJMP. The branch will be
within the same 2 Kbytes page of Program Memory as the first byte of the
following instruction.
rel
bit
Signed (2’s complement) 8-bit offset byte. Used by SJMP and all conditional
branches. The range is -128 to +127 bytes relative to first byte of the follow-
ing instruction.
Direct addressed bit in internal data RAM or SFR.
Table 26–1 Instruction Set for the N79E845/844/8432
N79E845/844/8432 vs.
Tradition 80C51 Speed
Ratio
Clock
Cycles
Instruction
OPCODE
Bytes
NOP
ADD
ADD
ADD
ADD
00
1
1
1
2
2
1
1
2
2
1
4
4
4
8
8
4
4
8
8
4
3.0
3.0
3.0
1.5
1.5
3.0
3.0
1.5
1.5
3.0
A, Rn
28~2F
26, 27
25
A, @Ri
A, direct
A, #data
24
ADDC A, Rn
ADDC A, @Ri
ADDC A, direct
ADDC A, #data
SUBB A, Rn
38~3F
36, 37
35
34
98~9F
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Table 26–1 Instruction Set for the N79E845/844/8432
N79E845/844/8432 vs.
Clock
Instruction
OPCODE
96, 97
Bytes
Tradition 80C51 Speed
Cycles
Ratio
SUBB A, @Ri
SUBB A, direct
SUBB A, #data
1
2
2
1
1
1
2
1
1
1
1
2
1
1
1
1
1
1
2
2
2
3
1
1
2
2
2
3
1
1
2
2
2
3
1
1
1
1
1
1
4
8
3.0
1.5
1.5
3.0
3.0
3.0
1.5
3.0
3.0
3.0
3.0
1.5
-
95
94
8
INC
A
04
4
INC
Rn
08~0F
06, 07
05
4
INC
@Ri
4
INC
direct
DPTR
A
8
INC
A3
8
DEC
DEC
DEC
DEC
DEC
MUL
DIV
14
4
Rn
18~1F
16, 17
15
4
@Ri
4
direct
DPTR
AB
8
A5
8
A4
20
20
4
2.4
2.4
3.0
3.0
3.0
1.5
1.5
1.5
2.0
3.0
3.0
1.5
1.5
1.5
2.0
3.0
3.0
1.5
1.5
1.5
2.0
3.0
3.0
3.0
3.0
3.0
3.0
AB
84
DA
A
D4
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A, Rn
A, @Ri
A, direct
A, #data
direct, A
direct, #data
A, Rn
A, @Ri
A, direct
A, #data
direct, A
direct, #data
A, Rn
A, @Ri
A, direct
A, #data
direct, A
direct, #data
A
58~5F
56, 57
55
4
4
8
54
8
52
8
53
12
4
48~4F
46, 47
45
4
8
44
8
42
8
43
12
4
68~6F
66, 67
65
4
8
64
8
62
8
63
12
4
E4
A
F4
4
A
23
4
RLC
RR
A
33
4
A
03
4
RRC
A
13
4
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Table 26–1 Instruction Set for the N79E845/844/8432
Instruction OPCODE
N79E845/844/8432 vs.
Clock
Bytes
Tradition 80C51 Speed
Cycles
Ratio
SWAP
A
C4
1
1
1
2
2
1
2
2
1
2
2
2
2
2
3
3
3
1
1
1
1
1
1
2
2
1
1
2
1
1
2
1
2
1
2
2
2
2
2
2
4
4
4
8
8
4
8
8
4
8
8
8
8
8
12
12
12
8
8
8
8
8
8
8
8
4
4
8
4
4
8
4
8
4
8
8
8
8
8
8
3.0
3.0
3.0
1.5
1.5
3.0
3.0
1.5
3.0
3.0
1.5
1.5
3.0
3.0
2.0
2.0
2.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
1.5
3.0
3.0
1.5
3.0
1.5
3.0
1.5
3.0
3.0
3.0
3.0
1.5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A, Rn
E8~EF
E6, E7
E5
A, @Ri
A, direct
A, #data
Rn, A
74
F8~FF
A8~AF
78~7F
F6, F7
A6, A7
76, 77
F5
Rn, direct
Rn, #data
@Ri, A
@Ri, direct
@Ri, #data
direct, A
direct, Rn
direct, @Ri
direct, direct
direct, #data
DPTR, #data16
88~8F
86, 87
85
75
90
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri[1]
MOVX A, @DPTR[1]
MOVX @Ri, A[1]
MOVX @DPTR, A[1]
PUSH direct
93
83
E2, E3
E0
F2, F3
F0
C0
POP
XCH
XCH
XCH
direct
D0
A, Rn
C8~CF
C6, C7
C5
A, @Ri
A, direct
XCHD A, @Ri
D6, D7
C3
CLR
CLR
SETB
C
bit
C
C2
D3
SETB bit
D2
CPL
CPL
ANL
ANL
ORL
ORL
MOV
C
B3
bit
B2
C, bit
C, /bit
C, bit
C, /bit
C, bit
82
B0
72
A0
A2
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Table 26–1 Instruction Set for the N79E845/844/8432
N79E845/844/8432 vs.
Clock
Instruction
OPCODE
Bytes
Tradition 80C51 Speed
Cycles
Ratio
MOV
bit, C
92
2
2
8
3.0
2.0
ACALL addr11
11, 31, 51, 71, 91,
B1, D1, F1[2]
12
LCALL addr16
RET
12
22
32
3
1
1
16
8
1.5
3.0
3.0
RETI
8
AJMP addr11
01, 21, 41, 61, 81,
A1, C1, E1
2
12
2.0
LJMP addr16
02
3
1
2
2
2
2
2
3
3
3
3
3
3
3
2
3
16
8
1.5
3.0
2.0
2.0
2.0
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
1.5
JMP
@A+DPTR
73
SJMP rel
80
12
12
12
12
12
16
16
16
16
16
16
16
12
16
JZ
rel
60
JNZ
JC
rel
70
rel
40
JNC
JB
rel
50
bit, rel
bit, rel
bit, rel
20
JNB
JBC
30
10
CJNE A, direct, rel
CJNE A, #data, rel
CJNE @Ri, #data, rel
CJNE Rn, #data, rel
DJNZ Rn, rel
B5
B4
B6, B7
B8~BF
D8~DF
D5
DJNZ direct, rel
[1] The most three significant bits in the 11-bit address [A10:A8] decide the ACALL hex code. The code will be
[A10,A9,A8,1,0,0,0,1].
[2] The most three significant bits in the 11-bit address [A10:A8] decide the AJMP hex code. The code will be
[A10,A9,A8,0,0,0,0,1].
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27 In-Circuit Program (ICP)
The ICP (In-Circuit-Program) mode is another approach to access the Flash EPROM. There are only 3 pins needed to per-
form the ICP function. One is input /RST pin, which should be fed to GND in the ICP working period. One is clock input,
shared with P1.7, which accepts serial clock from external device. Another is data I/O pin, shared with P1.6, that an exter-
nal ICP program tool shifts in/out data via P1.6 synchronized with clock(P1.7) to access the Flash EPROM of the
N79E845/844/8432.
Upon entry into ICP program mode, all pin will be set to quasi-bidirectional mode, and output to level “1”. The
N79E845/844/8432 supports programming of Flash EPROM (16K/8K/4K bytes APROM EPROM), Data Flash memory
(128 bytes per page) and LDROM. User has the option to program the APROM, Data Flash and LDROM.
Vcc
ICP Power
ICP Connector
Jumper
V
PP
*
*
*
*
RST
P1.7
App. device
App. device
Clock
V
DD
VDD
P1.6
Vss
Data
Vss
App. device
Switch
ICP
Writer Tool
System Board
N79E84x
*: Resistor is optional by application
Figure 27–1 ICP Connection with N79E84xA
Note:
1. When using ICP to upgrade code, the /RST, P1.6 and P1.7 should be taken within design system board.
2. After program finished by ICP, to suggest system power should power off and remove ICP connector then
power on.
3. It is recommended that user performs erase function and programming configure bits continuously without
any interruption.
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User may refer to the following website for ICP Program Tool. In item1, please select “Nuvoton ISP-ICP Programmer”.
1. http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx?tp_GUID=670aaf31-5d5c-45d3-8a9e-
040e148d55cf
Figure 27–2 Nuvoton ISP-ICP Programmer
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28 Electrical Characteristics
28.1 Absolute Maximum Ratings
Table 28–1 Absolute Maximum Ratings
Parameter
Rating
-40 to +85
Unit
°C
°C
V
Operating temperature under bias
Storage temperature range
Voltage on VDD pin to VSS
-55 to +150
-0.3 to +6.5
-0.3 to (VDD+0.3)
V
Voltage on any other pin to VSS
Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect de-
vice reliability.
28.2 DC Electrical Characteristics
Table 28–2 Operation Voltage
Parameter
Sym
Unit
MIN
4.5
TYP
MAX
5.5
Condition
Fosc = 4MHz ~ 24MHz
2.4
5.5
Fosc = 4MHz ~12MHz
Operating Voltage
VDD
V
V
3.0
2.4
5.5
5.5
Internal RC 22.1184MHz
Internal RC 11.0592MHz
VDD
3.0
5.5
Fosc = 4MHz ~ 24MHz
ISP Operating Voltage
Table 28–3 DC Characteristics
(VDD−VSS = 2.4~5.5V, TA = -40~85°C, unless otherwise specified.)
Sym
Parameter
Test Conditions
MIN
TYP
MAX
Unit
VDD Rise Rate to ensure
internal Power-on Reset signal
See section on Power-on
Reset for details
SVDD
0.05[7]
-
-
V/ms
Input Low Voltage
(general purpose I/O with TTL input)
VIL
2.4 < VDD < 5.5V
-0.5
0.2VDD-0.1
V
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Table 28–3 DC Characteristics
(VDD−VSS = 2.4~5.5V, TA = -40~85°C, unless otherwise specified.)
Sym
Parameter
Test Conditions
MIN
TYP
MAX
Unit
Input Low Voltage
(general purpose I/O with Schmitt
VIL1
2.4 < VDD < 5.5V
-0.5
0.3VDD
V
trigger
input)
Input Low Voltage
(/RST, XTAL1)
VIL2
2.4 < VDD < 5.5V
2.4 < VDD < 5.5V
-0.5
0.2VDD-0.1
VDD+0.5
V
V
Input High Voltage
(general purpose I/O with TTL input)
VIH
0.2VDD+0.9
Input High Voltage
(general purpose I/O with Schmitt
VIH1
2.4 < VDD < 5.5V
2.4 < VDD < 5.5V
0.7VDD
0.7VDD
VDD+0.5
V
trigger
input)
Input High Voltage
(/RST, XTAL1)
VIH2
VDD+0.5
0.45
V
V
V
V
V
V
V
V
V
V
V
I
DD=4.5V,
[4]
[4]
OL= 20mA[3]
,
,
Output Low Voltage
(general purpose I/O of P0,P3, all
modes except input only)
VDD=3.0V,
OL= 14mA[3]
VOL
VOL1
VOH
0.45
I
VDD=2.4V,
OL= 10mA[3], [4]
0.45
I
V
I
DD=4.5V,
0.45
[4]
[4]
OL= 38mA[3]
,
,
Output Low Voltage
(P10, P11, P14, P16, P17)
( All modes except input only)
VDD =3.0V,
OL= 27mA[3]
0.45
I
VDD =2.4V,
OL= 20mA[3], [4]
0.45
I
V
I
DD=4.5V
2.4
OH= -380μA[4]
Output High Voltage
(general purpose I/O, quasi bidirec-
tional)
VDD=3.0V
OH= -90μA[4]
2.4
2.0
I
VDD=2.4V
OH= -48μA[4]
I
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Table 28–3 DC Characteristics
(VDD−VSS = 2.4~5.5V, TA = -40~85°C, unless otherwise specified.)
Sym
Parameter
Test Conditions
MIN
TYP
MAX
Unit
V
I
DD=4.5V
2.4
2.4
2.0
V
OH= -28.0mA[3], [4]
Output High Voltage
(general purpose I/O, push-pull)
VDD=3.0V
VOH1
V
I
OH= -7mA[3], [4]
VDD=2.4V
OH= -3.5mA[3], [4]
V
I
Logical 0 Input Current
(general purpose I/O, quasi bi-
direction)
I IL
ITL
I LI
VDD=5.5V, VIN=0.4V
-40 at 5.5V
-50
-650
±10
μA
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
Logical 1 to 0 Transition Current
(general purpose I/O, quasi bi-
direction)
V
DD=5.5V, VIN=2.0V[2]
-550 at 5.5V
Input Leakage Current
(general purpose I/O, open-drain or
input only)
0 < VIN < VDD
<1
3.1
4.3
1.7
3.2
2.3
2.2
2.7
3.7
XTAL 12MHz, VDD=5.0V
XTAL 24MHz, VDD=5.5V
XTAL 12MHz, VDD=3.3V
XTAL 24MHz, VDD=3.3V
OP Current
I OP
(Active mode[5])
Internal
22.1184MHz,VDD=5V
Internal
22.1184MHz,VDD=3.3V
XTAL 12MHz, VDD=5.0V
XTAL 24MHz, VDD=5.5V
IIDLE
IDLE Current
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Table 28–3 DC Characteristics
(VDD−VSS = 2.4~5.5V, TA = -40~85°C, unless otherwise specified.)
Sym
Parameter
Test Conditions
MIN
TYP
MAX
Unit
XTAL 12MHz, VDD=3.3V
XTAL 24MHz, VDD=3.3V
1.3
2.3
1.6
1.6
<5
mA
mA
mA
mA
μA
Internal
22.1184MHz,VDD=5V
Internal
22.1184MHz,VDD=3.3V
Power-down mode
30
IPD
Power-down mode(BOD Enable)
100
μA
RST-pin Internal Pull-High
Resistor
RRST
2.4V < VDD < 5.5V
100
3.5
3.5
250
4.1
4.9
KΩ
V
BOD38 Detect Voltage
3.8
3.8
(Temp.=25℃)
BOD38 Detect Voltage
V
VBOD38
(Temp.=85℃)
BOD38 Detect Voltage
(Temp.=-40℃)
3.0
2.5
2.5
2.4
3.8
2.7
2.7
2.7
4.1
2.9
3.1
2.9
V
V
V
V
BOD27 Detect Voltage
(Temp.=25℃)
BOD27 Detect Voltage
VBOD27
(Temp.=85℃)
BOD27 Detect Voltage
(Temp.=-40℃)
[1] Typical values are not guaranteed. The values listed are tested at room temperature and based on a limited number of samples.
[2] Pins of ports 0,1,3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value
when VIN is approximately 2V.
[3] Under steady state (non-transient) conditions, IOL/IOH should be externally limited as follows:
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Maximum IOL/IOH of P0,P3 per port pin: 20 mA
Maximum IOL/IOH of P10, P11, P14, P16, P17: 38 mA
Maximum total IOL/IOH for all outputs: 100mA (Through VDD total current)
Maximum total IOL/IOH for all outputs: 150mA (Through VSS total current)
[4] If IOH exceeds the test condition, VOH will be lower than the listed specification.
If IOL exceeds the test condition, VOL will be higher than the listed specification.
[5] Tested while CPU is kept in reset state.
[6] general purpose I/O mean the general purpose I/O, such as P0, P1, P3.
[7] These parameters are characterized but not tested.
Other: P1.2 and P1.3 are open drain structure. They have not quasi or push pull modes.
28.3 AC Electrical Characteristics
28.3.1
10-bits SAR-ADC Specification
Table 28–4 Operation Voltage
Symbol
MIN
TYP
MAX
5.5
Unit
V
Operation voltage
Resolution
VDD
2.7
10
bit
[1]
Conversion time
Sampling rate
35tADC
us
150K
Hz
Integral Non-Linearity Error
Differential Non-Linearity
Gain error
INL
DNL
-1
-1
-1
-4
1
1
LSB
LSB
LSB
LSB
MHz
LSB
V
Ge
1
Offset error
Ofe
4
Clock frequency
Absolute error
ADCCLK
5.25
4
-4
1
Band-gap
VBG
1.3
1.6
[1] tADC The period time of ADC input clock
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N79E845/844/8432 Data Sheet
28.3.2 4 ~ 24 MHz XTAL Specifications
Parameter
Condition
MIN.
TYP.
MAX.
Unit
Input clock frequency
External crystal
4
24
MHz
Parameter
External crystal Frequency
Clock High Time
Clock Low Time
Symbol
1/tCLCL
tCHCX
MIN.
TYP.
MAX.
Units
MHz
nS
Notes
4
20.8
20.8
-
24
-
-
-
-
-
tCLCX
-
nS
Clock Rise Time
tCLCH
10
10
nS
Clock Fall Time
tCHCL
-
nS
tCLCL
tCLCH
tCLCX
tCHCL
tCHCX
Note: Duty cycle is 50%.
28.3.3
Internal RC Oscillator Specifications － 22.1184 MHz/11.0592 MHz
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
MHz
%
Center Frequency
22.1184/11.0592
+250C at VDD = 5V
-1
+1
+250C at VDD = 2.7~5.5V
-100C~+700C at VDD = 2.7~5.5V
-400C~+850C at VDD = 2.7~5.5V
-3
-5
-8
+3
+5
+8
%
%
%
Internal Oscillator Frequency
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N79E845/844/8432 Data Sheet
28.3.4 Internal RC Oscillator Specifications － 10 kHz
Parameter
Condition
MIN.
TYP.
MAX.
Unit
Center Frequency
VDD = 2.4V~5.5V
5
10
15
kHz
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N79E845/844/8432 Data Sheet
29 Application Circuit for EMC Immunity
The application circuit is shown below. The user is recommended follow the circuit enclosed by gray blocks to achieve
the most stable and reliable operation of MCU especially in a noisy power environment for a healthy EMC immunity. If
internal RC oscillator is used as the clock system, 0.1μF capacitor should be added to gain a precise RC frequency.
100Ω
33Ω
/RST
VDD
VDD
0.1μF
10μF
0.1μF
10μF
C1
C2
XTAL1
XTAL2
as close to MCU
as possible
Crystal
R
VSS
GND
as close to the
power source
as possible
Crystal Frequency
R
C1
C2
Depend on crystal
specifications
4MHz~24MHz
Without
Figure 29–1 Application Circuit for EFT Improvement
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N79E845/844/8432 Data Sheet
30 Package Dimensions
30.1 20-pin TSSOP - 4.4X6.5mm
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N79E845/844/8432 Data Sheet
30.2 16-pin SOP - 150 mil
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N79E845/844/8432 Data Sheet
31 Document Revision History
Revision
A1.0
Date
Description
-
Initial preliminary release
2011/10/05 Revised typos
A2.0
Removed the PDIP20 package
A2.1
A2.2
2011/11/03 Revised Table 12-3
Revised Figure 15-2
Revised Figure 29-1
2011/11/23
Revised Chapter 22.1
Revised the following operation voltage:
“VDD = 2.4V to 5.5V at FOSC = 4~12MHz or Internal RC 11.0592MHz”
2012/02/16 Revised CONFIG3[1:0]=10B as a reserved item
Revised operating and IDLE currents in Table 28–2
Revised Figure 24–1
A2.3
A2.4
Revised typos
Revised BOD27/38 of Table 28–2
Revised P16/P17 of Table 5–1
2012/05/11 Revised Figure 6-1
Removed the “N79E843A” part number
Revised Chapter 21.2
Revised Chapter 27
A2.5
A2.6
2012/06/26 Revised Chapter 2
Revised 20.2 ISP Command Table
Revised ADC Demo Code
2014/04/23
Revised SOP16 package
Removed SOP20 package
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunc-
tion or failure of which may cause loss of human life, bodily injury or severe property damage. Such
applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy
control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or
safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and
other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to
Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabili-
ties thus incurred by Nuvoton.
April 23 2014
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