N9H30F51IEC [NUVOTON]

ARM® ARM926EJ-STM Based 32-bit Microprocessor;
N9H30F51IEC
型号: N9H30F51IEC
厂家: NUVOTON    NUVOTON
描述:

ARM® ARM926EJ-STM Based 32-bit Microprocessor

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中文:  中文翻译
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N9H30  
ARM® ARM926EJ-STM Based  
32-bit Microprocessor  
N9H30 Series  
Datasheet  
The information described in this document is the exclusive intellectual property of  
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.  
Nuvoton is providing this document only for reference purposes of ARM926EJ-STM based system  
design. Nuvoton assumes no responsibility for errors or omissions.  
All data and specifications are subject to change without notice.  
For additional information or questions, please contact: Nuvoton Technology Corporation.  
www.nuvoton.com  
July 6, 2018  
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Table of Contents  
List of Figures .........................................................................................6  
1 GENERAL DESCRIPTION..................................................................8  
2 FEATURES.........................................................................................9  
1.1 Features............................................................................................ 9  
3 PARTS INFORMATION LIST AND PIN CONFIGURATION..............15  
3.1 N9H30 Series Part Number Naming Guide ..................................................15  
3.2 N9H30 Series Part Selection Guide...........................................................16  
3.3 Pin Configuration .................................................................................17  
3.3.1 N9H30KxxI Series Pin Diagram.....................................................................17  
3.3.2 N9H30FxxI Series Pin Diagram .....................................................................18  
4 Pin Description..................................................................................19  
5 BLOCK DIAGRAM ............................................................................36  
5.1 N9H30 Series Block Diagram ..................................................................36  
6 FUNCTIONAL DESCRIPTION ..........................................................37  
6.1 ARM® ARM926EJ-STM Processor Core.......................................................37  
6.1.1 Overview ................................................................................................37  
6.2 System Manager .................................................................................38  
6.2.1 Overview ................................................................................................38  
6.3 Clock Controller (CLK_CTL)....................................................................38  
6.3.1 Overview ................................................................................................38  
6.4 Advanced Interrupt Controller (AIC)...........................................................38  
6.4.1 Overview ................................................................................................38  
6.5 SDRAM Interface Controller (SDIC)...........................................................38  
6.5.1 Overview ................................................................................................38  
6.6 External Bus Interface (EBI)....................................................................39  
6.6.1 Overview ................................................................................................39  
6.7 General Purpose I/O (GPIO) ...................................................................39  
6.7.1 Overview ................................................................................................39  
6.8 General DMA Controller (GDMA)..............................................................39  
6.8.1 Overview ................................................................................................39  
6.9 Timer Controller (TMR)..........................................................................39  
6.9.1 Overview ................................................................................................39  
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6.10Enhance Timer Controller (ETMR) ............................................................39  
6.10.1 Overview ................................................................................................39  
6.11Pulse Width Modulation (PWM)................................................................40  
6.11.1 Overview ................................................................................................40  
6.12Watchdog Timer (WDT) .........................................................................40  
6.12.1 Overview ................................................................................................40  
6.13Windowed Watchdog Timer (WWDT).........................................................40  
6.13.1 Overview ................................................................................................40  
6.14Real Time Clock (RTC)..........................................................................40  
6.14.1 Overview ................................................................................................40  
6.15UART Interface Controller (UART) ............................................................41  
6.15.1 Overview ................................................................................................41  
6.16Smart Card Host Interface (SC)................................................................41  
6.16.1 Overview ................................................................................................41  
6.17I2C Synchronous Serial Interface Controller (I2C)...........................................41  
6.17.1 Overview ................................................................................................41  
6.18SPI Interface Controller (SPI) ..................................................................41  
6.18.1 Overview ................................................................................................41  
6.19I2S Controller (I2S)................................................................................41  
6.19.1 Overview ................................................................................................41  
6.20Ethernet MAC Controller (EMAC) .............................................................42  
6.20.1 Overview ................................................................................................42  
6.21USB 2.0 Device Controller (USBD)............................................................42  
6.21.1 Overview ................................................................................................42  
6.22USB Host Controller (USBH) ...................................................................42  
6.22.1 Overview ................................................................................................42  
6.23Controller Area Network (CAN) ................................................................43  
6.23.1 Overview ................................................................................................43  
6.24Flash Memory Interface (FMI)..................................................................43  
6.24.1 Overview ................................................................................................43  
6.25Secure Digital Host Controller (SDH) .........................................................43  
6.25.1 Overview ................................................................................................43  
6.262D Graphic Engine (GE2D).....................................................................43  
6.26.1 Overview ................................................................................................43  
6.27JPEG Codec (JPEG) ............................................................................44  
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6.27.1 Overview ................................................................................................44  
6.28LCD Display Interface Controller (LCM) ......................................................44  
6.28.1 Overview ................................................................................................44  
6.29Capture Sensor Interface Controller (CAP) ..................................................44  
6.29.1 Overview ................................................................................................44  
6.30Analog to Digital Converter (ADC).............................................................44  
6.30.1 Overview ................................................................................................44  
7 ELECTRICAL CHARACTERISTICS..................................................45  
7.1 Absolute Maximum Ratings.....................................................................45  
7.2 DC Electrical Characteristics ...................................................................46  
7.2.1 N9H30 Series DC Electrical Characteristics ......................................................46  
7.3 AC Electrical Characteristics ...................................................................49  
7.3.1 External 12 MHz High Speed Oscillator ...........................................................49  
7.3.2 Power-on Sequence & RESET......................................................................50  
7.3.3 External 12 MHz High Speed Crystal ..............................................................51  
7.3.4 External 32.768 kHz Low Speed Crystal...........................................................52  
7.3.5 EBI Timing ..............................................................................................53  
7.3.6 I2C Interface Timing ...................................................................................54  
7.3.7 SPI Interface Timing ..................................................................................55  
7.3.8 I2S Interface Timing ...................................................................................56  
7.3.9 Ethernet Interface Timing ............................................................................57  
7.3.10 NAND Interface Timing ...............................................................................59  
7.3.11 SD Interface Timing ...................................................................................60  
7.3.12 LCD Display Interface Timing........................................................................62  
7.3.13 Capture Sensor Interface Timing....................................................................63  
7.4 Analog Characteristics...........................................................................64  
7.4.1 12-bit SARADC ........................................................................................64  
7.4.2 Low Voltage Detection (LVD) and Low Voltage Reset (LVR) ..................................65  
7.4.3 3.3V Power-On Reset (POR33).....................................................................66  
7.4.4 1.2V Power-On Reset (POR12).....................................................................66  
7.4.5 USB 2.0 PHY...........................................................................................66  
7.5 Thermal Characteristics of N9H30 Package..............................................68  
7.5.1 Simulation Conditions.................................................................................68  
8 PACKAGE DIMENSIONS .................................................................69  
8.1 216L LQFP (24x24x1.4mm footprint 2.0mm) ................................................69  
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8.2 128L LQFP (14x14x1.4mm footprint) .........................................................70  
8.3 PCB Reflow Profile Suggestion ................................................................71  
8.3.1 Profile Setting Consideration ........................................................................71  
8.3.2 Profile Suggestion for N9H30 series ...............................................................72  
9 REVISION HISTORY ........................................................................73  
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LIST OF FIGURES  
Figure 3.1-2 N9H30 Series Part Number Naming Guide............................................................... 15  
Figure 3.3-1 N9H30KxxI Series LQFP 128-pin Pin Diagram......................................................... 17  
Figure 3.3-2 N9H30FxxI Series LQFP 216-pin Pin Diagram......................................................... 18  
Figure 5.1-1 N9H30 Series Block Diagram.................................................................................... 36  
Figure 7.3-1 External 12 MHz High Speed Oscillator Timing Diagram.......................................... 49  
Figure 7.3-1 Power on sequence................................................................................................... 50  
Figure 7.3-3 Typical HXT Crystal Application Circuit..................................................................... 51  
Figure 7.3-4 Typical LXT Crystal Application Circuit...................................................................... 52  
Figure 7.3-4 External Bus Interface Timing Diagram..................................................................... 53  
Figure 7.3-5 I2C Interface Timing Diagram .................................................................................... 54  
Figure 7.3-6 SPI Interface Timing Diagram ................................................................................... 55  
Figure 7.3-7 I2S Interface Timing Diagram..................................................................................... 56  
Figure 7.3-8 RMII Interface Timing Diagram.................................................................................. 57  
Figure 7.3-10 Ethernet PHY Management Interface Timing Diagram........................................... 58  
Figure 7.3-10 NAND Interface Timing Diagram............................................................................. 59  
Figure 7.3-11 SD Interface Default Mode Timing Diagram............................................................ 60  
Figure 7.3-12 SD Interface High-Speed Mode Timing Diagram.................................................... 61  
Figure 7.3-13 LCD Display Interface SYNC Type Timing Diagram............................................... 62  
Figure 7.3-14 Capture Sensor Interface Timing Diagram.............................................................. 63  
Figure 7.4-1 Thermal Performance of SLQFP under Forced Convection ..................................... 68  
Figure 7.4-1 Profile Setting Consideration ..................................................................................... 71  
Figure 8.3-2 Profile Suggestion for N9H30 series ......................................................................... 72  
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List of Tables  
Table 3.2-1 Selection Guide........................................................................................................... 16  
Table 3.2-1 Pin List Table .............................................................................................................. 35  
Table 7.1-1 Absolute Maximum Ratings ........................................................................................ 45  
Table 7.2-1 DC Electrical Characteristics ...................................................................................... 48  
Table 7.3-1 External 12 MHz High Speed Oscillator Electrical Characteristics............................. 49  
Table 7.3-1 EBI Timing .................................................................................................................. 53  
Table 7.3-1 I2C Interface Timing .................................................................................................... 54  
Table 7.3-1 SPI Interface Timing ................................................................................................... 55  
Table 7.3-1 I2S Interface Timing .................................................................................................... 56  
Table 7.3-1 RMII Interface Timing.................................................................................................. 57  
Table 7.3-7 Ethernet PHY Management Interface Timing............................................................. 58  
Table 7.3-7 NAND Interface Timing............................................................................................... 59  
Table 7.3-7 SD Interface Default Mode Timing.............................................................................. 60  
Table 7.3-7 SD Interface High-Speed Mode Timing...................................................................... 61  
Table 7.3-7 LCD Display Interface SYNC Type Timing................................................................. 62  
Table 7.3-12 Capture Sensor Interface Timing.............................................................................. 63  
Table 7.3-12 SAR ADC Characteristics......................................................................................... 64  
Table 7.3-12 LVD and LVR Characteristics................................................................................... 65  
Table 7.3-12 POR33 Characteristics ............................................................................................. 66  
Table 7.4-4 POR12 Characteristics ............................................................................................... 66  
Table 7.4-4 Low/Full-Speed DC Electrical Specifications.............................................................. 66  
Table 7.4-4 High-Speed DC Electrical Specifications.................................................................... 67  
Table 7.4-4 USB Low-Speed Driver AC Electrical Characteristics................................................ 67  
Table 7.4-4 USB Full-Speed Driver AC Electrical Characteristics................................................. 67  
Table 7.4-4 USB High-Speed Driver AC Electrical Characteristics ............................................... 67  
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1
GENERAL DESCRIPTION  
The N9H30 series targeted for general purpose 32-bit microcontroller embeds an outstanding  
CPU core ARM926EJ-S, runs up to 300 MHz, with 16 KB I-cache, 16 KB D-cache and MMU,  
56KB embedded SRAM and 16 KB IBR (Internal Boot ROM) for booting from USB, NAND and  
SPI FLASH.  
The N9H30 series integrates USB 2.0 HS HOST/Device controller with HS transceiver  
embedded, TFT type LCD controller, 2D graphics engine, I2S I/F controller, SD/MMC/NAND  
FLASH controller, GDMA and 8 channels 12-bit ADC controller with resistance touch screen  
functionality. It also integrates UART, SPI/MICROWIRE, I2C, LIN, PWM, Timer, WDT/Windowed-  
WDT, GPIO, Keypad, Smart Card I/F, 32.768 KHz XTL and RTC (Real Time Clock).  
Here, N9H30F51IEC and N9H30K41IEC support 10/100 Mb Ethernet MAC controllers and further  
support CAN BUS interface for connectivity.  
In addition, the N9H30 series integrates a DRAM I/F that runs up to 150MHz with supporting DDR  
or DDR2 type SDRAM. To reduce system complexity while cutting the BOM cost, the N9H30  
series provides MCP (Multi-Chip Package) to ensure higher performance and to minimize the  
system design efforts.  
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2
FEATURES  
1.1 Features  
Core  
ARM® ARM926EJ-Sprocessor core runs up to 300 MHz  
Support 16 KB instruction cache and 16 KB data cache  
Support MMU  
Support JTAG Debug interface  
DDR SDRAM Controller  
Support LVDDR and DDR2 SDRAM  
Clock speed up to 150 MHz  
Support 16-bit data bus width  
Memory size depended on embedded SDRAM configuration by different part number.  
Embedded SRAM and ROM  
Support 56K bytes embedded SRAM  
Support 16K bytes Internal Boot ROM (IBR)  
Support up to four booting modes  
Boot from USB  
Boot from eMMC  
Boot from NAND Flash  
Boot from SPI Flash  
Clock Control  
Support two PLLs, up to 500 MHz, for high performance system operation  
External 12 MHz high speed crystal input for precise timing operation  
External 32.768 kHz low speed crystal input for RTC function and low speed clock  
source  
Ethernet MAC Controller  
Support up to 2 Ethernet MAC controllers  
Support IEEE Std. 802.3 CSMA/CD protocol  
Support packet time stamping for IEEE Std. 1588 protocol  
Support 10 and 100 Mbps operations  
Support Half- and Full-duplex operations  
Support RMII interface to Ethernet physical layer PHY  
Support Ethernet physical layer PHY management through MDC and MDIO interface  
Support flow control in Full-duplex mode to receive, recognize and transmit PAUSE  
frame  
Support CAM-like function to recognize 48-bit Ethernet MAC address  
Support Wake-On-LAN by detecting Magic Packet  
Support 256 bytes transmit FIFO and 256 bytes receive FIFO  
Support DMA function  
Support internal loop back mode for diagnostic  
USB 2.0 Controller  
Support USB Revision 2.0 specification  
Support one set of USB 2.0 High-Speed (HS) Device/Host with embedded transceiver  
Support one set of USB 2.0 High-Speed (HS) Host with embedded transceiver  
Support Control, Bulk, Interrupt, Isochronous and Split transfers  
Support USB host function compliant to Enhanced Host Controller Interface (EHCI) 1.0  
specification to connect with USB 2.0 High-Speed (HS) device.  
Support USB host function compliant to Open Host Controller Interface (OHCI) 1.0  
specification to connect with USB 1.1 Full-Speed (FS) and Low-Speed (LS) devices  
Support USB High-Speed (HS) and Full-Speed (FS) device function  
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Support USB device function with 1 endpoint for Control IN/OUT transfers and 12  
programmable endpoints for Bulk, Interrupt and Isochronous IN/OUT transfers  
Support suspend, resume and remote wake-up capability  
Support DMA function  
Support 2048 Bytes internal SRAM for USB host function and 4096 Bytes internal  
SRAM for USB device function  
Flash Memory Interface  
Support NAND flash interface  
Support 8-bit data bus width  
Support SLC and MLC type NAND flash device  
Support 512 B, 2 KB, 4 KB and 8 KB page size NAND flash device  
Support ECC4, ECC8, ECC12, ECC15 and ECC24 BCH algorithm for ECC code  
generation, error detection and error correction.  
Support eMMC flash interface  
Support DMA function to accelerate the data transfer between system memory and  
NAND and eMMC flash.  
I2S Controller  
Support I2S interface  
Support both mono and stereo  
Support both record and playback  
Support 8-bit, 16-bit 20-bit and 24-bit data precision  
Support master and slave mode  
Support PCM interface  
Support 2 slots mode to connect 2 device  
Support 8-bit, 16-bit 20-bit and 24-bit data precision  
Support master mode  
Support four 8x24 (8 24-bit) buffer for left/right channel record and left/right playback  
Support DMA function to accelerate the data transfer between system memory and  
internal buffer  
Support 2 buffer address for left/right channel and 2 slots data transfer  
LCD Display Controller  
Support 8/9/16/18/24-bit data with to connect with 80/68 series MPU type LCD module  
Support resolution up to 1024x768  
Support data format conversion from RGB444, RGB565, RGB666, RGB888, YUV422  
and YUV444 to RGB444, RGB565, RGB666, RGB888, YUV422 and YUV444 for  
display output  
Support CCIR-656 (with VSYNC, HSYNC and data enable sync signal) 8/16-bit YUV  
data output to connect with external TV encoder  
Support 8/16 bpp OSD data with video overlay function to facilitate the diverse graphic  
UI  
Support linear 1X to 8X image scaling up function  
Support Picture-In-Picture display function  
Support hardware cursor  
2D Graphic Engine  
Support 2D Bit Block Transfer (BitBLT) functions defined in Microsoft GDI  
Support Host BLT  
Support Pattern BLT  
Support Color/Font Expanding BLT  
Support Transparent BLT  
Support Tile BLT  
Support Block Move BLT  
Support Copy File BLT  
Support Color/Font Expansion  
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Support Rectangle Fill  
Support RGB332/RGB565/RGB888 data format.  
Support fore/background colors and all Microsoft 256 ternary raster-operation codes  
(ROP)  
Support both inside and outside clipping function  
Support alpha-blending for source/destination picture overlaying  
Support fast Bresenham line drawing algorithm to draw solid/textured line  
Support rectangular border and frame drawing  
Support picture re-sizing  
Support down-scaling from 1/255 to 254/255  
Support up-scaling from 1 to 1.996 (1+254/255)  
Support object rotation with different degree  
Support L45 (45 degree left rotation) and L90 (90 degree left rotation)  
Support R45 (45 degree right rotation) and R90 (90 degree right rotation)  
Support M180 (mirror/flop)  
Support F180 (up-side-down (flip) and X180 (180 degree rotation)  
JPEG Codec  
Support Baseline Sequential mode JPEG codec function compliant with ISO/IEC  
10918-1 international JPEG standard  
Planar Format  
Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y only) format image  
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and gray-level (Y only)  
format image  
Support to decode YCbCr 4:2:2 transpose format  
Support arbitrary width and height image encode and decode  
Support three programmable quantization-tables  
Support standard default Huffman-table and programmable Huffman-table for decode  
Support arbitrarily 1X~8X image up-scaling function for encode mode  
Support down-scaling function for encode and decode modes  
Support specified window decode mode  
Support quantization-table adjustment for bit-rate and quality control in encode mode  
Support rotate function in encode mode  
Packet Format  
Support to encode interleaved YUYV format input image, output bit stream 4:2:2 and  
4:2:0 format  
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0 format image  
Support decoded output image RGB555, RGB565 and RGB888 formats.  
The encoded JPEG bit-stream format is fully compatible with JFIF and EXIF standards  
Support arbitrary width and height image encode and decode  
Support three programmable quantization-tables  
Support standard default Huffman-table and programmable Huffman-table for decode  
Support arbitrarily 1X~8X image up-scaling function for encode mode  
Support down-scaling function 1X~ 16X for Y422 and Y420, 1X~ 8X for Y444 for  
decode mode  
Support specified window decode mode  
Support quantization-table adjustment for bit-rate and quality control in encode mode  
GDMA (General DMA)  
Support 2 channels GDMA for memory-to-memory data transfer without CPU  
intervention  
Support increment and decrement for source and destination address calculation  
Support 8-bit, 16-bit and 32-bit width data transfer  
Support four 8-bit/16-bit/32-bit burst transfer  
UART  
Support up to 11 UART controllers  
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Support 1 UART (UART 1) port with full model function (TXD, RXD, CTS, RTS, CDn,  
RIn, DTR and DSR) and 64-byte FIFO  
Support 5 UART (UART 2/4/6/8/10) ports with flow control (TXD, RXD, CTS and RTS)  
and 64-byte FIFO  
Support 5 TXD/RXD only UART ports (UART 0/3/5/7/9) with 16-byte FIFO for standard  
device  
Support IrDA (SIR) and LIN function  
Support RS-485 9-bit mode and direction control  
Support programmable baud-rate generator up to 1/16 system clock  
C-CAN  
Supports CAN protocol version 2.0 part A and B  
Bit rates up to 1M bit/s  
32 Message Objects  
Each Message Object has its own identifier mask  
Programmable FIFO mode (concatenation of Message Object)  
Maskable interrupt  
Disabled Automatic Re-transmission mode for Time Triggered CAN applications  
Support power down wake-up function  
Smart Card Host (SC)  
Compliant to ISO-7816-3 T=0, T=1  
Supports up to two ISO-7816-3 ports  
Separate receive / transmit 4 bytes entry FIFO for data payloads  
Programmable transmission clock frequency  
Programmable receiver buffer trigger level  
Programmable guard time selection (11 ETU ~ 266 ETU)  
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting  
times processing  
Supports auto inverse convention function  
Supports transmitter and receiver error retry and error limit function  
Supports hardware activation sequence process  
Supports hardware warm reset sequence process  
Supports hardware deactivation sequence process  
Supports hardware auto deactivation sequence when detecting the card removal  
Timer  
Support 5 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter  
Independent clock source for each timer  
Support one-shot, periodic, toggle and continuous operation modes  
Enhanced Timer  
Support 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter  
Independent clock source for each timer  
Support one-shot, periodic, toggle and continuous operation modes  
Supports external pin capture for interval measurement  
Supports external pin capture for timer counter reset  
Watchdog Timer  
Multiple clock sources  
8 selectable time out period from 1.333us ~ 14.316sec (depends on clock source)  
WDT can wake-up from power down or idle mode  
Interrupt or reset selectable on watchdog timer time-out  
Windowed-Watchdog Timer  
6-bit down counter with 11-bit pre-scale for wide range window selected  
Interrupt on windowed-watchdog timer time-out  
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Reset on windowed-watchdog timer time out or reload in an unexpected time window  
Real Time Clock (RTC)  
Supports software compensation by setting frequency compensate register (FCR)  
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)  
Supports Alarm registers (second, minute, hour, day, month, year)  
Selectable 12-hour or 24-hour mode  
Automatic leap year recognition  
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,  
1/4, 1/2 and 1 second  
Supports battery power pin (VBAT)  
PWM  
Built-in up to two 16-bit PWM generators provide four PWM outputs  
Each PWM generator equipped with one clock source selector, one clock divider, one  
8-bit pre-scale, two 16-bit counters, and one Dead-Zone generator  
SPI  
Built-in up to two sets of SPI controller  
Support SPI master mode  
Support single/dual/quad bit data bus width  
Full duplex synchronous serial data transfer  
Variable length of transfer data from 8 to 32 bits  
MSB or LSB first data transfer  
Support burst mode operation that transmission and reception can be executed up to  
four times in a transfer  
I2C  
Up to two sets of I2C device  
Support master mode  
Bidirectional data transfer between masters and slaves  
Multi-master bus (no central master)  
Arbitration between simultaneously transmitting masters without corruption of serial  
data on the bus  
Serial clock synchronization allows devices with different bit rates to communicate via  
one serial bus  
Serial clock synchronization can be used as a handshake mechanism to suspend and  
resume serial transfer  
Programmable clocks allow versatile rate control  
Support software mode to generate I2C signaling  
Advanced Interrupt Controller  
Support 58 interrupt sources, including 8 external interrupt sources  
Support programmable normal or fast interrupt mode (IRQ, FIQ)  
Support programmable edge-triggered or level-sensitive for 8 external interrupt  
sources  
Support programmable low-active or high-active for 8 external interrupt sources  
Support encoded priority methodology to allow for interrupt daisy-chaining  
Support lower priority interrupt automatically mask out for nested interrupt  
Support to clear interrupt flag automatically if interrupt source is programmed as edge-  
triggered  
GPIO  
TTL/Schmitt trigger input selectable  
I/O pin can be configured as interrupt source with edge/level setting  
Support pull-up and pull-down control  
ADC  
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12-bit SAR ADC with 800K/160K SPS  
Up to 5-ch single-end input  
Support up to 800K SPS in channel 1 and up to 160K SPS in others channels.  
Support 4-wire or 5-wire resistance touch screen interface  
Support touch pressure measurement for 4-wire touch screen application  
Support pen down detection  
Low Voltage Detect (LVD) and Low Voltage Reset (LVR)  
Support two, 2.6V and 2.8V, voltage detection levels  
Interrupt when low voltage detected  
Reset when low voltage detected  
Low voltage reset threshold voltage levels: 2.4 V  
Power Management  
Advanced power management including Power Down, Deep Standby, CPU Standby  
and Normal Operating modes  
Normal Operating mode  
CPU run normally and all clocks on, the current consumption of CORE_VDD is  
around 185 mA (at CPU/DRAM clock is 300/150 MHz CPU).  
CPU Standby mode  
CPU clock stop, and all other clocks on.  
Deep Standby mode  
All clocks stop, except LXT, with SRAM retention, and the current consumption  
of CORE_VDD is typicaly 3 mA  
Power Down mode  
All powers are off except RTC_VDD (3.3V) and the current consumption of  
RTC_VDD is typicaly 7uA with RTC functionality on.  
Operating Voltage  
1.2V for core logic operating  
1.8V for DDR or DDR2 SDRAM I/O operating  
3.3V for normal I/O operating  
Operating Temperature: -40~85℃  
Packages:  
All Green package (RoHS)  
LQFP 216-pin  
LQFP 128-pin  
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3
PARTS INFORMATION LIST AND PIN CONFIGURATION  
3.1 N9H30 Series Part Number Naming Guide  
Figure 3.1-1 N9H30 Series Part Number Naming Guide  
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3.2 N9H30 Series Part Selection Guide  
Memory  
I/F  
Storage  
USB  
Timer  
Analog  
ADC  
MAC  
GFX LCD  
Peripheral  
Part No.  
N9H30F51IEC  
N9H30F51I  
32  
1
1
1
1
24  
2
2
2
2
2
-
2
1
1
1
1
24-bit  
24-bit  
16-bit  
16-bit  
5
5
5
5
4
4
1
1
4
4
4
4
8
8
5
5
200K*  
200K*  
200K*  
200K*  
-
146 11  
146 11  
2
-
2
2
2
2
2
2
2
2
2
2
2
2
-
-
-
-
-
-
-
-
1
1
1
1
LQFP216  
LQFP216  
LQFP128  
LQFP128  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
32  
16  
16  
24  
24  
24  
2
2
2
N9H30K41IEC  
N9H30K41I  
1
-
86  
86  
9
9
1
-
-
Table 3.2-1 Selection Guide  
July 6, 2018  
Page 16 of 74  
Rev 1.1  
N9H30  
3.3 Pin Configuration  
3.3.1 N9H30KxxI Series Pin Diagram  
Figure 3.3-1 N9H30KxxI Series LQFP 128-pin Pin Diagram  
July 6, 2018  
Page 17 of 74  
Rev 1.1  
N9H30  
3.3.2 N9H30FxxI Series Pin Diagram  
Figure 3.3-2 N9H30FxxI Series LQFP 216-pin Pin Diagram  
July 6, 2018  
Page 18 of 74  
Rev 1.1  
N9H30  
4
PIN DESCRIPTION  
4.1.1.1 N9H30 Pin List  
N9H30F51I(EC) N9H30K41I(EC) Pin Name  
Pin Type Description  
PG.3  
I/O  
I/O  
I/O  
O
General purpose digital I/O pin Port G Pin 3.  
1
2
3
4
-
-
I2C1_SDA  
PG.2  
I2C1 data input/output pin.  
General purpose digital I/O pin Port G Pin 2.  
I2C1 clock pin.  
I2C1_SCL  
PG.1  
I/O  
I/O  
I/O  
O
General purpose digital I/O pin Port G Pin 1.  
I2C0 data input/output pin.  
2
3
I2C0_SDA  
PG.0  
General purpose digital I/O pin Port G Pin 0.  
I2C0 clock pin.  
I2C0_SCL  
PG.14  
I/O  
O
General purpose digital I/O pin Port G Pin 14.  
I2S left right channel clock.  
I2S_LRCK  
UART6_CTS  
SC0_CD  
CLK_OUT  
PG.13  
5
4
I
Clear to send input pin for UART6.  
SmartCard0 card detect pin.  
Reference Clock Output.  
I
O
I/O  
I
General purpose digital I/O pin Port G Pin 13.  
I2S bit clock pin.  
I2S_BCLK  
UART6_RTS  
SC0_PWR  
PG.12  
6
7
5
6
O
Request to send output pin for UART6.  
SmartCard0 power pin.  
O
I/O  
I
General purpose digital I/O pin Port G Pin 12.  
I2S data input.  
I2S_DI  
UART6_RXD  
SC0_DAT  
PG.11  
I
Data receiver input pin for UART6.  
SmartCard0 data pin.  
I/O  
I/O  
O
General purpose digital I/O pin Port G Pin 11.  
I2S data output.  
I2S_DO  
8
9
7
8
UART6_TXD  
SC0_CLK  
PG.10  
O
Data transmitter output pin for UART6.  
SmartCard0 clock pin.  
O
I/O  
O
General purpose digital I/O pin Port G Pin 10.  
I2S master clock output pin.  
SmartCard0 reset pin.  
I2S_MCLK  
SC0_RST  
IO_VDD  
O
10  
11  
12  
13  
9
-
P
MCU I/O power pin.  
CORE_VSS  
CORE_VDD  
DDR_VSS  
P
MCU internal core ground pin.  
MCU internal core power pin.  
DDR ground pin.  
10  
-
P
P
July 6, 2018  
Page 19 of 74  
Rev 1.1  
N9H30  
14  
15  
16  
17  
18  
19  
20  
21  
11  
-
DDR_VDD  
DDR_VSS  
DDR_VDD  
DDR_VSS  
DDR_VDD  
CORE_VSS  
IO_VDD  
P
P
DDR power pin.  
DDR ground pin.  
11  
-
P
DDR power pin.  
P
DDR ground pin.  
12  
-
P
DDR power pin.  
P
MCU internal core ground pin.  
MCU I/O power pin.  
-
P
13  
CORE_VDD  
PF.14  
P
MCU internal core power pin.  
General purpose digital I/O pin Port F Pin 14.  
Clear to send input pin for UART2.  
Enhanced TIMER capture input pin.  
External interrupt 3 input pin.  
I/O  
I
UART2_CTS  
TM3_CAP  
INT3  
22  
23  
24  
25  
-
-
-
-
I
I
PF.13  
I/O  
O
O
I
General purpose digital I/O pin Port F Pin 13.  
Request to send output pin for UART2.  
Enhanced TIMER toggle output pin.  
External interrupt 2 input pin.  
UART2_RTS  
TM3_TGL  
INT2  
PF.12  
I/O  
I
General purpose digital I/O pin Port F Pin 12.  
Data receiver input pin for UART2.  
Enhanced TIMER capture input pin.  
External interrupt 1 input pin.  
UART2_RXD  
TM2_CAP  
INT1  
I
I
PF.11  
I/O  
O
O
I
General purpose digital I/O pin Port F Pin 11.  
Data transmitter output pin for UART2.  
Enhanced TIMER toggle output pin.  
External interrupt 0 input pin.  
UART2_TXD  
TM2_TGL  
INT0  
PG.9  
I/O  
O
I/O  
O
I/O  
O
I/O  
O
I/O  
O
I
General purpose digital I/O pin Port G Pin 9.  
Data enable or display control signal.  
General purpose digital I/O pin Port G Pin 8.  
Vertical sync or frame sync.  
26  
27  
28  
29  
14  
15  
16  
17  
LCD_DEN  
PG.8  
LCD_VSYNC  
PG.7  
General purpose digital I/O pin Port G Pin 7.  
Horizontal sync or line sync.  
LCD_HSYNC  
PG.6  
General purpose digital I/O pin Port G Pin 6.  
Pixel clock output.  
LCD_CLK  
PD.15  
General purpose digital I/O pin Port D Pin 15.  
LCD pixel data output bit 23.  
LCD_DATA23  
UART9_RXD  
PWM3  
30  
-
Data receiver input pin for UART9.  
PWM3 output pin.  
O
I
EBI_nWAIT  
External I/O wait control.  
July 6, 2018  
Page 20 of 74  
Rev 1.1  
N9H30  
PD.14  
I/O  
O
General purpose digital I/O pin Port D Pin 14.  
LCD pixel data output bit 22.  
LCD_DATA22  
UART9_TXD  
PWM2  
31  
32  
33  
34  
-
-
-
-
O
Data transmitter output pin for UART9.  
PWM2 output pin.  
O
EBI_nOE  
PD.13  
O
External I/O output enable.  
I/O  
O
General purpose digital I/O pin Port D Pin 13.  
LCD pixel data output bit 21.  
LCD_DATA21  
PWM1  
O
PWM1 output pin.  
EBI_nWE  
PD.12  
O
External I/O chip write enable.  
General purpose digital I/O pin Port D Pin 12.  
LCD pixel data output bit 20.  
I/O  
O
LCD_DATA20  
UART9_RXD  
PWM0  
I
Data receiver input pin for UART9.  
PWM0 output pin.  
O
EBI_nCS4  
PD.11  
O
External I/O chip select bank 4.  
General purpose digital I/O pin Port D Pin 11.  
LCD pixel data output bit 19.  
I/O  
O
LCD_DATA19  
UART9_TXD  
EBI_nCS3  
PD.10  
O
Data transmitter output pin for UART9.  
External I/O chip select bank 3.  
General purpose digital I/O pin Port D Pin 10.  
LCD pixel data output bit 18.  
O
I/O  
O
35  
36  
37  
38  
39  
40  
-
-
LCD_DATA18  
EBI_nCS2  
PD.9  
O
External I/O chip select bank 2.  
General purpose digital I/O pin Port D Pin 9.  
LCD pixel data output bit 17.  
I/O  
O
LCD_DATA17  
EBI_nCS1  
PD.8  
O
External I/O chip select bank 1.  
General purpose digital I/O pin Port D Pin 8.  
LCD pixel data output bit 16.  
I/O  
O
-
LCD_DATA16  
EBI_nCS0  
PA.15  
O
External I/O chip select bank 0.  
General purpose digital I/O pin Port A Pin 15.  
LCD pixel data output bit 15.  
I/O  
O
18  
19  
LCD_DATA15  
PWM3  
O
PWM3 output pin.  
PA.14  
I/O  
O
General purpose digital I/O pin Port A Pin 14.  
LCD pixel data output bit 14.  
LCD_DATA14  
PWM2  
O
PWM2 output pin.  
PA.13  
I/O  
O
General purpose digital I/O pin Port A Pin 13.  
LCD pixel data output bit 13.  
20  
21  
LCD_DATA13  
PWM1  
O
PWM1 output pin.  
41  
PA.12  
I/O  
General purpose digital I/O pin Port A Pin 12.  
July 6, 2018  
Page 21 of 74  
Rev 1.1  
N9H30  
LCD_DATA12  
PWM0  
O
O
LCD pixel data output bit 12.  
PWM0 output pin.  
PA.11  
I/O  
O
General purpose digital I/O pin Port A Pin 11.  
LCD pixel data output bit 11.  
General purpose digital I/O pin Port A Pin 10.  
LCD pixel data output bit 10.  
MCU I/O power pin.  
42  
22  
LCD_DATA11  
PA.10  
I/O  
O
43  
44  
23  
24  
LCD_DATA10  
IO_VDD  
P
PA.9  
I/O  
O
General purpose digital I/O pin Port A Pin 9.  
LCD pixel data output bit 9.  
45  
46  
47  
48  
49  
50  
51  
52  
53  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
LCD_DATA9  
PWRON_SET9  
PA.8  
IU  
I/O  
O
Power On Setting bit 9.  
General purpose digital I/O pin Port A Pin 8.  
LCD pixel data output bit 8.  
LCD_DATA8  
PWRON_SET8  
PA.7  
IU  
I/O  
O
Power On Setting bit 8.  
General purpose digital I/O pin Port A Pin 7.  
LCD pixel data output bit 7.  
LCD_DATA7  
PWRON_SET7  
PA.6  
IU  
I/O  
O
Power On Setting bit 7.  
General purpose digital I/O pin Port A Pin 6.  
LCD pixel data output bit 6.  
LCD_DATA6  
PWRON_SET6  
PA.5  
IU  
I/O  
O
Power On Setting bit 6.  
General purpose digital I/O pin Port A Pin 5.  
LCD pixel data output bit 5.  
LCD_DATA5  
PWRON_SET5  
PA.4  
IU  
I/O  
O
Power On Setting bit 5.  
General purpose digital I/O pin Port A Pin 4.  
LCD pixel data output bit 4.  
LCD_DATA4  
PWRON_SET4  
PA.3  
IU  
I/O  
O
Power On Setting bit 4.  
General purpose digital I/O pin Port A Pin 3.  
LCD pixel data output bit 3.  
LCD_DATA3  
PWRON_SET3  
PA.2  
IU  
I/O  
O
Power On Setting bit 3.  
General purpose digital I/O pin Port A Pin 2.  
LCD pixel data output bit 2.  
LCD_DATA2  
PWRON_SET2  
PA.1  
IU  
I/O  
O
Power On Setting bit 2.  
General purpose digital I/O pin Port A Pin 1.  
LCD pixel data output bit 1.  
LCD_DATA1  
PWRON_SET1  
PA.0  
IU  
I/O  
O
Power On Setting bit 1.  
General purpose digital I/O pin Port A Pin 0.  
LCD pixel data output bit 0.  
54  
LCD_DATA0  
PWRON_SET0  
IU  
Power On Setting bit 0.  
July 6, 2018  
Page 22 of 74  
Rev 1.1  
N9H30  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
-
ADC0  
ADC6  
ADC4  
AVSS  
AVDD  
ADC7  
ADC5  
ADC1  
ADC3  
ADC2  
VREF  
RTC_VDD  
AI  
AI  
AI  
AP  
AP  
AI  
AI  
AI  
AI  
AI  
AI  
P
ADC input channel 0 or VBAT.  
ADC input channel 6 or XM.  
ADC input channel 4 or YM.  
Ground pin for analog circuit.  
Power supply for internal analog circuit.  
ADC input channel 7 or XP.  
ADC input channel 5 or YP.  
ADC input channel 1.  
35  
36  
37  
38  
39  
40  
-
41  
-
ADC input channel 3 or VSENSE.  
ADC input channel 2.  
-
ADC voltage reference pin.  
RTC power input. (*. or 3.3V )  
42  
RTC wake-up output pin for external DC/DC enable pin  
control.  
67  
-
SYS_PWREN  
O
68  
69  
70  
-
SYS_nWAKEUP  
X32_IN  
IU  
AI  
AO  
I/O  
O
O
I
RTC wake-up interrupt input with internal pull-high.  
External 32.768kHz crystal input.  
External 32.768kHz crystal output.  
General purpose digital I/O pin Port H Pin 4.  
Data transmitter output pin for UART1.  
External I/O address bus bit 0.  
43  
44  
X32_OUT  
PH.4  
UART1_TXD  
EBI_ADDR0  
INT4  
71  
72  
-
-
External interrupt 4 input pin.  
PH.5  
I/O  
I
General purpose digital I/O pin Port H Pin 5.  
Data receiver input pin for UART1.  
External I/O address bus bit 1.  
UART1_RXD  
EBI_ADDR1  
INT5  
O
I
External interrupt 5 input pin.  
PH.6  
I/O  
O
O
O
I
General purpose digital I/O pin Port H Pin 6.  
SD/SDIO Port 1 command/response.  
Request to send output pin for UART1.  
External I/O address bus bit 2.  
SD1_CMD  
UART1_RTS  
EBI_ADDR2  
INT6  
73  
-
External interrupt 6 input pin.  
PH.7  
I/O  
O
I
General purpose digital I/O pin Port H Pin 7.  
SD/SDIO Port 1 clock.  
SD1_CLK  
UART1_CTS  
EBI_ADDR3  
INT7  
74  
-
-
Clear to send input pin for UART1.  
External I/O address bus bit 3.  
O
I
External interrupt 7 input pin.  
PH.8  
I/O  
I/O  
O
General purpose digital I/O pin Port H Pin 8.  
SD/SDIO mode #1 data line bit 0.  
Data transmitter output pin for UART4.  
75  
SD1_DAT0  
UART4_TXD  
July 6, 2018  
Page 23 of 74  
Rev 1.1  
N9H30  
EBI_ADDR4  
PH.9  
O
I/O  
I/O  
I
External I/O address bus bit 4.  
General purpose digital I/O pin Port H Pin 9.  
SD/SDIO mode #1 data line bit 1.  
Data receiver input pin for UART4.  
External I/O address bus bit 5.  
SD1_DAT1  
UART4_RXD  
EBI_ADDR5  
PH.10  
76  
77  
78  
-
-
-
O
I/O  
I/O  
O
General purpose digital I/O pin Port H Pin 10.  
SD/SDIO mode #1 data line bit 2.  
Request to send output pin for UART4.  
External I/O address bus bit 6.  
SD1_DAT2  
UART4_RTS  
EBI_ADDR6  
PH.11  
O
I/O  
I/O  
I
General purpose digital I/O pin Port H Pin 11.  
SD/SDIO mode #1 data line bit 3.  
Clear to send input pin for UART4.  
External I/O address bus bit 7.  
SD1_DAT3  
UART4_CTS  
EBI_ADDR7  
PH.12  
O
I/O  
I
General purpose digital I/O pin Port H Pin 12.  
SD/SDIO mode #1 card detect.  
Data transmitter output pin for UART8.  
2nd SPI0 chip select pin.  
SD1_nCD  
UART8_TXD  
SPI0_SS1  
EBI_ADDR8  
IO_VDD  
79  
-
O
O
O
External I/O address bus bit 8.  
80  
81  
82  
-
-
P
MCU I/O power pin.  
CORE_VSS  
CORE_VDD  
PH.13  
P
MCU internal core ground pin.  
45  
P
MCU internal core power pin.  
I/O  
O
General purpose digital I/O pin Port H Pin 13.  
SD/SDIO mode #1 power enable.  
Data receiver input pin for UART8.  
2nd SPI1 chip select pin.  
SD1_nPWR  
UART8_RXD  
SPI1_SS1  
EBI_ADDR9  
PH.14  
83  
-
I
O
O
External I/O address bus bit 9.  
I/O  
O
General purpose digital I/O pin Port H Pin 14.  
Request to send output pin for UART8.  
CAN bus receiver1 input.  
UART8_RTS  
CAN1_RXD  
EBI_nBE0  
PH.15  
84  
85  
-
-
I
O
External I/O low byte enable.  
I/O  
I
General purpose digital I/O pin Port H Pin 15.  
Clear to send input pin for UART8.  
CAN bus transmitter1 output.  
UART8_CTS  
CAN1_TXD  
EBI_nBE1  
PI.0  
O
O
External I/O high byte enable.  
I/O  
I/O  
I/O  
General purpose digital I/O pin Port I Pin 0.  
External I/O data bus bit 0.  
86  
87  
-
EBI_DATA0  
PI.1  
46  
General purpose digital I/O pin Port I Pin 1.  
July 6, 2018  
Page 24 of 74  
Rev 1.1  
N9H30  
NAND_nCS0  
UART7_TXD  
EBI_DATA1  
INT6  
O
O
NAND flash chip select 0.  
Data transmitter output pin for UART7.  
External I/O data bus bit 1.  
I/O  
I
External interrupt 6 input pin.  
General purpose digital I/O pin Port I Pin 2.  
NAND flash srite protect.  
PI.2  
I/O  
O
NAND_nWP  
UART7_RXD  
EBI_DATA2  
INT7  
88  
47  
I
Data receiver input pin for UART7.  
External I/O data bus bit 2.  
I/O  
I
External interrupt 7 input pin.  
General purpose digital I/O pin Port I Pin 3.  
Sensor interface system clock.  
NAND flash address latch enable.  
I2C1 clock pin.  
PI.3  
I/O  
O
VCAP_CLKO  
NAND_ALE  
I2C1_SCL  
EBI_DATA3  
CAN0_RXD  
RTC_TICK  
PI.4  
O
89  
48  
O
I/O  
I
External I/O data bus bit 3.  
CAN bus receiver0 input.  
O
RTC tick output  
I/O  
I
General purpose digital I/O pin Port I Pin 4.  
Sensor interface pixel clock.  
NAND flash command latch enable.  
I2C1 data input/output pin.  
VCAP_PCLK  
NAND_CLE  
I2C1_SDA  
EBI_DATA4  
CAN0_TX  
PI.5  
O
90  
49  
I/O  
I/O  
O
External I/O data bus bit 4.  
CAN bus transmitter0 output.  
General purpose digital I/O pin Port I Pin 5.  
Sensor interface HSYNC.  
I/O  
I
VCAP_HSYNC  
NAND_nWE  
eMMC_CMD  
EBI_DATA5  
SD1_CMD  
UART1_TXD  
SPI1_SS0  
PI.6  
O
NAND flash write enable.  
I/O  
I/O  
O
eMMC command/Response.  
External I/O data bus bit 5.  
91  
50  
SD/SDIO mode #1 command/response.  
Data transmitter output pin for UART1.  
1st SPI1 chip select pin.  
O
O
I/O  
I
General purpose digital I/O pin Port I Pin 6.  
Sensor interface VSYNC.  
VCAP_VSYNC  
NAND_nRE  
eMMC_CLK  
SC1_RST  
EBI_DATA6  
SD1_CLK  
O
NAND flash read enable.  
92  
51  
O
eMMC clock output.  
O
SmartCard1 reset pin.  
I/O  
O
External I/O data bus bit 6.  
SD/SDIO mode #1clock.  
July 6, 2018  
Page 25 of 74  
Rev 1.1  
N9H30  
UART1_RXD  
SPI1_CLK  
I
O
Data receiver input pin for UART1.  
SPI1 serial clock pin.  
PI.7  
I/O  
I
General purpose digital I/O pin Port I Pin 7.  
Sensor interface even/odd field indicator.  
NAND flash ready/busy channel 0.  
eMMC data line bit 3.  
VCAP_FIELD  
NAND_RDY0  
eMMC_DATA3  
SC1_CLK  
I
I/O  
O
SmartCard1 clock pin.  
93  
52  
EBI_DATA7  
SD1_DAT0  
UART1_RTS  
I/O  
I/O  
O
External I/O data bus bit 7.  
SD/SDIO mode #1 data line bit 0.  
Request to send output pin for UART1.  
SPI1 Data out pin.  
I
SPI1_DO (SPI1_DATA0)  
(I/O)  
I/O  
I
(SPI1 data 0 in dual/quad mode.)  
General purpose digital I/O pin Port I Pin 8.  
Sensor interface data bus bit 0.  
NAND flash data bus bit 0.  
PI.8  
VCAP_DATA0  
NAND_DATA0  
eMMC_DATA0  
SC1_DAT  
I/O  
I/O  
I/O  
I/O  
I/O  
I
eMMC data line bit 0.  
SmartCard1 data pin.  
94  
53  
EBI_DATA8  
SD1_DAT1  
UART1_CTS  
External I/O data bus bit 8.  
SD/SDIO mode #1 data line bit 1.  
Clear to send input pin for UART1.  
SPI1 Data input pin.  
I
SPI1_DI (SPI1_DATA1)  
(I/O)  
I/O  
I
(SPI1 data 1 in dual/quad mode.)  
General purpose digital I/O pin Port I Pin 9.  
Sensor interface data bus bit 1.  
NAND flash data bus bit 1.  
PI.9  
VCAP_DATA1  
NAND_DATA1  
eMMC_DATA1  
SC1_PWR  
I/O  
I/O  
O
eMMC data line bit 1.  
95  
54  
SmartCard1 power pin.  
EBI_DATA9  
SD1_DAT2  
UART4_TXD  
PI.10  
I/O  
I/O  
O
External I/O data bus bit 9.  
SD/SDIO mode #1 data line bit 2.  
Data transmitter output pin for UART4.  
General purpose digital I/O pin Port I Pin 10.  
Sensor interface data bus bit 2.  
NAND flash data bus bit 2.  
I/O  
I
VCAP_DATA2  
NAND_DATA2  
eMMC_DATA2  
SC1_CD  
I/O  
I/O  
I
96  
55  
eMMC data line bit 2.  
SmartCard1 card detect pin.  
External I/O data bus bit 10.  
SD/SDIO mode #1 data line bit 3.  
EBI_DATA10  
SD1_DAT3  
I/O  
I/O  
July 6, 2018  
Page 26 of 74  
Rev 1.1  
N9H30  
UART4_RXD  
PI.11  
I
Data receiver input pin for UART4.  
General purpose digital I/O pin Port I Pin 11.  
Sensor interface data bus bit 3.  
NAND flash data bus bit 3.  
I/O  
I
VCAP_DATA3  
NAND_DATA3  
SC0_RST  
97  
56  
I/O  
O
SmartCard0 reset pin.  
EBI_DATA11  
PI.12  
I/O  
I/O  
I
External I/O data bus bit 11.  
General purpose digital I/O pin Port I Pin 12.  
Sensor interface data bus bit 4.  
NAND flash data bus bit 4.  
VCAP_DATA4  
NAND_DATA4  
UART8_TXD  
SC0_CLK  
I/O  
O
98  
57  
Data transmitter output pin for UART8.  
SmartCard0 clock pin.  
O
EBI_DATA12  
SD1_nCD  
I/O  
I
External I/O data bus bit 12.  
SD/SDIO mode #1 card detect.  
General purpose digital I/O pin Port I Pin 13.  
Sensor interface data bus bit 5.  
NAND flash data bus bit 5.  
PI.13  
I/O  
I
VCAP_DATA5  
NAND_DATA5  
UART8_RXD  
SC0_DAT  
I/O  
I
99  
58  
59  
60  
Data receiver input pin for UART8.  
SmartCard0 data pin.  
I/O  
I/O  
O
EBI_DATA13  
SD1_nPWR  
PI.14  
External I/O data bus bit 13.  
SD/SDIO mode #1 power enable.  
General purpose digital I/O pin Port I Pin 14.  
Sensor interface data bus bit 6.  
NAND flash data bus bit 6.  
I/O  
I
VCAP_DATA6  
NAND_DATA6  
UART8_RTS  
SC0_PWR  
EBI_DATA14  
PI.15  
I/O  
O
100  
Request to send output pin for UART8.  
SmartCard0 power pin.  
O
I/O  
I/O  
I
External I/O data bus bit 14.  
General purpose digital I/O pin Port I Pin 15.  
Sensor interface data bus bit 7.  
NAND flash data bus bit 7.  
VCAP_DATA7  
NAND_DATA7  
UART8_CTS  
SC0_CD  
I/O  
I
101  
Clear to send input pin for UART8.  
SmartCard0 card detect pin.  
I
EBI_DATA15  
CLK_OUT  
I/O  
O
External I/O data bus bit 15.  
Clock output pin.  
102  
103  
104  
-
-
-
CORE_VDD  
CORE_VSS  
IO_VDD  
P
MCU internal core power pin.  
MCU internal core ground pin.  
MCU I/O power pin.  
P
61  
-
P
PG.15  
I/O  
General purpose digital I/O pin Port G Pin 15.  
July 6, 2018  
Page 27 of 74  
Rev 1.1  
N9H30  
INT5  
I
I/O  
O
External interrupt 5 input pin.  
PB.0  
General purpose digital I/O pin Port B Pin 0.  
NAND flash chip select 1.  
NAND_nCS1  
UART5_TXD  
SPI0_SS1  
TM1_TGL  
PB.1  
105  
-
O
Data transmitter output pin for UART5.  
2nd SPI0 chip select pin.  
O
O
Enhanced TIMER toggle output pin.  
General purpose digital I/O pin Port B Pin 1.  
NAND flash ready/busy channel 1.  
Data receiver input pin for UART5.  
2nd SPI1 chip select pin.  
I/O  
I
NAND_RDY1  
UART5_RXD  
SPI1_SS1  
TM1_CAP  
PB.2  
106  
107  
-
I
O
I
Enhanced TIMER capture input pin.  
General purpose digital I/O pin Port B Pin 2.  
Data transmitter output pin for UART6.  
PWM0 output pin.  
I/O  
O
UART6_TXD  
PWM0  
62  
O
TM0_TGL  
PB.3  
O
Enhanced TIMER toggle output pin.  
General purpose digital I/O pin Port B Pin 3.  
Data receiver input pin for UART6.  
PWM1 output pin.  
I/O  
I
UART6_RXD  
PWM1  
108  
109  
63  
O
TM0_CAP  
PB.4  
I
Enhanced TIMER capture input pin.  
General purpose digital I/O pin Port B Pin 4.  
Request to send output pin for UART6.  
General purpose digital I/O pin Port B Pin 5.  
Clear to send input pin for UART6.  
MCU I/O ground pin.  
I/O  
O
-
UART6_RTS  
PB.5  
I/O  
I
110  
-
-
UART6_CTS  
IO_VSS  
64  
65  
P
PB.6  
I/O  
O
General purpose digital I/O pin Port B Pin 6.  
1st SPI0 chip select pin.  
111  
SPI0_SS0  
PB.7  
I/O  
O
General purpose digital I/O pin Port B Pin 7.  
SPI0 serial clock pin.  
112  
113  
66  
67  
SPI0_CLK  
PB.8  
I/O  
O
General purpose digital I/O pin Port B Pin 8.  
SPI0 Data out pin.  
SPI0_DO  
(SPI0_DATA0)  
PB.9  
(I/O)  
I/O  
I
(SPI0 data 0 in dual/quad mode.)  
General purpose digital I/O pin Port B Pin 9.  
SPI0 Data input pin.  
114  
68  
SPI0_DI  
(SPI0_DATA1)  
GND  
(I/O)  
P
(SPI0 data 1 in dual/quad mode.)  
Ground pin for digital.  
-
-
PB.10  
I/O  
O
General purpose digital I/O pin Port B Pin 10.  
Data transmitter output pin for UART10.  
115  
69  
UART10_TXD  
July 6, 2018  
Page 28 of 74  
Rev 1.1  
N9H30  
SPI0_DATA2  
CAN0_RXD  
PB.11  
I/O  
I
SPI0 data 2 in dual/quad mode.  
CAN bus receiver0 input.  
I/O  
I
General purpose digital I/O pin Port B Pin 11.  
Data receiver input pin for UART10.  
SPI0 data 3 in dual/quad mode.  
CAN bus transmitter0 output.  
UART10_RXD  
SPI0_DATA3  
CAN0_TXD  
PB.12  
116  
70  
I/O  
O
I/O  
O
General purpose digital I/O pin Port B Pin 12.  
Data transmitter output pin for UART10.  
1st SPI1 chip select pin.  
117  
118  
71  
72  
UART10_TXD  
SPI1_SS0  
PB.13  
O
I/O  
I
General purpose digital I/O pin Port B Pin 13.  
Data receiver input pin for UART10.  
SPI1 serial clock pin.  
UART10_RXD  
SPI1_CLK  
PB.14  
O
I/O  
O
General purpose digital I/O pin Port B Pin 14.  
Request to send output pin for UART10.  
SPI1 Data out pin.  
UART10_RTS  
SPI1_DO  
119  
120  
121  
122  
73  
74  
-
O
(SPI1_DATA0)  
PB.15  
(I/O)  
I/O  
I
(SPI1 data 0 in dual/quad mode.)  
General purpose digital I/O pin Port B Pin 15.  
Clear to send input pin for UART10.  
SPI1 Data input pin.  
UART10_CTS  
SPI1_DI  
I
(SPI1_DATA1)  
PG.4  
(I/O)  
I/O  
O
(SPI1 data 1 in dual/quad mode.)  
General purpose digital I/O pin Port G Pin 4.  
NAND flash chip select 1.  
NAND_nCS1  
UART7_TXD  
SPI1_DATA2  
PG.5  
O
Data transmitter output pin for UART7.  
SPI1 data 2 in dual/quad mode.  
General purpose digital I/O pin Port G Pin 5.  
NAND flash ready/busy channel 1.  
Data receiver input pin for UART7.  
SPI1 data 3 in dual/quad mode.  
General purpose digital I/O pin Port C Pin 0.  
NAND flash data bus bit 0.  
I/O  
I/O  
I
NAND_RDY1  
UART7_RXD  
SPI1_DATA3  
PC.0  
-
I
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
123  
124  
-
-
-
NAND_DATA0  
eMMC_DATA0  
PC.1  
eMMC data line bit 0.  
General purpose digital I/O pin Port C Pin 1.  
NAND flash data bus bit 1.  
NAND_DATA1  
eMMC_DATA1  
PC.2  
eMMC data line bit 1.  
General purpose digital I/O pin Port C Pin 2.  
NAND flash data bus bit 2.  
125  
NAND_DATA2  
eMMC_DATA2  
eMMC data line bit 2.  
July 6, 2018  
Page 29 of 74  
Rev 1.1  
N9H30  
PC.3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
General purpose digital I/O pin Port C Pin 3.  
NAND flash data bus bit 3.  
126  
127  
128  
-
-
-
NAND_DATA3  
eMMC_DATA3  
PC.4  
eMMC data line bit 3.  
General purpose digital I/O pin Port C Pin 4.  
NAND flash data bus bit 4.  
NAND_DATA4  
eMMC_CMD  
PC.5  
eMMC command/Response.  
General purpose digital I/O pin Port C Pin 5.  
NAND flash data bus bit 5.  
NAND_DATA5  
eMMC_CLK  
PC.6  
eMMC clock output.  
I/O  
I/O  
O
General purpose digital I/O pin Port C Pin 6.  
NAND flash data bus bit 6.  
NAND_DATA6  
UART10_TXD  
TM0_TGL  
PC.7  
129  
130  
131  
132  
133  
134  
-
-
-
-
-
-
-
Data transmitter output pin for UART10.  
Enhanced TIMER toggle output pin.  
General purpose digital I/O pin Port C Pin 7.  
NAND flash data bus bit 7.  
O
I/O  
I/O  
I
NAND_DATA7  
UART10_RXD  
TM0_CAP  
PC.8  
Data receiver input pin for UART10.  
Enhanced TIMER capture input pin.  
General purpose digital I/O pin Port C Pin 8.  
NAND flash chip select 0.  
I
I/O  
O
NAND_nCS0  
UART10_RTS  
TM1_TGL  
PC.9  
O
Request to send output pin for UART10.  
Enhanced TIMER toggle output pin.  
General purpose digital I/O pin Port C Pin 9.  
NAND flash address latch enable.  
Clear to send input pin for UART10.  
Enhanced TIMER capture input pin.  
General purpose digital I/O pin Port C Pin 10.  
NAND flash command latch enable.  
Data transmitter output pin for UART4.  
Enhanced TIMER toggle output pin.  
General purpose digital I/O pin Port C Pin 11.  
NAND flash write enable.  
O
I/O  
O
NAND_ALE  
UART10_CTS  
TM1_CAP  
PC.10  
I
I
I/O  
O
NAND_CLE  
UART4_TXD  
TM2_TGL  
PC.11  
O
O
I/O  
O
NAND_nWE  
UART4_RXD  
TM2_CAP  
PC.12  
I
Data receiver input pin for UART4.  
Enhanced TIMER capture input pin.  
General purpose digital I/O pin Port C Pin 12.  
NAND flash read enable.  
I
I/O  
O
NAND_nRE  
UART4_RTS  
TM3_TGL  
135  
O
Request to send output pin for UART4.  
Enhanced TIMER toggle output pin.  
O
July 6, 2018  
Page 30 of 74  
Rev 1.1  
N9H30  
PC.13  
I/O  
I
General purpose digital I/O pin Port C Pin 13.  
NAND flash ready/busy channel 0.  
Clear to send input pin for UART4.  
Enhanced TIMER capture input pin.  
General purpose digital I/O pin Port C Pin 14.  
NAND flash write protect.  
NAND_RDY0  
UART4_CTS  
TM3_CAP  
PC.14  
136  
137  
-
-
I
I
I/O  
O
NAND_nWP  
PWM0  
O
PWM0 output pin.  
PJ.3  
I/O  
O
General purpose digital I/O pin Port J Pin 3.  
JTAG test data out.  
138  
139  
140  
141  
142  
75  
76  
77  
78  
79  
JTAG_TDO  
PJ.0  
I/O  
O
General purpose digital I/O pin Port J Pin 0.  
JTAG test clock.  
JTAG_TCK  
PJ.1  
I/O  
O
General purpose digital I/O pin Port J Pin 1.  
JTAG test mode select.  
JTAG_TMS  
PJ.2  
I/O  
I
General purpose digital I/O pin Port J Pin 2.  
JTAG test data in.  
JTAG_TDI  
PJ.4  
I/O  
O
General purpose digital I/O pin Port J Pin 4.  
JTAG Reset.  
JTAG_nTRST  
External reset input: active LOW, with an internal pull-  
up. Set this pin low reset to initial state.  
nRESET  
IU  
143  
80  
WDT_nRST  
IO_VDD  
O
P
Watch dog timer external reset output pin. Open-drain.  
MCU I/O power pin.  
144  
145  
146  
147  
148  
149  
150  
151  
152  
-
81  
-
CORE_VSS  
CORE_VDD  
DDR_VSS  
DDR_VDD  
DDR_VSS  
DDR_VDD  
DDR_VSS  
DDR_VDD  
DDR_VSS  
CORE_VSS  
IO_VDD  
P
MCU internal core ground pin.  
MCU internal core power pin.  
DDR ground pin.  
82  
-
P
P
83  
-
P
DDR power pin.  
P
DDR ground pin.  
83  
-
P
DDR power pin.  
P
DDR ground pin.  
84  
-
P
DDR power pin.  
P
DDR ground pin.  
153  
154  
-
P
MCU internal core ground pin.  
MCU I/O power pin.  
85  
P
PD.0  
I/O  
O
I/O  
O
I/O  
I/O  
General purpose digital I/O pin Port D Pin 0.  
SD/SDIO mode #0 command/response.  
General purpose digital I/O pin Port D Pin 1.  
SD/SDIO mode #0 clock.  
155  
156  
86  
87  
88  
SD0_CMD  
PD.1  
SD0_CLK  
PD.2  
General purpose digital I/O pin Port D Pin 2.  
SD/SDIO mode #0 data line bit 0.  
157  
SD0_DAT0  
July 6, 2018  
Page 31 of 74  
Rev 1.1  
N9H30  
PD.3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
General purpose digital I/O pin Port D Pin 3.  
SD/SDIO mode #0 data line bit 1.  
General purpose digital I/O pin Port D Pin 4.  
SD/SDIO mode #0 data line bit 2.  
General purpose digital I/O pin Port D Pin 5.  
SD/SDIO mode #0 data line bit 3.  
General purpose digital I/O pin Port D Pin 6.  
SD/SDIO mode #0 card detect.  
General purpose digital I/O pin Port D Pin 7.  
MCU internal core power pin.  
158  
159  
160  
161  
89  
90  
91  
92  
SD0_DAT1  
PD.4  
SD0_DAT2  
PD.5  
SD0_DAT3  
PD.6  
SD0_nCD  
PD.7  
162  
163  
164  
165  
166  
93  
94  
-
I/O  
P
CORE_VDD  
PLL_VDD  
PLL_VSS  
CORE_VDD  
PH.3  
P
PLL power input pin.  
95  
-
P
PLL ground.  
P
MCU internal core power pin.  
I/O  
I/O  
I
General purpose digital I/O pin Port H Pin 3.  
I2C1 data input/output pin.  
I2C1_SDA  
UART9_RXD  
CAN0_TXD  
PWM3  
Data receiver input pin for UART9.  
CAN bus transmitter0 output.  
167  
96  
O
O
PWM3 output pin.  
INT3  
I
External interrupt 3 input pin.  
PH.2  
I/O  
O
General purpose digital I/O pin Port H Pin 2.  
I2C1 clock pin.  
I2C1_SCL  
UART9_TXD  
CAN0_RXD  
PWM2  
O
Data transmitter output pin for UART9.  
CAN bus receiver0 input.  
168  
97  
I
O
PWM2 output pin.  
INT2  
I
External interrupt 2 input pin.  
PE.13  
I/O  
I
General purpose digital I/O pin Port E Pin 13.  
Clear to send input pin for UART8.  
Data receiver input pin for UART3.  
Reference Clock Output.  
UART8_CTS  
UART3_RXD  
CLK_OUT  
PE.12  
169  
98  
99  
I
O
I/O  
O
General purpose digital I/O pin Port E Pin 12.  
Request to send output pin for UART8.  
Data transmitter output pin for UART3.  
General purpose digital I/O pin Port E Pin 11.  
RMII1 receive data error.  
170  
171  
UART8_RTS  
UART3_TXD  
PE.11  
O
I/O  
I
-
-
RMII1_RXERR  
UART8_RXD  
PE.10  
I
Data receiver input pin for UART8.  
General purpose digital I/O pin Port E Pin 10.  
RMII1 carrier sense / receive data valid.  
I/O  
I
172  
RMII1_CRSDV  
July 6, 2018  
Page 32 of 74  
Rev 1.1  
N9H30  
UART8_TXD  
PE.9  
O
I/O  
I
Data transmitter output pin for UART8.  
General purpose digital I/O pin Port E Pin 9.  
RMII1 receive data bus bit 1.  
RMII1_RXDATA1  
SD1_nPWR  
UART1_CD  
PE.8  
173  
174  
175  
176  
-
-
-
-
O
SD/SDIO mode #1 power enable.  
Carrier detect input pin for UART1.  
General purpose digital I/O pin Port E Pin 8.  
RMII1 receive data bus bit 0.  
I
I/O  
I
RMII1_RXDATA0  
SD1_nCD  
UART1_RI  
PE.7  
I
SD/SDIO mode #1 card detect.  
I
Ring indicator input pin for UART1.  
General purpose digital I/O pin Port E Pin 7.  
RMII1 reference clock.  
I/O  
I
RMII1_REFCLK  
SD1_DAT3  
UART1_DSR  
PE.6  
I/O  
I
SD/SDIO mode #1 data line bit 3.  
Data set ready input pin for UART1.  
General purpose digital I/O pin Port E Pin 6.  
RMII1 transmit enable.  
I/O  
O
RMII1_TXEN  
SD1_DAT2  
UART1_DTR  
PE.5  
I/O  
O
SD/SDIO mode #1 data line bit 2.  
Data terminal ready output pin for UART1.  
General purpose digital I/O pin Port E Pin 5.  
RMII1 transmit data bus bit 1.  
I/O  
O
RMII1_TXDATA1  
SD1_DAT1  
UART1_CTS  
CLK_OUT  
PE.4  
177  
-
I/O  
I
SD/SDIO mode #1 data line bit 1.  
Clear to send input pin for UART1.  
Reference Clock Output.  
O
I/O  
O
General purpose digital I/O pin Port E Pin 4.  
RMII1 Transmit Data bus  
RMII1_TXDATA0  
SD1_DAT0  
UART1_RTS  
PE.3  
178  
179  
180  
-
-
-
I/O  
O
SD/SDIO mode #1 ata line bit 0.  
Request to send output pin for UART1.  
General purpose digital I/O pin Port E Pin 3.  
RMII1 Management Data I/O  
I/O  
I/O  
O
RMII1_MDIO  
SD1_CLK  
UART1_RXD  
PE.2  
SD/SDIO mode #1 clock.  
I
Data receiver input pin for UART1.  
General purpose digital I/O pin Port E Pin 2.  
RMII1 Management Data Clock  
I/O  
O
RMII1_MDC  
SD1_CMD  
UART1_TXD  
PE.1  
O
SD/SDIO mode #1 command/response.  
Data transmitter output pin for UART1.  
General purpose digital I/O pin Port E Pin 1.  
Data receiver input pin for UART0.  
General purpose digital I/O pin Port E Pin 0.  
O
I/O  
I
181  
182  
100  
101  
UART0_RXD  
PE.0  
I/O  
July 6, 2018  
Page 33 of 74  
Rev 1.1  
N9H30  
UART0_TXD  
IO_VDD  
O
P
Data transmitter output pin for UART0.  
MCU I/O power pin.  
183  
184  
185  
186  
102  
103  
104  
-
XT1_IN  
AI  
AO  
P
External 12MHz crystal input pin.  
External 12MHz crystal output pin.  
MCU I/O ground pin.  
XT1_OUT  
IO_VSS  
PF.9  
I/O  
I
General purpose digital I/O pin Port F Pin 9.  
RMII0 receive data error.  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
RMII0_RXERR  
PF.8  
I/O  
I
General purpose digital I/O pin Port F Pin 8.  
RMII0 carrier sense / receive data valid.  
General purpose digital I/O pin Port F Pin 7.  
RMII0 receive data bus bit 1.  
RMII0_CRSDV  
PF.7  
I/O  
I
RMII0_RXDATA1  
PF.6  
I/O  
I
General purpose digital I/O pin Port F Pin 6.  
RMII0 receive data bus bit 0.  
RMII0_RXDATA0  
PF.5  
I/O  
I
General purpose digital I/O pin Port F Pin 5.  
RMII0 reference clock.  
RMII0_REFCLK  
PF.4  
I/O  
O
General purpose digital I/O pin Port F Pin 4.  
RMII0 transmit enable.  
RMII0_TXEN  
PF.3  
I/O  
O
General purpose digital I/O pin Port F Pin 3.  
RMII0 transmit data bus bit 1.  
RMII0_TXDATA1  
PF.2  
I/O  
O
General purpose digital I/O pin Port F Pin 2.  
RMII0 Transmit Data bus bit 0.  
RMII0_TXDATA0  
PF.1  
I/O  
I/O  
I/O  
O
General purpose digital I/O pin Port F Pin 1.  
RMII0 Management Data I/O  
RMII0_MDIO  
PF.0  
General purpose digital I/O pin Port F Pin 0.  
RMII0 Management Data Clock  
General purpose digital I/O pin Port H Pin 1.  
USB overcurrent  
RMII0_MDC  
PH.1  
I/O  
I
197  
198  
115  
USB_OVRCUR  
INT1  
I
External interrupt 1 input pin.  
PH.0  
I/O  
I
General purpose digital I/O pin Port H Pin 0.  
USB0 VBUS valid.  
116  
117  
USB0_VBUSVLD  
INT0  
I
External interrupt 0 input pin.  
PF.10  
I/O  
General purpose digital I/O pin Port F Pin 10.  
199  
200  
USB host output power control pin for LQFP128  
package only.  
USB_PWREN  
O
PE.15  
I/O  
O
General purpose digital I/O pin Port E Pin 15.  
USB1 host output power control pin.  
-
-
USB1_PWREN  
PE.14  
I/O  
O
General purpose digital I/O pin Port E Pin 14.  
USB0 host output power control pin.  
201  
USB0_PWREN  
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N9H30  
202  
-
-
CORE_VSS  
CORE_VDD  
CORE_VDD  
USBPLL1_VDD  
USB1_VSS  
USB1_DM  
P
P
MCU internal core ground pin.  
MCU internal core power pin.  
MCU internal core power pin.  
USB1 PLL power pin.  
118  
118  
118  
-
203  
204  
205  
206  
207  
208  
209  
210  
211  
212  
213  
214  
215  
-
P
P
P
USB1 ground pin.  
119  
120  
121  
122  
123  
-
I/O  
I/O  
AP  
I
USB1 differential signal D-.  
USB1 differential signal D+.  
USB1 I/O power pin.  
USB1_DP  
USB1_VDD  
USB1_REXT  
USBPLL0_VDD  
USB0_VSS  
USB0_DM  
USB1 module reference Resister.  
USB0 PLL power pin.  
P
P
USB0 ground pin.  
124  
125  
126  
127  
128  
1
I/O  
I/O  
AP  
I
USB0 differential signal D-.  
USB0 differential signal D+.  
USB0 I/O power pin.  
USB0_DP  
USB0_VDD  
USB0_REXT  
IO_VSS  
USB0 module reference Resister.  
MCU I/O ground pin.  
P
216  
USB0_ID  
IU  
USB0 Host/Device select.  
Table 3.3-1 Pin List Table  
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5
BLOCK DIAGRAM  
5.1 N9H30 Series Block Diagram  
Hardware  
Accelerator  
ARM926EJ-S  
300 MHz  
Memory  
Storage  
Peripherals  
I-Cache  
16 KB  
NAND Flash  
Interface  
AIC  
2D Graphic  
Engine  
ROM 16KB  
Timer X 5  
ETimer X 4  
WDT/WWDT  
PWM X 4  
GDMA  
2-ch  
SRAM 56KB  
D-Cache  
16 KB  
eMMC Flash  
Interface  
JPEG  
DDR2  
SDRAM  
SD Card  
Interface  
MMU  
EBI  
AHB/APB Bus  
Power Control  
Clock Control  
Connectivity  
Human Interface  
UART X 11  
(IrDA, RS-485)  
HS Ext.  
Crystal Osc.  
12 MHz  
Video Capture  
Sensor Interface  
Ethernet MAC X 2  
POR  
USB 2.0  
High Speed Host  
CCAN X 2  
LCD Display  
Interface  
LS Ext.  
Crystal Osc.  
32.768 kHz  
USB 2.0  
High Speed Device  
LVR  
LVD  
SPI X 2, PIC  
I2C X 2  
ADC  
(Touch Screen)  
I2S  
PLL x 2  
SDIO  
Smart Card X 2  
Figure 5.1-1 N9H30 Series Block Diagram  
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6
FUNCTIONAL DESCRIPTION  
6.1 ARM® ARM926EJ-STM Processor Core  
6.1.1 Overview  
The ARM926EJ-STM processor core is a member of the ARM9 family of general-purpose  
microprocessors. The ARM926EJ-STM processor core is targeted at multi-tasking applications  
where full memory management, high performance, and low power are all important.  
The ARM926EJ-STM CP processor U core supports the 32-bit ARM and 16-bit Thumb instruction  
sets, enabling the user to choose between high performance and high code density. The  
ARM926EJ-STM processor core includes features for efficient execution of Java byte codes,  
providing Java performance similar to JIT, but without the associated code overhead.  
The ARM926EJ-STM processor provides support for external coprocessor enabling floating-point  
or other application-specific hardware acceleration to be added. The ARM926EJ-STM processor  
core implements ARM architecture version 5TEJ.  
The ARM926EJ-STM processor has a Harvard cached architecture and provides a complete high-  
performance processor subsystem, including:  
An ARM9EJ-S integer core.  
A Memory Management Unit (MMU).  
Separate instruction and data cache.  
Separate instruction and data AMBA AHB bus interfaces.  
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6.2 System Manager  
6.2.1 Overview  
The system management describes following information and functions.  
System Resets  
System Power Architecture  
System Memory Map  
System management registers for Product Identifier (PDID), Power-On Setting,  
System Wake-Up, Reset Control for on-chip controllers/peripherals, and multi-function  
pin control.  
System Control registers  
6.3 Clock Controller (CLK_CTL)  
6.3.1 Overview  
The clock controller generates all clocks for Video, Audio, CPU, AMBA and all the engine modules.  
This chip includes two PLL modules. The clock source for each module comes from the PLL, or from  
the external crystal input directly. For each clock there is bit on the CLKEN register to control the clock  
ON or OFF individually, and the divider setting is on the CLK_DIVCTL register. The register can also  
be used to control the clock enable or disable for power control.  
6.4 Advanced Interrupt Controller (AIC)  
6.4.1 Overview  
An interrupt temporarily changes the sequence of program execution to react to a particular event  
such as power failure, watchdog timer timeout and so on. The CPU processor provides two modes of  
interrupt, the Fast Interrupt (FIQ) mode for critical session and the Interrupt (IRQ) mode for general  
purpose. The IRQ request is occurred when the nIRQ input is asserted. Similarly, the FIQ request is  
occurred when the nFIQ input is asserted. The FIQ has privilege over the IRQ and can preempt an  
ongoing IRQ. It is possible to ignore the FIQ and the IRQ by setting the F and I bits in the current  
program status register (CPSR).  
6.5 SDRAM Interface Controller (SDIC)  
6.5.1 Overview  
The SDRAM Controller support DDR and DDR2 type SDRAM. Only 16-bit data bus width is  
supported.  
The SDRAM controller interface to three isolated AHB. All these AHB masters can access the memory  
independent. Except the memory access, the masters of AHB also could access the SDRAM control  
registers.  
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6.6 External Bus Interface (EBI)  
6.6.1 Overview  
This chip supports External Bus Interface (EBI), which controls the access to the external memory  
(SRAM) and External I/O devices. The EBI has up to 5 chip select signals to select different devices  
with 10-bit address bus. It supports 8-bit and 16-bit external data bus width for each bank.  
6.7 General Purpose I/O (GPIO)  
6.7.1 Overview  
The N9H30 series have up to 86 General-Purpose I/O (GPIO) pins and can be shared with other  
function pins depending on the chip configuration.  
6.8 General DMA Controller (GDMA)  
6.8.1 Overview  
The chip has a two-channel general DMA controller with or without descriptor fetch operation, called  
the GDMA. The two-channel GDMA performs the memory-to-memory data transfers without the CPU  
intervention:  
6.9 Timer Controller (TMR)  
6.9.1 Overview  
The general timer controller includes five channels, TIMER0, TIMER1, TIMER2, TIMER3, and  
TIMER4, which allow user to easily implement a counting scheme or timing control for applications.  
The timer can perform functions like frequency measurement, event counting, interval measurement,  
pulse generation, delay timing, and so on. The timer possesses features such as adjustable  
resolution, programmable counting period, and detailed information. The timer can generate an  
interrupt signal upon timeout, or provide the current value of count during operation.  
6.10 Enhance Timer Controller (ETMR)  
6.10.1 Overview  
This chip is equipped with four enhance timer modules including ETIMER0, ETIMER1, ETIMER2  
and ETIMER3, which allow user to easily implement a counting scheme or timing control for  
applications. The timer can perform functions like frequency measurement, event counting,  
interval measurement, clock generation, delay timing, and so on. The timer can generate an  
interrupt signal upon timeout, or provide the current value of count during operation.  
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6.11 Pulse Width Modulation (PWM)  
6.11.1 Overview  
This chip has one PWM controller, and it has 4 independent PWM outputs, CH0~CH3, or as 2  
complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone generators.  
Each PWM pair has one Prescaler, one clock divider, two clock selectors, two 16-bit PWM counters,  
two 16-bit comparators, and one Dead-Zone generator. They are all driven by APB system clock  
(PCLK) in chip. Each PWM channel can be used as a timer and issue interrupt independently.  
6.12 Watchdog Timer (WDT)  
6.12.1 Overview  
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an  
unknown state. This prevents system from hanging for an infinite period of time. Besides, this  
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.  
6.13 Windowed Watchdog Timer (WWDT)  
6.13.1 Overview  
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified  
window period to prevent software run to uncontrollable status by any unpredictable condition.  
6.14 Real Time Clock (RTC)  
6.14.1 Overview  
The Real Time Clock (RTC) controller provides the real time clock and calendar information. The clock  
source of RTC controller is from an external 32.768 kHz low-speed crystal which connected at pins  
X32_IN and X32_OUT (refer to pin Description). The RTC controller provides the real time clock (hour,  
minute, second) in RTC_TIME (RTC Time Loading Register) as well as calendar information (year,  
month, day) in RTC_CAL (RTC Calendar Loading Register). It also offers RTC alarm function that  
user can preset the alarm time in RTC_TALM (RTC Time Alarm Register) and alarm calendar in  
RTC_CALM (RTC Calendar Alarm Register). The data format of RTC time and calendar message are  
all expressed in BCD (Binary Coded Decimal) format.  
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6.15 UART Interface Controller (UART)  
6.15.1 Overview  
This chip equips up to 9 channels of Universal Asynchronous Receiver/Transmitters (UART).  
UART1/4/6/8/10 supports High-speed UART and UART0/5/7/9 perform Normal Speed UART,  
besides, all the UART channels support flow control function. The UART controller also supports IrDA  
(SIR), LIN Master/Slave and RS-485 function modes.  
6.16 Smart Card Host Interface (SC)  
6.16.1 Overview  
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully  
compliant with PC/SC Specifications. It also provides status of card insertion/removal.  
6.17 I2C Synchronous Serial Interface Controller (I2C)  
6.17.1 Overview  
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data  
exchange between devices. The I2C standard is a true multi-master bus including collision  
detection and arbitration that prevents data corruption if two or more masters attempt to control  
the bus simultaneously.  
6.18 SPI Interface Controller (SPI)  
6.18.1 Overview  
The SPI is a synchronous serial interface performs a serial-to-parallel conversion on data characters  
received from the peripheral, and a parallel-to-serial conversion on data characters received from  
CPU. This interface can drive up to 2 external peripherals and is seen as the master.  
6.19 I2S Controller (I2S)  
6.19.1 Overview  
The I2S controller consists of I2S and PCM protocols to interface with external audio CODEC. The I2S  
and PCM interface supports 8, 16, 18, 20 and 24-bit left/right precision in record and playback. When  
operating in 18/20/24-bit precision, each left/right-channel sample is stored in a 32-bit word. Each  
left/right-channel sample has 24/20/18 MSB bits of valid data and other LSB bits are the padding  
zeros. When operating in 16-bit precision, right-channel sample is stored in MSB of a 32-bit word and  
left-channel sample is stored in LSB of a 32-bit word.  
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6.20 Ethernet MAC Controller (EMAC)  
6.20.1 Overview  
This chip provides 2 Ethernet MAC Controller (EMAC) for Network application.  
The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM  
function for recognizing Ethernet MAC addresses; Transmit-FIFO, Receive-FIFO, TX/RX state  
machine controller, time stamping engine for IEEE 1588, Magic Packet parsing engine and status  
controller.  
The EMAC supports RMII (Reduced MII) interface to connect with external Ethernet PHY.  
6.21 USB 2.0 Device Controller (USBD)  
6.21.1 Overview  
The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains  
both the AHB master interface and AHB slave interface. CPU programs the USB controller registers  
through the AHB slave interface. For IN or OUT transfer, the USB device controller needs to write data  
to memory or read data from memory through the AHB master interface. The USB device controller is  
complaint with USB 2.0 specification and it contains 12 configurable endpoints in addition to control  
endpoint. These endpoints could be configured to BULK, INTERRUPT or ISO. The USB device  
controller has a built-in DMA to relieve the load of CPU.  
6.22 USB Host Controller (USBH)  
6.22.1 Overview  
The Universal Serial Bus (USB) is a fast, bi-directional, isochronous, low-cost, dynamically attachable  
serial interface standard intended for modem, scanners, PDAs, keyboards, mice, and digital imaging  
devices. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host  
Controller and a network of peripheral devices. The attached peripherals share USB bandwidth  
through a host-scheduled, token-based protocol. Peripherals may be attached, configured, used, and  
detached, while the host and other peripherals continue operation (i.e. hot plug and unplug is  
supported).  
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6.23 Controller Area Network (CAN)  
6.23.1 Overview  
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and  
Module Interface. The CAN Core performs communication according to the CAN protocol version 2.0  
part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the  
physical layer, additional transceiver hardware is required.  
For communication on a CAN network, individual Message Objects are configured. The Message  
Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message  
RAM. All functions concerning the handling of messages are implemented in the Message Handler.  
These functions include acceptance filtering, the transfer of messages between the CAN Core and the  
Message RAM, and the handling of transmission requests as well as the generation of the module  
interrupt.  
The register set of the C_CAN can be accessed directly by the software through the module interface.  
These registers are used to control/configure the CAN Core and the Message Handler and to access  
the Message RAM.  
6.24 Flash Memory Interface (FMI)  
6.24.1 Overview  
The Flash Memory Interface (FMI) of this Chip has DMA unit and FMI unit. The DMA unit provides a  
DMA (Direct Memory Access) function for FMI to exchange data between system memory (ex.  
SDRAM) and shared buffer (128 bytes), and the FMI unit control the interface of eMMC or NAND  
flash. The interface controller can support eMMC and NAND-type flash and the FMI is cooperated with  
DMAC to provide a fast data transfer between system memory and cards.  
6.25 Secure Digital Host Controller (SDH)  
6.25.1 Overview  
The Secure-Digital Card Host Controller (SDH) equips DMAC unit and SD unit. The DMAC unit  
provides a DMA (Direct Memory Access) function for SD to exchange data between system memory  
and shared buffer (128 bytes), and the SD unit controls the interface of SD/SDHC/SDIO. The SDH  
controller supports SD/SDHC/SDIO card and cooperates with DMAC to provide a fast data transfer  
between system memory and cards.  
6.26 2D Graphic Engine (GE2D)  
6.26.1 Overview  
A 32-bit 2D Graphics Engine (GE2D) is specially designed to improve the performance of graphic  
processing. It can accelerate the operation of individual GUI functions such as BitBLTs and  
Bresenham Line Draw to operate at all pixel depths including 8/16/32 bit-per-pixel.  
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6.27 JPEG Codec (JPEG)  
6.27.1 Overview  
The JPEG Codec supports Baseline Sequential Mode JPEG still image compression and  
decompression that is fully compliant with ISO/IEC International Standard 10918-1 (T.81). The  
features and capability of the JPEG codec are listed below.  
6.28 LCD Display Interface Controller (LCM)  
6.28.1 Overview  
The main purpose of Display Controller is used to display the video/image data to LCD device or  
connect with external TV-encoder. The data source may come from the JPEG decoder and the  
OSD pattern which have been stored in system memory (SDRAM). The input data format of the  
display controller can be packet YUV422, packet YUV444, packet RGB444, packet RGB565,  
packet RGB666, and packet RGB888. The OSD (On Screen Display) function supports packet  
YUV422 and 8/16-bit direct-color mode. The LCD controller supports both sync-type and MPU-  
type LCDM. This LCD Controller is a bus master and can transfer display data from system  
memory (SDRAM) without CPU intervention.  
6.29 Capture Sensor Interface Controller (CAP)  
6.29.1 Overview  
The Image Capture Interface is designed to capture image data from a sensor. After capturing or  
fetching image data, it will process the image data, and then FIFO output them into frame buffer.  
6.30 Analog to Digital Converter (ADC)  
6.30.1 Overview  
The N9H30 series contains one 12-bit Successive Approximation Register analog-to-digital  
converter (SAR A/D converter) with 5 input channels. The A/D converter supports two operation  
modes: 4-wire or 5-wire mode. The ADC is especially suitable to act as touch screen controller.  
July 6, 2018  
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7
ELECTRICAL CHARACTERISTICS  
7.1 Absolute Maximum Ratings  
PARAMETER  
SYMBOL  
MIN.  
MAX  
+1.26  
+3.63  
+1.90  
+3.6  
24  
UNIT  
V
Core DC Power Supply  
-0.3  
VCORE_VDDVCORE_VSS  
I/O DC Power Supply  
-0.3  
V
VIO_VDDVIO_VSS  
DDR I/O DC Power Supply  
Input Voltage  
-0.3  
V
VDDR_VDDVDDR_VSS  
VIN  
1/tCLCL  
TA  
VIO_VSS-0.3  
V
Oscillator Frequency  
4
MHz  
C  
Operating Temperature  
-40  
+85  
+150  
200  
TST  
Storage Temperature  
-55  
C  
IDD  
Maximum Current into CORE_VDD  
Maximum Current out of CORE_VSS  
Maximum Current sunk by a I/O pin  
Maximum Current sourced by a I/O pin  
Maximum Current sunk by total I/O pins  
Maximum Current sourced by total I/O pins  
-
-
-
-
-
-
mA  
mA  
mA  
mA  
mA  
mA  
ISS  
200  
20  
30  
IIO  
200  
200  
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability  
of the device.  
Table 7.1-1 Absolute Maximum Ratings  
July 6, 2018  
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7.2 DC Electrical Characteristics  
7.2.1 N9H30 Series DC Electrical Characteristics  
(VDD-VSS=3.3 V, TA = 25C, FOSC = 12 MHz unless otherwise specified.)  
SPECIFICATION  
PARAMETER  
Core Operation voltage  
I/O Operation Voltage  
DDR I/O Operation Voltage  
Power Ground  
SYM.  
VCORE_VDD  
VIO_VDD  
TEST CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
1.14  
1.2  
1.26  
V
2.97  
1.70  
-0.3  
2.97  
0
3.3  
1.8  
3.63  
1.90  
V
V
V
V
V
VDDR_VDD  
VSS  
AVSS  
Analog Operating Voltage  
Analog Reference Voltage  
AVDD  
Vref  
3.3  
3.63  
AVDD  
ICORE_VDD1  
IDDR_VDD1  
IUSBPLL_VDD1  
IUSB0_VDD1  
185  
40  
15  
35  
35  
100  
165  
35  
15  
35  
35  
100  
3
mA  
mA  
mA  
mA  
mA  
uA  
Frequency of CPUCLK/DDR_CLK is 300/150  
MHz.  
The functionalities enabled are GE2D, LCD,  
JPEG, graphic Engine, EMAC, USBD, USBH  
and UART.  
Current Consumption of  
Normal Operating Mode 1  
IUSB1_VDD1  
IRTC_VDD1  
ICORE_VDD2  
mA  
mA  
mA  
mA  
mA  
uA  
Frequency of CPUCLK/DDR_CLK is 264/132  
MHz.  
IDDR_VDD2  
The functionalities enabled are GE2D, LCD,  
JPEG, graphic Engine, EMAC, USBD, USBH  
and UART.  
IUSBPLL_VDD2  
IUSB0_VDD2  
Current Consumption of  
Normal Operating Mode 2  
IUSB1_VDD2  
IRTC_VDD2  
ISTDBY_CORE_VDD  
ISTDBY_DDR_VDD  
ISTDBY_IO_VDD  
ISTDBY_USB0_VDD  
ISTDBY_USB1_VDD  
mA  
mA  
A  
VCORE_VDD = 1.2V  
VDDR_VDD = 1.8V  
VIO_VDD = 3.3V  
6
Current Consumption of  
Deep Standby Mode  
5
0
VUSB0_VDD = 3.3V  
VUSB1_VDD = 3.3V  
A  
0
A  
July 6, 2018  
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SPECIFICATION  
PARAMETER  
SYM.  
TEST CONDITIONS  
MIN.  
TYP.  
5
MAX.  
UNIT  
A  
ISTDBY_UPLL0_VDD  
ISTDBY_UPLL1_VDD  
ISTDBY_AVDD  
VUSBPLL0_VDD = 1.2V  
5
VUSBPLL1_VDD = 1.2V  
VAVDD = 3.3V  
A  
25  
100  
A  
ISTDBY_RTC_VDD  
VRTC_VDD = 3.3V  
A  
Current Consumption of  
Power Down Mode  
IPWD_RTC_VDD  
7
-
uA  
VRTC_VDD = 3.0V  
Input Leakage Current  
VIO_VDD = 3.63V  
0V < VIN < 3.6V  
ILK1  
-10  
40  
10  
A  
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ  
Input Leakage Current with  
Pull-Down Resistor on  
ILK2  
-
-
160  
VIN = VIO_VDD  
A  
A  
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ  
Input Leakage Current with  
Pull-Up Resistor on  
ILK3  
-160  
40  
VIN = 0  
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ  
Input Low Voltage  
VIL1  
VIH1  
VIL2  
VIH2  
VHY  
-
-
0.8  
-
V
V
V
V
V
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ (TTL input)  
Input High Voltage  
2.0  
-
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ (TTL input)  
Input Low Voltage  
0.9  
1.05  
1.9  
0.85  
1.2  
2.1  
0.9  
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ (Schmitt input)  
Input High Voltage  
1.65  
0.75  
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ (Schmitt input)  
Hysteresis voltage  
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ (Schmitt input)  
Negative going threshold  
(Schmitt input), nRESET  
VILS  
0.75  
1.65  
-
-
0.9  
2.1  
V
V
Positive going threshold  
(Schmitt input), nRESET  
VIHS  
Source Current  
ISR21  
8
8
-
-
28  
18  
mA  
mA  
PA, PB, PD, PE, PF, PH, PI,  
PJ (Push-pull Mode)  
Sink Current  
ISK1  
PA, PB, PD, PE (Push-pull  
Mode)  
July 6, 2018  
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SPECIFICATION  
PARAMETER  
SYM.  
TEST CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Input Pull-up Resistance  
kΩ  
RPU  
45  
53  
82  
VIN = 0  
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ  
Input Pull-down Resistance  
kΩ  
kΩ  
RPD  
37  
45  
49  
53  
91  
85  
VIN = VIO_VDD  
PA, PB, PD, PE, PF, PC, PH,  
PI, PJ  
Input Pull-up Resistance  
nRESET  
RRST  
Note:  
1. nRESET pin is a Schmitt trigger input.  
2. Pins of PA, PB, PD, PE, PF, PG, PH, PI and PJ can source a transition current when they are being externally driven  
from 1 to 0. In the condition of VDD=3.63 V, the transition current reaches its maximum value when VIN approximates to 1.5  
V.  
Table 7.2-1 DC Electrical Characteristics  
July 6, 2018  
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7.3 AC Electrical Characteristics  
7.3.1 External 12 MHz High Speed Oscillator  
Symbol  
tCHCX  
Parameter  
Min  
20  
20  
-
Typ  
Max  
-
Unit  
ns  
Test Condition  
Clock High Time  
Clock Low Time  
Clock Rise Time  
Clock Fall Time  
-
-
-
-
-
-
-
-
tCLCX  
-
ns  
tCLCH  
10  
10  
ns  
tCHCL  
-
ns  
Table 7.3-1 External 12 MHz High Speed Oscillator Electrical Characteristics  
tCLCL  
tCLCH  
tCLCX  
90%  
10%  
0.7 VDD  
0.3 VDD  
tCHCL  
tCHCX  
Note: Duty cycle is 50%.  
Figure 7.3-1 External 12 MHz High Speed Oscillator Timing Diagram  
July 6, 2018  
Page 49 of 74  
Rev 1.1  
N9H30  
7.3.2 Power-on Sequence & RESET  
Figure 7.3-2 Power on sequence  
7.3.2.1 Power up Sequence  
Higher Voltage (3.3V) First  
Sequence: T33 ≥ T18 ≥ T12, (The time delay gap between < 1mS is prefer, typical  
0mS is recommend)  
7.3.2.2 Power down Sequence,  
The lower voltage (1.2V) should be powered down first and then the higher one (3.3V)  
Sequence: T12 ≥ T18 ≥ T33  
Note.  
T12 represents 1.2V powered time for Core power  
T18 represents 1.8V powered time for MVDD power  
T33 represents 3.3V powered time for I/O power  
July 6, 2018  
Page 50 of 74  
Rev 1.1  
N9H30  
7.3.3 External 12 MHz High Speed Crystal  
Symbol  
VHXT  
TA  
Parameter  
Operation Voltage  
Temperature  
Min.  
2.97  
-40  
4
Typ.  
Max  
3.63  
85  
Unit  
V
Test Conditions  
3.3  
-
-
-
-
-
C  
fHXT  
Clock Frequency  
24  
MHz  
7.3.3.1 Typical Crystal Application Circuits  
Crystal  
ESR (ohm)  
C1, C2  
12 MHz  
< 50  
14 pf  
XT1_IN  
XT1_OUT  
4~24 MHz  
Crystal  
C1  
C2  
Vss  
Vss  
Figure 7.3-3 Typical HXT Crystal Application Circuit  
July 6, 2018  
Page 51 of 74  
Rev 1.1  
N9H30  
7.3.4 External 32.768 kHz Low Speed Crystal  
Symbol  
VLXT  
TA  
Parameter  
Operation Voltage  
Temperature  
Min.  
2.97  
-40  
-
Typ.  
3.3  
Max  
3.63  
85  
Unit  
V
Test Conditions  
-
-
-
-
C  
fLXT  
Clock Frequency  
32.768  
-
kHz  
7.3.4.1 Typical Crystal Application Circuits  
Crystal  
C1  
C2  
32.768 kHz  
20pf  
20pf  
X32_IN  
X32_OUT  
Crystal  
C1  
C2  
Vss  
Vss  
Figure 7.3-4 Typical LXT Crystal Application Circuit  
July 6, 2018  
Page 52 of 74  
Rev 1.1  
N9H30  
7.3.5 EBI Timing  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Condition  
Address Setup Time to EBI_nCS  
Falling Edge  
TtACS  
0
-
7
THCLK  
-
EBI_nCS Setup Time to  
EBI_nWE or EBI_nOE Falling  
Edge  
TtCOS  
0
1
0
1
-
-
-
-
7
23  
7
THCLK  
THCLK  
THCLK  
THCLK  
-
-
-
-
EBI_nWE or EBI_nOE Active Low  
Time  
TtACC  
EBI_nCS Hold Time from  
EBI_nWE or EBI_nOE Rising  
Edge  
TtCOH  
EBI_DATA Read Setup Time to  
EBI_nOE Rising Edge  
TSU_EBI_RD  
-
Note: THCLK is the period of EBIs operating clock.  
Table 7.3-2 EBI Timing  
EBI_ADDR[9:0]  
EBI_nCS[4:0]  
TtACS  
TtCOS  
TtCOH  
EBI_nWE,  
EBI_nBE[1:0]  
TtACC+2  
EBI_DATA[15:0  
(Write)]  
Valid Data  
TtCOS  
TtCOH  
EBI_nOE  
TtACC+2  
TSU_EBI_RD  
EBI_DATA[15:0  
(Write)]  
Valid Data  
Figure 7.3-5 External Bus Interface Timing Diagram  
July 6, 2018  
Page 53 of 74  
Rev 1.1  
N9H30  
7.3.6 I2C Interface Timing  
100K  
400K  
Symbol  
Parameter  
Unit  
Test Condition  
Min  
4.7  
4
Max  
Min  
1.2  
0.6  
Max  
TLOW  
THIGH  
I2C_SCL Low Period  
I2C_SCL High Period  
-
-
-
-
us  
-
-
us  
Repeated START Condition  
Setup Time  
TSU_STA  
4.7  
-
1.2  
-
us  
-
THD_STA  
TSU_STO  
TBUF  
START Condition Hold Time  
STOP Condition Setup Time  
Bus Free Time  
4
4
-
-
0.6  
0.6  
1.2  
0.3  
0
-
-
us  
us  
us  
us  
us  
ns  
ns  
-
-
-
-
-
-
-
4.7  
2
-
-
TSU_DAT  
THD_DAT  
TR  
Data Setup Time  
-
-
Data Hold Time  
0
4.2  
1000  
300  
0.8  
300  
300  
I2C_SCL/I2C_SDA Rise Time  
I2C_SCL/I2C_SDA Fall Time  
-
20+0.1Cb  
TF  
-
-
Capacitive Load for Each Bus  
Line  
Cb  
-
400  
-
400  
pF  
-
Table 7.3-3 I2C Interface Timing  
Repeated  
START  
STOP  
START  
STOP  
I2C_SDA  
TBUF  
TLOW  
TR  
TF  
I2C_SCL  
THIGH  
THD_STA  
TSU_STA  
TSU_STO  
TSU_DAT  
THD_DAT  
Figure 7.3-6 I2C Interface Timing Diagram  
July 6, 2018  
Page 54 of 74  
Rev 1.1  
N9H30  
7.3.7 SPI Interface Timing  
Symbol  
TP_SPI_CLK  
TH_SPI_CLK  
TL_SPI_CLK  
Parameter  
Min  
56  
Typ  
Max  
Unit  
ns  
Test Condition  
SPI_CLK Period  
SPI_CLK High Time  
SPI_CLK Low Time  
-
-
-
-
-
-
-
-
-
28  
ns  
28  
ns  
SPI_DI or SPI_DATA[3:0] Setup  
Time to SPI_CLK Active Edge  
TSU_SPI_DI  
THD_SPI_DI  
TDLY_SPI_DO  
THD_SPI_DO  
11  
1
-
-
-
-
-
ns  
ns  
ns  
ns  
-
-
-
SPI_DI or SPI_DATA[3:0] Hold  
Time from SPI_CLK Active Edge  
SPI_CLK Active Edge to Valid  
SPI_DO or SPI_DATA[3:0] Delay  
-
4
SPI_DO or SPI_DATA[3:0] Hold  
Time from SPI_CLK Active Edge  
0.2  
Table 7.3-4 SPI Interface Timing  
TP_SPI_CLK  
TL_SPI_CLK  
TH_SPI_CLK  
SPIx_CLK  
TL_SPI_CLK  
TH_SPI_CLK  
SPIx_DI  
SPIx_DATA[3:0]  
TSU_SPI_DI  
THD_SPI_DI  
SPIx_DO  
SPIx_DATA[3:0]  
TDLY_SPI_DO  
THD_SPI_DO  
Figure 7.3-7 SPI Interface Timing Diagram  
July 6, 2018  
Page 55 of 74  
Rev 1.1  
N9H30  
7.3.8 I2S Interface Timing  
Symbol  
Parameter  
Min  
50  
Typ  
Max  
Unit  
ns  
Test Condition  
TP_I2S_BITCLK  
TH_I2S_BITCLK  
TL_I2S_BITCLK  
I2S_BITCLK Period  
I2S_BITCLK High Time  
I2S_BITCLK Low Time  
-
-
-
-
-
-
-
-
-
25  
ns  
25  
ns  
I2S_BITCLK Rising to Valid  
I2S_WS or I2S_DATAO Delay  
TDLY_I2S_DO  
THD_I2S_DO  
TSU_I2S_DI  
THD_I2S_DI  
-
-
-
-
-
6
-
ns  
ns  
ns  
Ns  
-
I2S_WS or I2S_DATAO Hold Time  
from I2S_BITCLK Rising  
1
5
3
I2S_DATAI Setup Time to  
I2S_BITCLK Rising  
-
-
-
I2S_DATAI Hold Time from  
I2S_BITCLK Rising  
-
Table 7.3-5 I2S Interface Timing  
TP_I2S_BITCLK  
TL_I2S_BITCLK  
TH_I2S_BITCLK  
I2S_BITCLK  
I2S_DATAI  
TSU_I2S_DI  
THD_I2S_DI  
I2S_WS  
I2S_DATAO  
TDLY_I2S_DO  
THD_I2S_DO  
Figure 7.3-8 I2S Interface Timing Diagram  
July 6, 2018  
Page 56 of 74  
Rev 1.1  
N9H30  
7.3.9 Ethernet Interface Timing  
7.3.9.1 RMII Interface Timing  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Condition  
20.0 +/- 50  
TP_RMII_REFCLK  
RMII_REFCLK Period  
-
-
ns  
-
ppm  
TH_RMII_REFCLK  
TL_RMII_REFCLK  
RMII_REFCLK High Time  
8.0  
8.0  
10.0  
10.0  
12.0  
12.0  
ns  
ns  
-
-
RMII_REFCLK Low Time  
RMII_REFCLK Rising to Valid  
RMII_TXEN, RMII_TXDATA0 and  
RMII_TXDATA1 Delay  
TDLY_RMII_TX  
TSU_RMII_RX  
THD_RMII_RX  
-
-
-
-
10  
-
ns  
ns  
ns  
-
-
-
RMII_CRSDV, RMII_RXDATA0  
and RMII_RXDATA1 Setup Time to  
RMII_REFCLK Rising  
5
2
RMII_CRSDV, RMII_RXDATA0  
and RMII_RXDATA1 Hold Time  
from RMII_REFCLK Rising  
-
Table 7.3-6 RMII Interface Timing  
TP_RMII_REFCLK  
TH_RMII_REFCLK  
TL_RMII_REFCLK  
RMIIx_REFCLK  
RMIIx_TXEN  
RMIIx_TXDATA0  
RMIIx_TXDATA1  
TDLY_RMII_TX  
RMIIx_CRSDV  
RMIIx_RXDATA0  
RMIIx_RXDATA1  
TSU_RMII_RX  
THD_RMII_RX  
Figure 7.3-9 RMII Interface Timing Diagram  
July 6, 2018  
Page 57 of 74  
Rev 1.1  
N9H30  
7.3.9.2 Ethernet PHY Management Interface Timing  
Symbol  
TP_RMII_MDC  
TH_RMII_MDC  
TL_RMII_MDC  
Parameter  
Min  
400  
200  
200  
Typ  
Max  
Unit  
ns  
Test Condition  
RMII_MDC Period  
RMII_MDC High Time  
RMII_MDC Low Time  
-
-
-
-
-
-
-
-
-
ns  
ns  
RMII_MDC Falling to Valid  
RMII_MDIO Delay  
TDLY_RMII_MDIOWR  
TSU_RMII_MDIORD  
THD_RMII_MDIORD  
-
-
-
-
10  
-
ns  
ns  
ns  
-
-
-
RMII_MDIO Setup Time to  
RMII_MDC Rising  
10  
10  
RMII_MDIO Hold Time from  
RMII_MDC Rising  
-
Table 7.3-7 Ethernet PHY Management Interface Timing  
TP_RMII_MDC  
TH_RMII_MDC  
TL_RMII_MDC  
RMIIx_MDC  
RMIIx_MDIO  
(Write)  
TDLY_RMII_MDIOWR  
RMIIx_MDIO  
(Read)  
TSU_RMII_MDIORD  
THD_RMII_MDIORD  
Figure 7.3-10 Ethernet PHY Management Interface Timing Diagram  
July 6, 2018  
Page 58 of 74  
Rev 1.1  
N9H30  
7.3.10 NAND Interface Timing  
Symbol  
TH_NAND_nWE  
TL_NAND_nWE  
Parameter  
Min  
Typ  
151  
452  
Max  
Unit  
Ns  
Test Condition  
NAND_nWE High Time  
NAND_nWE Low Time  
-
-
-
-
-
-
ns  
NAND_nWE Falling to Valid  
NAND_DATA Delay  
TDLY_DATA_OUT  
THD_DATA_OUT  
TSU_DATA_IN  
-
153-  
ns  
Ns  
ns  
ns  
-
-
-
-
NAND_DATA Hold Time from  
NAND_nWE Rising  
7.53  
153  
7.53  
-
-
-
-
-
-
NAND_DATA Setup Time to  
NAND_nRE Rising  
NAND_DATA Hold Time from  
NAND_nRE Rising  
THD_DATA_IN  
Note 1: NAND controller operating clock is 132 MHz and HI_WID (FMI_NANDTMCTL[15:8]) is 0x1.  
Note 2: NAND controller operating clock is 132 MHz and LO_WID (FMI_NANDTMCTL[7:0]) is 0x5.  
Note 2: NAND controller operating clock is 132 MHz  
Table 7.3-8 NAND Interface Timing  
NAND_nCS0  
NAND_nCS1  
NAND_ALE  
NAND_CLE  
NAND_nWE  
TL_NAND_nWE  
TH_NAND_nWE  
THD_DATA_OUT  
TDLY_DATA_OUT  
NAND_DATA[7:0]  
(Write)  
NAND_nRE  
THD_DATA_IN  
TSU_DATA_IN  
NAND_DATA[7:0]  
(Read)  
Figure 7.3-11 NAND Interface Timing Diagram  
July 6, 2018  
Page 59 of 74  
Rev 1.1  
N9H30  
7.3.11 SD Interface Timing  
7.3.11.1 Default Mode Timing  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Condition  
SD_CLK Period  
TP_SD_CLK  
40  
-
-
ns  
-
(Data Transfer Mode)  
SD_CLK Period  
TP_SD_CLK_ID  
2,500  
-
-
ns  
(Identification Mode)  
TH_SD_CLK  
TL_SD_CLK  
SD_CLK High Time  
-
-
20  
20  
-
-
ns  
ns  
-
-
SD_CLK Low Time  
SD_DATA Setup Time to  
SD_CLK Rising  
TSU_SD_IN  
5
5
-
-
-
-
-
-
ns  
ns  
ns  
-
-
-
SD_DATA Hold Time from  
SD_CLK Rising  
THD_SD_IN  
SD_CLK Falling to  
TDLY_SD_OUT  
14  
Valid SD_DATA Delay  
Table 7.3-9 SD Interface Default Mode Timing  
TP_SD_CLK  
TL_SD_CLK  
TH_SD_CLK  
SDx_CLK  
SDx_CMD  
SDx_DATA[3:0]  
(Input Mode)  
TSU_SD_IN  
THD_SD_IN  
SDx_CMD  
SDx_DATA[3:0]  
(Output Mode)  
TDLY_SD_OUT  
Figure 7.3-12 SD Interface Default Mode Timing Diagram  
July 6, 2018  
Page 60 of 74  
Rev 1.1  
N9H30  
7.3.11.2 High-Speed Mode Timing  
Symbol  
TP_SD_CLK  
TH_SD_CLK  
TL_SD_CLK  
Parameter  
Min  
20  
7
Typ  
Max  
Unit  
ns  
Test Condition  
SD_CLK Period  
SD_CLK High Time  
SD_CLK Low Time  
-
-
-
-
-
-
-
-
-
ns  
7
ns  
SD_DATA Setup Time to  
SD_CLK Rising  
TSU_SD_IN  
6
2
-
-
-
-
-
-
ns  
ns  
ns  
ns  
-
-
-
-
SD_DATA Hold Time from  
SD_CLK Rising  
THD_SD_IN  
SD_CLK Falling to  
TDLY_SD_OUT  
-
14  
-
Valid SD_DATA Delay  
SD_DATA Hold Time from  
SD_CLK Rising  
THD_SD_OUT  
2.5  
Table 7.3-10 SD Interface High-Speed Mode Timing  
TP_SD_CLK  
TL_SD_CLK  
TH_SD_CLK  
SDx_CLK  
SDx_CMD  
SDx_DATA[3:0]  
(Input Mode)  
TSU_SD_IN  
THD_SD_IN  
SDx_CMD  
SDx_DATA[3:0]  
(Output Mode)  
TDLY_SD_OUT  
THD_SD_OUT  
Figure 7.3-13 SD Interface High-Speed Mode Timing Diagram  
July 6, 2018  
Page 61 of 74  
Rev 1.1  
N9H30  
7.3.12 LCD Display Interface Timing  
7.3.12.1 SYNC Type Timing  
Symbol  
TP_LCD_CLK  
TH_LCD_CLK  
TL_LCD_CLK  
Parameter  
Min  
13  
Typ  
Max  
Unit  
ns  
Test Condition  
LCD_CLK Period  
LCD_CLK High Time  
LCD_CLK Low Time  
-
-
-
-
-
-
-
-
-
6.5  
6.5  
ns  
ns  
LCD_CLK Rising to Valid  
LCD_HSYNC, LCD_VSYNC,  
LCD_DEN and LCD_DATA Delay  
TDLY_LCD_OUT  
-
-
-
6
ns  
-
-
LCD_HSYNC, LCD_VSYNC,  
LCD_DEN and LCD_DATA Hold  
Time from LCD_CLK Rising  
THD_LCD_OUT  
1
-
ns  
Table 7.3-11 LCD Display Interface SYNC Type Timing  
TP_LCD_CLK  
TL_LCD_CLK  
TH_LCD_CLK  
LCD_CLK  
LCD_HSYNC  
LCD_VSYNC  
LCD_DEN  
LCD_DATA  
TDLY_LCD_OUT  
THD_LCD_OUT  
Figure 7.3-14 LCD Display Interface SYNC Type Timing Diagram  
July 6, 2018  
Page 62 of 74  
Rev 1.1  
N9H30  
7.3.13 Capture Sensor Interface Timing  
Symbol  
Parameter  
Min  
Typ  
-
Max  
Unit  
ns  
Test Condition  
TP_VCAP_PCLK  
TH_VCAP_PCLK  
TL_VCAP_PCLK  
VCAP_PCLK Period  
VCAP_PCLK High Time  
VCAP_PCLK Low Time  
20  
-
-
-
-
-
-
-
10.0  
10.0  
ns  
-
ns  
VCAP_HSYNC, VCAP_VSYNC,  
VCAP_FIELD and VCAP_DATA  
Setup Time to VCAP_PCLK Rising  
TSU_VCAP_IN  
4
1
-
-
-
-
ns  
-
-
VCAP_HSYNC, VCAP_VSYNC,  
VCAP_FIELD and VCAP_DATA  
Hold Time from VCAP_PCLK  
Rising  
THD_VCAP_IN  
ns  
Table 7.3-12 Capture Sensor Interface Timing  
TP_VCAP_PCLK  
TH_VCAP_PCLK  
TL_VCAP_PCLK  
VCAP_PCLK  
VCAP_HSYNC  
VCAP_VSYNC  
VCAP_FIELD  
VCAP_DATA  
TSU_VCAP_IN  
THD_VCAP_IN  
Figure 7.3-15 Capture Sensor Interface Timing Diagram  
July 6, 2018  
Page 63 of 74  
Rev 1.1  
N9H30  
7.4 Analog Characteristics  
7.4.1 12-bit SARADC  
Symbol  
-
Parameter  
Resolution  
Min.  
Typ.  
12  
Max.  
Unit  
Test Conditions  
-
-
-
-
-
-
-
-
-
-
-
-
Bit  
DNL  
INL  
EO  
Differential Nonlinearity Error  
Integral Nonlinearity Error  
Offset Error  
±1  
LSB VREF is external AVREF pin  
LSB VREF is external AVREF pin  
LSB VREF is external AVREF pin  
LSB VREF is external AVREF pin  
LSB VREF is external AVREF pin  
-1.2  
+3.7  
-6.6  
4.2  
EG  
Gain Error (Transfer Gain)  
Absolute Error  
EA  
-
Monotonic  
Guaranteed  
FADC  
TCAL  
TS  
ADC Clock Frequency  
Calibration Time  
Sample Time  
-
-
3
16  
-
MHz  
Clock  
Clock  
Clock  
k SPS  
V
-
-
-
17  
20  
-
-
TADC  
FS  
Conversion Time  
Sample Rate  
-
800[1]  
3.6  
VAVDD  
Supply Voltage  
2.7  
3.3  
ADC channel 1 high speed  
mode  
IDDA1  
Supply Current (Avg.)  
Supply Current (Avg.)  
-
-
1.2  
1.0  
mA  
ADC channel 1 low speed  
mode  
IDDA2  
IDDA3  
ILK  
mA  
Supply Current (Avg.)  
Leakage Current  
-
-
0.4  
mA  
uA  
V
0.1  
-
VREF  
VIN  
Reference Voltage  
Analog Input Voltage  
Analog Input Impedance  
Capacitance  
2
0
-
-
VAVDD  
VREF  
2
-
-
V
MΩ  
pF  
RIN  
CIN  
-
25.6  
Note:  
1. ADC channel 1 supports sample rate higher than 160k SPS. Other ADC channels support sampel rate up to 160k SPS.  
Table 7.4-1 SAR ADC Characteristics  
July 6, 2018  
Page 64 of 74  
Rev 1.1  
N9H30  
7.4.2 Low Voltage Detection (LVD) and Low Voltage Reset (LVR)  
Symbol  
VDD  
Parameter  
Min.  
Typ.  
3.3  
21  
Max  
Unit  
V
Test Conditions  
Operation Voltage  
Operating Current  
2.0  
3.63  
-
-
IDD  
uA  
LVR_EN (SYS_LVRDCR[0]) = 0,  
LVD_EN (SYS_LVRDCR[8]) = 0  
ILK  
TA  
Quiescent Current  
Temperature  
-
0.1  
0.5  
uA  
-40  
-
85  
-
C  
V
V
V
V
V
V
2.295  
2.475  
2.115  
0.045  
0.045  
0.045  
2.55  
2.75  
2.35  
0.05  
0.05  
0.05  
2.805  
3.025  
2.585  
0.055  
0.055  
0.055  
LVD_SEL (SYS_LVRDCR[9]) = 0  
VTH_LVD  
VTH_LVR  
VHY_LVD  
VHY_LVR  
LVD Threshold Voltage  
LVR Threshold Voltage  
LVD Hysteresis  
LVD_SEL (SYS_LVRDCR[9]) = 1  
-
LVD_SEL (SYS_LVRDCR[9]) = 0  
LVD_SEL (SYS_LVRDCR[9]) = 1  
-
LVR Hysteresis  
Table 7.4-2 LVD and LVR Characteristics  
July 6, 2018  
Page 65 of 74  
Rev 1.1  
N9H30  
7.4.3 3.3V Power-On Reset (POR33)  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Condition  
TA  
Temperature  
-40  
25  
125  
-
C  
AVDD rising from 0V to  
3.3V  
VPOR  
Reset Voltage  
-
-
1.83  
5
-
-
V
IPOR33  
Quiescent current  
nA  
Vin > reset voltage  
Table 7.4-3 POR33 Characteristics  
7.4.4 1.2V Power-On Reset (POR12)  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Condition  
TA  
Temperature  
-40  
25  
125  
-
C  
CORE_VDD rising from  
0V to 1.2V  
VPOR  
Reset Voltage  
-
-
0.76  
10  
-
-
V
IPOR12  
Quiescent current  
nA  
Vin > reset voltage  
Table 7.4-4 POR12 Characteristics  
7.4.5 USB 2.0 PHY  
7.4.5.1 Low/Full-Speed DC Electrical Specifications  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Condition  
VOL  
Output Low (Driven)  
-
-
0.3  
V
1.5K RPU on DP to 3.6v  
15K RPD on DP, DM to  
GND  
VOH  
Output High (Driven)  
2.8  
-
-
V
VDI  
VCM  
VIL  
Differential Input Sensitivity  
Differential Common-Mode Range  
Single-Ended Input Low  
Single-Ended Input High  
Pull-Up Resistor  
0.2  
0.8  
-
-
-
2.5  
0.8  
-
V
V
|VUSB0_DP–VUSB0_DM|  
-
-
V
-
-
VIH  
2.0  
1.35  
-
V
kΩ  
RPU  
1.5  
1.65  
kΩ  
kΩ  
Ω
RPD_DP  
RPD_DM  
D+ Pull-Down Resistor  
D- Pull-Down Resistor  
Driver Output Resistance  
13.5  
13.5  
28  
15  
15  
-
16.5  
16.5  
44  
ZDRV  
Steady state drive[1]  
Note:  
1. Driver output resistance doesn’t include series resistor resistance.  
Table 7.4-5 Low/Full-Speed DC Electrical Specifications  
July 6, 2018  
Page 66 of 74  
Rev 1.1  
N9H30  
7.4.5.2 High-Speed DC Electrical Specifications  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Condition  
High Speed Differential Input  
Signal Level  
VHSDI  
150  
-
-
mV  
|VUSB0_DP–VUSB0_DM  
|
|
High Speed Squelch Detection  
Threshold  
VHSQ  
100  
125  
150  
500  
mV  
mV  
|VUSB0_DP–VUSB0_DM  
High Speed Common Mode  
Voltage Range  
VHSCM  
-50  
-
VHSOH  
VHSOL  
VCHIRPJ  
VCHIRPK  
High Speed Data Signaling High  
High Speed Data Signaling Low  
Chirp J Level  
300  
-10  
400  
440  
10  
mV  
mV  
mV  
mV  
0
-
700  
-900  
1100  
-500  
Chirp K Level  
-
High Speed Driver Output  
Resistance  
Ω
RHSDRV  
40.5  
45  
49.5  
Table 7.4-6 High-Speed DC Electrical Specifications  
7.4.5.3 USB Low-Speed Driver AC Electrical Characteristics  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Condition  
CL=200pF, 10% to 90% of  
|VOH-VOL  
TLRISE  
Rise Time  
75  
-
300  
ns  
|
CL=200pF, 10% to 90% of  
|VOH-VOL  
TLFALL  
Fall Time  
75  
-
-
300  
2.0  
ns  
V
|
Excluding the first  
transition from idle state  
VLCR  
Crossover Voltage  
1.3  
Table 7.4-7 USB Low-Speed Driver AC Electrical Characteristics  
7.4.5.4 USB Full-Speed Driver AC Electrical Characteristics  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Condition  
CL=50pF, 10% to 90% of  
VFRISE  
Rise Time  
4
-
20  
ns  
|VOH-VOL  
|
CL=50pF, 10% to 90% of  
|VOH-VOL  
VFFALL  
Fall Time  
4
-
-
20  
ns  
V
|
Excluding the first  
transition from idle state  
VFCR  
Crossover Voltage  
1.3  
2.0  
Table 7.4-8 USB Full-Speed Driver AC Electrical Characteristics  
7.4.5.5 USB High-Speed Driver AC Electrical Characteristics  
Symbol  
VHRISE  
Parameter  
Min  
500  
500  
Typ  
Max  
900  
900  
Unit  
ps  
Test Condition  
CL<10pF  
High Speed Driver Rise Time  
High Speed Driver Fall Time  
-
-
VHFALL  
ps  
CL<10pF  
Table 7.4-9 USB High-Speed Driver AC Electrical Characteristics  
July 6, 2018  
Page 67 of 74  
Rev 1.1  
N9H30  
7.5 Thermal Characteristics of N9H30 Package  
Figure 7.4-1 Thermal Performance of SLQFP under Forced Convection  
7.5.1 Simulation Conditions  
Input Power  
Top Die: 0.6W  
Bottom die: 0.6 W  
Test Board (PCB)  
Control Condition  
4 layers  
Air Flow = 0, 1, 2, 3 m/s  
July 6, 2018  
Page 68 of 74  
Rev 1.1  
N9H30  
8
PACKAGE DIMENSIONS  
8.1 216L LQFP (24x24x1.4mm footprint 2.0mm)  
July 6, 2018  
Page 69 of 74  
Rev 1.1  
N9H30  
8.2 128L LQFP (14x14x1.4mm footprint)  
July 6, 2018  
Page 70 of 74  
Rev 1.1  
N9H30  
8.3 PCB Reflow Profile Suggestion  
8.3.1 Profile Setting Consideration  
Figure 8.3-1 Profile Setting Consideration  
Sn-Pb Eutestic Assembly  
Large Body Small Body  
< 3°C/second  
Pb-Free Eutestic Assembly  
Large Body Small Body  
< 3°C/second  
Profile Feature  
Average ramp-up rate (TL to TP)  
Preheat  
100°C  
150°C  
150°C  
200°C  
Temperature Min (Tsmin)  
Temperature Max (Tsmax  
Time (min to max) (ts)  
)
60-120 seconds  
60-180 seconds  
Time maintained above:  
183°C  
1217°C  
Temperature (TL)  
Time (tL)  
60-150 seconds  
60-150 seconds  
Peak Temperature (Tp)  
225+0/-5°C  
245+5/-5°C  
Time within 5°C of actual Peak  
Temperature (tp)  
10-20 seconds  
10-30 seconds  
Ramp-down Rate  
3°C/second max.  
6 minutes max.  
3°C/second max.  
8 minutes max.  
Time 25°C to Peak Temperature  
Note 1: All temperatures refer to topside of the package, measured on the package body surface.  
Note 2: Depends on other parts on board density and follower solder paste manufacturers’s guideline.  
July 6, 2018  
Page 71 of 74  
Rev 1.1  
N9H30  
8.3.2 Profile Suggestion for N9H30 series  
Figure 8.3-2 Profile Suggestion for N9H30 series  
Reheat time  
Dwell time  
150°C-200°C: 105+/-15sec  
Over 220°C: 70+5/-10 sec  
240+10/-5°C  
Peak Temp  
Up: 3 +0/-2°C/sec  
Ramp Up/Dwon Rate  
Down: 2+0/-1°C/sec  
July 6, 2018  
Page 72 of 74  
Rev 1.1  
N9H30  
9
REVISION HISTORY  
Date  
Revision  
Description  
2018, 05,16  
2018, 07,06  
1.0  
1.  
2.  
Preliminary version.  
Added N9H30FxxI series  
1.1  
July 6, 2018  
Page 73 of 74  
Rev 1.1  
N9H30  
Important Notice  
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any  
malfunction or failure of which may cause loss of human life, bodily injury or severe property  
damage. Such applications are deemed, “Insecure Usage”.  
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic  
energy control instruments, airplane or spaceship instruments, the control or operation of  
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all  
types of safety devices, and other applications intended to support or sustain life.  
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay  
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the  
damages and liabilities thus incurred by Nuvoton.  
July 6, 2018  
Page 74 of 74  
Rev 1.1  

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