NAU88L21IG [NUVOTON]
Ultra-Low Power Audio CODEC Ground-Referenced Headphone Amplifier;
| 型号： | NAU88L21IG |
| 厂家： | 
NUVOTON |
| 描述： | Ultra-Low Power Audio CODEC Ground-Referenced Headphone Amplifier |
| 文件： | 总69页 (文件大小：1602K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAU88L21
Ultra-Low Power Audio CODEC Ground-Referenced Headphone Amplifier
GENERAL DESCRIPTION
The NAU88L21 is an ultra-low power high performance audio codec that supports both analog and digital audio functions. It includes
one I2S/PCM interface, one digital microphone interface, one digital mixer, two high quality DACs and ADC’s, and one stereo class
G headphone amplifier. The advanced on-chip signal processing engine that includes dynamic range compressor (DRC),
programmable biquad filter, as well as an integrated frequency locked loop (FLL) to support various input clocks.
FEATURES
Class G Headphone Amplifier (28mW @ 32Ω, 1%
THD+N)
DAC: 105dB SNR, (A-weighted) @ 0dB gain, 1.8V and -
80dB THD @ 20mW and RL= 32Ω, DAC playback to
headphone output mode
ADC: 103dB SNR (A-weighted) @ 0dB MIC gain, 1.8V, Fs
= 48kHz and -93dB THD, 1.8V, MIC gain 0dB, OSR 256x
1 Digital I2S/PCM I/O port
Two mono differential or one stereo differential analog
microphone inputs, two single-ended microphone inputs or
one stereo digital microphone input
Cap-free Low noise Microphone bias with 7uVrms noise
between 20Hz-20kHz, internal pull high resistor for
microphone.
Sampling rate from 8k to 192 kHz
Dynamic Range Compressor (DRC)Programmable Biquad
filter Integrated DSP with specific functions:Input
automatic level control (ALC/AGC)/limiter
Output dynamic-range-compressor/limiter
Package: 32 Pin QFN package
Applications
Gaming controller
Wireless Headset
Smart Remote Controller
NAU88L21 Datasheet Rev1.7
Page 1 of 69
Feb, 2020
Block Diagram : QFN32
BIAS
VREF
MICL+
MICL -
ADC
DAC Effect
Digital Audio
Effects
HPL
HPR
ADC Effect
DAC
DAC
DMIC I/F
Volume
DRC
Programmable
BiQuad
Volume
DRC
Programmable
BiQuad
Mixers
Sidetone
MICR+
MICR-
ADC
MICBIAS
MICDET
MICBIAS
MICDET
CPOUTP
VSSCP
CPOUTN
Charge
Pump
FLL
I2 C Slave
& Registers
I2S/PCM
Interface
& MUX
CPCB
CPCA
MUX
NAU88L21 Datasheet Rev1.7
Page 2 of 69
Feb, 2020
Table of Contents
BLOCK DIAGRAM : QFN32...................................................................... 2
PIN DIAGRAM :......................................................................................... 5
PIN DESCRIPTION.................................................................................... 6
ELECTRICAL CHARACTERISTICS.......................................................... 7
1. GENERAL DESCRIPTION................................................................ 10
1.1 Inputs............................................................................................................... 10
1.2 Outputs............................................................................................................ 10
1.3 ADC, DAC and Digital Signal Processing........................................................ 10
1.4 Digital Interfaces.............................................................................................. 10
2. POWER SUPPLY ............................................................................. 11
2.1 Power on and off reset..................................................................................... 11
3. INPUT PATH DETAILED DESCRIPTIONS....................................... 12
3.1 Analog Microphone Inputs............................................................................... 12
3.2 Digital Microphone Input.................................................................................. 13
3.3 VREF............................................................................................................... 13
3.4 MIC Bias.......................................................................................................... 14
3.5 MIC detect ....................................................................................................... 14
3.5.1
Key Release .......................................................................................................................................16
4. ADC DIGITAL BLOCK...................................................................... 17
4.1 ADC Dynamic Range Compressors (DRC) ..................................................... 17
4.1.1
Level Estimation .................................................................................................................................17
4.1.2
Static Curve ........................................................................................................................................18
4.2 ADC Digital Volume Control ............................................................................ 19
4.3 ADC Programmable Biquad Filter ................................................................... 19
4.4 Companding .................................................................................................... 20
4.5 Additional ADC Application Notes ................................................................... 20
5. DAC DIGITAL BLOCK...................................................................... 21
5.1 DAC Dynamic Range Control (DRC)............................................................... 21
5.1.1
Level Estimation .................................................................................................................................21
5.1.2
Static Curve ........................................................................................................................................22
5.2 DAC Digital Volume Control, Mute and Channel selection.............................. 23
5.3 DAC Soft Mute................................................................................................. 23
5.4 DAC Auto Attenuate ........................................................................................ 23
5.5 DAC Path Digital Mixer with Side tone............................................................. 23
5.6 Companding .................................................................................................... 25
5.6.1
µ-law...................................................................................................................................................25
5.6.2
A-law...................................................................................................................................................25
NAU88L21 Datasheet Rev1.7
Page 3 of 69
Feb, 2020
6. CLOCKING AND SAMPLE RATES.................................................. 26
6.1 I2S/PCM Clock Generation.............................................................................. 27
6.2 Frequency Locked Loop(FLL).......................................................................... 29
7. CONTROL INTERFACES................................................................. 32
7.1 2-Wire-Serial Control Mode (I2C Style Interface) ............................................. 32
7.2 2-Wire Protocol Convention............................................................................. 32
7.3 2-Wire Write Operation.................................................................................... 33
7.4 2-Wire Read Operation.................................................................................... 34
7.5 Digital Serial Interface Timing.......................................................................... 35
7.6 Software Reset................................................................................................ 36
8. DIGITAL AUDIO INTERFACES........................................................ 37
8.1 Right-Justified Audio Data ............................................................................... 37
8.2 Left-Justified Audio Data.................................................................................. 37
8.3 I2S Audio Data ................................................................................................ 37
8.4 PCMA Audio Data ........................................................................................... 38
8.5 PCMB Audio Data ........................................................................................... 38
8.6 PCM Time Slot Audio Data.............................................................................. 38
8.7 TDM I2S Audio Data........................................................................................ 39
8.8 TDM PCMA Audio Data................................................................................... 39
8.9 TDM PCMB Audio Data................................................................................... 40
8.10 TDM PCM Offset Audio Data........................................................................... 40
9. OUTPUTS ......................................................................................... 42
9.1 Class G Headphone Driver and Charge Pump................................................ 42
10. CONTROL AND STATUS REGISTERS ........................................... 43
11. TYPICAL APPLICATION DIAGRAM................................................ 64
12. PACKAGE INFORMATION .............................................................. 65
13. ORDERING INFORMATION............................................................. 67
REVISION HISTORY ............................................................................... 68
IMPORTANT NOTICE............................................................................ 69
NAU88L21 Datasheet Rev1.7
Page 4 of 69
Feb, 2020
Pin Diagram :
MICDET
MICBIAS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
FS
BITCLK
MCLK
VDDMIC
VREF
VDDA
VSSD
QFN 32-pin
VSSA
VDDA
CPOUTP
VSSCP
VDDB
SCLK
SDIO
NAU88L21 Datasheet Rev1.7
Page 5 of 69
Feb, 2020
Pin Description
Pin #
Name
MICDET
MICBIAS
VDDMIC
VREF
Type
Analog IO
Functionality
1
Microphone/button detect, 2kOhm between Mic and Mic Bias
Microphone Bias Output
2
Analog Output
Supply
3
Microphone supply
4
Analog I/O
Ground
Internal DAC & ADC voltage reference decoupling I/O
Analog Ground
5
VSSA
6
VDDA
Supply
Analog Supply
7
CPOUTP
VSSCP
CPOUTN
CPCB
Analog I/O
Ground
Charge Pump positive voltage
Charge Pump Supply ground
Charge Pump negative voltage
Charge Pump switching capacitor node B
Charge Pump switching capacitor node A
Jack Tip; Headphone left channel output
Jack Ring1; Headphone right channel output
Headphone Ground
8
9
Analog I/O
Analog I/O
Analog I/O
Analog Output
Analog Output
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CPCA
JKTIP(HPL)
JKR1(HPR)
HPFB
IRQ
Digital I/O
IRQ
GPIO1/CSB
SDIO
Digital I/O
General Purpose IO/CSB
Digital I/O
Serial Data for I2C
SCLK
Digital Input
Supply
Serial Data Clock for I2C
VDDB
Digital IO Supply
VSSD
Ground
Digital IO ground
VDDA
Supply
Digital core supply
MCLK
Digital Input
Digital I/O
CODEC Master clock input
BCLK
Serial data bit clock input or output for I2S or PCM data
Frame Sync input or output for I2S or PCM data
Serial Audio data input for I2S or PCM data
Serial Audio data Output for I2S or PCM data
Jack detect input
FS
Digital I/O
DACIN
Digital Input
Digital Output
Analog Input
Analog Input
Analog/Digital Output
Analog Input/Digital Input
Analog Input
Supply
ADCOUT
JKDET
MICR+
PGA MICR+ Analog Input
MICR-/DMCLK
MICL-/DMDATA
MICL+
PGA MICR- Analog Input / Digital Microphone Clk output
PGA MICL- Analog Input / Digital Microphone Data input
PGA MICL+ Analog Input
VDDA
Analog Supply
NAU88L21 Datasheet Rev1.7
Page 6 of 69
Feb, 2020
Electrical Characteristics
Conditions: VDDA = VDDB = 1.8V; VDDMIC= 3.6V.
RL(Headphone) = 32 Ω, f = 1kHz, MCLK=12.88MHz, unless otherwise specified. Limits apply for TA = 25°C
Symbol
Parameter
Conditions
Typical
Limit
Units
VDD
A
B
2
6
ISD
Shutdown Current
µA
VDD
VDDMIC
0.2
0.2
1
1
Headset Detection Standby
MCLK off, Jack Insertion, IRQ enabled
5
5
µA
Mode
IDD
Active Current Normal Playback
Mode
fS = 48kHz, Stereo HP DAC On, HP
mA
On, POUT = 0mW. RL(HP) = 32Ω
Headphone Amplifier
Stereo RL = 32Ω, DAC Input, CPVVDD
1.8V, f=1020Hz, 22kHz BW,
=
=
28
mW
THD+N = 1% (QFN package),
PO
Output Power
Stereo RL = 16Ω, DAC Input, CPVVDD
1.8V, f=1020Hz, 22kHz BW,
33
mW
dB
THD+N = 1% (QFN Package)
Total Harmonic Distortion +
Noise
THD+N
RL = 32Ω, f=1020Hz, PO = 20mW
-80
VOUT = 1VRMS, DAC Input,
DAC_Gain = 0dB, HP_Gain = 0dB,
Digital Zero Input, f=1020Hz, A-
Weighted)
105
108
90
dB
dB
dB
SNR
Signal to Noise Ratio
VOUT = 1 VRMS, DAC Input,
DAC_Gain = 0dB, HP_Gain = 0dB,
Digital Zero Input, f=1020Hz, A-
Weighted, auto attenuate enabled,
fRIPPLE = 217Hz, VRIPPLE = 200mVP_P
Input Referred, HP_GAIN = 0dB
DAC Input, DAC_Gain = 0dB Ripple
Applied to VDD
Mono_Gain = 0dB Ripple Applied to
VDD
Stereo Single Ended Input Terminated,
Stereo_Gain = 0dB Ripple Applied
A
PSRR
Power Supply Rejection Ratio
Channel Crosstalk
90
90
dB
dB
A
to VDD
A
Left Channel to Right Channel, -
1dBFS, Gain = 0dB, f = 1020Hz
XTALK
70
dB
Interchannel Level Mismatch
Frequency Response
Pop up Noise
+/- 0.1
dB
dB
F = 20Hz ~ 20kHz
TBD
+0.1/-0.2
1
mVrms
DAC_Gain = 0dB, HP_Gain = 0dB,
fS=48kHz, OSRDAC = 128, A-
Weighted
eOS
Output Noise
4.4
uVRMS
Out of Band Noise Level
Output Offset Voltage
-60dB
±0.1
HP_Gain = 0dB, DAC_Gain= 0dB,
DAC Input
VOS
±0.5
mV
No Load, No Signal, Amp on
fS = 48kHz, Stereo DAC On, Amp On,
POUT = 0mW. RL = 32Ω
Power Consunption MP3 Mode
6
mW
NAU88L21 Datasheet Rev1.7
Page 7 of 69
Feb, 2020
Symbol
Parameter
Conditions
Typical
Limit
Units
+/-
0.02%
Fs Accuracy (44.1 / 48 kHz)
Pop and Click Noise
1
mVrms
dB
ADC
MIC Input, MIC_GAIN = 0dB, VIN =
0.8Vrms, f=1020Hz, fs = 48KHz,
Mono Differential Input
-91
-80
ADC Total Harmonic Distortion +
Noise
THD+N
MIC Input, MIC_GAIN = 30dB, Volume
= 0dB, Vin=28.5mVrms, f=1020Hz,
Digital Gain = 0dB, Mono
dB
Differential Input
Reference = VOUT(0dBFS), A-
Weighted, MIC Input, MIC Gain =
0dB,fs = 8kHz, Mono Differential
Input
102
101
dB
dB
SNR
Signal to Noise Ratio
Reference = VOUT(0dBFS), A-
Weighted, MIC Input, MIC Gain =
6dB,fs = 8kHz, Mono Differential
Input
VRIPPLE = 200mVPP applied to VDDA,
fRIPPLE = 217Hz, Input Referred,
MIC_GAIN = 0dB Differential Input
PSRR
Power Supply Rejection Ratio
Common Mode Rejection Ratio
90
65
dB
dB
Differential Input 100mVrms, PGA gain
= 20dB, frequency sweep from
20Hz to 20KHz
CMRR
FSADC
ADC Full Scale Input Level
Minimum Input Impedance
VDDA= 1.8V
1
VRMS
10
kOhm
Frequency Response
Pop up Noise
f = 20Hz ~ 20kHz
TBD
+0.1/-0.2
1
dB
mVrms
No Signal, ADC on
fs = 44.1kHz
Power Consumption
5
mW
MICBIAS
VBIAS
IOUT
eos
Output Voltage
Output Current
Output Noise
Programmable 1.8V to 3.0V in 6 steps
2.5
V
4
mA
Low noise mode, at 1kHz
47
nV/√Hz
Digital I/O
Parameter
Symbol
Comments/Conditions
Min
Max
Units
VDDB = 1.8V
VDDB = 3.3V
VDDB = 1.8V
VDDB = 3.3V
0.33*VDD
0.37*VDD
B
B
Input LOW level
Input HIGH level
Output HIGH level
VIL
V
0.57*VDD
0.63*VDD
0.9*VDDB
B
B
VIH
VOH
VOL
V
V
V
VDDB=1.8V
VDDB = 3.3V
ILoad= 1mA
0.95*VDD
B
VDDB = 1.8V
VDDB=3.3V
0.1*VDDB
Output LOW level
ILoad= 1mA
0.05*VDD
B
Recommended Operating Conditions
NAU88L21 Datasheet Rev1.7
Page 8 of 69
Feb, 2020
Condition
Symbol
Min
Typical
Max
Units
Digital I/O Supply Range
Analog Supply Range
Headphone Supply Range
Microphone Bias Supply Voltage
Temperature Range
VDD
VDD
VDD
VDDMIC
TA
B
A
A
1.62
1.62
1.62
3.0
3.3
1.8
1.8
3.3
3.6
1.98
1.98
3.6
V
V
V
V
°C
-40
+85
Absolute Maximum Ratings
Parameter
Min
Max
Units
Digital Supply Range
Digital I/O Supply Range
Analog Supply Range
Headphone Supply Range
Microphone Bias Supply Voltage
Voltage Input Digital Range
Voltage Input Analog Range
Junction Temperature, TJ
Storage Temperature
-0.3
-0.3
-0.3
-0.3
-0.3
2.2
4.0
2.2
2.2
4.0
V
V
V
V
V
V
V
°C
°C
DGND - 0.3
AGND - 0.3
-40
VDD + 0.3
VDD + 0.3
+150
-65
+150
CAUTION: Do not operate at or near the maximum ratings listed for extended periods. Exposure to such conditions may adversely
influence product reliability and result in failures not covered by warranty.
NAU88L21 Datasheet Rev1.7
Page 9 of 69
Feb, 2020
1. General Description
NAU88L21 is an ultra-low power CODECs that has both analog and digital blocks operating at 1.8V. This CODEC
includes DSP functions including DRCs (Dynamic Range Compression) and programmable biquad filters. Mic bias
supply is upgraded to support voltages up to 3V.
1.1 Inputs
The NAU88L21 provides analog inputs to acquire and process audio signals from microphones with high fidelity and
flexibility. There is a stereo input path that can be used to capture signals from single-ended or differential sources.
The channel has a fully differential programmable gain amplifier (PGA). The outputs of the PGA connect to the ADC.
The NAU88L21 also has an input for one digital microphone. The NAU88L21 provides a DMCLK, the clock signal for
the digital microphones.
The analog and the digital microphone inputs cannot be used simultaneously.
1.2 Outputs
NAU88L21 has one pair of ground-referenced Class G headphone outputs that are fed by two DACs. The headphone
amplifier has a gain range of -9dB to 0dB.
The Class G headphone amplifier is powered by the charge pump output voltages CPOUTP and CPOUTN. When
there is no loading the CPOUTP is equal to VDDA, and CPOUTN is equal to –VDDA.
This headphone output can also be used as a lineout.
1.3 ADC, DAC and Digital Signal Processing
The NAU88L21 has two independent high quality ADC’s and DACs. These are high performance 24-bit sigma-delta
converters, which are suitable for a very wide range of applications.
The ADCs and DACs have functions that individually support digital mixing and routing. The ADCs and DACs blocks
also support advanced digital signal processing subsystems that enable a very wide range of programmable signal
conditioning and signal optimizing functions. All digital processing is done with 24-bit precision to minimize processing
artifacts and maximize the audio dynamic range supported by the NAU88L21.
The ADCs and DACs digital signal process can support two-point dynamic range compressors (DRCs), programmable
biquad filters configurable for low pass filters, high pass filters, Notch filter, Bell, low shelf, and high shelf filters with
various gain, Q, and frequency controls. Two-point DRCs can be programmed to limit the maximum output level and/or
boost a low output level. The biquad filters can be configured as high pass filters intended for DC-blocking or low
frequency noise reduction, such as reducing unwanted ambient noise or “wind noise” on a microphone inputs.
1.4 Digital Interfaces
Command and control of the device is accomplished by using the I2C interface.
The digital audio I/O data streams transfer separately from command and control using either I2S or PCM audio data
protocols
These simple but highly flexible interface protocols are compatible with most commonly used serial data protocols, host
drivers, and industry standard I2S and PCM devices.
NAU88L21 Datasheet Rev1.7
Page 10 of 69
Feb, 2020
2. Power Supply
This NAU88L21 has been designed to operate reliably using a wide range of power supply conditions and power-
on/power-off sequences. Because of this, there are no special requirements for the sequence or rate at which the
various power supply pins change. Any supply can rise or fall at any time without harming the device. However, pops
and clicks may result from some sequences.
2.1 Power on and off reset
The NAU88L21 includes a power on reset circuit on chip. The circuit resets the internal logic control at VDDA supply
power up and this reset function is automatically generated internally when power supplies are too low for reliable
operation. The reset threshold is approximately 0.55Vdc and 1.0Vdc for VDDA. It should be noted that these values
are much lower than the required voltage for normal operation of the chip.
The reset is held on while the power levels for VDDA are below their respective thresholds. Once the power levels rise
above their thresholds, the reset is released. Once the reset is released, the registers are ready to be written to. It is
also important to note that all the registers should be kept in their reset state for at least 6µs.
An additional internal RC filter based circuit is added which helps the circuit respond for fast ramp rates (~10µs) and
generate the desired reset period width (~10µs at typical corner). This filter is also used to eliminate supply glitches
which can generate a false reset condition, typically 50ns.
For reliable operation, it is recommended to write any value to register upon power up. This will reset all registers to the
known default state.
Note that when VDDA are below the power on reset threshold, then the digital IO pins will go into a tri-state condition.
NAU88L21 Datasheet Rev1.7
Page 11 of 69
Feb, 2020
3. Input Path Detailed Descriptions
NAU88L21 has two low noise, high common mode rejection ratio analog microphone differential input. The microphone
inputs MICL+/- & MICR+/- which are followed by -1dB to 36dB PGA gain stages that have a fixed 12kOhm input
impedance.
Inputs are maintained at a DC bias of approximately ½ of the VDDA supply voltage. Connections to these inputs
should be AC-coupled by means of external DC blocking capacitors suitable for the device application.
The differential microphone input structure is essential in noisy digital systems where amplification of low-amplitude
analog signals is necessary such as in portable digital media devices and cell phones. Differential inputs are also
very useful to reduce ground noise in systems in which there are ground voltage differences between different chips
and components. When properly implemented, the differential input architecture offers an improved power-supply
rejection ratio (PSRR) and higher ground noise immunity.
3.1 Analog Microphone Inputs
The analog microphone inputs are routed to the FEPGA (Front End Programmable Gain Amplifier). The input stage
can be configured in different modes. The FEPGA gain can be varied from -1dB to 36dB in 1dB steps. The gain stage
has a fixed 12kOhm input impedance and can be individually enabled or disabled by using register.
NAU88L21 Datasheet Rev1.7
Page 12 of 69
Feb, 2020
FEPGA_gainL[0]
FEPGA_modeL[0]
-1 or 0 dB
FEPGA_modeL[1]
INP1L
0 to 36 dB
2 dB Steps
FEPGASEL[1],ACDC_ctrl[1]
FEPGA_gainL[5:1]
muteL
VREF
VREF
To Left
Audio
ADC
AUXL-
AUXL+
FEPGASEL[2],ACDC_ctrl[2]
INN1L/DMDATA
FEPGA_gainL[0]
FEPGA_modeL[1]
FEPGA_gainL[5:1]
-1 or 0 dB
FEPGA_modeL[0]
ADCDATA
To decimators
DMIC
Interface
DMSELECT
FEPGA_modeR[0]
FEPGA_gainL[0]
FEPGA_modeR[1]
-1 or 0 dB
INP1R
0 to 36 dB
FEPGASER[1],ACDC_ctrl[1]
2 dB Steps
FEPGA_gainR[5:1]
muteR
VREF
VREF
AUXR-
AUXR+
To Right
Audio
ADC
FEPGASER[2],ACDC_ctrl[2]
INN1R/DMCLK
FEPGA_gainR[0]
FEPGA_modeR[1]
FEPGA_gainR[5:1]
-1 or 0 dB
FEPGA_modeR[0]
Figure 1: Microphone Input Block Diagram with Registers
3.2 Digital Microphone Input
The MICL- and MICR- pins can be used for the digital microphone input. MICR- is the clock for the digital microphones
and the MICL- is the data in.
3.3 VREF
The NAU88L21 includes a mid-supply reference circuit that produces a voltage close to VDDA/2. This “VREF” pin
should be decoupled to VSS through an external bypass capacitor. Because VREF is used as a reference voltage
inside the NAU88L21, a large capacitance is required to achieve good power supply rejection at low frequency.
Typically, a value of 4.7µF should be used. This larger capacitance may introduce longer rise time of VREF and delay
the line output signal. However, a pre-charge circuit can be supported to help reduce the rise time. Due to the high
impedance of the VREF pin, it is important to use a low leakage capacitor. A pre-charge circuit has been implemented
to reduce the VREF rise time. Once charged, this can be disabled using to save power or prevent rapid changes in
level due to fluctuations in VDDA. The below Table 1 shows the VREF tie-off resister selection.
NAU88L21 Datasheet Rev1.7
Page 13 of 69
Feb, 2020
VMIDSEL VREF Resistor Selection VREF Impedance
00
01
10
11
Open, no resistor selected Open, no impedance installed
50kOhm
250kOhm
5kOhm
25kOhm
125kOhm
2.5kOhm
Table 1: VREF Impedance Selection
VMIDSEL
5, 50, 250 kΩ
VMIDEN
VDDA Pin
VREF Pin
VSSA Pin
Exterior
Connections
Pre-Charge
PDVMDFST
4.7µF
Register: BOOST
Register: BIAS_ADJ
Figure 2: VREF Circuitry
3.4 MIC Bias
The NAU88L21 provides one MIC bias pin, which can be used to power various microphones. The output level of MIC
Bias can be set between VDDA and 1.53 X VDDA using register settings.
It is recommended that the microphones do not draw more than 4mA from the MICBIAS pin. There are options for
connecting internal 2 Kohm resistor to the microphone and for low noise or low power mode. If MICBIAS is used in low
power mode, typically 100nF or 200nF capacitor can be used along with MIC Bias level at VDDA. In the low noise
mode, external 1uF or 4.7uF capacitor can be omitted by register settings when MIC Bias is used to power analog
microphones.
3.5 MIC detect
The MIC detect block can detect whether a microphone is connected between the MICBIAS output and the MICDET
pin. Either the internal 2kOhm resistor or an external 2kOhm resistor can be used to connect the microphone to the
MICDET pin and MICBIAS. See Figure 3, where the internal hookup of the MICDET and MICBIAS blocks is shown.
NAU88L21 Datasheet Rev1.7
Page 14 of 69
Feb, 2020
MicBias
MICBIAS
MICDET
Mic Detect
MicDet
Button Detect
Figure 3. Mic Detect and MICBIAS blocks
Application note: Adding a simple RC on the MICDET pin can help reduce noise coupling. These may be board level
related, or component related effects.
Figure 4. Reducing noise coupling effects
If the optional external 2KOhm resistor is used, then the internal 2K Ohm resistor (Between MICBIAS and MICDET)
should be disabled.
NAU88L21 Datasheet Rev1.7
Page 15 of 69
Feb, 2020
3.5.1 Key Release
This feature detects the edge case where the key press interrupt is not followed by a release interrupt until later on in
the sequence and clears the x11 register to prepare for further interrupts.
Write Register x11
to Clear
Wait for
Interrupt
Key Release
Figure 5. Key Release Flowchart
NAU88L21 Datasheet Rev1.7
Page 16 of 69
Feb, 2020
4. ADC Digital Block
ADC Digital Path
Volume
Control
-90~24dB
Soft Mute
Digital Audio
Interface
PCM
TX CH1
ƩΔ
Programmable
Biquad Filter
Two Points
DECM
ADC
DRC
I2S
Figure 6: ADC Digital Path
The ADC digital block takes the output of the 24-bit Analog-to-Digital converter and performs signal processing aimed
at producing a high quality audio sample stream to the audio path digital interface. The Figure 7 shows the various
steps associated with the ADC digital path.
Oversampling is used to improve noise and distortion performance; however this does not affect the final audio sample
rate. The oversampling rate configured between 32X and 256X using register settings.
The polarity of either ADC output signal can be changed independently on either ADC logic output as a feature
sometimes useful in management of the audio phase. This feature can help minimize any audio processing that may
be otherwise required as the data is passed to other stages in the system.
The full-scale input level is proportional to VDDA. For example, with a 1.8V supply voltage, the full-scale level is
1.0VRMS.
4.1 ADC Dynamic Range Compressors (DRC)
The ADC’s in the digital signal path each support a two-point dynamic range compressor (DRC) for advanced signal processing.
Each DRC can be programmed to limit the maximum output level and/or boost a low output level signal. The DRC’s function
consists of level estimation and static curve control.
4.1.1 Level Estimation
The NAU88L21 uses Peak level estimation that depends on the attack and decay time settings, which can be programmable by
register settings as shown in the Table 2.
NAU88L21 Datasheet Rev1.7
Page 17 of 69
Feb, 2020
BITS DRC_PK_COEF1_ADC DRC_PK_COEF2_ADC
0000 TS
63*TS
0001 3*Ts
0010 7*Ts
0011 15*Ts
0100 31*Ts
0101 63*Ts
0110 127*Ts
0111 255*Ts
127*Ts
255*Ts
511*Ts
1023*Ts
2047*Ts
4095*Ts
8191*Ts
Table 2: ADC Level Estimation - Attack and Decay Time Register Settings
Please note that Ts is the sampling time given by 1/(Sampling Frequency)
4.1.2 Static Curve
The DRC static curve supports up to five programmable sections as shown in the Figure 6.
Input (dB)
Knee 4
Knee 3
Knee 2
Knee 1
0dB
X
0dB
Y0
LMT
Y1
1
CMP
CMP2
Y2
Y3
EXP
Y4
NG
y
Figure 8: DRC Static Characteristic
Each section on the characteristic (labeled NG, EXP, CMP2, CMP1, and LMT) can be controlled by setting the slope
and knee point values, in their respective registers. The table below provides the corresponding register locations.
Static Curve Section
Slope
Knee Point
LMT
0, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1
CMP1
CMP2
0, 1/2, 1/4, 1/8, 1/16, 1
0, 1/2, 1/4, 1/8, 1/16, 1
0 to -31dB with -1dB step
0 to -63dB with -1dB step
EXP
NG
1, 2, 4
-18 to -81dB with -1dB step
-35 to -98dB with -1dB step
1, 2, 4, 8
Table 3: ADC DRC Static Curve control registers
The output Y values can be determined based on the slopes and knee points selected. Y1 is always equal to Knee 1,
as an initial and default condition.
Y1 = Knee 1
Y0 = Y1 - (Knee 1) * (LMT Slope)
Y2 = (Knee 2 - Knee 1) * (CMP1 Slope) + Y1
Y3 = (Knee 3 - Knee 2) * (CMP2 Slope) + Y2
Y4 = (Knee 4 - Knee 3) * (EXP Slope) + Y3
NAU88L21 Datasheet Rev1.7
Page 18 of 69
Feb, 2020
The attack time and decay time is programmable as shown in the Table 4. And the smooth knee filter can be also
enabled by register setting.
BITS
DRC_ATK_ADC_CH##
TS
3*Ts
7*Ts
15*Ts
DRC_DCY_ADC_CH##
63*TS
127*Ts
255*Ts
511*Ts
1023*Ts
2047*Ts
4905*Ts
8191*Ts
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
31*Ts
63*Ts
127*Ts
255*Ts
511*Ts
1023*Ts
2047*Ts
4095*Ts
8191*Ts
16383*Ts
32757*Ts
65535*Ts
Table 4: ADC Attack and Decay Time Register Settings
4.2 ADC Digital Volume Control
The digital volume control feature allows adjustment of the audio volume coming from ADC using a two-stage volume
control. This allows the gain to be adjusted from -103dB to +24dB. Also included is a mute value that will reduce the
output signal of the ADCs to zero.
4.3 ADC Programmable Biquad Filter
The NAU88L21 has 4 dedicated digital biquad filters. Two for the ADC path, and two for the DAC path. The biquad
filter is a second-order recursive linear filter with two poles and two zeros. Its transfer function is the Z-domain consists
of two quadratic functions:
ꢂ0 + ꢂ1ꢃ−1 + ꢂ2ꢃ−2
1 + ꢄ1ꢃ−1 + ꢄ2ꢃ−2
( )
ꢀ ꢁ =
The coefficients A1, A2, B0, B1, B2 are represented in the 3.16 format described below
2-16 Bit
2-4 Bit
2-1 Bit
Fraction Point
Sign Bit
S xx. xxxx xxxx xxxx xxxx
Each Biquad Coefficient has 19 bits in Sxx.16 format where
NAU88L21 Datasheet Rev1.7
Page 19 of 69
Feb, 2020
•
•
•
S is the sign bit (1 bit),
xx are integers ( 2bits)
16 fractional bits (16 bits)
2-1
S
x
x
2-16
1
2
16
Fractional bits
Sign bit Integer bits
Figure 9: Number format description for biquad filters coefficients.
4.4 Companding
Companding is used in digital communication systems to optimize signal-to-noise ratios with reduced data bit rates
using non-linear algorithms. The NAU88L21 supports the two main telecommunications companding standards on
both transmit and receive sides: A-law and µ-law. The A-law algorithm is primarily used in European communication
systems and the µ-law algorithm is primarily used by North America, Japan, and Australia.
4.5 Additional ADC Application Notes
The ADC clock polarity can be inverted if necessary by register setting. It is recommend to match ADC oversampling
rate with ADC clock rate as shown in the Table 5.
ADC_RATE
00(OSR=32)
01(OSR=64)
10(OSR=128)
11(OSR=256)
CLK_ADC_SRC
11(CODEC 1/8)
10(CODEC1/4)
01(CODEC 1/2)
00(CODEC CLK)
Table 5: ADC_RATE and CLK_ADC_SRC Pairs
NAU88L21 Datasheet Rev1.7
Page 20 of 69
Feb, 2020
5. DAC Digital Block
DAC Digital Path
Digital
Audio
Interface
PCM
Volume
Control
-90~24dB
Soft Mute
Auto Mute
Program
DAC
Mixer
mable
Biquad
Filter
ƩΔ
DAC
INTP
DRC
(Sidetone)
I2S
Figure 10: DAC Digital Path
The DAC digital block uses 24-bit signal processing to generate analog audio with a 16-bit digital sample stream input.
This block consists of a sigma-delta modulator, digital decimator/filter, programmable biquad filter, and a DRC. The full-
scale output level is proportional to VDDA. For example, with a 1.8V supply voltage, the full-scale level is 1.0 VRMS.
The oversampling rate of the DAC can be changed from 32x to 256x for improved audio performance at higher power
consumption. The DAC output signal polarity can be changed using register setting. This can help minimize any audio
processing that may be required as the data is passed from other stages of the system.
5.1 DAC Dynamic Range Control (DRC)
The DAC DRC functions in the same way as the ADC DRC explained in Section 4.1. However, different control
registers are used.
5.1.1 Level Estimation
The Table 6 shows the attack and decay times for the peak level estimation. And, the time constant Ts is the the
sampling time given by 1/(Sampling Frequency).
BITS
DRC_PK_COEF1_ADC DRC_PK_COEF2_ADC
0000 TS
63*TS
0001 3*Ts
0010 7*Ts
0011 15*Ts
0100 31*Ts
0101 63*Ts
0110 127*Ts
0111 255*Ts
127*Ts
255*Ts
511*Ts
1023*Ts
2047*Ts
4095*Ts
8191*Ts
Table 6: DAC Level Estimation Attack and Decay Time Register Settings
NAU88L21 Datasheet Rev1.7
Page 21 of 69
Feb, 2020
5.1.2 Static Curve
The DRC static curve supports five programmable sections, and slope and knee points can be configured as shown in
the Table 7.
Static Curve
Slope
Knee Point
Section
LMT
0, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1
0, 1/2, 1/4, 1/8, 1/16, 1
0, 1/2, 1/4, 1/8, 1/16, 1
1, 2, 4, 8
CMP1
CMP2
EXP
0 to -31dB with -1dB step
0 to -63dB with -1dB step
-18 to -81dB with -1dB step
-35 to -98dB with -1dB step
NG
1, 2, 4, 8
Table 7: DAC DRC Static Curve Control Registers
The Table 8 shows the attack and decay time for DRC. And, it needs to be carefully used combination with cross talk
function because DRC is the last blocks in the path after mixer. Small cross-talk signal might be filtered out by DRC.
The smooth knee function can be also enabled by register setting.
BITS
0000 TS
DRC_ATK_DAC
DRC_DCY_DAC
63*TS
0001 3*Ts
127*Ts
0010 7*Ts
255*Ts
0011 15*Ts
0100 31*Ts
0101 63*Ts
0110 127*Ts
0111 255*Ts
1000 511*Ts
1001 1023*Ts
1010 2047*Ts
1011 4095*Ts
1100 8191*Ts
511*Ts
1023*Ts
2047*Ts
4095*Ts
8191*Ts
16383*Ts
32757*Ts
65535*Ts
Table 8: DAC Static Curve Attack and Delay Time Register Settings
NAU88L21 Datasheet Rev1.7
Page 22 of 69
Feb, 2020
5.2 DAC Digital Volume Control, Mute and Channel selection
DACL and DACR both have separate digital volume controls that allow the user to adjust the gain from -103dB to
+24dB in 0.5dB steps as well as mutes. Left and Right channels can be adjusted separately and control is accessed
through register settings.
5.3 DAC Soft Mute
The soft mute function ramps the DAC digital volume down to zero when enabled. When disabled, the volume
increases to the register specified volume level for each channel. This feature provides a tool that is useful for using
the DAC without introducing pop and click sounds.
5.4 DAC Auto Attenuate
Auto-attenuate can greatly increase the perceived SNR during playback of silence. The last analog output stage is
attenuated such that the noise contribution of the preceding stages is eliminated. The use of auto-attenuate by
attenuating the analog output on a DAC path when the digital input represents a zero signal needs to be done
gradually in order to avoid audible pops due to sudden offset changes. It is desirable to slowly ramp down the gain of
the analog output stage to the maximum attenuation level. This function will be referred to as auto-attenuate. The auto-
attenuate feature is used to increase the Signal to Noise Ratio. In addition, the auto attenuate logic can be used to
attenuate the analog output manually,saving some software routines and allowing pop-less ramp up and down of the
analog outputs with little register writes.
The auto-attenuate function can be enabled manually or automatically. In the automatic mode, if both the left and right
channel receive 1024 consecutive samples of „0‟, then it will read and store the value of the headset driver volume
control into internal temporary registers and then attenuate the headset driver output by 1dB for every 128 samples,
until -54dB is reached (54 steps maximum). If , at any time, the I2S DACIN signal receives non-zero signal samples,
the headset output driver gain is increased by 1dB per step and in 1, 16, 32 or 128 samples per step (programmable
by register) until the gain will be stepped up until the original gain setting is reached. In the manual mode, once
enabled, it will immediately start saving the volume control into temporary registers and attenuate signals by 1dB for
every 128 samples untile -54dB is reached. If the manual attenuate is disabled, the gain will be fully recovered by 1dB
step in 1, 16, 32, or 128 samples per step.
5.5 DAC Path Digital Mixer with Side tone
The NAU88L21 implements a channel based digital mixer architecture. Each DAC outputs can be selected between
the different inputs. The ADC input channels, I2S channels are capable of being mixed into either output of the DAC.
The figure below shows a block diagram of how the mixer works along with the related registers.
NAU88L21 Datasheet Rev1.7
Page 23 of 69
Feb, 2020
REG0X30[7]
DAC_ST_SEL0
REG0X30[15:12]
ADC0_TO_DAC0_ST
-42dB~0dB/3dB & Mute
ADC CH 0
ADC CH 1
0
1
REG0X34[7:0]
DGAINL_DAC
-103dB~24dB/.5dB & Mute
DAC CH L
REG0X2F[15:8]
DAC1_TO_DAC0_ST
Ʃ
-96dB~24dB/.5dB & Mute
DAC CH0
DAC CH1
REG0X2F[7:0]
DAC0_TO_DAC1_ST
-96dB~24dB/.5dB & Mute
DAC CH R
Ʃ
REG0X30[6]
DAC_ST_SEL1
REG0X34[15:8]
DGAINR_DAC
-103dB~24dB/.5dB & Mute
ADC CH 1
ADC CH 0
0
1
DAC channel sidetone calculation:
DAC CH0 Mixer = DAC CH0 Data * DGAINL_DAC + DAC CH1 Data * DAC1_TO_DAC0_ST +
(ADC CH0 Data or ADC CH1 Data) * ADC0_TO_DAC0_ST
REG0X30[11:8]
ADC1_TO_DAC1_ST
-42dB~0dB/3dB & Mute
DAC CH1 Mixer = DAC CH1 Data * DGAINR_DAC + DAC CH0 Data * DAC0_TO_DAC1_ST +
(ADC CH1 Data or ADC CH0 Data) * ADC1_TO_DAC1_ST
Figure 11: DAC Path Digital Mixer with Side tone.
NAU88L21 Datasheet Rev1.7
Page 24 of 69
Feb, 2020
5.6 Companding
Companding is used in digital communication systems to optimize signal-to-noise ratios with reduced data bit rates
using non-linear algorithms. The NAU88L21 supports the two main telecommunications companding standards on
both transmit and receive sides: A-law and μ-law. The A-law algorithm is primarily used in European communication
systems and the μ-law algorithm is primarily used by North America, Japan, and Australia.
Companding converts 14 bits (μ-law) or 13 bits (A-law) to 8 bits using non-linear quantization resulting in 1 sign bit, 3
exponent bits and 4 mantissa bits. When the companding mode is enabled, 8 bit word operation must be enabled.
Sections 5.6.1 and 5.6.2 contain the compression equations set by the ITU-T G.711 standard and implemented in the
NAU88L21.
5.6.1 µ-law
( )
ꢅ ꢆ
ꢈ1 < ꢆ < 1
ꢇ = 255
| |
ln(1 + ꢇ × ꢆ )
=
,
ln(1 + ꢇ)
5.6.2 A-law
1
( )
ꢅ ꢆ
0 < ꢆ <
| |
ꢄ × ꢆ
ꢄ
=
,
(
( ))
1 + ln ꢄ
1
( )
ꢅ ꢆ
≤ ꢆ ≤ 1
| |
(1 + ln(ꢄ × ꢆ )
ꢄ
=
,
( )
(1 + ln ꢄ )
ꢄ = 87.6
NAU88L21 Datasheet Rev1.7
Page 25 of 69
Feb, 2020
6. Clocking and Sample Rates
The internal clocks for the NAU88L21 are derived from a common internal clock source. This master system clock can
set directly by the MCLK pin input or it can be generated from a Frequency Locked Loop (FLL) using the MCLK_PIN,
BCLK or FS as a reference. While most of the common audio sample rates can be derived directly from typical MCLK
frequencies, the FLL provides additional flexibility for a wide range of MCLK inputs or as a free running clock in the
absence of an external reference.
The figures below is a block diagram illustrating how the various register settings can be used to adjust/select the
MCLK, BCLK, FS, and ADC_CLK clock frequency.
SYSCLK_SRC
MCLK_SRC
MCLKI
VCO/2
0
1
MCLK=256*Fs
÷
0
1
1
0
CLK_ADC
÷
CLK_ADC_SRC
CLK_CODEC_SRC
CLK_ADC_PL
Register: CLK_DIVIDER
Figure 12: MCLK and ADC_CLK Frequency Selection
Bits
MCLK_SRC
0000 Divide by 1
0001 Invert
0010 Divide by 2
0011 Divide by 4
0100 Divide by 8
0101 Divide by 16
0110 Divide by 32
0111 Divide by 3
1001 Invert
1010 Divide by 6
1011 Divide by 12
1100 Divide by 24
1101 Divide by 48
1110 Divide by 96
1111 Divide by 5
Table 9: Register Settings
Bits CLK_ADC_SRC
00
01
10
11
Divide by 1
Divide by 2
Divide by 4
Divide by 8
NAU88L21 Datasheet Rev1.7
Page 26 of 69
Feb, 2020
Table 10: Register Settings
The internal clock frequency MCLK must be running at 256*Fs (Fs = sample rate in Hz) in order to achieve the best
performance. For example, when targeting 48 kHz sample rate audio, the MCLK must be set to 256*48k =
12.288MHz.
The OSR (over sampling rate) is defined as CLK_ADC frequency divided by the audio sample rate.
ꢌꢍꢎ_ꢄꢏꢌ
ꢉꢊꢋ =
ꢅꢐ
Available over-sampling rates are 32, 64, 128 or 256 as set in the register.
It should be noted that the OSR and Fs must be selected so that the max frequency of CLK_ADC is less than or equal
to 6.144MHz. When CLK_ADC is determined, ADC OSR should be set to provide appropriate down sampling
through digital filters.
Example 1:
To configure Fs = 48 kHz, MCLK = (256*Fs) = 12.288MHz, and CLK_ADC = 6.144MHZ
Set:
•
•
•
SYSCLK_SRC = MCLK
CLK_ADC_SRC = 1/2
ADC OSR = 128
Example 2:
To configure Fs = 16 kHz, MCLKI = 12.288MHz, and CLK_ADC = 4.096MHz
Set:
•
•
•
•
SYSCLK_SRC = MCLK
MCLK_SRC = 1/3
CLK_ADC_SRC = 1
ADC OSR = 256
6.1 I2S/PCM Clock Generation
In master mode, BCLK can be derived from MCLK via a programmable divider, and the FS can be derived from BCLK
via another programmable divider.
To select specific Fs values, both dividers must be set according to the block diagram and the equation below.
ꢂꢌꢍꢎ = ꢅꢐ × ꢑꢒꢓꢒ ꢔꢕꢖꢗꢓℎ × ꢘℎꢒꢖꢖꢕꢔꢐ
NAU88L21 Datasheet Rev1.7
Page 27 of 69
Feb, 2020
BCLK_DIV
MCLK
BCLK
FS
÷
÷
LRC_DIV
Register: I2S_PCM_CTRL2
Figure 13: BCLK and FS Frequency Selection
Bits BCLK_DIV
000
001
010
011
100
101
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Table 11: Register Settings
Bits
000
001
010
101
LRC_DIV
Divide by 256
Divide by 128
Divide by 64
Divide by 32
Table 12: Register Settings
Example 1:
If we want an Fs of 48 kHz and 16 bit data is to be sent to the I2S bus (2 channel)
•
•
•
BCLK = 48000*16*2 = 1.536MHz and MCLK = 48000*256 = 12.288MHz
Set BCLK_DIV = 1/8
Set LRC_DIV = 1/32
Or 32 bit data is to be sent
•
•
•
BCLK = 48000*32*2 = 3.073MHz and MCLK = 48000*256 = 12.288MHz
Set BCLK_DIV = 1/4
Set LRC_DIV = 1/64
Example 2:
If we want an Fs of 16 kHz and 16 bit data is to be sent to the I2S bus (2 channel)
•
•
•
BCLK = 16000*16*2 = 512kHz and MCLK = 16000*256 = 4.096MHz
Set BCLK_DIV = 1/8
Set LRC_DIV = 1/32
32 bit data is to be sent,
•
•
BCLK = 16000*32*2 = 1.024MHz and MCLK = 16000*256 = 4.096MHz
Set BCLK_DIV = 1/4
NAU88L21 Datasheet Rev1.7
Page 28 of 69
Feb, 2020
•
•
Set LRC_DIV = 1/64
Example 3:
If we want an Fs of 16 kHz and 32 bit data is to be sent to the I2S TDM bus (4 channels)
•
•
BCLK = 16000*32*4 = 2.048MHz and MCLK = 16000*256 = 4.096MHz
Set BCLK_DIV = 1/2
•
Set LRC_DIV = 1/128
6.2 Frequency Locked Loop(FLL)
FLL_CLK_REF_SRC
FLL_CLK_REF_DIV
MCLKI
BCLK
FS
00/01
10
FREF
÷
Frequency Detector
DLF
IDAC
DCO
11
Register: FLL4
Register: FLL3
FLL_INTEGER
Register: FLL3
FLL_RATIO
Register: FLL1
3rd Order ƩΔ
-1, 0, 1, 2
÷2
FLL_FRAC
Register: FLL2
0
1
MCLK_SRC
MCLK=256*FS
SYSCLK_SRC
Register: CLK_DIVIDER
Figure 14: FLL Block diagram
The integrated FLL can be used to generate a SYSMCLK from a wide variety of reference sources such as, MCLK,
BCLK, and FS or as a free running clock in the absence of an external reference. It can also create a stable SYSMCLK
from less stable sources due to its tolerance of jitter.
NAU88L21 Datasheet Rev1.7
Page 29 of 69
Feb, 2020
The FLL output frequency is determined by the following parameters.
•
•
•
•
•
FLL_RATIO based on input clock frequency
MCLK_SRC Divider
FLL_INTEGER: 10 bit Integer Input
FLL_FRAC: 16 bit Fractional Input
FLL_CLK_REF_DIV Divider
To determine these settings, the following output frequency equations are used.
1.
2.
FDCO = (FREF / FLL_CLK_REF_DIV) X FLL_INTEGER.FLL_FRAC X FLL_RATIO
MCLK = (FDCO X MCLK_SRC) / 2
Where FREF is the reference clock frequency for FLL, MCLK is the desired system frequency, and FDCO is the
frequency of DCO in decimal.
Example:
If the reference frequency (FREF) is 12MHz, the desired sampling rate (Fs) is 48 kHz, and SYSCLK = 256Fs, what are
the output frequency parameters?
Using these requirements, the following can be determined.
•
•
MCLK = 256 × 48kHz = 12.288MHz
Using Equation 2:
o
FDCO = 2 X MCLK / MCLK_SRC = 2 X 12.288MHz X MCLK_SRC
•
For FDCO to remain between 90MHz – 100MHz, MCLK_SRC must be chosen to be
1/4. This and other values for MCLK_SRC can be seen on the register tables.
o
FDCO = (2 × 12.288MHz) / (1/4) = 98.304MHz
•
Using Equation 1:
o
FLL_INTEGER.FLL_FRAC = FDCO X FLL_CLK_REF_DIV / (FREF X FLL_RATIO)
.
.
.
FDCO = 98.304MHz
FLL_RATIO = 1 because of FREF ≥ 512 kHz.
FLL_CLK_REF_DIV = 1 since FREF = MCLKI (12MHz)
o
FLL_INTEGER.FLL_FRAC = 98.304MHz X 1 / (12MHz X 1) = 8.192
•
Now retrieve or convert the parameter values into their corresponding HEX values
o
o
o
o
FLL_RATIO = 1 (for input clock frequency ≥ 512Khz)
MCLK_SRC = 1/4
FLL_INTEGER = 8
FLL_FRAC = 0.192 = 12583 (0.192 X 2^16) = 24’h3126
Please Note:
•
FLL_CLK_REF_DIV can be used to reduce the reference frequency for SYSMCLK by dividing the input by
1, 2, 4, or 8. Use this to ensure the reference clock frequency is less than or equal to 13.5MHz.
FDCO must be within the 90MHz – 100MHz or the FLL cannot be guaranteed across the full range of
operation.
•
•
FLL_FRAC must be set to 0 for low power mode.
•
FLL6.SDM_EN REG0X09[14] to create decimal part of frequency, if (DCO frequency)/(FLL input reference
frequency) is not a integer . If the ratio is integer, it still can be on for lower noise output but higher power
consumption.
•
•
When FLL uses free running mode, NAU88L25 needs to be set as a master in I2S_PCM_CTRL2.MS0
REG0X1D[3]=1
Set FLL6.CHB_FILTER_EN REG0X08[14] = ‘1’ to enable FLL Loop Filter. Select filter clock source by
FLL6.CHB_FILTER¬_EN REG0X08[13]. Select DCO input by FLL6.FILTER_SW REG0X08[12].
FLL6.CUTOFF500 REG0X09[13] & FLL6.CUTOFF600 REG0X09[12] can be used to define FLL cuttoff
frequency at 500KHz or 600KHz. 500KHz will provide the best FLL performance but consume more power.
NAU88L21 Datasheet Rev1.7
Page 30 of 69
Feb, 2020
•
set FLL6.FLL_FLTR_DITHER_SEL REG0X09[7:6] = ‘01’ or ‘10’ or ‘11’ as 1LSB / 2LSB / 3LSB random bits to
Randomize the number of Filter Output Bits to average out output noise. If ‘00’, there is no dither.
NAU88L21 Datasheet Rev1.7
Page 31 of 69
Feb, 2020
7. Control Interfaces
The NAU88L21 includes a serial control bus that provides access to all the device control registers, it may be
configured as a 2-wire interface that conforms to industry standard implementations of the I2C serial bus protocol.
7.1 2-Wire-Serial Control Mode (I2C Style Interface)
The 2-wire bus is a bidirectional serial bus protocol. This protocol defines any device that sends data onto the bus as a
transmitter (or master), and any device receiving data as the receiver (or slave). The NAU88L21 can function only as a
slave when in the 2-wire interface configuration.
7.2 2-Wire Protocol Convention
All 2-Wire interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDIO while
SCLK is HIGH. All 2-Wire interface operations are terminated by a STOP condition, which is a LOW to HIGH transition
of SDIO while SCLK is HIGH. A STOP condition at the end of a read or write operation places the device in a standby
mode.
An acknowledge (ACK), is a software convention used to indicate a successful data transfer. To allow for the ACK
response, the transmitting device releases the SDIO bus after transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDIO line LOW to acknowledge the reception of the eight bits of data.
Following a START condition, the master must output a device address byte. This consists of a 7-bit device address,
and the LSB of the device address byte is the R/W (Read/Write) control bit. When R/W=1, this indicates the master is
initiating a read operation from the slave device, and when R/W=0, the master is initiating a write operation to the slave
device. If the device address matches the address of the slave device, the slave will output an ACK during the period
when the master allows for the ACK signal.
9th
Clock
SCLK
SCLK
SDIO
SCLK
SDIO
SDIO
Receive
ACK
SDIO
Transmit
START
Figure 15: Valid START Condition
STOP
Figure 16: Valid Acknowledge
Figure 17: Valid STOP Condition
Please Note:
•
Sometimes, I2C needs to use level shifter between different supplies domains. During Acknowledge, such as
Figure 16, receiver side (CODEC) will pull low, and transmit side (MCU) is disable and pull high by pull high
resistor. Because NAU88L21 SDIO can sink 2mA by default setting (maximum up to 8mA,) shown as below
Figure 18, RPU1 and RPU2 need to be select such that total current VDDB/RPU1+ VDD_MCU/RPU2 during
Acknowledge should not be too large to exceed SDIO sinking capability.
NAU88L21 Datasheet Rev1.7
Page 32 of 69
Feb, 2020
Figure 18: Typical I2C level shifter circuit
7.3 2-Wire Write Operation
A Write operation consists of a three-byte instruction followed by one or more Data Bytes. A Write operation requires
a START condition, followed by a valid device address byte with R/W=0, a valid control address byte, data byte(s), and
a STOP condition.
The Device Address of the NAU88L21 is either 0x1B (CSB=0) or 0x54 (CSB=1). If the Device Address matches this
value, the NAU88L21 will respond with the expected ACK signaling as it accepts the data being transmitted to it.
Figure 19: Slave Address Byte, Control Address Byte, and Data Byte
NAU88L21 Datasheet Rev1.7
Page 33 of 69
Feb, 2020
SCLK
SDIO
0
0
1
1
0
1
1
0
A6 A5 A4 A3 A2 A1 A0
D8
D7 D6 D5 D4 D3 D2 D1 D0
A7
D15 D14 D13 D12 D11 D10 D9
A15 A14 A13 A12 A11 A10 A9 A8
S
T
O
P
A
C
K
A
C
K
S
T
A
R
T
A
C
K
A
C
K
Device Address = 1Bh
Control Register Address
16-bit Data Byte
R/W
Figure 20:2-Wire Write Sequence
7.4 2-Wire Read Operation
A Read operation consists of a three-byte Write instruction followed by a Read instruction of one or more data bytes.
The bus master initiates the operation issuing the following sequence: a START condition, device address byte with
the R/W bit set to “0”, and a Control Register Address byte. This indicates to the slave device which of its control
registers is to be accessed.
If the device address matches this value, the NAU88L21 will respond with the expected ACK signaling as it accepts the
Control Register Address being transmitted into it. After this, the master transmits a second START condition, and a
second instantiation of the same device address, but now with R/W=1.
After again recognizing its device address, the NAU88L21 transmits an ACK, followed by a two byte value containing
the 16 bits of data from the selected control register inside the NAU88L21.
During this phase, the master generates the ACK signaling with each byte transferred from the NAU85L40. If there is
no STOP signal from the master, the NAU88L21 will internally auto-increment the target Control Register Address and
then output the two data bytes for this next register in the sequence.
This process will continue as long as the master continues to issue ACK signaling. If the Control Register Address
being indexed inside the NAU88L21 reaches the value 0xFFFF (hexadecimal) and the value for this register is output,
the index will roll over to 0x0000. The data bytes will continue to be output until the master terminates the read
operation by issuing a STOP condition.
NAU88L21 Datasheet Rev1.7
Page 34 of 69
Feb, 2020
SCLK
A7 A6 A5 A4 A3 A2 A1 A0
0
0
1
1
0
1
1
0
A15 A14A13 A12 A11 A10 A9 A8
Control Register Address
A
C
K
S
T
A
R
T
A
C
K
A
C
K
Device Address = 1Bh
R/W
0
0
1
1
0
1
1
1
D6 D5 D4 D3 D2 D1 D0
D7
D15 D14 D13 D12 D11 D10 D9 D8
16-bit Data
S
T
A
R
T
A
C
K
A
C
K
N
S
T
O
P
A
C
K
2ND Device Address = 1Bh
R/W
Figure 21:2-Wire Read Sequence
7.5 Digital Serial Interface Timing
TSTAH
TSDIOS
TSDIOH
TSTAH
SDIO
SCLK
TSCKH
TFALL
TSCKL
TRISE
TSTAS
TSTOS
Figure 22: Two-wire Control Mode Timing
Symbol
Description
min
typ
max
unit
TSTAH
TSTAS
TSTOS
SDIO falling edge to SCLK falling edge hold timing in
START / Repeat START condition
600
-
-
ns
SCLK rising edge to SDIO falling edge setup timing in
Repeat START condition
600
600
-
-
-
-
ns
ns
SCLK rising edge to SDIO rising edge setup timing in
STOP condition
TSCKH
TSCKL
TRISE
SCLK High Pulse Width
600
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
SCLK Low Pulse Width
1,300
-
Rise Time for all 2-wire Mode Signals
Fall Time for all 2-wire Mode Signals
SDIO to SCLK Rising Edge DATA Setup Time
SCLK falling Edge to SDIO DATA Hold Time
-
-
300
300
-
TFALL
TSDIOS
TSDIOH
100
0
600
NAU88L21 Datasheet Rev1.7
Page 35 of 69
Feb, 2020
7.6 Software Reset
The NAU88L21 and all of its control registers can be reset to “default”, initial conditions by writing any value to
REG0X00 using the two-wire interface mode.
NAU88L21 Datasheet Rev1.7
Page 36 of 69
Feb, 2020
8. Digital Audio Interfaces
The NAU88L21 can be configured as either the master or the slave, and the Slave mode is the default if this bit is not
written. In master mode, NAU88L21 outputs both Frame Sync (FS) and the audio data bit clock (BCLK) and has full
control of the data transfer. In the slave mode, an external controller supplies BCLK and FS. Data is latched on the
rising edge of BCLK; SDO clocks out ADC data, while SDI clocks in data for the DACs.
When not transmitting data, SDO pulls LOW in the default state. Depending on the application, the output can be
configured to pull up or pull down. When the time slot function is enabled (see below), there are additional output state
modes including controlled tristate capability.
NAU88L21 supports six audio formats; right justified, left justified, I2S, PCMA, PCMB, and PCM Time Slot.
8.1 Right-Justified Audio Data
In right-justified mode, the LSB is clocked on the last BCLK rising edge before FS transitions. When FS is HIGH,
channel_0 data is transmitted and when FS is LOW, channel_1 data is transmitted. This can be seen in the image
below.
FS
BCLK
CHANNEL 0
CHANNEL 1
SDI/SDO
N-1 N-2
MSB
0
N-1 N-2
MSB
1
0
1
LSB
LSB
Figure 23: Right-Justified Audio Interface
8.2 Left-Justified Audio Data
In left-justified mode, the MSB is clocked on the first BCLK rising edge after FS transitions. When FS is HIGH,
channel_0 data is transmitted and when FS is LOW, channel_1 data is transmitted. This can be seen in the figure
below.
FS
CHANNEL 0
CHANNEL 1
BCLK
1
SDI/SDO
N-1 N-2
MSB
0
N-1 N-2
MSB
1
0
LSB
LSB
Figure 24: Left-Justified Audio Interface
8.3 I2S Audio Data
In I2S mode, the MSB is clocked on the second BCLK rising edge after FS transitions. When FS is LOW, left channel
data is transmitted and when FS is HIGH, right channel data is transmitted. This can be seen in the figure below.
NAU88L21 Datasheet Rev1.7
Page 37 of 69
Feb, 2020
FS
BCLK
LEFT CHANNEL
RIGHT CHANNEL
1
SDI/SDO
N-1
0
N-1
1
0
MSB
LSB
MSB
LSB
Figure 25: I2S Audio Interface
8.4 PCMA Audio Data
In the PCM A mode, channel 0 data is transmitted first followed immediately by channel 1 data. The channel 0 MSB
is clocked on the second BCLK rising edge after the FS pulse rising edge, and channel 1 MSB is clocked on the next
BCLK after the left channel LSB. This can be seen in the figure below.
FS
CHANNEL 0
CHANNEL 1
BCLK
1
SDI/SDO
N-1 N-2
MSB
0
N-1 N-2
1
0
LSB MSB
LSB
Figure 26: PCMA Audio Interface
8.5 PCMB Audio Data
In the PCMB mode, channel_0 data is transmitted first followed immediately by channel_1 data. Channel 0 MSB is
clocked on the first BCLK rising edge after the FS pulse rising edge, and channel_1 MSB is clocked on the next BCLK
after channel_0 LSB. This can be seen in the figure below.
FS
BCLK
CHANNEL 0
CHANNEL 1
1
SDI/SDO
N-1 N-2
MSB
0
N-1 N-2
1
0
LSB MSB
LSB
Figure 27: PCMB Audio Interface
8.6 PCM Time Slot Audio Data
The PCM time slot mode is used to allocate different time slots for ADC and DAC data. This can be useful when
multiple NAU88L21 chips or other devices are sharing the same audio bus. This will allow each chip‟s audio to be
delayed around each other without interference.
Normally, the DAC and ADC data are clocked immediately after the Frame Sync (FS), however, in the PCM time slot
mode; the audio data can be delayed by left / right channel PCM time slot start value in the registers.
NAU88L21 Datasheet Rev1.7
Page 38 of 69
Feb, 2020
These delays can be seen before the MSB in the figure below.
FS
BCLK
CHANNEL 0
CHANNEL 1
SDI/SDO
N-1 N-2
MSB
0
N-1 N-2
MSB
1
0
1
LSB
LSB
Figure 28: PCM Time Slot Audio Interface
The PMC time slot mode can be also used to swap channel 0 and channel 1 audio or cause both channels to use the
same data. When using the NAU88L25B with other driver chips, the SDO pin can be set to pull up or pull down or high
impedance during no transmission. Tri-stating on the negative edge allows the transmission of data by multiple sources
in adjacent timeslots with reduced risk of bus driver contention.
8.7 TDM I2S Audio Data
In I2S mode, the MSB is clocked on the second BCLK rising edge after FS transitions. When FS is LOW, channel_0
then channel_2 data is transmitted and when FS is HIGH, channel_1 then channel_3 data is transmitted. This is shown
in the figure below.
CHANNEL 0/
CHANNEL 2
CHANNEL 1/
CHANNLE 3
FS
BCLK
DO34
N-1
1
0
N-1
1
0
N-1
1
0
N-1
1
0
MSB
LSB MSB
LSB
MSB
LSB MSB
LSB
CH0
CH2
CH3
CH1
1 BCLK
Figure Figure 29: TDM I2S Audio Format
8.8 TDM PCMA Audio Data
In the PCMA mode, channel_0 data is transmitted first followed sequentially by channel_1, 2, and 3 immediately after.
The channel_0 MSB is clocked on the second BCLK rising edge after the FS pulse rising edge, and the subsequent
channel’s MSB is clocked on the next BCLK after the previous channel’s LSB. This is shown in the figure below.
NAU88L21 Datasheet Rev1.7
Page 39 of 69
Feb, 2020
1 BCLK
FS
BCLK
DO34
CHANNEL1
CHANNEL2
CHANNEL3
CHANNEL0
N-1
MSB
1
0
N-1
N-1
N-1
1
0
1
0
1
0
LSB
LSB
LSB
MSB
LSB
MSB
MSB
Figure Figure 30: TDM PCMA Audio Format
8.9 TDM PCMB Audio Data
In TDM PCMB mode, channel_0 data is transmitted first followed immediately by channel_1 data. The channel_0
MSB is clocked on the first BCLK rising edge after the FS pulse rising edge, and channel_1 MSB is clocked on the next
SCLK after channel_0 LSB.
1 BCLK
FS
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
BCLK
DO34
N-1
1
0
N-1
N-1
N-1
1
0
1
0
1
0
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB
Figure 31: TDM PCMB Audio Format
8.10TDM PCM Offset Audio Data
The PCM offset mode is used to delay the time at which DAC data is clocked. This increases the flexibility of the
NAU88L21 to be used in a wide range of system designs. One key application of this feature is to enable multiple
NAU88L21 or other devices to share the audio data bus, thus enabling more than four channels of audio. This feature
may also be used to swap channel data, or to cause multiple channels to use the same data.
Normally, the DAC data are clocked immediately after the Frame Sync (FS). In this mode audio data is delayed by a
delay count specified in the device control registers. The channel 0 MSB is clocked on the BCLK rising edge defined
by the delay count set in .This can be seen in the figure below.
NAU88L21 Datasheet Rev1.7
Page 40 of 69
Feb, 2020
FS
CHANNEL 3
CHANNEL2
CHANNEL 0
CHANNEL 1
BCLK
N-1
MSB
1
0
N-1
N-1
1
0
1
0
1
0
N-1
DO34
LSB
LSB
LSB
LSB
MSB
MSB
MSB
Figure
Figure 32: TDM PCM Offset Audio Format
NAU88L21 Datasheet Rev1.7
Page 41 of 69
Feb, 2020
9. Outputs
The NAU88L21 provides a pair of Class G ground-reference headphone outputs.
9.1 Class G Headphone Driver and Charge Pump
The NAU88L21 uses Class G speaker drivers powered by a charge pump for the headphones. For typical operation
with large and small signals the charge pump provides ±1.8V and ±0.9V, respectively. These output drivers are driven
by dedicated left and right DACs and can provide 30mW of power to a 32Ω load (in CSP package).
Three capacitors are needed to generate the negative voltage from the positive 1.8V. Typically, 2μF ceramic
capacitors are used.
•
•
•
The Fly Back capacitor is connected between pins CPCA and CPCB.
The Positive Output Decoupling capacitor is applied from pin CPVOUTP to ground (VSSCP).
The Negative Output Decoupling capacitor is applied from pin CPOUTN to ground (VSSCP).
The Class G will be turned on only if DAC signal level is bigger than the threshold in the register settings, and the peak
output can be also configured differently by register settings.
HSPGA0_VOL
DACR/CH1
HPR
HSPGA1_VOL
HPL
DACL/CH0
Figure 33: DAC to Headphone out path diagram
NAU88L21 Datasheet Rev1.7
Page 42 of 69
Feb, 2020
10. Control and Status Registers
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
SOFTWA
RE_RST
RESET_N_SO
FT_PRE
0
Reset the signal once write to the register.
CMLCK_ENB
PGA Common Mode Lock; ‘0’=enabled, ‘1’=disabled
DAC clock inversion in analog domain
1 = Enable
0 = Disable
CLK_DAC_IN
V
Right Channel DAC Enable
1 = ON
0 = OFF
Left Channel DAC Enable
1 = ON
0 = OFF
Right Channel ADC Enable
1 = ON
0 = OFF
Left Channel ADC Enable
1 = ON
RDACEN
LDACEN
RADCEN
LADCEN
0 = OFF
ADC Clock Enable
1 = ON
0 = OFF
DAC Clock Enable
1 = ON
0 = OFF
DCLK_ADC_E
N
ENA_CTR
L
1
DCLK_DAC_E
N
IMM Clock Enable
1 = ON
0 = OFF
I2S Clock Enable
1 = ON
0 = OFF
BIST Clock Enable
1 = ON
0 = OFF
OTP Clock Enable
1 = ON
CLK_IMM_EN
CLK_I2S_EN
CLK_BIST_EN
CLK_OTP_EN
0 = OFF
DRC Clock Enable
1 = ON
CLK_DRC_EN
0 = OFF
Default
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0x00ff
Master CLOCK sources
1 = ½ VCO_CLK
SYSCLK_SRC
0 = MCLK_PIN
ADC clock and DAC clock source selection
1 = from MCLK_PIN or ½ VCO_CLK
0 = from internal MCLK
CLK_CODEC_
SRC
Invert DAC Clock Polarity in digital domain
CLK_DAC_PL
CLK_ADC_PL
1= Invert
0= No change
Invert ADC Clock Polarity
1= Invert
0= No change
CLK_DIVI
DER
3
Scaling MCLK for GPIO clock divider
00 = 1/8
10 = 1/2
CLK_GPIO_S
RC
01 = MCLK/2
11 = 1/4
Scaling for ADC clock from CODEC_SRC Output
CLK_ADC_SR
C
00 = 1
01 = 1/2
11 = 1/8
10 = 1/4
Scaling for DCA clock from CODEC_SRC Output
CLK_DAC_SR
C
00 = 1
01 = 1/2
11 = 1/8
10 = 1/4
Scaling for MCLK from SYSCLK_SRC Output
0000 = 1
0001 = Inverted
0011 = 1/4
0101 = 1/16
MCLK_SRC
0010 = 1/2
0100 = 1/8
0110 = 1/32
0111 = 1/3
NAU88L21 Datasheet Rev1.7
Page 43 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
0
8
7
0
6
1
5
0
4
1
3
0
2
0
1
0
0
0
1000 = 1
1001 = inverted
1011 = 1/12
1101 = 1/48
1010 = 1/6
1100 = 1/24
1110 = 1/96
1111 = 1/5
Default
0
0
0
0
0
0
0
0x0050
Recommended default 000
FLLISELDAC
FLL: Increase the drive strength of the FLL DAC.
FLL Latch drive strength multiplier. This register is
using thermometer coding.
000 = Default
011 = 2x
Amp half bias-current selector. Amp bias current must
be reduced to 50% of its nominal value
00 = No Power Reduction
01 = Half Bias Current on FLL_BIAS_AMP2X
10 = Half Bias Current on FLL_BIAS_AMP
11 = Half Current on Both Amps
ICTRL_LATCH
ICTRL_V2I
001 = 1x
111 = 3x
4
FLL1
Manually force FLL to lock.
0 - Default Setting
1 - Force Lock Enabled
FLL_LOCK_B
P
0000001 = for input clock frequency ≥ 512Khz,
0000010 = for input clock frequency ≥ 256Khz
0000100 = for input clock frequency ≥ 128Khz
0001000 = for input clock frequency ≥ 64Khz
0010000 = for input clock frequency ≥ 32Khz
0100000 = for input clock frequency ≥ 8Khz
1000000 = for input clock frequency ≥ 4Khz
0x0000
FLL_RATIO
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
0
0
DOUT2VCO_
RSV
Default
Set the FLL VCO frequency in free-running
mode.
0x00bc
5
FLL2
FLL gain error
0000 = (Rec)
0010 = x2
0100 = x4
0110 = x6
1000 = x9
1010 = x12
1100 = x17
1110 = x20
0001 = x1
0011 = x3
0101 = x5
0111 = x8
1001 = x10
1011 = x16
1101 = x18
1111 = x24
GAIN_ERR
6
FLL3
FLL Reference CLK Source Select
00 & 01 = MCLK Pin
10 = BCLK_PIN
FLL_CLK_REF
_SRC
11 = LRC_PIN
FLL_INTEGER
FLL 10-bit integer input
0x0008
Default
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
HIGHBWE
High Bandwidth enable (0-disable, 1-enable)
FLL CLK_REF divider for accurate lock detection
000 = 1 (Rec)
010 = 1/4
100 = 1/16
FLL pre-scalar
00 = 1
001 = 1/2
011 = 1/8
101 = 1/32
FLL_CLK_REF
_DIV_4CHK
7
FLL4
FLL_CLK_REF
_DIV
01 = 1/2
11 = 1/8
10 = 1/4
FLL_N2
FLL 10-bit integer VCO divider for FLL Filter Clock
Default
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0x0010
Drive strength control block of FLL DAC enable
1 = Enable
0 = Disable
PDB_DACICT
RL
FLL Loop Filter enable
1 = Enable
0 = Disable
CHB_FILTER_
EN
1 = Select divided VCO clock based on register
FLL_N2
0 = Select REFCLK
8
FLL5
CLK_FILTER_
SW
1 = Select accumulator output
0 = Select filter output
FILTER_SW
FLL_LOCK_LE
NGTH
Set the time that FLL must stay within the lock-in
range before lock signal goes high
NAU88L21 Datasheet Rev1.7
Page 44 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
0
1
4
1
1
3
0
1
2
0
1
1
0
1
0
0
9
0
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Default
0
0x4000
FLL free-running mode enable
1 = Enable
DCO_EN
0 = Disable
FLL sigma delta modulator enable
1 = Enable
SDM_EN
0 = Disable
FLL 500Khz cutoff frequency enable
1 = Enable
CUTOFF500
0 = Disable
FLL 600Khz cutoff frequency enable
1 = Enable
0 = Disable
CUTOFF600
VREFSEL
Vref select
00 = 1.8V, 01 = 1.56V, 10 = 1.65V, 11 = 1.75V
0 = Disable
1 = Enable the function to check for 256
samples/frame sync
CHKFS256_E
N
9
FLL6
0 = Total samples per 4 frame sync
1 = Total samples per 8 frame sync
FS8X_SEL
Randomize the number of Filter output
00: no dither
FLL_FLTR_DI
THER_SEL
01: the LSB is a random bit
10: two LSBs are random bits
11: three LSBs are random bits
Randomize the number of bits for the input of SD
modulator
FLL_SD_DITH
ER_SEL
00: no dither
01: the LSB is a random bit
10: two LSBs are random bits
11: three LSBs are random bits
FLL dynamic lock range.
0000 = recommended
DLR
Default
0
0
0
1
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
0x6900
MSB potion of FLL 24-bit fractional input
FLL_FRAC[23:16]
0x0031
FLL_FRAC_H
A
B
FLL7
FLL8
Default
LSB potion of FLL 24-bit fractional input
FLL_FRAC[15:0]
0x26e9
FLL_FRAC_L
Default
MANU_SPKR_
DWN1R
Manual Access SPKR_DWN1R
0 = Pull Down
MANU_SPKR_
DWN1L
Manual Access SPKR_DWN1L
0 = Pull Down
Jack Detection Source 2 Configuration
00 = from JKDETL
JK_2_PL
JK_1_PL
01 = from Inverted JKDETL
10 = ignore the input and set to 0
11 = ignore the input and set to 1
Jack Detection Source 1 Configuration
00 = from GPIO2JD1
01 = from Inverted GPIO2JD1
10 = ignore the input and set to 0
11 = ignore the input and set to 1
Manual Restart Jack Detect de-bounce
Toggle this bit to 1 and
JACK_DE
T_CTRL
D
JD_RESTART
then to 0 to restart the
JACK DETECTION.
Jack Detect de-bounce bypass
DB_BP_MOD
E
1=Bypass the de-bounce circuit
0=Will enable de-bounce circuit (need to set
REG4B[0] = 1 to enable the CLK)
Insertion de-bounce time
2^( INSERT_DT +2) ms
INSERT_DT
EJECT_DT
Ejection de-bounce time
2^( EJECT_DT +2) ms
Jack Insertion/ Detection Logic polarity
0 = Invert the JACK Detection logic before de-bounce
circuit.
JKDET_PL
1 = Not inverted
NAU88L21 Datasheet Rev1.7
Page 45 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
0
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Jack Detection Logic control
JKDET_LOGI
C
1 = AND Gate
0 = OR Gate
0x0000
Default
0
0
0
0
0
0
0
Default IRQ Logic
1 = Active High
0 = Active Low
IRQ_PL
IRQ Pin Pull select
0 = Pull Down
1 = Pull Up
IRQ_PS
IRQ Pin Pull enable
1 = Enable
0 = Disable
IRQ_PE
IRQ_DS
IRQ_OE
1 = High drive current
0 = Low drive current
IRQ Output Enable
1 = Enable
0 = Disable
APR_EMRGE
NCY_SHTDW
N1_INTP_MA
SK
APR Emergency Shutdown Interrupt mask
1 = Mask the interrupt
0 = Unmask
RMS Interrupt mask
1 = Mask the interrupt
0 = Unmask
RMS_INTP_M
ASK
INTERRU
PT_MASK
F
KEY_RELEAS
E_INTP_MAS
K
Key Release Interrupt mask
1 = Mask the interrupt
0 = Unmask
Key Pressed Interrupt mask
1 = Mask the interrupt
0 = Unmask
KEY_INTP_M
ASK
Missing MCLK Detection Interrupt mask
1 = Mask the interrupt
0 = Unmask
MCLKDET_IN
TP_MASK
MIC Detection Interrupt mask
1 = Mask the interrupt
0 = Unmask
MIC_DET_INT
P_MASK
Jack Ejection Interrupt mask
1 = Mask the interrupt
0 = Unmask
JK_EJECT_IN
TP_MASK
Jack Insertion Interrupt mask
1 = Mask the interrupt
0 = Unmask
JK_DET_INTP
_MASK
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
APR_EMRG_
SHTDWN
APR Emergency Short Circuit Shutdown IRQ
Impedance Measurement Interrupt IRQ Status
RMS_INT
KEY_RELEAS
E_INT
KEY_INT
MCLK_DET_I
NT
Key Release for Key Detection IRQ Status
key Detection IRQ Status
Missing MCLK Detection IRQ Status
MIC Detection IRQ Status
MIC_DET_INT
Jack Ejection IRQ Status
00 = cleared state
01 = JACK ejection detected
10 = a jack detected was cleared due to a jack
insertion before write REG 11[3:2] to clear it.
11 = undefined
1
0
IRQ_STA
TUS
JACK_EJCT_I
RQ
Jack insertion IRQ status.
00=cleared state
JACK_DET_IR
Q
01= Jack insertion detected
10= a jack insertion interrupt was cleared due to jack
removal detection before write REG 11[1:0] to clear it.
11 = undefined
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read Only
NAU88L21 Datasheet Rev1.7
Page 46 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Write Operation:
Write bits[15:0] clear corresponding REG10 [15:0]
Write 1s to bits that you want to reset to 0, except
INT_CLR_KEY
_STATUS
INT_CLR_
KEY_STA
TUS
1
1
Bit0 or Bit1 = clear Jack insertion interrupt
Bit2 or Bit3 = clear Jack ejection interrupt
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read/Write
APR Emergency Short Circuit Shutdown Interrupt
Disable Control
1 = Disable
0 = Enable
APR_EMRG_
SHTDWN
_INT_DIS
RMS Impedance Measurement Interrupt Disable
control
1 = Disable
RMS_INT_DIS
0 = Enable
Key Release Interrupt Disable Control
1 = Disable
0 = Enable
KEY_RELEAS
E_INT_DIS
Key Interrupt Disable Control
1 = Disable
0 = Enable
Missing MCLK Detection Interrupt Disable Control
1 = Disable
0 = Enable
INTERRU
PT_DIS_C
TRL
(Write
Mode)
KEY_INT_DIS
1
2
MCLKDET_IN
T_DIS
MIC Detection/Headset Configuration interrupt disable
MIC_DET_INT
_DIS
control
1 = Disable
0 = Enable
Jack Ejection Interrupt Disable Control
1 = Disable
0 = Enable
JACK_EJCT_I
NT_DIS
Jack Insertion/Detection Interrupt Disable Control
1 = Disable
0 = Enable
JACK_DET_IN
T_DIS
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xffff
DMIC in Driving Select
DMIC_DS
1 = High drive current
0 = Low drive current
DMIC_SLEW
DMMIC Pin Slew Rate Selection
DMIC Clock Speed Selection:
CLK_DMIC_S
RC
1
3
DMIC_CT
RL
00 = ADC Clock
01 = ADC Clock / 2
10 = ADC Clock / 4 11 = ADC Clock / 8
Digital Microphone Mode Enable
1 = Enabled
DMICEN
0 = Disabled
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
GPIO2OUT
Programmable output to GPIO2
GPIO2JD1 Pull Select
GPIO2_PS
GPIO2JD1 Driving Select
1 = High drive current
0 = Low drive current
GPIO2JD1 Pin Pull enable
0 = Enable
GPIO2_DS
1
A
GPIO12_
CTRL
GPIO2_PE
GPIO2_OE
1 = Disable
GPIO2JD1 Output Enable
1 = Enable
0 = Disable
NAU88L21 Datasheet Rev1.7
Page 47 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
GPIO1 polarity inversion control
1 = Inverted logic of the CSB/GPIO1 function output
selected by GPIO1SEL
GPIO1POL
0 = non inverted
CSB/GPIO1 function select (input default)
000 = output 0
001 = JACK Status from the AND/OR logic
010 = SCLK_I
GPIO1SEL
011 = SD_I
100 = output divided FLL clock
101 = FLL locked condition (logic 1 = PLL locked)
110 = SD_O
111 = OSC_CLK
GPIO1CSB pull select
GPIO1_PS
GPIO1_DS
1 = High drive current
0 = Low drive current
GPIO1CSB Pin Pull enable
1 = Enable
GPIO1_PE
0 = Disable
GPIO1CSB Output Enable
1 = Enable
GPIO1_OE
0 = Disable
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
TDM Enable
TDM
1 = Enable
0 = Disable
PCM Offset Control in TDM
1 = Enable
0 = Disable
PCM_OFFSET
_MODE_CTRL
ADC audio data left-right ordering
0 = left ADC data in left phase of LRP
1 = left ADC data in right phase of LRP (left-right
reversed)
DAC right channel audio data left-right ordering
0 = right DAC data in right phase of LRP
1 = right DAC data in left phase of LRP (left-right
reversed)
DAC left channel audio data left-right ordering
0 = left DAC data in left phase of LRP
1 = left DAC data in right phase of LRP (left-right
reversed)
ADCPHS0
DACPHS1
DACPHS0
DAC left channel source under TDM mode
I2S :
000 : from Slot 0
010 : from Slot 2
100 : Reserved
110 : Reserved
001: from Slot 1
011: from Slot 3
101: Reserved
111 : Reserved
1
B
TDM_CTR
L
DAC_LEFT_S
EL
PCM:
000: from slot 0
010: from slot 2
100: from slot 4
110: from slot 6
001: from slot 1
011: from slot 3
101: from slot 5
111: from slot 7
DAC right channel source under TDM mode
I2S:
000 : from Slot 0
010 : from Slot 2
100 : Reserved
110 : Reserved
PCM:
001: from Slot 1
011: from Slot 3
101: Reserved
111 : Reserved
DAC_RIGHT_
SEL
000: from slot 0
010: from slot 2
100: from slot 4
110: from slot 6
001: from slot 1
011: from slot 3
101: from slot 5
111: from slot 7
ADC left channel source under TDM mode
00: from Slot 0
10: from slot 4
01: from Slot 2
11: from slot 6
ADC_TX_SEL
_L
NAU88L21 Datasheet Rev1.7
Page 48 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
0
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
ADC right channel source under TDM mode
I2S:
00: from Slot 1
10: from slot 5
01: from Slot 3
11: from slot 7
ADC_TX_SEL
_R
Default
0
0
0
0
0
0
0
0x0000
DAC companding mode control
00 = Off (normal linear operation)
01 = Reserved
DACCM0
10 = U-law companding
11 = A-law companding
ADC companding mode control
00 = Off (normal linear operation)
01 = Reserved
10 = U-law companding
11 = A-law companding
DAC audio data input option to route directly from
ADC data stream
0 = No pass through, normal operation
1 = ADC output data stream routed to DAC input data
path
ADCCM0
ADDAP0
8-bit word enable for companding mode of operation
0 = Normal operation (no companding)
1 = 8-bit operation for companding mode
uLaw offset
0 = 1’s complement
1 = 2’s complement
CMB8_0
UA_OFFSET
BCP0
1
C
I2S_PCM_
CTRL1
Bit clock phase inversion option for BCLK
0 = Normal phase
1 = Input logic sense inverted
PCMA and PCMB left/right word order control
0 = Right Justified/Left Justified/I2S/PCMA mode
1 = PCMB Mode Enable: MSB is valid on 1st rising
edge of BCLK after rising edge of FS
Port Word length (24-bits default) of audio data stream
00 = 16-bit word length
LRP0
WLEN0
01 = 20-bit word length
10 = 24-bit word length
11 = 32-bit word length
Port Audio interface data format (default setting is I2S)
00 = Right justified
AIFMT0
01 = Left justified
10 = Standard I2S format
11 = PCMA or PCMB audio data format option
Default
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0x000a
I2S tri state
I2S_TRI
0 = Normal mode
1 = Output high Z
I2S driving enable
0 = Normal mode
1 = Always out
LRC divide coefficient setting
00 = 1/256
10 = 1/64
I2S_DRV
LRC_DIV
01 = 1/128
11 = 1/32
0 = Only PCM_A_MODE or PCM_B_MODE
(STEREO Only) can be used when PCM Mode is
selected
1 = Time slot function enable for PCM mode
Without TDM mode
0 = Drive the full Clock of LSB
1 = Tri-State the 2nd half of LSB
0 = Use I2S_PCM_CTRL.WLEN to select Word
Length
1 = PCM Select 8-bit word length
Reserved to 0
PCM_TS_EN0
TRI0
1
D
I2S_PCM_
CTRL2
PCM8BIT0
PCM_TS_SEL
ADCDAT0_PE
ADCDAT IO Pull Enable
1 = Enable
0 = Disable
ADCDAT IO Pull Up/Down Enable
1 = Pull Up
ADCDAT0_PS
0 = Pull Down
NAU88L21 Datasheet Rev1.7
Page 49 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
0 = ADCDAT is not always out (when no data out,
ADCOUT pin becomes high)
1 = ADCDAT always out
Master/Slave Mode Enable
0 = Slave Mode
ADCDAT0_OE
MS0
1 = Master Mode
BCLK DIVIDE Setting from MCLK frequency
000 = 1
010 = 1/4
100 = 1/16
0x8010
001 = 1/2
011 = 1/8
101 = 1/32
BCLKDIV
Default
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Triggers short frame sync signal if frame sync is less
than
FS_ERR_CMP
_SEL
00 = 252 x MCLK
10 = 254 x MCLK
01 = 253 x MCLK
11 = 255 x MCLK
Short Gram Sync detection logic Enable
0 = Enable
1 = Disable
1
E
LEFT_TIM
E_SLOT
DIS_FS_SHO
RT_DET
Left channel PCM time slot start value
Or PCM TDM Offset Mode Slot start value
TSLOT_L0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Right channel PCM time slot start value
Or unused for PCM TDM Offset Mode
0x0000
TSLOT_R0
1
F
RIGHT_TI
ME_SLOT
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIQ0_A1_L
Program ADC BIQ_A1 parameter Bit[15:0]
2
1
BIQ0_
COF1
Default
0x0000
BIQ0_A1_H
Program ADC BIQ_A1 parameter Bit[18:16]
2
2
BIQ0_
COF2
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
BIQ0_A2_L
Program ADC BIQ_A2 parameter Bit[15:0]
2
3
BIQ0_
COF3
Default
0x0000
BIQ0_A2_H
Program ADC BIQ_A2 parameter Bit[18:16]
2
4
BIQ0_CO
F4
Default
0x0000
BIQ0_B0_L
Program ADC BIQ_B0 parameter Bit[15:0]
2
5
BIQ0_
COF5
Default
0x0000
BIQ0_B0_H
Program ADC BIQ_B0 parameter Bit[18:16]
2
6
BIQ0_
COF6
Default
0x0000
BIQ0_B1_L
Program ADC BIQ_B1 parameter Bit[15:0]
2
7
BIQ0_
COF7
Default
0x0000
BIQ0_B1_H
Program ADC BIQ_B1 parameter Bit[18:16]
2
8
BIQ0_CO
F8
Default
0x0000
BIQ0_B2_L
Program ADC BIQ_B2 parameter Bit[15:0]
2
9
BIQ0_
COF9
Default
0x0000
BIQ ADC Path Enable
1 : Enable
BIQ0_EN
0 : Disable
2
A
BIQ0_CO
F10
BIQ0_B2_H
Program ADC BIQ_B2 parameter Bit[18:16]
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
In Non-DMIC Mode:
0 : Latch Left Channel Analog data input into the Left
Channel Filter
1: Latch Right Channel Analog data input into the
Left Channel Filter
In DMIC Mode:
0 = Left Channel in Rising Edge
1 = Left Channel in Falling Edge
In Non-DMIC Mode:
ADC_L_SRC
2
B
ADC_RAT
E
ADC_R_SRC
0 : Latch Right Channel Analog data input into the
Right Channel Filter
NAU88L21 Datasheet Rev1.7
Page 50 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
1: Latch Left Channel Analog data input into the
Right Channel Filter
In DMIC Mode:
0 = Right Channel in Falling Edge
1 = Right Channel in Rising Edge
Generating 2.048MKHz based on the Sample Rates
SMPL_RATE
GAINCMP
000 = 48k SR(default)
110 = 96k SR
001 = 32k SR
111 = 192 SR
Reserved, always set to zero
ADC SINC Down selection
ADC_RATE
00 = Down 32
10 = Down 128
0x0002
01 = Down 64
11 = Down 256
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
CICCLP_OFF
CIC_GAIN_AD
J
Recommended default 1
For fine tuning the DAC output
2
C
DAC_CTR
L1
DAC oversample rate selection
DAC_RATE
000 = 64
010 = 128
0x0082
001 = 256
100 = 32
Default
Reserved
Reserved to 0
Number of bits of dithering on SD modulator. Each
level increments dithering by 1 bit
0000 = No dithering
0010 = 2
0100 = 4
0110 = 6
1000 = 8
1010 = 10
1100 = 12
1110 = 14
0001 = 1
0011 = 3
0101 = 5
0111 = 7
1001 = 9
1011 = 11
1101 = 13
1111 = 15
SDMOD_DITH
ER
2
D
DAC_TRL
2
Reserved
Reserved to 0
Reserved
Reserved to 0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
DAC CH1 to DAC CH0 crosstalk suppression sidetone
selection. Step size is 0.5db
0xff = +24dB
0xfe = +23.5dB
▼
DAC1_TO_DA
C0_ST
0xcf = 0dB
▼
0x43 = -70dB
0x42 = Reserved
▼
0x0f = Reserved
0x0e = Mute
0x00 = Mute
2
F
DAC_DGA
IN_CTRL
DAC CH0 to DAC CH1 crosstalk suppression sidetone
selection. Step size is 0.5db
0xff = +24dB
0xfe = +23.5dB
▼
0xcf = 0dB
▼
DAC0_TO_DA
C1_ST
0x43 = -70dB
0x42 = Reserved
▼
0x0f = Reserved
0x0e = Mute
0x00 = Mute
0x0000
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NAU88L21 Datasheet Rev1.7
Page 51 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
ADC to DAC CH0 Sidetone selection. Step size is 3db
0000 = mute
0001 = -42db
▼
ADC_TO_DAC
_ST0
1110 = -3dB
1111 = 0dB
ADC to DAC CH1 Sidetone Attenuation. Step size is
3db
0000 = mute
0001 = -42db
▼
1110 = -3dB
1111 = 0dB
ADC_TO_DAC
_ST1
3
0
ADC_DGA
IN_CTRL
0 = Select ADC CH0 as the side tone source of the
DAC_ST_SEL
0
DAC CH0
1 = Select ADC CH1 as the side tone source of the
DAC CH0
0 = Select ADC CH1 as the side tone source of the
DAC_ST_SEL
1
DAC CH1
1 = Select ADC CH0 as the side tone source of the
DAC CH1
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Analog Attn Mute Step
00 = 128 sample
10 = 16 sample
PGA_SMUTE_
STEP
01 = 32 sample
11 = 1 sample
DAC Slow Soft Unmute Enable
1 = Enable (512 MCLK per step soft unmute)
0 = Disable (16 MCLK per step soft unmute)
DAC Zero Crossing Enable
1 = Enable
0 = Disable
DAC_SLOW_
UM
DAC_ZC_UP_
EN
Auto mute enable
Generate null output to analog circuitry when 1024
consecutive zeros are detected. De-assert as soon
as first non-zero sample is detected.
Auto mute control
1 = Either Ch0 or Ch1 must have 1024 consecutive
zero samples
AMUTE_EN
3
1
AMUTE_CTRL
MUTE_CT
RL
0 = Both DAC channels must have 0 values for 1024
samples before AMUTE turns on
Soft mute enable
1 = Gradually lower DAC volume to zero
0 = Gradually increase DAC volume to volume register
setting
SMUTE_EN
ADC Zero Crossing Enable
1 = Enable
0 = Disable
ADC_ZC_UP_
EN
ADC Soft mute Enable
1 = Enable
0 = Disable
ADC_SMUTE_
EN
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Headphone diver manual attn Enable(Enable
HSPGA_ATTN_EN and AMUTE_EN)
1 = Enable
HSPGA_ATTN
_EN
0 = Disable
Headphone driver Auto attn Enable(Enable
HSPGA_ATTN_AUTO_MODE, and AMUTE_EN)
1 = Enable
HSPGA_ATTN
_AUTO_MOD
E
0 = Disable
MUTE_HSPG
HSPGA Right Channel Manual Mute
1 = Mute
HSPGA Left Channel Manual Mute
1 = Mute
3
2
HSVOL_C
TRL
A2
MUTE_HSPG
A1
Left Channel Headphone driver Volume control;
HSPGA1_VOL
00 = 0dB
10 = -6dB
01 = -3dB
11 = -9dB
Right Channel Headphone driver Volume control;
HSPGA2_VOL
00 = 0dB
10 = -6dB
0x0000
01 = -3dB
11 = -9dB
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NAU88L21 Datasheet Rev1.7
Page 52 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
DAC Right Volume control. Expressed as a gain or
attenuation in 0.5db steps
0xff = +24dB
0xfe = +23.5dB
ꢀ
▼
0xcf = 0dB
DGAINR_DAC
▼
0x43 = -70dB
0x42 = Reserved
▼
0x0f = Reserved
0x0e = Mute
0x00 = Mute
3
4
DACR_CT
RL
DAC Left Volume control. Expressed as a gain or
attenuation in 0.5db steps
0xff = +24dB
0xfe = +23.5dB
ꢀ
▼
0xcf = 0dB
DGAINL_DAC
▼
0x43 = -70dB
0x42 = Reserved
▼
0x0f = Reserved
0x0e = Mute
0x00 = Mute
Default
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0xcfcf
ADC Right Volume control. Expressed as a gain or
attenuation in 0.5db steps
0xff = +24dB
0xfe = +23.5dB
ꢀ
▼
0xcf = 0dB
DGAINR_ADC
▼
0x43 = -70dB
0x42 = Reserved
▼
0x0f = Reserved
0x0e = Mute
0x00 = Mute
3
5
ADC_DGA
IN_CTRL1
ADC Left Volume control. Expressed as a gain or
attenuation in 0.5db steps
0xff = +24dB
0xfe = +23.5dB
ꢀ
▼
0xcf = 0dB
DGAINL_ADC
▼
0x43 = -70dB
0x42 = Reserved
▼
0x0f = Reserved
0x0e = Mute
0x00 = Mute
Default
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0xcfcf
ADC channel DRC enable
1 = Enable
0 = Disable
DRC_ENA_AD
C
ADC DRC Knee point 2 setting, increments in
-1dB steps
0x00 = 0dB
0x01 = -1dB
▼
DRC_KNEE2_
IP_ADC
0x3E = -62dB
0x3F = -63dB
ADC_DRC
_KNEE_IP
12
3
6
DRC_SMTH_E
NA_ADC
1= ADC Smooth filter enable
ADC DRC Knee point 1 setting, increments in
-1dB steps
0x00 = 0dB
0x01 = ꢀ1dB
▼
DRC_KNEE1_
IP_ADC
0x1E = -30dB
0x1F = -31dB
NAU88L21 Datasheet Rev1.7
Page 53 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
0
1
4
0
1
3
0
1
2
1
1
1
0
1
0
1
9
0
8
7
1
6
0
5
0
4
0
3
0
2
1
1
1
0
0
Default
0
0x1486
ADC DRC Knee point 4 setting, increments in
-1dB steps
0x00 = -35dB
0x01 = -36dB
DRC_KNEE4_
IP_ADC
▼
0x3E = -97dB
0x3F = -98dB
ADC DRC Knee point 3 setting, increments in
-1dB steps
0x00 = -18dB
0x01 = -19dB
▼
ADC_DRC
_KNEE_IP
34
3
7
DRC_KNEE3_
IP_ADC
0x3E = -80dB
0x3F = -81dB
0x0F12
Default
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
0
ADC DRC Noise Gate Slope
DRC_NG_SLP
_ADC
00 = 1:1
01 = 2:1
11 = 8:1
10 = 4:1 (default)
ADC DRC Expansion Slope
DRC_EXP_SL
P_ADC
00 = 1:1
01 = 2:1
11 = Reserved
10 = 4:1 (default)
ADC DRC Compressor Slope (lower region)
000 = 0
010 = 1:4
100 = 1:16
111 = 1 (default)
001 = 1:2
011 = 1:8
101-110 = Reserved
DRC_CMP2_S
LP_ADC
3
8
ADC_DRC
_SLOPES
ADC DRC Compressor Slope (higher region)
000 = 0
010 = 1:4
100 = 1:16
111 = 1 (default)
ADC DRC Limiter Slope
000 = 0
001 = 1:2
011 = 1:8
101-110 = Reserved
DRC_CMP1_S
LP_ADC
001 = 1:2
011 = 1:8
101 = 1:32
111 = 1 (default)
DRC_LMT_SL
P_ADC
010 = 1:4
100 = 1:16
110 = 1:64
0x25FF
Default
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
ADC DRC Peak detection attack time
Ts = 1/SMPL_RATE
0000 = Ts
0001 = 3*Ts
DRC_PK_COE
F1_ADC
0010 = 7*Ts
0100 = 31*Ts
0110 = 127*Ts
1xxx reserved
0011 = 15*Ts
0101 = 63*Ts
0111 = 255*Ts
ADC DRC Peak detection release time
Ts = 1/ SMPL_RATE
0000 = 63*Ts
0010 = 255*Ts
0100 = 1023*Ts
0110 = 4095*Ts
1xxx reserved
0001 = 127*Ts
0011 = 511*Ts
0101 = 2047*Ts
0111 = 8191*Ts
DRC_PK_COE
F2_ADC
ADC DRC Attack time
Ts = 1 SMPL_RATE
0000 = Ts
3
9
ADC_DRC
_ATKDCY
0001 = 3*Ts
0010 = 7*Ts
0100 = 31*Ts
0011 = 15*Ts
0101 = 63*Ts
0111 = 255*Ts
1001 = 1023*Ts
1011 = 4095*Ts
DRC_ATK_AD
C
0110 = 127*Ts
1000 = 511*Ts
1010 = 2047*Ts
1100 = 8191*Ts
ADC DRC Decay time
Ts = 1/Error! Reference source not found.
0000 = 63*Ts
0010 = 255*Ts
0100 = 1023*Ts
0110 =4095*Ts
1000 = 16383*Ts
1010 = 65535*Ts
0x3457
0001 = 127*Ts
0011 = 511*Ts
0101 = 2047*Ts
0111 = 8191*Ts
1001 = 32757*Ts
DRC_DCY_AD
C
Default
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
1
3
A
DRC_ENA_DA
C
DAC channel DRC enable
1 = Enable. 0 = Disable
NAU88L21 Datasheet Rev1.7
Page 54 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
DRC DAC Knee point 2 setting, increments in
-1dB/step
0x00 = 0dB
0x01 = -1dB
DRC_KNEE2_
IP_DAC
▼
0x3E = -62dB
0x3F = -63dB
DRC_SMTH_E
NA_DAC
DRC DAC Smooth filter enable
1 = Enable. 0 = Disable
DRC DAC Knee point 1 setting, increments in
-1dB steps
DAC_DRC
_KNEE_IP
12
0x00 = 0dB
0x01 = -1dB
DRC_KNEE1_
IP_DAC
▼
0x1E = -30dB
0x1F = -31dB
Default
0
0
0
1
0
1
0
0
1
0
0
0
0
1
1
0
0x1486
DRC DAC Knee point 4 setting, increments in
-1dB steps
0x00 = -35dB
0x01 = -36dB
DRC_KNEE4_
IP_DAC
▼
0x3E = -97dB
0x3F = -98dB
DRC DAC Knee point 3 setting, increments in
-1dB steps
0x00 = -18dB
0x01 = -19dB
▼
DAC_DRC
_KNEE_IP
34
3
B
DRC_KNEE3_
IP_DAC
0x3E = -80dB
0x3F = -ꢀ1dB
0x0F12
Default
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
0
DAC Noise Gate Slope
00 =ꢀ1:1
10 = 4:1 (default)
DRC_NG_SLP
_DAC
01 = 2:1
11 = 8:1
DAC DRC Expansion Slope
DRC_EXP_SL
P_DAC
00 = 1:1
01 = 2:1
11 = 8:1
10 = 4:1 (default)
DAC Compressor Slope (lower region)
000 = 0
010 = 1:4
100 = 1:16
111 = 1 (default)
001 = 1:2
011 = 1:8
101-110 = Reserved
DRC_CMP2_S
LP_DAC
3
C
DAC_DRC
_SLOPES
DAC Compressor Slope (higher region)
000 = 0
010 = 1:4
100 = 1:16
111 = 1 (default)
DAC Limiter Slope
000 = 0
001 = 1:2
011 = 1:8
101-110 = Reserved
DRC_CMP1_S
LP_DAC
001 = 1:2 (default)
011 = 1:8
101 = 1:32
111 = 1
DRC_LMT_SL
P_DAC
010 = 1:4
100 = 1:16
110 = 1:64
0x25F9
Default
0
0
1
0
0
1
0
1
1
1
1
1
1
0
0
1
DAC Peak detection attack time
Ts = 1/ SMPL_RATE
0000 = Ts
0001 = 3*Ts
DRC_PK_COE
F1_DAC
0010 = 7*Ts
0100 = 31*Ts
0110 = 127*Ts
1xxx reserved
0011 = 15*Ts
0101 = 63*Ts
0111 = 255*Ts
3
D
DAC_DRC
_ATKDCY
DAC Peak detection release time
Ts = 1/ SMPL_RATE
0000 = 63*Ts
0001 = 127*Ts
DRC_PK_COE
F2_DAC
0010 = 255*Ts
0100 = 1023*Ts
0110 = 4095*Ts
1xxx reserved
0011 = 511*Ts
0101 = 2047*Ts
0111 = 8191*Ts
NAU88L21 Datasheet Rev1.7
Page 55 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
DAC Attack time
Ts = 1/ SMPL_RATE
0000 = Ts
0001 = 3*Ts
0010 = 7*Ts
0100 = 31*Ts
0110 = 127*Ts
1000 = 511*Ts
1010 = 2047*Ts
1100 = 8191*Ts
0011 = 15*Ts
0101 = 63*Ts
0111 = 255*Ts
1001 = 1023*Ts
1011 = 4095*Ts
DRC_ATK_DA
C
DAC Decay time
Ts = 1/ SMPL_RATE
0000 = 63*Ts
0001 = 127*Ts
0011 = 511*Ts
0101 = 2047*Ts
0111 = 8191*Ts
1001 =32757*Ts
DRC_DCY_DA
C
0010 = 255*Ts
0100 = 1023*Ts
0110 = 4095*Ts
1000 = 16383*Ts
1010 = 65535*Ts
Default
BIQ1_A1_L
Default
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0x3457
Program DAC BIQ_A1 parameter Bit[15:0]
4
1
BIQ1_
COF1
0x0000
BIQ1_A1_H
Program DAC BIQ_A1 parameter Bit[18:16]
4
2
BIQ1_
COF2
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
BIQ1_A2_L
Program DAC BIQ_A2 parameter Bit[15:0]
4
3
BIQ1_
COF3
Default
0x0000
BIQ1_A2_H
Program DAC BIQ_A2 parameter Bit[18:16]
4
4
BIQ1_CO
F4
Default
0x0000
BIQ1_B0_L
Program DAC BIQ_B0 parameter Bit[15:0]
4
5
BIQ1_
COF5
Default
0x0000
BIQ1_B0_H
Program DAC BIQ_B0 parameter Bit[18:16]
4
6
BIQ1_
COF6
Default
0x0000
BIQ1_B1_L
Program DAC BIQ_B1 parameter Bit[15:0]
4
7
BIQ1_
COF7
Default
0x0000
BIQ1_B1_H
Program DAC BIQ_B1 parameter Bit[18:16]
4
8
BIQ1_CO
F8
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
BIQ1_B2_L
Program DAC BIQ_B2 parameter Bit[15:0]
4
9
BIQ1_
COF9
Default
0x0000
BIQ DAC Path Enable
1 : Enable
0 : Disable
BIQ1_EN
4
A
BIQ1_CO
F10
BIQ1_B2_H
Program DAC BIQ_B2 parameter Bit[18:16]
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
NAU88L21 Datasheet Rev1.7
Page 56 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Class G function clock divider
CLASSG_CLK
_SRC
00 = Clock 2Mhz
10 = MCLK
01 = 1/3 MCLK
11 = Disable CLK
Define the number of milliseconds when a Class G
mode signal to go low after it has been below the
threshold
CLASSG_TIM
ER
000001 = 1ms
000100 = 8ms
010000 = 32ms
000010 = 2ms
001000 = 16ms
100000 = 64ms
Threshold for DAC signal level comparison to
generate the Class G mode signal
4
B
CLASSG_
CTRL
CLASSG_THR
SLD
00 = 1/16 Full
Scale
01 = 1/8 Full Scale
10 = 3/16 Full
Scale
11 = 1/4 Full Scale
Class G Compare path Enable bit. Each Bit enables
according DAC path
Bit 0 = Left DAC
CLASSG_CM
P_EN
Bit 1 = Right DAC
Class G function enable
1 = Enable
CLASSG_EN
0 = Disable
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Reserved
Reserved to zero
Impedance measurement threshold to avoid false
detection. Each increase raises the floor of the ADC
requiring higher signal levels before activation.
0x00 = [23:0] Full
Range
0x01 = [23:1]
▼
IMM_THRESH
OLD
0x14 = [23:20]
0x15 = [23:21]
Signal level of the 23Hz sine wave generation
for impedance measurement.
IMM_GEN_VO
L
00 = 1/2 Full Scale
10 = 1/8 Full Scale
01 = 1/4 Full Scale
11 = 1/16 Full Scale
4
C
IMM_MOD
E_CTRL
Number of MCLK used to calculate
the impedance
IMM_CYCLE_
CNT
00 = 1024
10 = 4096
01 = 2048
11 = 8192
Impedance measurement mode enable
1 = Enable. 0 = Disable
IMM_MODE
DAC Filter Input Source Selection
IMM_MODE Enabled, from Built-in Sin Generator
00: from DRC DAC Output
01: from DAC Mixer Output
10: from u/A-law decode output
11: 0
DACIN_SRC
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Left Headset speaker Impedance readout. It is
recommended to characterize this before use with
known Impedance values
4
D
IMM_RMS
_L
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read Only
OTPDOUT_L
OTP read out data Low 16 bits
5
3
OTPDOU
T_1
Default
Read Only
OTPDOUT_H
OTP read out data High two bits
5
4
OTPDOU
T_2
Default
Read Only
3-wire Mode Control
1 = Enable
0 = Disable
Ram Test Control
1 = Enable
SPI 3-WIRE
ENA
5
5
MISC_CT
RL
RAM_TEST_S
TART
NAU88L21 Datasheet Rev1.7
Page 57 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
0
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0 = Disable
1: Use DAC Left Filter Input as ADC decimation filter
output
0x0000
D2A_LOOP
Default
0
0
0
0
0
0
0
I2C_DEVICE_I
D[6:1]
I2C Device ID read in
MICDET
KEYDET
MICDETECT Status Bit
Key Detect Status Bit
5
8
I2C_DEVI
CE_ID
Silicon
Silicon revision bits
Revision ID
Software ID
Default
Software ID 00=NAU88L21
Read Only
X
0
0
1
1
0
1
X
0
0
1
0
0
0
0
0
RATM_TEST_
FINISH
RAM_TEST_F
AIL
1 = Test is finished
0 = Test is not complete
1 = Test is failed
0 = Test is passed
Analog mute enable
1 = Enable
SARDOU
T_RAM_S
TATUS
5
9
ANALOG_MU
TE
0 = Disable
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read Only
Enable Headphone Impedance
Test/ IMM_MODE
1 = Enable
TESTRL
0 = Disable
Mute Left PGA
1 = Enable
0 = Disable
Mute Right PGA
1 = Enable
MUTEL
MUTER
0 = Disable
TESTDAC
Reserved
DAC Right, Left Test only
Reserved to 0
VMID enable
1 = Enable
0 = Disable
6
6
BIAS_ADJ
VMIDEN
VMID tie-off selection options
00 = Open
(default)
01 = 25k Ohm
VMIDSEL
10 = 125k Ohm
11 = 2.5k Ohm
Reserved
Reserved
PGA Master bias current power options
00 = normal operation (default)
01 = 9% reduced bias current from default
10 = 17% reduced bias current from default
11 = 11% increased bias current from default
0x0000
BIASADJ
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TESTDACIN
DAC Test signal;‘00’ & ‘11’=gnd;‘01’,‘10’ high and low
GPIO3JD2 Pull Up select; ‘0’=1MOhm, ‘1’=100kOhm
Pullup_GPIO3
GPIO3 JKDET2 Threshold Low select
00 = 0.22 x VDDA
10 = 0.40 x VDDA
GPIO3THL[1:0
]
11 = 0.5 x VDDA
GPIO3 JKDET2 Threshold High select
00 = 0.85 x VDDA
ANALOG_
CONTRO
L_1
6
9
GPIO3THH[1:0
]
10 = 0.78 x VDDA
11 = 0.6 x VDDA
Pullup_GPIO2
GPIO2JD1 Pull Up select; ‘0’=1MOhm, ‘1’=100kOhm
GPIO2 JKDET1 Threshold Low select
00 = 0.22 x VDDA
10 = 0.40 x VDDA
GPIO2THL[1:0
]
11 = 0.5 x VDDA
NAU88L21 Datasheet Rev1.7
Page 58 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
GPIO2 JKDET1 Threshold High select
00 = 0.85 x VDDA
10 = 0.78 x VDDA
GPIO2THH[1:0
]
11 = 0.6 x VDDA
Reserved
JD1POL
JKDETL JD1 Polarity; ‘0’=default, ‘1’=inverted
JKDETL Output Polarity; ‘0’=default, ‘1’=inverted
JKDETLPOL
ENJKDETL
Enable Jack Tip insertion detection circuit
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Headphone driver Class AB bias current adjust
ANALOG_CO
NTROL2
in non-Class-G mode
0 = Default
1 = 2x
Headphone driver bias current adjust in
ANALOG_CO
NTROL2
class-G mode
0 = Default
1 = 0.5x
Headphone driver bias current adjust in
ANALOG_CO
NTROL2
non-Class-G mode
0 = Default
1 = 2.5x
Headphone Out Boost Driver Bias current
ANALOG_CO
NTROL2
adjust2 in Class-G mode
0 = Default
1 = Low
Headphone Out Boost Driver Bias current adjust1 in
ANALOG_CO
NTROL2
Class-G mode
0 = Default
1 = Low
ANALOG_
CONTRO
L_2
6
A
Headphone Driver Class-AB adjust; ‘0’=default, ‘1’ is
increased bias
AB_ADJ
Reserved
Reserved
Reserved
Reserved
Reserved
CAP[1]
DAC Reference Decoupling Capacitor enable msb
CAP[0]
DAC Reference Decoupling Capacitor enable lsb
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
MUTENL
MUTENR
MUTEPL
MUTEPR
MUTE MICLN Input to PGA when set to ‘1’
MUTE MICRN Input to PGA when set to ‘1’
MUTE MICLP Input to PGA when set to ‘1’
MUTE MICRP Input to PGA when set to ‘1’
Reserved ‘0’
6
B
TEST_ANALO
G
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0x0000
Reserved
7
1
ANALOG_
ADC_1
0 = power on mic detection
1 = power down mic detect
0x0011
pdmicdet
Default
Reserved
Reserved
7
2
ANALOG_
ADC_2
NAU88L21 Datasheet Rev1.7
Page 59 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Left channel PGA bias current increase enable for
driving the ADC at high sample rates
1 = Enable
ADC_UPL
ADC_UPR
0 = Disable
Right channel PGA bias current increase enable for
driving the ADC at high sample rates
1 = Enable
0 = Disable
Change bias currents in ADC
BIAS
00 = Nominal
10 = Half
01 = Double
11 = Quarter
VREF select in ADC
00 = Analog
supply
01 = VMID
VREFSEL
10 = VMID +
0.5dB
11 = VMID + 1dB
Reserved
PDNOTL
PDNOTR
Default
Reserved ‘0’
1 = Power on signal left ADC
1 = Power on signal right ADC
0x0020
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
DAC enable
Bit 1 = Right DAC
Bit 0 = Left DAC
1 = Enable
DAC_EN
0 = Disable
DAC CLOCK enable
Bit 1 = Right DAC
Bit 0 = Left DAC
1 = Enable
0 = Disable
DAC Smoothing Filter on HS Output enable
1 = Enable
CLK_DAC_EN
FC_CTR
7
3
RDAC
0 = Disable
CLK_DAC_DE
LAY
DAC clock delay setting
DAC Reference voltage setting
(default:1.6V)
DACVREFSEL
Default
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0x0008
MICBIAS1 internal 2k Ohm resistor for MCGND2
enable
1 = Enable
0 = Disable
INT2KA
0 = Low power mode
1 = Low noise mode
0 = Power down MICBIAS1
1 = Power on MICBIAS1
Set output level for MICBIAS1
LOWNOISE
POWERUP
7
4
MIC_BIAS
000 = VDDA
010 = 1.1x
100 = 1.3x
110 = 1.53x
0x0006
001 = 1x
MICBIASLVL1
011 = 1.2x
101 = 1.4x
111 = 1.53x
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
CLR_APR_EM
RGENCY_SH
TDWN
Clear Headset short circuit shut down IRQ
1 = Reset (momentary)
0 = Default
PGA in class A mode of operation enable instead of
class AB (default)
1 = Enable
STG2_SEL
0 = Disable
VMID Pre-charge disable
1 = Disable
0 = Enable
Global Analog Bias enable
7
6
BOOST
PDVMDFST
BIASEN
1 = Enable
0 = Disable
Charges inputs selected by Error! Reference source
not found.
1 = Enable
0 = Disable
DISCHRG
NAU88L21 Datasheet Rev1.7
Page 60 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Bypass PGA current control enable
1 = Enable
0 = Disable
BYPS_IBCTR
BOOSTDIS
Disable HP boost driver
1 = Disable
0 = Enable
Disable HP boost driver in Class-G mode
1 = Disable
BOOSTGDIS
0 = Enable
Short Circuit Shut Down Digital Part Enable
1 = Enable
0 = Disable
SHRT_SHTD
WN_DIG_EN
Enable Automatic Short-circuit Shutdown
1:headset driver power down immediately when short
detected. No interrupt will be generated.
0&[8]=0: driver shut down after 16.3 usec debounce
when short detected. interrupt generated and
‘apr_emrgncy_shtdwn’ cleared if the interrupt
cleared.
EN_SHRT_SH
TDWN
0&[8]=1: same as 0&[8]=0, plus apr_emrgncy_shtdwn
cleared 1630 usec after short removed, but interrupt
remains to be cleared by the user
Headset Short Circuit protection limit
00= at 115mA at +FS(Default)
11= 155mA at +FS
HS_SHRT_TH
RESHLD[1:0]
Adjust HS boost p-driver bias current
11 = Decrease current
00 = Default
PAMP_THRS
HLD
Adjust HS boost n-driver bias current
11 = Decrease current
00 = Default
NAMP_THRS
HLD
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
DC state control for Input pins. Action takes effect
when DISCHRG=1
ACDC_CTRL[0] charges MICP to VREF
ACDC_CTRL[1] charges MICN to VREF
1 = Enable
ACDC_CTRL
0 = Disable
PGA Common mode Threshold lock adjust. It is
recommended to leave this in default.
CMLCK_ADJ
Reserved
Reserved
Reserved
Reserved
Left PGA mode selection;
MODE[0] = Anti-aliasing filter adjust
MODE[1] = Disconnects MICP & MICN
MODE[2] = No function
MODE[3] = Shorts the inputs and terminates with
12kOhm differentially
7
7
FEPGA
FEPGA_MOD
EL
1 = Enable
0 = Disable
Right PGA mode selection;
MODE[0] = Anti-aliasing filter adjust
MODE[1] = Disconnects MICP & MICN
MODE[2] = No function
MODE[3] = Shorts the inputs and terminates with
12kOhm differentially
FEPGA_MOD
ER
1 = Enable
0 = Disable
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Left PGA gain, increments in 1dB steps
000000 = -1dB
000001 = 0dB
▼
7
E
PGA_GAI
N
PGA_GAIN_L
100100 = 35dB
100101 = 36dB
NAU88L21 Datasheet Rev1.7
Page 61 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Right PGA gain, increments in 1dB steps
000000 = -1dB
000001 = 0dB
▼
PGA_GAIN_R
100100 = 35dB
100101 = 36dB
Default
PUPGA
PUPR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Power Up Left PGA
1 = Enable
0 = Disable
Power Up Right PGA
1 = Enable
0 = Disable
Power Up Output driver
1 = Power up
PUP_INTEG
0 = Power down
Bit 0 = Left HP driver
Bit 1 = Right HP driver
Power Up Output driver
1 = Power up
0 = Power down
Bit 0 = Left HP driver
Bit 1 = Right HP driver
Power Up main driver
1 = Power up
POWER_
UP_CONT
ROL
7
F
PUP_DRV_IN
STG
PUP_MAIN_D
RV
0 = Power down
Bit 0 = Left HP driver
Bit 1 = Right HP driver
0x0000
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
BCLK IO Drive Strength
1 = Stronger
0 = Default
FS IO Drive Strength
1 = Stronger
BCLK_DS
FS_DS
0 = Default
ADCDAT IO Drive Strength
1 = Stronger
0 = Default
SDA IO Drive Strength
1 = Stronger
ADCDAT_DS
SDA_DS
0 = Default
JAMNODCLO
W
Reserved
DAC Right, Left Power Down Bar enable
PDB_DAC
11 = Enable
00 = Disable
CHARGE_
PUMP_AN
D_POWE
R_DOWN
_CONTR
OL
Register output forces the charge pump clock to not
slow
1 = Enable
0 = Disable
8
0
JAMFORCE2
Register output forces the charge pump clock to not
slow down
1 = Enable
JAMFORCE1
0 = Disable
Charge Pump enable
1 = Enable
RNIN
0 = Disable
VPOS Pre-charge enable for faster startup
1 = Enable
PRECHARGE
0 = Disable
VEE pad discharge enable
1 = Enable
0 = Disable
DISCHARGEV
EE
VPOS pad discharge enable
1 = Enable
0 = Disable
DISCHARGEV
POS
NAU88L21 Datasheet Rev1.7
Page 62 of 69
Feb, 2020
Bit
R
E
G
Function
Name
Description
1
5
1
4
1
3
1
2
1
1
1
0
9
0
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Charge up current limit
0 = Default low
1 = High
Charge up current limit
0 = Default low
1 = High
SHCIRSEL2
SHCIRSEL1
Default
0
0
0
0
0
0
0
0x0000
APR_EMRGN
CY_SHTDWN
1
APR emergency short circuit shutdown IRQ
MODE1BUF
Monitors the MODE1 state of Charge Pump block
Monitors if the charge pump is drawing DC current
0 = Power drawn
NODCBUF
1 = No power drawn
Monitors charge pump enable status
0 = OFF
1 = ON
Monitors the high voltage status of VPOS
1 = Max output (OK)
CHARGE_
PUMP_IN
PUT_REA
D
RN2BUF
VPOSOK
8
1
0 = Possible short circuit
Monitors the low voltage and low current status of the
charge pump
VCOMPBUF
0 = No current
Monitors charge pump frequency status
1 = Max frequency
FORCE1BUF
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read Only
JK_EJECT_IN
TR
JK_INSERT_I
NTR
JACK Ejection Interrupt
JACK Insertion Interrupt
8
2
GENERAL
_STATUS
JKDET_ON
JKDETL
FUSEBNKOU
T
Pre-debounce JACK status
JKDETL
Fuse Bank Select Output
GPIO2_IN
GPIO1_IN
Default
GPIO2 Input
GPIO1 Input
Read Only
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NAU88L21 Datasheet Rev1.7
Page 63 of 69
Feb, 2020
11. Typical Application Diagram
VDDA
VDDMIC
4u7 0u1
4u7 0u1
200 Ω
OMTP
1n
1n
MICDET
MICBIAS
FS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
BCLK
MCLK
VDDC
VDDMIC
MIC
4u7
VREF
*200R
QFN 32-pin
HPR
*2kΩ
VSSA
10kΩ
VSSD
VDDB
4k7 Ω
VDDA
CPOUTP
VSSCP
*10u
1 n
HPL
SCLK
SDIO
10nF
10nF
2u2
33R
Zobel
Network
Zobel
Network
33R
VDDB
VDDC
4u7 0u1
4u7 0u1
2u2
2u2
Note: * indicates optional components for improved noise reduction (refer to section 3.5)
NAU88L21 Datasheet Rev1.7
Page 64 of 69
Feb, 2020
12.Package Information
32-lead plastic QFN 32L; 5X5mm2, 0.8mm thickness, 0.5mm lead pitch
(Saw Type) EP SIZE 3.5X3.5 mm
32
25
1
24
8
17
16
9
32
25
24
1
17
8
16
9
NAU88L21 Datasheet Rev1.7
Page 65 of 69
Feb, 2020
32-lead plastic QFN 32L; 4X4mm2, 0.8mm(Max) thickness, 0.4mm lead pitch
(Saw Type) EP SIZE 3.5X3.5 mm
NAU88L21 Datasheet Rev1.7
Page 66 of 69
Feb, 2020
13.Ordering Information
Part Number
Dimension
Package
Package
Material
Green
NAU88L21YG
NAU88L21IG
5x5 mm
4x4 mm
QFN-32
QFN-32
Green
NAU88L21 _ _
Package Material:
Pb-free Package
G
=
Package Type:
Y
I
=
=
32-Pin QFN Package
32-Pin QFN Package
NAU88L21 Datasheet Rev1.7
Page 67 of 69
Feb, 2020
Revision History
Version
Date
February 18, 2019
DESCRIPTION
Page(s)
All
#
1.0
1.1
1.2
1.3
1.4
initial version
March 8, 2019
Front page
Add Cap-free and internal Resistor in MICBIAS
Add Zebol Network in Application circuit.
Added RC for MICDET – noise coupling.
June, 12, 2019
64
15
September, 22, 2019
October, 17, 2019
34
Modified Figure 34:2-Wire Read Sequence.
Add QFN4x4mm2 IC package
1.5
November, 8, 2019
66, 67
1.6
1.7
January 17, 2020
Febuary 24, 2020
30,31
Enhance FLL application note
Changed VDDC to VDDA
2,5,6,7,9,64
NAU88L21 Datasheet Rev1.7
Page 68 of 69
Feb, 2020
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which
may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments,
airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use,
traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of
customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.
NAU88L21 Datasheet Rev1.7
Page 69 of 69
Feb, 2020
相关型号：
NAU88L25
Ultra-Low Power Audio CODEC for Headphone/Headsets Application With 124dB Class G Headphone Drive and Advanced Headset Features
NUVOTON
NAU88L25B
Ultra-Low Power Audio CODEC for Headphone/Headsets Application With 124dB Class G Headphone Drive and Advanced Headset Features
NUVOTON
NAU88L25VGB
Ultra-Low Power Audio CODEC for Headphone/Headsets Application With 124dB Class G Headphone Drive and Advanced Headset Features
NUVOTON
NAU88L25YG
Ultra-Low Power Audio CODEC for Headphone/Headsets Application With 124dB Class G Headphone Drive and Advanced Headset Features
NUVOTON
NAU88L25YGB
Ultra-Low Power Audio CODEC for Headphone/Headsets Application With 124dB Class G Headphone Drive and Advanced Headset Features
NUVOTON
©2020 ICPDF网 联系我们和版权申明