NUC029NXE [NUVOTON]
ARM® Cortex®-M0 32-bit Microcontroller;型号: | NUC029NXE |
厂家: | NUVOTON |
描述: | ARM® Cortex®-M0 32-bit Microcontroller 微控制器 |
文件: | 总102页 (文件大小:1983K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NUC029
ARM® Cortex® -M0
32-bit Microcontroller
NuMicro® Family
NUC029 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Apr 3, 2019
Page 1 of 102
Rev 1.06
NUC029
Table of Contents
LIST OF FIGURES .....................................................................................................6
LIST OF TABLES.......................................................................................................7
1 GENERAL DESCRIPTION.....................................................................................8
2 FEATURES ............................................................................................................9
3 ABBREVIATIONS ................................................................................................13
4 PARTS INFORMATION LIST AND PIN CONFIGURATION................................14
4.1 NuMicro® NUC029 Series Selection Guide ..................................................14
4.2 Pin Configuration .................................................................................16
4.2.1 NuMicro® NUC029 Pin Diagram.....................................................................16
4.3 Pin Description....................................................................................20
4.3.1 NuMicro® NUC029 Pin Description .................................................................20
5 FUNCTIONAL DESCRIPTION.............................................................................27
5.1 ARM® Cortex® -M0 Core ........................................................................27
5.2 System Manager .................................................................................29
5.2.1 Overview ................................................................................................29
5.2.2 System Reset ..........................................................................................29
5.2.3 System Power Distribution ...........................................................................30
5.2.4 System Memory Map .................................................................................31
5.2.5 Whole System Memory Mapping....................................................................34
5.2.6 System Timer (SysTick) ..............................................................................36
5.2.7 Nested Vectored Interrupt Controller (NVIC)......................................................36
5.3 Clock Controller of NuMicro® NUC029xAN ..................................................41
5.3.1 Overview ................................................................................................41
5.3.2 System Clock and SysTick Clock ...................................................................44
5.3.3 Power-down Mode Clock.............................................................................45
5.3.4 Frequency Divider Output ............................................................................46
5.4 Clock Controller of NuMicro® NUC029FAE ..................................................47
5.4.1 Overview ................................................................................................47
5.4.2 System Clock and SysTick Clock ...................................................................48
5.4.3 ISP Clock Source Selection..........................................................................49
5.4.4 Module Clock Source Selection .....................................................................49
5.4.5 Power-down Mode Clock.............................................................................50
5.5 Flash Memory Controller (FMC) ...............................................................51
5.5.1 Overview ................................................................................................51
Apr 3, 2019
Page 2 of 102
Rev 1.06
NUC029
5.5.2 Features.................................................................................................51
5.6 External Bus Interface (EBI) (NUC029LAN/NUC029NAN Only) .........................52
5.6.1 Overview ................................................................................................52
5.6.2 Features.................................................................................................52
5.7 General Purpose I/O (GPIO) ...................................................................53
5.7.1 Overview ................................................................................................53
5.7.2 Features.................................................................................................53
5.8 Timer Controller (TIMER) .......................................................................54
5.8.1 Overview ................................................................................................54
5.8.2 Features.................................................................................................54
5.9 PWM Generator and Capture Timer (PWM) (NUC029xAN Only) ........................55
5.9.1 Overview ................................................................................................55
5.9.2 Features.................................................................................................56
5.10Enhanced PWM Generator (NUC029FAE Only)............................................57
5.10.1 Overview ................................................................................................57
5.10.2 Features.................................................................................................57
5.11Watchdog Timer (WDT) .........................................................................59
5.11.1 Overview ................................................................................................59
5.11.2 Features.................................................................................................59
5.12Window Watchdog Timer (WWDT) (NUC029xAN Only)...................................60
5.12.1 Overview ................................................................................................60
5.12.2 Features.................................................................................................60
5.13UART Interface Controller (UART) ............................................................61
5.13.1 Overview ................................................................................................61
5.13.2 Features.................................................................................................61
5.14I2C Serial Interface Controller (I2C)............................................................62
5.14.1 Overview ................................................................................................62
5.14.2 Features.................................................................................................62
5.15Serial Peripheral Interface (SPI) ...............................................................63
5.15.1 Overview ................................................................................................63
5.15.2 Features.................................................................................................63
5.16Analog-to-Digital Converter (ADC) ............................................................64
5.16.1 Overview ................................................................................................64
5.16.2 Features.................................................................................................64
5.17Analog Comparator (ACMP)....................................................................66
Apr 3, 2019
Page 3 of 102
Rev 1.06
NUC029
5.17.1 Overview ................................................................................................66
5.17.2 Features.................................................................................................66
5.18Hardware Divider (HDIV) (NUC029xAN Only)...............................................67
5.18.1 Overview ................................................................................................67
5.18.2 Features.................................................................................................67
6 APPLICATION CIRCUIT......................................................................................68
7 NUC029XAN ELECTRICAL CHARACTERISTICS..............................................69
7.1 Absolute Maximum Ratings.....................................................................69
7.2 DC Electrical Characteristics ...................................................................70
7.3 AC Electrical Characteristics ...................................................................74
7.3.1 External Input Clock...................................................................................74
7.3.2 External 4~24 MHz High Speed Crystal (HXT) ...................................................74
7.3.3 Internal 22.1184 MHz High Speed RC Oscillator (HIRC) .......................................75
7.3.4 Internal 10 kHz Low Speed RC Oscillator (LIRC) ................................................75
7.4 Analog Characteristics...........................................................................76
7.4.1 12-bit SAR ADC Specification .......................................................................76
7.4.2 LDO and Power Management Specification ......................................................77
7.4.3 Low Voltage Reset Specification....................................................................78
7.4.4 Brown-out Detector Specification ...................................................................78
7.4.5 Power-on Reset Specification .......................................................................78
7.4.6 Temperature Sensor Specification..................................................................80
7.4.7 Comparator Specification ............................................................................80
7.5 Flash DC Electrical Characteristics............................................................81
8 NUC029FAE ELECTRICAL CHARACTERISTICS ..............................................82
8.1 Absolute Maximum Ratings.....................................................................82
8.2 DC Electrical Characteristics ...................................................................83
8.3 AC Electrical Characteristics ...................................................................87
8.3.1 External Input Clock...................................................................................87
8.3.2 External 4~24 MHz High Speed Crystal (HXT) ...................................................87
8.3.3 Internal 22.1184 MHz High Speed RC Oscillator (HIRC) .......................................88
8.3.4 Internal 10 kHz Low Speed RC Oscillator (LIRC) ................................................89
8.4 Analog Characteristics...........................................................................90
8.4.1 10-bit SAR ADC Specification .......................................................................90
8.4.2 LDO and Power Management Specification ......................................................91
8.4.3 Low Voltage Reset Specification....................................................................92
Apr 3, 2019
Page 4 of 102
Rev 1.06
NUC029
8.4.4 Brown-out Detector Specification ...................................................................92
8.4.5 Power-on Reset Specification .......................................................................92
8.4.6 Comparator Specification ............................................................................94
8.5 Flash DC Electrical Characteristics............................................................95
9 PACKAGE DIMENSIONS ....................................................................................96
9.1 48-pin LQFP (7x7x1.4 mm).....................................................................96
9.2 48-pin QFN (7x7x0.8 mm) ......................................................................97
9.3 33-pin QFN (5x5x0.75 mm).....................................................................98
9.4 33-pin QFN (4x4x0.75 mm).....................................................................99
9.5 20-pin TSSOP (6.5x4.4x1.2 mm) ............................................................100
10REVISION HISTORY..........................................................................................101
Apr 3, 2019
Page 5 of 102
Rev 1.06
NUC029
LIST OF FIGURES
Figure 4-1 NuMicro® NUC029 Series Selection Code ................................................................... 15
Figure 4-2 NuMicro® NUC029LAN LQFP 48-pin Diagram............................................................. 16
Figure 4-3 NuMicro® NUC029NAN QFN 48-pin Diagram.............................................................. 17
Figure 4-4 NuMicro® NUC029ZAN/NUC029TAN QFN 33-pin Diagram ........................................ 18
Figure 4-5 NuMicro® NUC029FAE TSSOP 20-pin Diagram.......................................................... 19
Figure 5-1 Functional Controller Diagram...................................................................................... 27
Figure 5-2 NuMicro® NUC029xAN Power Distribution Diagram.................................................... 30
Figure 5-3 NuMicro® NUC029FAE Power Distribution Diagram.................................................... 31
Figure 5-4 NuMicro® NUC029xAN Whole System Memory Mapping............................................ 34
Figure 5-5 NuMicro® NUC029FAE Whole System Memory Mapping ........................................... 35
Figure 5-6 NuMicro® NUC029xAN Clock Generator Block Diagram ............................................. 41
Figure 5-7 NuMicro® NUC029xAN Clock Source Controller Overview (1/2) ................................. 42
Figure 5-8 NuMicro® NUC029xAN Clock Source Controller Overview (2/2) ................................. 43
Figure 5-9 NuMicro® NUC029xAN System Clock Block Diagram ................................................. 44
Figure 5-10 NuMicro® NUC029xAN SysTick Clock Control Block Diagram .................................. 44
Figure 5-11 NuMicro® NUC029xAN Clock Source of Frequency Divider...................................... 46
Figure 5-12 NuMicro® NUC029xAN Frequency Divider Block Diagram ........................................ 46
Figure 5-13 NuMicro® NUC029FAE Clock Generator Block Diagram........................................... 47
Figure 5-14 NuMicro® NUC029FAE System Clock Block Diagram ............................................... 48
Figure 5-15 NuMicro® NUC029FAE SysTick Clock Control Block Diagram.................................. 48
Figure 5-16 NuMicro® NUC029FAE AHB Clock Source for HCLK................................................ 49
Figure 5-17 NuMicro® NUC029FAE Peripherals Clock Source Selection for PCLK ..................... 50
Figure 7-1 NUC029xAN Typical Crystal Application Circuit .......................................................... 75
Figure 7-2 NUC029xAN Power-up Ramp Condition...................................................................... 79
Figure 8-1 NUC029FAE Typical Crystal Application Circuit .......................................................... 88
Figure 8-2 NUC029xAN Power-up Ramp Condition...................................................................... 93
Apr 3, 2019
Page 6 of 102
Rev 1.06
NUC029
LIST OF TABLES
Table 1-1 NuMicro® NUC029 Series Difference List........................................................................ 8
Table 3-1 List of Abbreviations....................................................................................................... 13
Table 4-1 NuMicro® NUC029 Series Selection Guide ................................................................... 14
Table 5-1 NuMicro® NUC029xAN Address Space Assignments for On-Chip Controllers............. 32
Table 5-2 NuMicro® NUC029FAE Address Space Assignments for On-Chip Controllers ............ 33
Table 5-3 Exception Model ............................................................................................................ 37
Table 5-4 NuMicro® NUC029xAN System Interrupt Map............................................................... 38
Table 5-5 NuMicro® NUC029FAE System Interrupt Map .............................................................. 39
Table 5-6 Vector Table Format ...................................................................................................... 40
Table 5-7 NuMicro® NUC029FAE Peripheral Clock Source Selection Table................................ 50
Apr 3, 2019
Page 7 of 102
Rev 1.06
NUC029
1
GENERAL DESCRIPTION
The NuMicro® NUC029 series 32-bit microcontroller is embedded with ARM® Cortex® -M0 core for
industrial control and applications which need rich communication interfaces or require high
performance, high integration, and low cost. The Cortex® -M0 is the newest ARM® embedded
processor with 32-bit performance at a cost equivalent to the traditional 8-bit microcontroller. The
NuMicro® NUC029 series includes four part numbers: NUC029LAN, NUC029NAN, NUC029ZAN,
NUC029TAN and NUC029FAE.
The NUC029LAN/NUC029NAN/NUC029ZAN/NUC029TAN can run up to 50 MHz and operate at
2.5V ~ 5.5V, -40℃ ~ 85℃, and the NUC029FAE can run up to 24 MHz and operate at 2.5V ~
5.5V, -40℃ ~ 105℃. Therefore, the NUC029 series can afford to support a variety of industrial
control and applications which need high CPU performance.
The NUC029LAN/NUC029NAN/NUC029ZAN/NUC029TAN offers 64K/64K/32K bytes flash, 4
Kbytes Data Flash, 4 Kbytes flash for the ISP, and 4 Kbytes SRAM. The NUC029FAE offers 16
Kbytes flash, size configurable Data Flash (shared with program flash), 2 Kbytes flash for the ISP,
and 2K-bytes SRAM.
Many system level peripheral functions, such as I/O Port, EBI (External Bus Interface), Timer,
UART, SPI, I2C, PWM, ADC, WDT (Watchdog Timer), WWDT (Window Watchdog Timer), Analog
Comparator and Brown-out Detector, have been incorporated into the NUC029 series in order to
reduce component count, board space and system cost. These useful functions make the
NUC029 series powerful for a wide range of applications.
Additionally, the NuMicro® NUC029 series is equipped with ISP (In-System Programming) and
ICP (In-Circuit Programming) functions, and IAP (In-Application Programming), which allow the
user to update the program memory without removing the chip from the actual end product.
NUC029LAN/NUC029NAN/
NUC029ZAN/NUC029TAN
Item
NUC029FAE
Core
Up to 50 MHz
Up to 24 MHz
-40℃ ~ +85℃
-40℃ ~ +105℃
Operating Temp.
Hardware Divider
√
-
-
Supports PLL as clock source
Clock Control
Supports external 32.768 kHz crystal
oscillator as clock source
-
Window WDT
PWM
√
-
PWM Generator and Capture Timer
Enhanced PWM Generator
12-bit SAR ADC with 760 kSPS (Supports Single,
Burst, Single-Cycle, and Continuous Scan mode)
10-bit SAR ADC with 300 kSPS (Only
supports Single mode)
ADC
EBI
√
√
-
-
Built-in Temp.Sensor
Table 1-1 NuMicro® NUC029 Series Difference List
Apr 3, 2019
Page 8 of 102
Rev 1.06
NUC029
2
FEATURES
ARM® Cortex® -M0 core
–
–
–
–
–
–
–
Runs up to 50 MHz
One 24-bit system timer
Supports Low Power Sleep mode
A single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Supports Serial Wire Debug (SWD) interface and two watchpoints/four breakpoints
Provides hardware divider and supports signed 32-bit dividend, 16-bit divisor
operation(NUC029xAN only)
Operating voltage ranges from 2.5 V to 5.5 V
Memory
–
16/32/64 KB Flash for program memory (APROM)
Up to 4 KB Flash for loader (LDROM)
Up to 4 KB SRAM for internal scratch-pad RAM (SRAM)
4 KB Flash for data memory (Data Flash) (NUC029xAN only)
Configurable Data Flash (NUC029FAE only)
–
–
–
–
Clock Control
–
–
Programmable system clock source
22.1184 MHz internal oscillator
Dynamically calibrating the HIRC OSC to 22.1184 MHz ±3% from -40℃ to 105℃
by external 32.768 kHz crystal oscillator (LXT) (NUC029FAE only)
–
–
–
–
4~24 MHz external crystal input
10 kHz low-power oscillator for Watchdog Timer and wake-up in Sleep mode
PLL allows CPU operation up to the maximum 50 MHz (NUC029xAN only)
32.768 kHz external crystal input (LXT) for Power-down wake-up and system operation
clock (NUC029FAE only)
GPIO
–
–
Up to 40 general-purpose I/O (GPIO) pins for LQFP/QFN 48-pin package
Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
–
–
–
–
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports high driver and high sink I/O mode
Configurable I/O mode after POR
Timer
–
–
–
Up to four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides up to four timer counting modes: one-shot, periodic, toggle and continuous
counting
–
–
–
–
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the input event from external counter pin
24-bit capture value is readable through TCAP (Timer Capture Data Register)
Supports external capture pin for interval measurement
Supports external capture pin to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
–
Supports internal capture triggered while internal ACMP output signal transition
Apr 3, 2019
Page 9 of 102
Rev 1.06
NUC029
(NUC029xAN only)
–
–
Supports Inter-Timer trigger mode (NUC029xAN only)
Supports internal signal (CPO0, CPO1) for interval measurement (NUC029FAE only)
WDT (Watchdog Timer)
–
Multiple clock sources
–
–
–
Supports wake-up from Power-down or Sleep mode
Interrupt or reset selectable on watchdog time-out
Time-out reset delay period can be selected to 3/18/130/1026 * WDT_CLK
(NUC029xAN only)
WWDT (Window Watchdog Timer) (NUC029xAN only)
–
6-bit down counter with 11-bit pre-scale for wide range window selected
PWM Generator and Capture Timer (NUC029xAN only)
–
Up to four built-in 16-bit PWM generators, providing eight PWM outputs or four
complementary paired PWM outputs
–
Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for
each PWM generator
–
–
–
–
–
–
–
–
–
–
–
PWM interrupt synchronized to PWM period
16-bit digital Capture timers with rising/falling capture inputs
Supports capture interrupt
Internal 10 kHz to PWM clock source
Polar inverse function
Center-aligned type function
Timer duty interrupt enable function
Two kinds of PWM interrupt period type selection
Two kinds of PWM interrupt duty type selection
Period/duty trigger ADC function
PWM Timer synchronous start function
Enhanced PWM Generator (NUC029FAE only)
–
Independent 16-bit PWM duty control units with maximum three outputs
Supports group/synchronous/independent/ complementary modes
Supports One-shot or Auto-reload mode
–
–
–
–
–
–
–
–
–
–
–
Supports Edge-aligned and Center-aligned type
Programmable dead-zone insertion between complementary channels
Each output has independent polarity setting control
Hardware fault brake protections
Supports duty, period, and fault break interrupts
Supports duty/period trigger ADC conversion
Timer comparing matching event trigger PWM to do phase change
Supports comparator event trigger PWM to force PWM output low for current period
Provides interrupt accumulation function
UART
–
–
–
–
–
–
–
Up to two sets of UART devices
Programmable baud-rate generator
Buffered receiver and transmitter, each with 16 bytes FIFO
Optional flow control function (CTS and RTS)
Supports IrDA(SIR) function
Supports RS-485 function
Supports LIN function (NUC029xAN only)
SPI
–
–
Up to two sets of SPI devices
Supports Master/Slave mode
Apr 3, 2019
Page 10 of 102
Rev 1.06
NUC029
–
–
–
–
–
–
–
–
–
Full-duplex synchronous serial data transfer
Provides 3 wire function
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx latching data can be either at rising edge or at falling edge of serial clock
Tx sending data can be either at rising edge or at falling edge of serial clock
Supports Byte Suspend mode in 32-bit transmission
4-level depth FIFO buffer
PLL clock source (NUC029xAN only)
I2C
–
–
–
–
–
Up to two sets of I2C modules
Supports Master/Slave mode
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
–
–
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
–
–
–
–
–
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
Supports Power-down wake-up function
Supports FIFO function (NUC029FAE only)
ADC
–
–
–
12-bit SAR ADC with 760 kSPS for NUC029xAN, and 10-bit SAR ADC with 300 kSPS
for NUC029FAE
Up to eight single-end analog input channels
Or four differential analog input channels (NUC029xAN only)
Four operation modes (NUC029FAE only support Single mode)
Single mode: A/D conversion is performed one time on a specified channel
Burst mode: A/D converter samples and converts the specified single channel
and sequentially stores the result in FIFO
Single-cycle Scan mode: A/D conversion is performed only one cycle on all
specified channels with the sequence from the smallest numbered channel to
the largest numbered channel
Continuous Scan mode: A/D converter continuously performs Single-cycle Scan
mode until software stops A/D conversion
–
An A/D conversion can be started by:
Software Write 1 to ADST bit
External pin (STADC)
PWM trigger with optional start delay period
–
–
–
Each conversion result is held in data register with valid and overrun indicators
Each channel has individual data register (NUC029xAN only)
Conversion result can be compared with specified value and user can select whether
to generate an interrupt when conversion result matches the compare register setting
Internal temperature sensor output (NUC029xAN only)
–
Analog Comparator
–
Up to four sets of Comparator analog modules
External input or internal band-gap voltage selectable at negative node
Interrupt when compared results change
–
–
–
Power-down wake-up
Apr 3, 2019
Page 11 of 102
Rev 1.06
NUC029
EBI (External Bus Interface) for external memory-mapped device access (NUC029LAN/
NUC029NAN only)
–
–
–
Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8-bit or 16-bit data width
Supports byte-write in 16-bit data width
ISP (In-System Programming) and ICP (In-Circuit Programming)
IAP (In-Application Programming)
One built-in temperature sensor with 1℃ resolution (NUC029xAN only)
BOD (Brown-out Detector)
–
–
With 4 levels: 4.4V/3.7V/2.7V/2.2V
Supports Brown-out interrupt and reset option
96-bit unique ID (UID)
LVR (Low Voltage Reset)
–
Threshold voltage level: 2.0V
Operating Temperature:
–
NUC029LAN/NUC029NAN/NUC029ZAN/NUC029TAN: -40℃~85℃
NUC029FAE:-40℃~105℃
–
Reliability: EFT > ± 4 KV, ESD HBM pass 4 KV
Packages:
–
–
All Green package (RoHS)
48-pin LQFP, 48-pin QFN, 33-pin QFN, 20-pin TSSOP
Apr 3, 2019
Page 12 of 102
Rev 1.06
NUC029
3
ABBREVIATIONS
Acronym
Description
ACMP
ADC
APB
AHB
BOD
EBI
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Peripheral Bus
Advanced High-Performance Bus
Brown-out Detection
External Bus Interface
FIFO
FMC
GPIO
HCLK
HIRC
HXT
IAP
First In, First Out
Flash Memory Controller
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
32.768 kHz External Low Speed Crystal Oscillator
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Phase-Locked Loop
LIRC
LXT
NVIC
PCLK
PLL
PWM
SPI
Pulse Width Modulation
Serial Peripheral Interface
SPS
TMR
UART
UCID
USB
WDT
WWDT
Samples per Second
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
Watchdog Timer
Window Watchdog Timer
Table 3-1 List of Abbreviations
Apr 3, 2019
Page 13 of 102
Rev 1.06
NUC029
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® NUC029 Series Selection Guide
Connectivity
NUC029LAN
NUC029NAN
64
64
4
4
4
4
4
4
40
40
4
4
2
2
2
2
2
2
8
8
8
8
-
-
4
4
√
√
√
√
√
√
√
√
-
-
√
√
LQFP48
QFN48
-40 to +85
-40 to +85
QFN33
(5x5)
NUC029ZAN
64
4
4
4
24
4
2
1
2
5
5
-
3*
√
√
-
√
-
√
-40 to +85
QFN33
(4x4)
NUC029TAN
NUC029FAE
32
16
4
2
4
4
2
24
17
4
2
2
1
1
1
2
1
5
3
5
-
-
3*
√
√
√
-
-
√
-
√
√
-40 to +85
Config.
4
2**
-
-
√
TSSOP20
-40 to +105
Table 4-1 NuMicro® NUC029 Series Selection Guide
Note:
*: ACMP3 only has positive and negative input.
**: ACMP0 only has positive and negative input, and ACMP1 only has positive input.
Apr 3, 2019
Page 14 of 102
Rev 1.06
NUC029
NUC029 X X X
CPU core
ARM Cortex M0
Part Number
Temperature
℃
N: -40 ~ + 85℃
℃
E: -40 ~ +105℃
Reserved
Package
L: LQFP 48
N: QFN 48
Z: QFN 33 (5x5)
T: QFN 33 (4x4)
F: TSSOP 20
Figure 4-1 NuMicro® NUC029 Series Selection Code
Apr 3, 2019
Page 15 of 102
Rev 1.06
NUC029
4.2 Pin Configuration
4.2.1 NuMicro® NUC029 Pin Diagram
4.2.1.1 NuMicro® NUC029LAN LQFP 48 pin
P4.1, PWM1, T3EX
P0.4, AD4, SPISS1
P0.5, AD5, MOSI_1
P0.6, AD6, MISO_1
P0.7, AD7, SPICLK1
P4.7, ICE_DAT
ACMP0_P, MOSI_0, AIN5, P1.5
ACMP2_N, MISO_0, AIN6, P1.6
1
36
35
34
33
32
31
30
29
28
27
26
25
2
3
ACMP2_P, SPICLK0, AIN7, P1.7
nRST
4
5
ACMP1_N, RXD, P3.0
AVSS
6
LQFP-48 pin
P4.6, ICE_CLK
ACMP1_P, TXD, P3.1
T0EX, STADC, nINT0, P3.2
T1EX, MCLK, nINT1, P3.3
SDA0, T0, P3.4
7
P4.5, ALE, SDA1
8
P4.4, nCS, SCL1
9
P2.7, AD15, PWM7
P2.6, AD14, PWM6, ACMP1_O
P2.5, AD13, PWM5, SDA1
10
11
12
CKO, SCL0, T1, P3.5
PWM3, P4.3
Figure 4-2 NuMicro® NUC029LAN LQFP 48-pin Diagram
Apr 3, 2019
Page 16 of 102
Rev 1.06
NUC029
4.2.1.2 NuMicro® NUC029NAN QFN 48 pin
1
36
35
34
33
32
31
30
29
28
27
26
25
ACMP0_P, MOSI_0, AIN5, P1.5
P4.1, PWM1, T3EX
P0.4, AD4, SPISS1
P0.6, AD6, MISO_1
P0.7, AD7, SPICLK1
P4.7, ICE_DAT
2
ACMP2_N, MISO_0, AIN6, P1.6
3
ACMP2_P, SPICLK0, AIN7, P1.7
4
nRST
5
ACMP1_N, RXD, P3.0
6
AVSS
P4.6, ICE_CLK
QFN48
7
ACMP1_P, TXD, P3.1
LDO_CAP
8
T0EX, STADC, nINT0, P3.2
P4.5, ALE, SDA1
9
T1EX, MCLK, nINT1, P3.3
P4.4, nCS, SCL1
10
SDA0, T0, P3.4
P2.7, AD15, PWM7
P2.6, AD14, PWM6, ACMP1_O
P2.5, AD13, PWM5, SDA1
11
CKO, SCL0, T1, P3.5
49 VSS
12
PWM3, P4.3
Figure 4-3 NuMicro® NUC029NAN QFN 48-pin Diagram
Apr 3, 2019
Page 17 of 102
Rev 1.06
NUC029
4.2.1.3 NuMicro® NUC029ZAN/NUC029TAN QFN 33 pin
32 31 30 29 28 27 26 25
24
23
22
ACMP0_P, AIN5, P1.5
P0.4, SPISS1
P0.5, MOSI_1
P0.6, MISO_1
1
2
3
4
5
6
nRST
ACMP1_N, RXD, P3.0
AVSS
ACMP1_P, TXD, P3.1
T0EX, STADC, nINT0, P3.2
SDA0, T0, P3.4
21 P0.7, SPICLK1
QFN-33 Pin
P4.7, ICE_DAT
20
P4.6, ICE_CLK
19
18
17
P2.6, PWM6, ACMP1_O
P2.5, PWM5, SDA1
7
8
33 VSS
10 11 12 13 14 15 16
CKO, SCL0, T1, P3.5
9
Figure 4-4 NuMicro® NUC029ZAN/NUC029TAN QFN 33-pin Diagram
Apr 3, 2019
Page 18 of 102
Rev 1.06
NUC029
4.2.1.4 NuMicro® NUC029FAE TSSOP 20 pin
ACMP0_P,RXD,AIN2,P1.2
ACMP0_P,TXD,AIN3,P1.3
ACMP0_N,AIN4,P1.4
ACMP0_P,AIN5,P1.5
1
2
3
4
5
6
7
8
9
20 VDD
19 P0.4,SPISS0,PWM5
18 P0.5,MOSI_0
17 P0.6,MISO_0
16 P0.7,SPICLK0
15 P4.7,ICE_DAT
14 P4.6,ICE_CLK
13 P2.5,PWM3
12 P2.4,PWM2
11 Vss
TSSOP-20
Pin
nRST
ACMP1_P,T0EX,STADC,nINT0,P3.2
ACMP1_P,SDA0,T0,P3.4
ACMP1_P,SCL0,T1,P3.5
XTAL2,P5.1
XTAL1,P5.0 10
Figure 4-5 NuMicro® NUC029FAE TSSOP 20-pin Diagram
Apr 3, 2019
Page 19 of 102
Rev 1.06
NUC029
4.3 Pin Description
4.3.1 NuMicro® NUC029 Pin Description
Pin No.
Pin
Type
Pin Name
Description
LQFP/QFN
48-pin
QFN
33-pin
P1.5
I/O
AI
General purpose digital I/O pin.
ADC5 analog input.
1
AIN5
1
2
ACMP0_P
MOSI_0
P1.6
AI
Comparator0 positive input pin.
SPI0 MISO (Master Out, Slave In) pin.
General purpose digital I/O pin.
ADC6 analog input.
-
I/O
I/O
AI
AIN6
-
MISO_0
ACMP2_N
P1.7
I/O
AI
SPI0 MISO (Master In, Slave Out) pin.
Comparator2 negative input pin.
General purpose digital I/O pin.
ADC7 analog input.
I/O
AI
AIN7
-
3
4
SPICLK0
ACMP2_P
I/O
AI
SPI0 serial clock pin.
Comparator2 positive input pin.
I
External reset input: active LOW, with an internal pull-up. Set this pin
low reset chip to initial state.
2
nRST
(ST)
P3.0
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
Comparator1 negative input pin.
Ground pin for analog circuit.
5
6
7
3
4
5
RXD[2]
ACMP1_N
AVSS
AI
AP
I/O
O
AI
I/O
I
P3.1
General purpose digital I/O pin.
Data transmitter output pin for UART0.
Comparator1 positive input pin
General purpose digital I/O pin.
External interrupt0 input pin.
TXD[2]
ACMP1_P
P3.2
nINT0
STADC
T0EX
P3.3
8
6
I
ADC external trigger input.
I
Timer0 external capture/reset trigger input pin.
General purpose digital I/O pin.
External interrupt1 input pin.
I/O
I
nINT1
MCLK
TIEX
-
9
O
I
EBI external clock output pin.
Timer1 external capture/reset trigger input pin.
General purpose digital I/O pin.
10
7
P3.4
I/O
Apr 3, 2019
Page 20 of 102
Rev 1.06
NUC029
Pin No.
LQFP/QFN
Pin
Type
Pin Name
Description
QFN
48-pin
33-pin
T0
I/O
i/O
I/O
I/O
I/O
O
Timer0 external event counter input pin
I2C0 data input/output pin.
SDA0
P3.5
General purpose digital I/O pin.
Timer1 external event counter input pin.
I2C0 clock I/O pin.
T1
11
12
13
14
8
SCL0
CKO[2]
P4.3
Frequency divider output pin.
General purpose digital I/O pin.
PWM3 output/Capture input.
I/O
I/O
I/O
O
-
PWM3[2]
P3.6
General purpose digital I/O pin.
Frequency divider output pin.
Analog comparator0 output pin.
EBI write enable output pin.
CKO[2]
ACMP0_O
nWR
9
-
O
O
P3.7
I/O
O
General purpose digital I/O pin.
EBI read enable output pin.
-
nRD
15
16
10
11
XTAL2
O
External 4~24 MHz (high speed) crystal output pin.
I
XTAL1
VSS
External 4~24 MHz (high speed) crystal input pin.
Ground pin for digital circuit.
(ST)
12
33
13
17
18
P
LDO_CAP
P2.0
P
LDO output pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General purpose digital I/O pin.
EBI Address/Data bus bit8
PWM0 output/Capture input.
General purpose digital I/O pin.
EBI Address/Data bus bit9
PWM1 output/Capture input.
General purpose digital I/O pin.
PWM2 output/Capture input.
EBI Address/Data bus bit10.
General purpose digital I/O pin.
PWM3 output/Capture input.
EBI Address/Data bus bit11.
General purpose digital I/O pin.
-
-
19
20
21
AD8
PWM0[2]
P2.1
AD9
PWM1[2]
P2.2
14
-
15
PWM2[2]
AD10
P2.3
PWM3[2]
AD11
22
23
-
16
P2.4
Apr 3, 2019
Page 21 of 102
Rev 1.06
NUC029
Pin No.
LQFP/QFN
Pin
Type
Pin Name
Description
QFN
48-pin
33-pin
PWM4
SCL1[2]
AD12
I/O
I/O
I/O
I/O
I/O
I
PWM4 output/Capture input.
I2C1 clock I/O pin.
-
-
EBI Address/Data bus bit12.
General purpose digital I/O pin.
PWM0 output/Capture input.
Timer2 external capture/reset trigger input pin.
General purpose digital I/O pin.
PWM5 output/Capture input.
I2C1 data input/output pin.
P4.0
24
25
PWM0[2]
T2EX
P2.5
I/O
I/O
i/O
I/O
I/O
I/O
O
17
-
18
-
-
PWM5
SDA1[2]
AD13
EBI Address/Data bus bit13.
General purpose digital I/O pin.
PWM6 output/Capture input.
Analog comparator1 output pin.
EBI Address/Data bus bit14.
General purpose digital I/O pin.
EBI Address/Data bus bit15.
PWM7 output/Capture input.
General purpose digital I/O pin.
EBI chip select enable output pin.
I2C1 clock I/O pin.
P2.6
PWM6
ACMP1_O
AD14
26
I/O
I/O
I/O
I/O
I/O
O
P2.7
27
28
29
AD15
PWM7
P4.4
-
-
nCS
SCL1[2]
P4.5
I/O
I/O
O
General purpose digital I/O pin.
EBI address latch enable output pin.
I2C1 data input/output pin.
ALE
SDA1[2]
P4.6
i/O
I/O
I
General purpose digital I/O pin.
Serial Wired Debugger Clock pin.
General purpose digital I/O pin.
Serial Wired Debugger Data pin.
General purpose digital I/O pin.
SPI1 serial clock pin.
30
31
19
20
ICE_CLK
P4.7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ICE_DAT
P0.7
21
-
22
SPICLK1
AD7
32
33
EBI Address/Data bus bit7.
P0.6
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
MISO_1
Apr 3, 2019
Page 22 of 102
Rev 1.06
NUC029
Pin No.
LQFP/QFN
Pin
Type
Pin Name
Description
QFN
48-pin
33-pin
-
23
-
24
-
AD6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
EBI Address/Data bus bit6.
P0.5
General purpose digital I/O pin.
SPI1 MISO (Master Out, Slave In) pin.
EBI Address/Data bus bit5.
MOSI_1
AD5
34
35
36
P0.4
General purpose digital I/O pin.
SPI1 slave select pin.
SPISS1
AD4
EBI Address/Data bus bit4.
P4.1
General purpose digital I/O pin.
PWM1 output/Capture input.
PWM1[2]
T3EX
P0.3
-
-
Timer3 external capture/reset trigger input pin.
General purpose digital I/O pin.
EBI Address/Data bus bit3.
I/O
I/O
O
AD3
37
38
RTS0
RXD[2]
Request to Send output pin for UART0.
Data receiver input pin for UART0.
I
P0.2
I/O
I/O
I
General purpose digital I/O pin.
EBI Address/Data bus bit2.
AD2
-
CTS0
TXD[2]
Clear to Send input pin for UART0.
Data transmitter output pin for UART0.
O
P0.1
I/O
O
General purpose digital I/O pin.
Request to Send output pin for UART1.
Data receiver input pin for UART1.
Comparator3 negative input pin.
EBI Address/Data bus bit1.
RTS1
25
-
26
RXD1[2]
ACMP3_N
AD1
I
39
AI
I/O
I/O
I
P0.0
General purpose digital I/O pin.
Clear to Send input pin for UART1.
Data transmitter output pin for UART1.
Comparator3 positive input pin.
EBI Address/Data bus bit0.
CTS1
TXD1[2]
ACMP3_P
AD0
O
40
41
AI
I/O
-
Power supply for I/O ports and LDO source for internal PLL and digital
circuit.
27
VDD
P
42
43
28
29
AVDD
P1.0
AP
I/O
Power supply for internal analog circuit.
General purpose digital I/O pin.
Apr 3, 2019
Page 23 of 102
Rev 1.06
NUC029
Pin No.
LQFP/QFN
Pin
Type
Pin Name
Description
QFN
48-pin
33-pin
AIN0
T2
AI
I/O
O
ADC0 analog input.
Timer2 external event counter input pin.
EBI low byte write enable output pin.
-
-
nWRL
P1.1
AIN1
T3
I/O
AI
General purpose digital I/O pin.
ADC1 analog input.
44
I/O
O
Timer3 external event counter input pin.
EBI high byte write enable output pin.
General purpose digital I/O pin.
nWRH
P1.2
I/O
45
46
30
AIN2
AI
ADC2 analog input.
RXD1[2]
P1.3
I
Data receiver input pin for UART1.
General purpose digital I/O pin.
ADC3 analog input.
I/O
AI
31
32
AIN3
TXD1[2]
P1.4
O
Data transmitter output pin for UART1.
General purpose digital I/O pin.
ADC4 analog input.
I/O
AI
AIN4
47
48
ACMP0_N
SPISS0
P4.2
AI
Comparator0 negative input pin.
SPI0 slave select pin.
-
-
I/O
I/O
I/O
General purpose digital I/O pin.
PWM2 output/Capture input.
PWM2[2]
Note1: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power; ST = Schmitt trigger
Note2: The PWM0 ~ PWM3, RXD, TXD, RXD1, TXD1, SCL1, SDA1 and CKO can be assigned to different pins. However, a pin
function can only be assigned to a pin at the same time, i.e. software cannot assign RXD to P0.3 and P3.0 at the same time.
Apr 3, 2019
Page 24 of 102
Rev 1.06
NUC029
Pin No.
Pin
Type
Pin Name
Description
TSSOP
20-pin
P1.2
I/O
AI
I
General purpose digital I/O pin.
ADC2 analog input.
AIN2
1
2
RXD
Data receiver input pin for UART0.
Comparator0 positive input pin.
General purpose digital I/O pin.
ADC3 analog input.
ACMP0_P
P1.3
AI
I/O
AI
O
AIN3
TXD
Data transmitter output pin for UART0.
Comparator0 positive input pin.
General purpose digital I/O pin.
ADC4 analog input.
ACMP0_P
P1.4
AI
I/O
AI
AI
I/O
AI
AI
AP
3
4
AIN4
ACMP0_N
P1.5
Comparator0 negative input pin.
General purpose digital I/O pin.
ADC5 analog input.
AIN5
ACMP0_P
AVSS
Comparator0 positive input pin.
Ground pin for analog circuit.
I
External reset input: active LOW, with an internal pull-up. Set this pin low reset
chip to initial state.
5
6
nRST
(ST)
P3.2
I/O
I
General purpose digital I/O pin.
External interrupt0 input pin.
nINT0
STADC
T0EX
ACMP1_P
P3.4
I
ADC external trigger input.
I
Timer0 external capture/reset trigger input pin.
Comparator1 positive input pin
General purpose digital I/O pin.
Timer0 external event counter input pin
I2C0 data input/output pin.
AI
I/O
I/O
i/O
AI
I/O
I/O
I/O
AI
I/O
O
T0
7
8
SDA0
ACMP1_P
P3.5
Comparator1 positive input pin
General purpose digital I/O pin.
Timer1 external event counter input pin.
I2C0 clock I/O pin.
T1
SCL0
ACMP1_P
P5.1
Comparator1 positive input pin
General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal output pin.
General purpose digital I/O pin.
9
XTAL2
P5.0
10
I/O
Apr 3, 2019
Page 25 of 102
Rev 1.06
NUC029
Pin No.
Pin
Type
Pin Name
Description
TSSOP
20-pin
I
XTAL1
External 4~24 MHz (high speed) crystal input pin.
(ST)
11
12
VSS
P
Ground pin for digital circuit.
General purpose digital I/O pin.
PWM0 output.
P2.4
I/O
I/O
I/O
I/O
I/O
I
PWM2
P2.5
General purpose digital I/O pin.
PWM3 output.
13
14
15
16
17
18
PWM3
P4.6
General purpose digital I/O pin.
Serial Wired Debugger Clock pin.
General purpose digital I/O pin.
Serial Wired Debugger Data pin.
General purpose digital I/O pin.
SPI0 serial clock pin.
ICE_CLK
P4.7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
ICE_DAT
P0.7
SPICLK0
P0.6
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
SPI0 MISO (Master Out, Slave In) pin.
General purpose digital I/O pin.
SPI1 slave select pin.
MISO_0
P0.5
MOSI_0
P0.4
SPISS0
PWM5
VDD
19
20
PWM5 output.
Power supply for I/O ports and LDO source for internal PLL and digital circuit.
Note1: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power; ST = Schmitt trigger
Apr 3, 2019
Page 26 of 102
Rev 1.06
NUC029
5
FUNCTIONAL DESCRIPTION
5.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entere d on Reset, and can be entered as a result of an exception return.
Figure 5-1 shows the functional controller of processor.
Cortex® -M0 Components
Cortex®-M0 processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
Cortex®-M0
Processor
Core
Debug
Access
Port
Wakeup
Interrupt
Controller
(WIC)
Debugger
Interface
Bus Matrix
(DAP)
AHB-Lite
Interface
Serial Wire or
JTAG Debug Port
Figure 5-1 Functional Controller Diagram
The implemented device provides the following components and features:
A low gate count processor:
-
-
-
-
-
-
-
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
-
-
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
NVIC:
Apr 3, 2019
Page 27 of 102
Rev 1.06
NUC029
-
-
-
-
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support
-
-
-
-
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
-
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
-
Single 32-bit slave port that supports the DAP (Debug Access Port)
Apr 3, 2019
Page 28 of 102
Rev 1.06
NUC029
5.2 System Manager
5.2.1 Overview
System management includes the following sections:
System Resets
System Power Architecture
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
5.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Hardware Reset
–
–
–
–
–
Power-on Reset (POR)
Low level on the RESET pin (nRST)
Watchdog Time-out Reset (WDT)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD)
Software Reset
–
–
–
MCU Reset - SYSRESETREQ(AIRCR[2])
Cortex® -M0 Core One-shot Reset - CPU_RST(IPRSTC1[1])
Chip One-shot Reset - Chip_RST(IPRSTC1[0])
Note: ISPCON.BS keeps the original value after MCUReset and CPU Reset.
Apr 3, 2019
Page 29 of 102
Rev 1.06
NUC029
5.2.3 System Power Distribution
In this chip, the power distribution is divided into three segments.
Analog power from AVDD and AVSS provides the power for analog components
operation. AVDD must be equal to VDD to avoid leakage current.
Digital power from VDD and VSS supplies the power to the I/O pins and internal
regulator which provides a fixed 1.8 V power for digital operation.
Build-in a capacitor for internal voltage regulator. (NUC029FAE only)
The output of internal voltage regulator, LDO_CAP, requires an external capacitor which should
be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level
with the digital power (VDD). Figure 5-2 shows the NuMicro® NUC029xAN power distribution and
Figure 5-3 shows the NuMicro® NUC029FAE power distribution.
Analog Comparator
AVDD
12-bit
SAR-ADC
Low
Voltage
Reset
Brown
Out
Detector
AVSS
Internal
22.1184 MHz and
10 kHz Oscillator
Temperature
Sensor
FLASH
Digital Logic
LDO_CAP
1uF
1.8V
POR18
POR50
5V to 1.8V
LDO
PLL
IO cell
GPIO Pins
VDD VSS
NuMicro® NUC029xAN Power Distribution
Figure 5-2 NuMicro® NUC029xAN Power Distribution Diagram
Apr 3, 2019
Page 30 of 102
Rev 1.06
NUC029
Analog Comparator
10-bit
SAR-ADC
Low
Voltage
Reset
Brown
Out
Detector
Internal
FLASH
Digital Logic
22.1184 MHz and
10 kHz Oscillator
1.8V
500pF
POR18
5V to 1.8V
LDO
IO cell
GPIO Pins
VDD VSS
NuMicro® NUC029FAE Power Distribution
Figure 5-3 NuMicro® NUC029FAE Power Distribution Diagram
5.2.4 System Memory Map
The NuMicro® NUC029 series provides 4G-byte addressing space. The memory locations
assigned to each on-chip controllers are shown in the following table. The detailed register
definition, addressing space, and programming detailed will be described in the following sections
for each on-chip peripheral. The NuMicro® NUC029 series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0000_FFFF
0x2000_0000 – 0x2000_0FFF
FLASH_BA
SRAM_BA
FLASH Memory Space (64 KB)
SRAM Memory Space (4 KB)
EBI Space (0x6000_0000 ~ 0x6001_FFFF) (NUC029LAN/NUC029NAN Only)
0x6000_0000 – 0x6001_FFFF
EBI_BA
External Memory Space (128 KB )
AHB Controllers Space (0x5000_0000 ~ 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
GCR_BA
System Global Control Registers
Apr 3, 2019
Page 31 of 102
Rev 1.06
NUC029
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_C000 – 0x5000_FFFF
0x5001_0000 – 0x5001_03FF
0x5001_4000 – 0x5001_7FFF
CLK_BA
Clock Control Registers
INT_BA
Interrupt Multiplexer Control Registers
GPIO (P0 ~ P4) Control Registers
GPIO_BA
FMC_BA
EBI_CTL_BA
HDIV_BA
Flash Memory Control Registers
EBI Control Registers (NUC029LAN/NUC029NAN only)
Hardware Divider Register (NUC029xAN only)
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_40FF
0x4000_4100 – 0x4000_7FFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4003_4000 – 0x4003_7FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_FFFF
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
0x4014_0000 – 0x4014_3FFF
0x4015_0000 – 0x4015_3FFF
0x401D_0000 – 0x401D_3FFF
WDT_BA
Watchdog Timer Control Registers
WWDT_BA
TMR01_BA
I2C0_BA
Window Watchdog Timer Control Registers (NUC029xAN only)
Timer0/Timer1 Control Registers
I2C0 Interface Control Registers
SPI0_BA
SPI0 with master/slave function Control Registers
SPI1 with master/slave function Control Registers
PWM0/1/2/3 Control Registers
SPI1_BA
PWMA_BA
UART0_BA
ACMP01_BA
ADC_BA
UART0 Control Registers
Analog Comparator0/ Analog Comparator1 Control Registers
Analog-Digital-Converter (ADC) Control Registers
Timer2/Timer3 Control Registers
TMR23_BA
I2C1_BA
I2C1 Interface Control Registers (Nuc029xAN only)
PWM4/5/6/7 Control Registers
PWMB_BA
UART1_BA
ACMP23_BA
UART1 Control Registers
Analog Comparator2/ Analog Comparator3 Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SYST_BA
NVIC_BA
SCB_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 5-1 NuMicro® NUC029xAN Address Space Assignments for On-Chip Controllers
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0000_3FFF
0x2000_0000 – 0x2000_0FFF
FLASH_BA
SRAM_BA
FLASH Memory Space (16 KB)
SRAM Memory Space (2 KB)
AHB Controllers Space (0x5000_0000 ~ 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
GCR_BA
CLK_BA
System Global Control Registers
Clock Control Registers
Apr 3, 2019
Page 32 of 102
Rev 1.06
NUC029
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_C000 – 0x5000_FFFF
INT_BA
GP_BA
FMC_BA
Interrupt Multiplexer Control Registers
GPIO (P0 ~ P5) Control Registers
Flash Memory Control Registers
APB Controllers Space (0x4000_0000 ~ 0x401F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_3FFF
WDT_BA
TMR_BA
I2C_BA
Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
I2C Interface Control Registers
SPI_BA
SPI with master/slave function Control Registers
PWM Control Registers
PWMA_BA
UART_BA
ACMP_BA
ADC_BA
UART Control Registers
Analog Comparator Control Registers
Analog-Digital-Converter (ADC) Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCB_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 5-2 NuMicro® NUC029FAE Address Space Assignments for On-Chip Controllers
Apr 3, 2019
Page 33 of 102
Rev 1.06
NUC029
5.2.5 Whole System Memory Mapping
4 GB
0xFFFF_FFFF
|
Reserved
System Control
Reserved
EBI
System Control
0xE000_F000
0xE000_EFFF
0xE000_E000
0xE000_DFFF
|
System Control Block
0xE000_ED00
SCB_BA
NVIC_BA
SYST_BA
SCS_BA
External Interrupt Controller 0xE000_E100
System Timer Control
System Control Space
0xE000_E010
0xE000_E000
0x6002_0000
0x6001_FFFF
0x6000_0000
0x5FFF_FFFF
|
Reserved
0x5020_0000
AHB peripherals
Hardware Divider Control
EBI Control
0x501F_FFFF
0x5000_0000
0x4FFF_FFFF
0x5001_4000
0x5001_0000
0x5000_C000
0x5000_4000
HDIV_BA
EBI_CTL_BA
FLASH_BA
GPIO_BA
INT_BA
AHB
FMC
GPIO Control
Reserved
|
Interrupt Multiplexer Control 0x5000_0300
0x4020_0000
0x401F_FFFF
Clock Control
0x5000_0200
0x5000_0000
CLK_BA
System Global Control
GCR_BA
APB
|
1 GB
0x4000_0000
0x3FFF_FFFF
APB peripherals
ACMPB Control
UART1 Control
PWM4/5/6/7 Control
I2C1 Control
0x401D_0000
0x4015_0000
0x4014_0000
0x4012_0000
0x4011_0000
0x400E_0000
0x400D_0000
0x4005_0000
0x4004_0000
0x4003_4000
0x4003_0000
0x4002_0000
ACMP23_BA
UART1_BA
PWMB_BA
I2C1_BA
Reserved
|
0x2000_1000
0x2000_0FFF
Timer2/Timer3 Control
ADC Control
TMR23_BA
ADC_BA
4 KB SRAM
Reserved
|
ACMPA Control
UART0 Control
PWM0/1/2/3 Control
SPI1 Control
ACMP01_BA
UART0_BA
PWMA_BA
SPI1_BA
0.5 GB
0x2000_0000
0x1FFF_FFFF
|
SPI0 Control
SPI0_BA
0x0001_0000
0x0000_FFFF
I2C Control
I2C0_BA
64 KB on-chip Flash
(NUC029LAN/NUC029NAN)
Timer0/Timer1 Control
0x4001_0000
TMR01_BA
0x0000_7FFF
0x0000_0000
WDT Control
0x4000_4100
0x4000_4000
WWDT_BA
WDT_BA
32 KB on-chip Flash
(NUC029ZAN/NUC029TAN)
0 GB
WWDT Control
Figure 5-4 NuMicro® NUC029xAN Whole System Memory Mapping
Apr 3, 2019
Page 34 of 102
Rev 1.06
NUC029
System Control
System Control
4 GB
0xFFFF_FFFF
|
0xE000_ED00 SCS_BA
0xE000_E100 SCS_BA
0xE000_E010 SCS_BA
Reserved
System Control
Reserved
Reserved
Reserved
AHB
External Interrupt Control
System Timer Control
0xE000_F000
0xE000_EFFF
0xE000_E000
0xE000_E00F
|
0x6002_0000
0x6001_FFFF
0x6000_0000
0x5FFF_FFFF
|
0x5020_0000
0x501F_FFFF
0x5000_0000
0x4FFF_FFFF
AHB peripherals
FMC
0x5000_C000 FMC_BA
0x5000_4000 GP_BA
GPIO Control
Interrupt Multiplexer Control 0x5000_0300 INT_BA
Clock Control
0x5000_0200 CLK_BA
0x5000_0000 GCR_BA
Reserved
|
System Global Control
0x4020_0000
0x401F_FFFF
APB
|
1 GB
0x4000_0000
0x3FFF_FFFF
APB peripherals
ADC Control
0x400E_0000 ADC_BA
0x400D_0000 CMP_BA
0x4005_0000 UART_BA
0x4004_0000 PWM_BA
0x4003_0000 SPI_BA
0x4002_0000 I2C_BA
0x4001_0000 TMR_BA
0x4000_4000 WDT_BA
Reserved
|
ACMP Control
UART Control
0x2000_0800
0x2000_07FF
0x2000_0000
0x1FFF_FFFF
PWM Control
SPI Control
2 KB SRAM
Reserved
0.5 GB
I2C Control
Timer0/Timer1 Control
WDT Control
|
0x0000_4000
0x0000_3FFF
0x0000_0000
16 KB on-chip Flash
(NUC029FAE)
0 GB
Figure 5-5 NuMicro® NUC029FAE Whole System Memory Mapping
Apr 3, 2019
Page 35 of 102
Rev 1.06
NUC029
5.2.6 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
5.2.7 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core
and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
Apr 3, 2019
Page 36 of 102
Rev 1.06
NUC029
5.2.7.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by NuMicro® NUC029 series. Software
can set four levels of priority on some of these exceptions as well as on all interrupts. The highest
user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default
priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth
priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Reset
Vector Number
Priority
-3
1
NMI
2
-2
Hard Fault
Reserved
3
-1
4 ~ 10
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
11
Reserved
12 ~ 13
PendSV
14
SysTick
15
16 ~ 47
Interrupt (IRQ0 ~ IRQ31)
Table 5-3 Exception Model
Apr 3, 2019
Page 37 of 102
Rev 1.06
NUC029
Interrupt Number
Vector
Number
Interrupt
Name
Source
Module
Power-Down
Wake-Up
Interrupt Description
(Bit In Interrupt
Registers)
1 ~ 15
16
-
-
-
System exceptions
-
0
1
2
3
4
BOD_INT
WDT_INT
EINT0
Brown-out Brown-out low voltage detected interrupt
Yes
Yes
Yes
Yes
Yes
17
WDT
GPIO
GPIO
GPIO
Watchdog Timer interrupt
18
External signal interrupt from P3.2 pin
External signal interrupt from P3.3 pin
External signal interrupt from P0[7:0]/P1[7:0]
19
EINT1
20
P0/1_INT
External signal interrupt from
P2[7:0]/P3[7:0]/P4[7:0], except P3.2 and P3.3
21
5
P2/3/4_INT
GPIO
Yes
22
23
6
7
PWMA_INT
PWMB_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART0_INT
UART1_INT
SPI0_INT
SPI1_INT
-
PWM0~3
PWM4~7
TMR0
TMR1
TMR2
TMR3
UART0
UART1
SPI0
PWM0, PWM1, PWM2 and PWM3 interrupt
PWM4, PWM5, PWM6 and PWM7 interrupt
Timer0 interrupt
No
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
-
24
8
25
9
Timer1 interrupt
26
10
Timer2interrupt
27
11
Timer3 interrupt
28
12
UART0 interrupt
29
13
UART1 interrupt
30
14
SPI0 interrupt
31
15
SPI1
SPI1 interrupt
32 ~ 33
34
16 ~ 17
18
-
Reserved
I2C0_INT
I2C1_INT
-
I2C0
I2C0 interrupt
Yes
Yes
-
35
19
I2C1
I2C1 interrupt
36 ~ 40
41
20 ~ 24
25
-
Reserved
ACMP01_INT
ACMP23_INT
-
ACMP0/1
ACMP2/3
-
Analog Comparator0 or Comparator1 interrupt
Analog Comparator2 or Comparator3 interrupt
Reserved
Yes
Yes
-
42
26
43
27
Clock controller interrupt for chip wake-up from
Power-down state
44
28
PWRWU_INT
CLKC
Yes
45
29
ADC_INT
-
ADC
ADC interrupt
Reserved
No
46 ~ 47
30 ~ 31
-
-
Table 5-4 NuMicro® NUC029xAN System Interrupt Map
Apr 3, 2019
Page 38 of 102
Rev 1.06
NUC029
Interrupt Number
Vector
Number
Interrupt
Name
Source
Module
Power-Down
Wake-Up
Interrupt Description
(Bit In Interrupt
Registers)
1 ~ 15
16
-
-
-
System exceptions
-
0
1
2
3
4
BOD_INT
WDT_INT
EINT0
-
Brown-out Brown-out low voltage detected interrupt
Yes
Yes
Yes
-
17
WDT
GPIO
-
Watchdog Timer interrupt
18
External signal interrupt from P3.2 pin
Reserved
19
20
P0/1_INT
GPIO
External signal interrupt from P0[7:0]/P1[7:0]
Yes
External signal interrupt from
P2[7:0]/P3[7:0]/P4[7:0], except P3.2
21
5
P2/3/4_INT
GPIO
Yes
22
23
6
7
PWM_INT
BRAKE_INT
TMR0_INT
TMR1_INT
-
PWM
PWM
TMR0
TMR1
-
PWM interrupt
PWM interrupt
Timer0 interrupt
Timer1 interrupt
Reserved
No
No
Yes
Yes
-
24
8
25
9
26 ~ 27
28
10 ~ 11
12
UART_INT
-
UART
-
UART interrupt
Reserved
Yes
-
29
13
30
14
SPI_INT
-
SPI
SPI interrupt
No
-
31
15
-
Reserved
32
16
GP5_INT
GPIO
External signal interrupt from P5
Yes
HIRC_TRIM_
INT
33
17
HIRC
HIRC trim interrupt
NO
34
18
I2C_INT
I2C
I2C interrupt
Yes
35 ~ 40
41
19 ~ 24
25
-
-
ACMP
-
Reserved
-
Yes
-
ACMP_INT
-
Analog Comparator interrupt
Reserved
42 ~ 43
26 ~ 27
Clock controller interrupt for chip wake-up from
Power-down state
44
28
PWRWU_INT
CLKC
Yes
45
29
ADC_INT
-
ADC
ADC interrupt
No
46 ~ 47
30 ~ 31
-
Reserved
-
Table 5-5 NuMicro® NUC029FAE System Interrupt Map
Apr 3, 2019
Page 39 of 102
Rev 1.06
NUC029
5.2.7.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Table 5-6 Vector Table Format
Vector Number
5.2.7.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
Apr 3, 2019
Page 40 of 102
Rev 1.06
NUC029
5.3 Clock Controller of NuMicro® NUC029xAN
5.3.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex® -M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave
Power-down mode. In the Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal oscillator (HXT) and 22.1184 MHz internal high speed RC oscillator (HIRC)to
reduce the overall system power consumption. The following figures show the clock generator
and the overview of the clock source control.
The clock generator consists of 4 clock sources as listed below:
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLL source can be selected from external
4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz internal high
speed RC oscillator (HIRC)) (PLL FOUT)
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
XTL12M_EN (PWRCON[0])
HXT
XTAL1
XTAL2
PLL_SRC (PLLCON[19])
4~24 MHz HXT
0
1
PLL FOUT
PLL
OSC22M_EN (PWRCON[2])
22.1184 MHz
HIRC
HIRC
LIRC
OSC10K_EN(PWRCON[3])
10 kHz
LIRC
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 5-6 NuMicro® NUC029xAN Clock Generator Block Diagram
Apr 3, 2019
Page 41 of 102
Rev 1.06
NUC029
HIRC
111
011
010
001
000
CPUCLK
HCLK
CPU
HDIV
EBI
LIRC
PLL FOUT
Reserved
HXT
1/(HCLK_N+1)
ACMP0
ACMP1
ACMP2
ACMP3
PCLK
CLKSEL0[2:0]
I2C0
I2C1
HIRC
FMC
HCLK
1
0
SPI0
SPI1
PLL FOUT
CLKSEL1[4:5]
HIRC
11
10
01
00
HCLK
1/(ADC_N+1)
ADC
PLL FOUT
HXT
CLKSEL1[3:2]
HIRC
11
01
00
PLL FOUT
HXT
1/(UART_N+1)
UART 0-2
CLKSEL1[25:24]
LIRC
BOD
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 5-7 NuMicro® NUC029xAN Clock Source Controller Overview (1/2)
Apr 3, 2019
Page 42 of 102
Rev 1.06
NUC029
HIRC
LIRC
111
101
011
TMR 0
TMR 1
TMR 2
TMR 3
T0~T3
HCLK
HXT
010
000
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
HIRC
HCLK
HXT
1/2
1/2
1/2
111
011
010
001
000
CPUCLK
1
0
SysTick
Reserved
HXT
SYST_CSR[2]
CLKSEL0[5:3]
HIRC
11
10
01
00
FDIV
HCLK
Reserved
HXT
PWM 6-7
PWM 4-5
PWM 2-3
PWM 0-1
CLKSEL2[7:2]
CLKSEL1[31:28]
LIRC
11
10
WWDT
WDT
HCLK/2048
CLKSEL2[17:16]
LIRC
11
10
01
HCLK
1/2048
Reserved
CLKSEL1[1:0]
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 5-8 NuMicro® NUC029xAN Clock Source Controller Overview (2/2)
Apr 3, 2019
Page 43 of 102
Rev 1.06
NUC029
5.3.2 System Clock and SysTick Clock
The system clock has 4 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 5-9.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
HIRC
111
10 kHz LIRC
011
CPUCLK
CPU
PLL FOUT
010
HCLK
1/(HCLK_N+1)
AHB
APB
Reserved
001
000
HCLK_N (CLKDIV[3:0])
PCLK
4~24 MHz HXT
CPU in Power Down Mode
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 5-9 NuMicro® NUC029xAN System Clock Block Diagram
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 5-10.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
111
011
010
001
000
1/2
1/2
1/2
HCLK
STCLK
4~24 MHz
32.768 kHz
4~24 MHz
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 5-10 NuMicro® NUC029xAN SysTick Clock Control Block Diagram
Apr 3, 2019
Page 44 of 102
Rev 1.06
NUC029
5.3.3 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
-
10 kHz internal low speed RC oscillator clock (LIRC)
Peripherals Clock (when 10 kHz intertnal low speed RC oscillator is adopted as clock
source)
Apr 3, 2019
Page 45 of 102
Rev 1.06
NUC029
5.3.4 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CKO pin. Therefore there are 16 options of power-of-2 divided clocks
with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN (APBCLK[6])
22.1184 MHz
HIRC
11
HCLK
FRQDIV_CLK
10
01
00
10 kHz LIRC
4~24 MHz HXT
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 5-11 NuMicro® NUC029xAN Clock Source of Frequency Divider
DIVIDER_EN
(FRQDIV[4])
Enable
FSEL
(FRQDIV[3:0])
divide-by-2 counter
16 chained
divide-by-2 counter
FRQDIV_CLK
1/2
1/22
1/23
…...
1/215 1/216
0000
0001
:
CKO
16 to 1
MUX
:
1110
1111
Figure 5-12 NuMicro® NUC029xAN Frequency Divider Block Diagram
Apr 3, 2019
Page 46 of 102
Rev 1.06
NUC029
5.4 Clock Controller of NuMicro® NUC029FAE
5.4.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex® -M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave
Power-down mode. In the Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal oscillator (HXT) and 22.1184 MHz internal high speed RC oscillator (HIRC)to
reduce the overall system power consumption. The following figures show the clock generator
and the overview of the clock source control.
The clock generator consists of 3 clock sources as listed below:
4~24 MHz external high speed crystal oscillator (HXT) or 32.768 kHz external low
speed crystal oscillator (LXT)
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
XTLCLK_EN (PWRCON[1:0])
HXT or LXT
4~24 MHz HXT
or
32.768 kHz LXT
XTAL1
XTAL2
OSC22M_EN (PWRCON[2])
HIRC
LIRC
22.1184 MHz
HIRC
OSC10K_EN(PWRCON[3])
10 kHz
LIRC
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
LXT = 32.768 kHz external low speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 5-13 NuMicro® NUC029FAE Clock Generator Block Diagram
Apr 3, 2019
Page 47 of 102
Rev 1.06
NUC029
5.4.2 System Clock and SysTick Clock
The system clock has 3 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 5-14.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
HIRC
111
10 kHz LIRC
011
CPUCLK
CPU
Reserved
010
HCLK
1/(HCLK_N+1)
AHB
APB
Reserved
001
000
HCLK_N (CLKDIV[3:0])
PCLK
4~24 MHz HXT or
32.768 kHz LXT
CPU in Power Down Mode
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 5-14 NuMicro® NUC029FAE System Clock Block Diagram
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 5-15.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
111
011
010
001
000
1/2
1/2
1/2
HCLK
STCLK
4~24 MHz
32.768 kHz
4~24 MHz
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 5-15 NuMicro® NUC029FAE SysTick Clock Control Block Diagram
Apr 3, 2019
Page 48 of 102
Rev 1.06
NUC029
5.4.3 ISP Clock Source Selection
The clock source of ISP is from AHB clock (HCLK). Please refer to the register AHBCLK.
HCLK
ISP (In System
Programmer)
ISP_EN (AHBCLK[2])
Figure 5-16 NuMicro® NUC029FAE AHB Clock Source for HCLK
5.4.4 Module Clock Source Selection
The peripheral clock has different clock source switch settings depending on different peripherals.
PCLK
Watch Dog Timer
WDT_EN (APBCLK[0])
Timer0
TMR0_EN (APBCLK[2])
Timer1
TMR1_EN (APBCLK[3])
Frequency Divider
FDIV_EN (APBCLK[6])
I2C
I2C_EN (APBCLK[8])
SPI
SPI_EN (APBCLK[12])
UART
UART_EN (APBCLK[16])
PWM01
PWM01_EN (APBCLK[20])
PWM23
PWM23_EN (APBCLK[21])
PWM45
PWM45_EN (APBCLK[22])
ADC
ADC_EN (APBCLK[28])
ACMP
CMP_EN (APBCLK[30])
Apr 3, 2019
Page 49 of 102
Rev 1.06
NUC029
Figure 5-17 NuMicro® NUC029FAE Peripherals Clock Source Selection for PCLK
Ext. CLK (HXT Or
HIRC
LIRC
PCLK
LXT)
Yes
Yes
Yes
No
WDT
Timer0
Timer1
I2C
No
Yes
Yes
No
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
SPI
No
No
No
UART
PWM
ADC
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
No
No
ACMP
No
Table 5-7 NuMicro® NUC029FAE Peripheral Clock Source Selection Table
5.4.5 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
-
10 kHz internal low speed RC oscillator clock (LIRC)
32.768 kHz external low speed crystal oscillator (LXT) clock (If PD_32K = 1 and
XTLCLK_EN[1:0] = 10)
Peripherals Clock (When 10 kHz low speed oscillator is adopted as clock source)
-
-
Watchdog Clock
Timer 0/1 Clock
Apr 3, 2019
Page 50 of 102
Rev 1.06
NUC029
5.5 Flash Memory Controller (FMC)
5.5.1 Overview
The NuMicro® NUC029 series has 64/32/16K bytes on-chip embedded Flash for application
program memory (APROM) that can be updated through ISP procedure. The In-System-
Programming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip is powered on, Cortex® -M0 CPU fetches code from APROM or LDROM decided
by boot select (CBS) in CONFIG0.
The NuMicro® NUC029 series also provides additional Data Flash for user to store some
application dependent data before chip power off. The NUC029xAN provides additional 4 Kbytes
DATA Flash, and NUC029FAE provides Data Flash that is shared with APROM and its start
address is configurable and defined by user in CONFIG1.
5.5.2 Features
Runs up to 50 MHz with zero wait cycle for continuous address read access
64/32/16 KB application program memory (APROM)
Up to 4KB In-System-Programming (ISP) loader program memory (LDROM)
Fixed 4KB Data Flash for NUC029xAN
Configurable Data Flash size and Programmable Data Flash start address for
NUC029FAE
All embedded flash memory supports 512 bytes page erase
Supports In-Application-Programming (IAP) to switch code between APROM and
LDROM without reset
In-System-Programming (ISP) to update on-chip Flash
Apr 3, 2019
Page 51 of 102
Rev 1.06
NUC029
5.6 External Bus Interface (EBI) (NUC029LAN/NUC029NAN Only)
5.6.1 Overview
The NuMicro® NUC029LAN/NUC029NAN has an external bus interface (EBI) to access external
device. To save the connections between external device and this chip, EBI support address bus
and data bus multiplex mode. Also, address latch enable (ALE) signal is used to differentiate the
address and data cycle.
5.6.2 Features
Supports external devices with maximum 64 KB size (8-bit data width) / 128 KB (16-
bit data width)
Supports variable external bus base clock (MCLK) which based on HCLK
Supports 8-bit or 16-bit data width
Supports variable data access time (tACC), address latch enable time (tALE) and
address hold time (tAHD)
Supports address bus and data bus multiplex mode to save the address pins
Supports configurable idle cycle for different access condition: Write command finish
(W2X), Read-to-Read (R2R)
Supports zero address hold time with read/write operation and write buffer for write
operation to enhance read/write performance
Apr 3, 2019
Page 52 of 102
Rev 1.06
NUC029
5.7 General Purpose I/O (GPIO)
5.7.1 Overview
The NuMicro® NUC029 series has up to 40 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 40 pins are arranged in 6 ports named
as P0, P1, P2, P3, P4 and P5. Each port has the maximum of 8 pins. Each of the 40 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull
output, Open-drain output or Quasi-bidirectional mode. Each I/O pin has a very weak individual
pull-up resistor which is about 110~300 K for VDD is from 5.0 V to 2.5 V.
5.7.2 Features
Four I/O modes:
Quasi-bidirectional
-
-
-
-
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable by Px_TYPE[15:0] in Px_MFP[23:16]
I/O pin configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by CIOINI(CONFIG[10]) setting
-
For NUC029xAN:
If CIOINI is 0, all GPIO pins in input tri-state mode after chip reset
If CIOINI is 1, all GPIO pins in Quasi-bidirectional mode after chip reset
(Default)
After reset, the I/O mode of all pins are stay in Quasi-bidirectional mode and
each port data register Px_DOUT[7:0] resets to 0x000_00FF.
-
For NUC029FAE:
If CIOINI is 0, all GPIO pins in Quasi-bidirectional mode after chip reset
If CIOINI is 1, all GPIO pins in input tri-state mode after chip reset (Default)
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function.
Apr 3, 2019
Page 53 of 102
Rev 1.06
NUC029
5.8 Timer Controller (TIMER)
5.8.1 Overview
The timer controller includes up to 4 sets 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
5.8.2 Features
Up to 4 sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides four timer counting modes: one-shot, periodic, toggle and continuous
counting
Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the event from external counter pin (T0~T3)
24-bit capture value is readable through TCAP (Timer Capture Data Register)
Supports external pin capture (T0EX~T3EX) for interval measurement
Supports external pin capture (T0EX~T3EX) for reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Supports internal capture triggered while internal ACMP output signal transition
(NUC029xAN only)
Supports Inter-Timer trigger mode (NUC029xAN only)
Supports internal signal (CPO0, CPO1) for interval measurement (NUC029FAE only)
Apr 3, 2019
Page 54 of 102
Rev 1.06
NUC029
5.9 PWM Generator and Capture Timer (PWM) (NUC029xAN Only)
5.9.1 Overview
The NuMicro® NUC029xAN has 2 sets of PWM group supporting a total of 4 sets of PWM
generators that can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4
complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6,
PWM7) with 4 programmable Dead-zone generators.
Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM
period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 4
sets of PWM generators provide 8 independent PWM interrupt flags set by hardware when the
corresponding PWM period down counter reaches 0. Each PWM interrupt source with its
corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be
configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to
output PWM waveform continuously.
When DZEN01 (PCR[4]) is set, PWM0 and PWM1 perform complementary PWM paired function;
the paired PWM period, duty and Dead-time are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers, the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching 0. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-timer
is set as auto-reload mode, when the down counter reaches 0, it is reloaded with PWM Counter
Register (CNRx) automatically then starts decreasing, repeatedly. If the PWM-timer is set as one-
shot mode, the down counter will stop and generate one interrupt request when it reaches 0.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CRL_IE0 (CCR0[1]) (Rising latch Interrupt enable) and CFL_IE0
(CCR0[2]) (Falling latch Interrupt enable) to decide the condition of interrupt occur. Capture
channel 1 has the same feature by setting CRL_IE1 (CCR0[17]) and CFL_IE1 (CCR0[18]). And
capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, including: Read
PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write
1 to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0.
Apr 3, 2019
Page 55 of 102
Rev 1.06
NUC029
5.9.2 Features
5.9.2.1 PWM Function:
Up to 2 PWM groups (PWMA/PWMB) to support 8 PWM channels or 4
complementary PWM paired channels
Each PWM group has two PWM generators with each PWM generator supporting one
8-bit prescaler, one clock divider, two PWM-timers, one Dead-zone generator and two
PWM outputs.
Up to 16-bit resolution
One-shot or Auto-reload mode
Edge-aligned type or Center-aligned type option
PWM trigger ADC start-to-conversion
5.9.2.2 Capture Function:
Timing control logic shared with PWM Generators
Supports 8 Capture input channels shared with 8 PWM output channels
Each channel supports one rising latch register (CRLRx), one falling latch register
(CFLRx) and Capture interrupt flag (CAPIFx)
Apr 3, 2019
Page 56 of 102
Rev 1.06
NUC029
5.10 Enhanced PWM Generator (NUC029FAE Only)
5.10.1 Overview
The NuMicro® NUC029FAE has built one PWM unit which is specially designed for motor driving
control applications. The PWM unit supports six PWM generators which can be configured as
three independent PWM outputs, PWM2, PWM3 and PWM5, or as three complementary PWM
pairs, (PWM0, PWM1), (PWM2, PWM3) and (PWM4, PWM5) with three programmable dead-
zone generators.
Every complementary PWM pairs share one 8-bit prescaler. There are six clock dividers providing
five divided frequencies (1, 1/2, 1/4, 1/8, 1/16) for each channel. Each PWM output has
independent 16-bit counter for PWM period control, and 16-bit comparators for PWM duty control.
The six PWM generators provide twelve independent PWM interrupt flags which are set by
hardware when the corresponding PWM period counter comparison matched period and duty.
Each PWM interrupt source with its corresponding enable bit can request PWM interrupt. The
PWM generators can be configured as One-shot mode to produce only one PWM cycle signal or
Auto-reload mode to output PWM waveform continuously.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers, the updated value will be loaded into the 16-bit down
counter/ comparator at the end of current period. The double buffering feature avoids glitch at
PWM outputs.
Besides PWM, Motor controlling also need Timer, ACMP and ADC to work together. In order to
control motor more precisely, we provide some registers that not only configure PWM but also
Timer, ADC and ACMP, by doing so, it can save more CPU time and control motor with ease
especially in BLDC.
5.10.2 Features
The PWM unit supports the following features:
Independent 16-bit PWM duty control units with maximum six port pins:
-
-
Three independent PWM outputs –PWM2, PWM3 and PWM5
Three complementary PWM pairs, with each pin in a pair mutually complement
to each other and capable of programmable dead-zone insertion – (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5)
Group control bit – PWM2 and PWM4 are synchronized with PWM0, PWM3 and
PWM5 are synchronized with PWM1
One-shot (only support edge alignment mode) or Auto-reload mode PWM
Up to 16-bit resolution
Supports Edge-aligned and Center-aligned mode
Programmable dead-zone insertion between complementary paired PWMs
Each pin of PWM0 to PWM5 has independent polarity setting control
Hardware fault brake protections
-
Two Interrupt source types:
Apr 3, 2019
Page 57 of 102
Rev 1.06
NUC029
Synchronously requested at PWM frequency when down counter
comparison matched (edge- and center-aligned mode) or underflow (edge-
aligned mode)
Requested when external fault brake asserted
BKP0: EINT0 or CPO1
The PWM signals before polarity control stage are defined in the view of positive logic.
The PWM ports is active high or active low are controlled by polarity control register
Supports independently rising CMR matching (in Center-aligned mode), CNR
matching (in Center-aligned mode), falling CMR matching, period matching to trigger
ADC conversion
Timer comparing matching event trigger PWM to do phase change in BLDC
application
Supports ACMP output event trigger PWM to force PWM output at most one period
low, this feature is usually for step motor control
Provides interrupt accumulation function
Apr 3, 2019
Page 58 of 102
Rev 1.06
NUC029
5.11 Watchdog Timer (WDT)
5.11.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up system from Idle/Power-down mode.
5.11.2 Features
18-bit free running up counter for Watchdog Timer time-out interval.
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval period
is 104 ms ~ 26.3168 s if WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports Watchdog Timer reset delay period (NUC029xAN only)
-
Selectable it includes (1026、130、18 or 3) * WDT_CLK reset delay period
Supports to force Watchdog Timer enabled after chip powered on or reset while
CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0 (NUC029xAN only)
Supports Watchdog Timer time-out wake-up function only if WDT clock source is
selected as 10 kHz
Apr 3, 2019
Page 59 of 102
Rev 1.06
NUC029
5.12 Window Watchdog Timer (WWDT) (NUC029xAN Only)
5.12.1 Overview
The NuMicro® NUC029xAN supports The Window Watchdog Timer (WWDT). WWDT is used to
perform a system reset within a specified window period to prevent software run to uncontrollable
status by any unpredictable condition.
5.12.2 Features
6-bit down counter value WWDTCVAL (WWDTVAL[5:0]) and 6-bit compare window
value WINCMP (WWDTCR[21:16]) to make the WWDT time-out window period
flexible
Supports 4-bit value to programmable maximum 11-bit prescale counter period of
WWDT counter
Apr 3, 2019
Page 60 of 102
Rev 1.06
NUC029
5.13 UART Interface Controller (UART)
5.13.1 Overview
The NuMicro® NUC029 series provides up to 2 channels of Universal Asynchronous
Receiver/Transmitters (UART). UART Controller performs Normal Speed UART, and supports
flow control function. The UART Controller performs a serial-to-parallel conversion on data
received from the peripheral, and a parallel-to-serial conversion on data transmitted from the
CPU. The UART controller also supports IrDA SIR Function and RS-485 function mode. The
NUC029xAN also supports LIN master/slave function mode. Each UART Controller channel
supports six types of interrupts. NUC029xAN has seventh interrupt, LIN receiver break field
detected interrupt (LIN_RX_BREAK_INT).
5.13.2 Features
Full duplex, asynchronous communications
Separates receive / transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto flow control/flow control function (CTS, RTS) and
programmable RTS flow control trigger level
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit
by setting DLY (UA_TOR [15:8]) register
Supports break error, frame error, parity error and receive / transmit buffer overflow
detect function
Fully programmable serial-interface characteristics
-
-
Programmable data bit length, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
-
Programmable stop bit length, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports 3-/16-bit duration for normal mode
Supports RS-485 function mode.
-
-
Supports RS-485 9-bit mode
-
Supports hardware or software enable to control RS-485 transmission direction
by programming RTS pin
Supports LIN function mode (NUC029xAN only)
-
-
-
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
Apr 3, 2019
Page 61 of 102
Rev 1.06
NUC029
5.14 I2C Serial Interface Controller (I2C)
5.14.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
5.14.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the I2C bus include:
Supports up to two I2C serial interface controller
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allow devices with different bit rates to communicate via
one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
Built-in a 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows.
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
Support FIFO function (NUC029FAE only)
Apr 3, 2019
Page 62 of 102
Rev 1.06
NUC029
5.15 Serial Peripheral Interface (SPI)
5.15.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NuMicro® NUC029 series contains up to 2 sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller
can be configured as a master or a slave device.
5.15.2 Features
Up to 2 sets of SPI controllers
Supports Master or Slave mode operation
Configurable bit length of a transaction word from 8 to 32 bits
Provides separate 4-layer depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports the Byte Reorder function
Supports Byte or Word Suspend mode
Supports Slave 3-wire mode
Supports PLL clock source (NUC029xAN only)
Apr 3, 2019
Page 63 of 102
Rev 1.06
NUC029
5.16 Analog-to-Digital Converter (ADC)
5.16.1 Overview
The NuMicro® NUC029xAN contains one 12-bit successive approximation analog-to-digital
converters (SAR A/D converter) with 8 input channels, and The NuMicro® NUC029FAE contains
one 10-bit successive approximation analog-to-digital converters (SAR A/D converter) with 8 input
channels.
The A/D converter of NUC029xAN supports four operation modes: Single, Burst, Single-cycle
Scan and Continuous Scan mode, and the A/D converter of NUC029xAN only supports Single
mode.
The A/D converter can be started by software, PWM trigger and external STADC pin.
5.16.2 Features
Analog input voltage range: 0~AVDD
12-bit resolution and 10-bit accuracy is guaranteed (NUC029xAN only)
10-bit resolution and 8-bit accuracy is guaranteed (NUC029FAE only)
Up to 8 single-end analog input channels
-
Or 4 differential analog input channels (NUC029xAN only)
Up to 760 kSPS sample rate for NUC029xAN
300 KSPS (VDD 4.5V - 5.5V) and 200 KSPS (VDD 2.5V - 5.5V) conversion rate for
NUC029FAE
Four operating modes (NUC029FAE only supports Single mode)
-
-
Single mode: A/D conversion is performed one time on a specified channel
Burst mode: A/D converter samples and converts the specified single channel
and sequentially stores the result in FIFO.
-
-
Single-cycle Scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel
Continuous Scan mode: A/D converter continuously performs Single-cycle scan
mode until software stops A/D conversion
An A/D conversion can be started by:
-
-
-
Writing 1 to ADST bit (ADCR[11]) through software
PWM trigger with optional start delay period
External pin STADC
Each conversion result is held in data register with valid and overrun indicators
Each channel has individual data regiter (NUC029xAN only)
The conversion result can be compared with specify value and user can select
whether to generate an interrupt when conversion result matches the compare
register setting
Channel 7 supports 3 input sources:
-
-
external analog voltage
internal Band-gap voltage
Apr 3, 2019
Page 64 of 102
Rev 1.06
NUC029
-
internal temperature sensor output (NUC029xAN only)
Apr 3, 2019
Page 65 of 102
Rev 1.06
NUC029
5.17 Analog Comparator (ACMP)
5.17.1 Overview
The NuMicro® NUC029 series contains up to four sets of comparators which can be used in a
number of different configurations. The comparator output is logic 1 when positive input voltage is
greater than negative input voltage; otherwise the output is logic 0. Each comparator can be
configured to generate interrupt request when the comparator output value changes.
5.17.2 Features
Up to four sets of Comparator analog modules
Analog input voltage range: 0~ VDD
Supports Hysteresis function
Optional internal reference voltage source for each comparator negative input
Two interrupt vectors for the four analog comparators
External input or internal band-gap voltage selectable at negative node
Interrupt when compared results change
Power-down wake-up
Apr 3, 2019
Page 66 of 102
Rev 1.06
NUC029
5.18 Hardware Divider (HDIV) (NUC029xAN Only)
5.18.1 Overview
The NuMicro® NUC029xAN has the hardware divider (HDIV). HDIV is useful to the high
performance application. The hardware divider is a signed, integer divider with both quotient and
remainder outputs.
5.18.2 Features
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-
bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Write divisor to trigger calculation
Waiting for calculation ready automatically when reading quotient and remainder
Apr 3, 2019
Page 67 of 102
Rev 1.06
NUC029
6
APPLICATION CIRCUIT
DVCC
[1]
AVCC
SPISS0
SPICLK0
MISO_0
CS
CLK
MISO
MOSI
VDD
AVDD
SPI Device
FB
FB
DVCC
VSS
VDD
Power
MOSI_0
0.1uF
0.1uF
VSS
DVCC
4.7K
DVCC
AVSS
4.7K
DVCC
100 K
CLK
DIO
SCL0
SDA0
VDD
I2C Device
100 K
VSS
VDD
ICE_DAT
ICE_CLK
nRST
VSS
SWD
Interface
64K x 16-bit
SRAM
LATCH
20p
20p
NUC029LAN
LQFP48
XTAL1
XTAL2
D
Q
Addr[15:0]
En
ALE
Crystal
4~24 MHz
crystal
nCE
nOE
nWE
nLB
nCS
nRD
nWR
nWRL
nWRH
EBI
nUB
DVCC
AD[15:0]
Data[15:0]
10K
Reset
Circuit
RS232 Transceiver
ROUT RIN
PC COM Port
nRST
RXD
TXD
10uF/25V
UART
TIN
TOUT
LDO_CAP
1uF
Note: For the SPI device, the NUC029xAN chip
supply voltage must be equal to SPI device
working voltage. For example, when the SPI
Flash working voltage is 3.3 V, the NUC029xAN
chip supply voltage must also be 3.3V.
LDO
Apr 3, 2019
Page 68 of 102
Rev 1.06
NUC029
7
NUC029XAN ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN.
MAX
+7.0
VDD+0.3
24
UNIT
V
DC Power Supply
-0.3
VDDVSS
VIN
Input Voltage
VSS-0.3
V
Oscillator Frequency
1/tCLCL
TA
4
MHz
C
Operating Temperature
-40
+85
+150
120
Storage Temperature
TST
-55
C
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
IDD
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
ISS
120
35
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
Apr 3, 2019
Page 69 of 102
Rev 1.06
NUC029
7.2 DC Electrical Characteristics
(VDD-VSS=5.5 V, TA = 25C)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
VDD = 2.5V ~ 5.5V up to 50 MHz
-
MIN. TYP. MAX. UNIT
Operation Voltage
VDD
2.5
-
-
5.5
-
V
V
VSS
Power Ground
-0.3
AVSS
LDO Output Voltage
VLDO
1.62 1.8 1.98
1.16 1.20 1.24
1.14 1.20 1.24
V
VDD > 2.5V
V
VDD = 2.5 V ~ 5.5 V, TA = 25C
Band-gap Voltage
VBG
VDD = 2.5 V ~ 5.5 V,
V
TA = -40C ~ 85C
Allowed Voltage Difference for VDD
and AVDD
VDD-AVDD -0.3
0
0.3
-
V
-
All digital
modules
VDD
HXT
HIRC
PLL
IDD1
-
21
mA
Operating Current
Normal Run Mode
HCLK = 50 MHz
while(1){}
5.5V 12 MHz
X
X
V
V
V
X
IDD2
IDD3
IDD4
-
-
-
15
20
13
-
-
-
mA 5.5V 12 MHz
mA 3.3V 12 MHz
mA 3.3V 12 MHz
X
X
V
V
V
X
Excuted from Flash
All digital
modules
VDD
HXT
HIRC
PLL
IDD5
-
6.6
-
mA
Operating Current
Normal Run Mode
HCLK = 22.184 MHz
while(1){}
5.5V
X
X
V
V
X
X
V
X
IDD6
IDD7
IDD8
-
-
-
3.7
6.4
3.6
-
-
-
mA 5.5V
mA 3.3V
mA 3.3V
X
X
V
V
X
X
V
X
Excuted from Flash
All digital
modules
VDD
mA
HXT
HIRC
PLL
IDD9
-
5.4
-
Operating Current
Normal Run Mode
HCLK = 12 MHz
while(1){}
5.5V 12 MHz
X
X
X
X
V
X
IDD10
IDD11
IDD12
-
-
-
3.6
4.0
2.3
-
-
-
mA 5.5V 12 MHz
mA 3.3V 12 MHz
mA 3.3V 12 MHz
X
X
X
X
V
X
Excuted from Flash
All digital
modules
VDD
HXT
HIRC
PLL
IDD13
-
3.3
-
mA
Operating Current
Normal Run Mode
HCLK = 4 MHz
while(1){}
5.5V
4 MHz
4 MHz
X
X
X
X
V
X
IDD14
IDD15
IDD16
-
-
-
2.5
2.0
1.3
-
-
-
mA 5.5V
mA 3.3V
mA 3.3V
4 MHz
4 MHz
X
X
X
X
V
X
Excuted from Flash
Apr 3, 2019
Page 70 of 102
Rev 1.06
NUC029
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
All digital
modules
VDD HXT HIRC LIRC PLL
IDD17
-
110
-
A
Operating Current
5.5V
5.5V
X
X
X
X
V
V
X
X
V[4]
Normal Run Mode
HCLK = 10 kHz
while(1){}
IDD18
IDD19
IDD20
-
-
-
105
92
-
-
-
X
A
A
A
3.3V
3.3V
X
X
X
X
V
V
X
X
V[4]
X
Excuted from Flash
90
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE1
-
17
-
mA
5.5V 12 MHz
X
X
V
V
V
X
Operating Current
Idle Mode
IIDLE2
IIDLE3
IIDLE4
-
-
-
10
15
8
-
-
-
mA 5.5V 12 MHz
mA 3.3V 12 MHz
mA 3.3V 12 MHz
HCLK = 50 MHz
X
X
V
V
V
X
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE5
-
4.5
-
mA
5.5V
X
X
V
V
X
X
V
X
Operating Current
Idle Mode
IIDLE6
IIDLE7
IIDLE8
-
-
-
1.6
4.4
1.6
-
-
-
mA 5.5V
mA 3.3V
mA 3.3V
HCLK= 22.1184 MHz
X
X
V
V
X
X
V
X
All digital
modules
VDD
mA
HXT
HIRC
PLL
IIDLE9
-
4.1
-
5.5V 12 MHz
X
X
X
X
V
X
Operating Current
Idle Mode
IIDLE10
IIDLE11
IIDLE12
-
-
2.4
2.8
-
-
mA 5.5V 12 MHz
HCLK = 12 MHz
mA 3.3V 12 MHz
mA 3.3V 12 MHz
X
X
X
X
V
X
-
-
1.2
2.9
-
-
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE13
mA
5.5V
4 MHz
4 MHz
X
X
X
X
V
X
Operating Current
Idle Mode
IIDLE14
IIDLE15
IIDLE16
-
-
2.1
1.6
-
-
mA 5.5V
mA 3.3V
HCLK = 4 MHz
4 MHz
4 MHz
X
X
X
X
V
X
-
-
0.9
-
-
mA 3.3V
All digital
modules
VDD HXT HIRC LIRC PLL
IIDLE17
106
A
5.5V
5.5V
X
X
X
X
V
V
X
X
V[4]
Operating Current
Idle Mode
IIDLE18
IIDLE19
IIDLE20
-
-
-
104
90
-
-
-
X
A
A
A
HCLK = 10 kHz
3.3V
3.3V
X
X
X
X
V
V
X
X
V[4]
X
89
VDD = 5.5V, All oscillators and analog blocks turned
off
Standby Current
IPWD1
-
10
-
A
Apr 3, 2019
Page 71 of 102
Rev 1.06
NUC029
SPECIFICATION
PARAMETER
Power-down Mode
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VDD = 3.3V, All oscillators and analog blocks turned
off
IPWD2
-
-
8
-
A
A
(Deep Sleep Mode)
Logic 0 Input Current P0/1/2/3/4
(Quasi-bidirectional mode)
IIL
-65
-75
VDD = 5.5V, VIN = 0V
VDD = 5.5V, VIN = 2.0V
Logic 1 to 0 Transition Current
P0/1/2/3/4 (Quasi-bidirectional
mode)
[3]
ITL
-
-690 -750
A
A
V
VDD = 5.5V, 0<VIN<VDD
Input Leakage Current P0/1/2/3/4
ILK
-1
-
+1
Open-drain or input only mode
-0.3
-0.3
-
-
0.8
0.6
VDD = 4.5V
VDD = 2.5V
Input Low Voltage P0/1/2/3/4 (TTL
input)
VIL1
VDD
+0.3
2.0
1.5
-
-
VDD = 5.5V
VDD =3.0V
Input High Voltage P0/1/2/3/4 (TTL
input)
VIH1
V
V
VDD
+0.3
0
0
-
-
0.8
0.4
VDD = 4.5V
VDD = 2.5V
Input Low Voltage XTAL1[*2]
Input High Voltage XTAL1[*2]
VIL3
VDD
+0.3
3.5
2.4
-
-
VDD = 5.5V
VDD = 3.0V
VIH3
V
V
VDD
+0.3
Negative going threshold
(Schmitt input), nRST
0.2
VDD
VILS
-0.3
-
-
-
Positive going threshold
(Schmitt input), nRST
0.7
VDD
VDD
+0.3
VIHS
RRST
VILS
V
kΩ
V
-
-
-
Internal nRST Pin Pull-up Resistor
40
150
Negative going threshold
(Schmitt input), P0/1/2/3/4
0.3
VDD
-0.3
-
-
Positive going threshold
(Schmitt input), P0/1/2/3/4
0.7
VDD
VDD
+0.3
VIHS
V
-
ISR11
ISR12
ISR12
ISR21
ISR22
ISR22
ISK11
ISK12
-300 -420
-50 -75
-40 -67
-20 -26
-
-
-
-
-
-
-
-
VDD = 4.5V, VS = 2.4V
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
A
A
A
Source Current P0/1/2/3/4 (Quasi-
bidirectional Mode)
mA VDD = 4.5V, VS = 2.4V
mA VDD = 2.7V, VS = 2.2V
mA VDD = 2.5V, VS = 2.0V
mA VDD = 4.5V, VS = 0.45V
mA VDD = 2.7V, VS = 0.45V
Source Current P0/1/2/3/4 (Push-
pull Mode)
-3
-5
-2.5 -4.2
10
6
16
9
Sink Current P0/1/2/3/4 (Quasi-
bidirectional and Push-pull Mode)
Apr 3, 2019
Page 72 of 102
Rev 1.06
NUC029
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
ISK13
5
8
-
mA VDD = 2.5V, VS = 0.45V
Note 1: nRST pin is a Schmitt trigger input.
Note 2: XTAL1 is a CMOS input.
Note 3: Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1 to 0. In the
condition of VDD = 5.5 V, the transition current reaches its maximum value when VIN approximates to 2 V.
Note 4: Only enable modules which support 10 kHz LIRC clock source.
Apr 3, 2019
Page 73 of 102
Rev 1.06
NUC029
7.3 AC Electrical Characteristics
7.3.1 External Input Clock
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
SYMBOL
tCHCX
PARAMETER
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
CONDITION
MIN.
10
10
2
TYP.
MAX.
UNIT
ns
-
-
-
-
-
-
-
-
-
tCLCX
-
ns
tCLCH
15
15
ns
tCHCL
2
ns
7.3.2 External 4~24 MHz High Speed Crystal (HXT)
SYMBOL
VHXT
PARAMETER
Operation Voltage VDD
Temperature
CONDITION
MIN.
2.5
-40
-
TYP.
MAX.
5.5
85
-
UNIT
V
-
-
-
℃
TA
-
12 MHz at VDD = 5V
12 MHz at VDD = 3.3V
-
2
mA
mA
MHz
IHXT
Operating Current
Clock Frequency
-
0.8
-
-
fHXT
4
24
7.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
10~20pF
4 MHz ~ 24 MHz
10~20pF
Apr 3, 2019
Page 74 of 102
Rev 1.06
NUC029
XTAL1
XTAL2
4~24 MHz
Crystal
C1
C2
Vss
Vss
Figure 7-1 NUC029xAN Typical Crystal Application Circuit
7.3.3 Internal 22.1184 MHz High Speed RC Oscillator (HIRC)
SYMBOL
PARAMETER
Operation Voltage VDD
Center Frequency
CONDITION
MIN.
1.62
-
TYP.
1.8
MAX.
1.98
-
UNIT
V
[1]
VHRC
-
-
22.1184
MHz
TA = 25 ℃,
-1
-3
-
-
-
+1
+3
-
%
%
fHRC
VDD = 5 V
Calibrated Internal Oscillator
Frequency
TA = -40 ~ 85 ℃,
VDD = 2.5 V ~ 5.5 V
TA = 25 ℃,
IHRC
Operation Current
800
uA
VDD = 5 V
Note: Operation voltage comes from internal LDO.
7.3.4 Internal 10 kHz Low Speed RC Oscillator (LIRC)
SYMBOL
PARAMETER
Operation Voltage VDD
Center Frequency
CONDITION
MIN.
2.5
-
TYP.
-
MAX.
5.5
-
UNIT
V
VLRC
-
-
10
kHz
TA = 25 ℃,
-10
-40
-
-
+10
+40
%
%
fLRC
VDD = 2.5 V ~ 5.5 V
Calibrated Internal Oscillator
Frequency
TA = -40 ~ 85 ℃,
VDD = 2.5 V ~ 5.5 V
Apr 3, 2019
Page 75 of 102
Rev 1.06
NUC029
7.4 Analog Characteristics
7.4.1 12-bit SAR ADC Specification
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
12
UNIT
Bit
-
DNL
INL
EO
EG
EA
Resolution
-
-
-
-
-
-
-
Differential nonlinearity error
Integral nonlinearity error
Offset error
±1
-1~4
±4
LSB
LSB
LSB
LSB
LSB
±2
2
4
Gain error (Transfer gain)
Absolute Error
-2
-4
3
4
-
Monotonic
Guaranteed
ADC clock frequency (AVDD = 4.5V ~ 5.5V)
ADC clock frequency (AVDD = 2.5V ~ 5.5V)
Sample rate (FADC/TCONV) (AVDD = 4.5V ~ 5.5V)
Sample rate (FADC/TCONV) (AVDD = 2.5V ~ 5.5V)
Acquisition Time (Sample Stage)
Total Conversion Time
-
-
-
-
-
-
16
8
MHz
MHz
FADC
-
800
400
kSPS
kSPS
1/ FADC
1/ FADC
V
FS
-
TACQ
TCONV
AVDD
IDDA
7
20
-
Supply voltage
2.5
5.5
Supply current (Avg.) (AVDD = 5V)
Analog Input voltage
-
0
-
2.9
-
-
mA
VIN
AVDD
V
CIN
Input Capacitance
3.2
6
-
-
pF
RIN
Input Load
-
kΩ
Apr 3, 2019
Page 76 of 102
Rev 1.06
NUC029
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal
transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve.
7.4.2 LDO and Power Management Specification
SYMBOL
VDD
PARAMETER
Input Voltage VDD
Output Voltage
CONDITION
MIN.
2.5
1.62
-40
-
TYP.
MAX.
5.5
1.98
85
UNIT
V
-
VLDO
-
1.8
25
1
V
℃
TA
Operating Temperature
Capacitor
-
CLDO
RESR = 1 Ω
-
F
Note 1: It is recommended that a 0.1 uF bypass capacitor is connected between VDD and the closest VSS pin of the device.
Note 2: To ensure power stability, a 1 F or higher capacitor must be connected between LDO_CAP pin and the closest VSS
pin of the device.
Apr 3, 2019
Page 77 of 102
Rev 1.06
NUC029
7.4.3 Low Voltage Reset Specification
SYMBOL
AVDD
TA
PARAMETER
Input Voltage AVDD
Operating Temperature
Capacitor
CONDITION
MIN.
0
TYP.
-
MAX.
5.5
85
UNIT
V
-
℃
-
-40
-
25
ILVR
AVDD = 5.5 V
TA = 25 ℃
1
5
F
V
1.90
2.00
2.20
TA = -40 ℃
TA = 85 ℃
VLVR
Threshold Voltage
2.00
1.70
2.10
1.90
2.40
2.10
V
V
7.4.4 Brown-out Detector Specification
SYMBOL
AVDD
TA
PARAMETER
Input Voltage AVDD
Operating Temperature
Quiescent Current
CONDITION
-
MIN.
0
TYP.
-
MAX.
5.5
UNIT
V
℃
μA
V
-
-40
-
25
85
IBOD
AVDD = 5.5 V
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
-
140
4.2
3.5
2.5
2.0
4.3
3.5
2.5
2.0
4.38
3.68
2.68
2.18
4.52
3.8
4.55
3.85
2.85
2.35
4.75
4.05
3.05
2.55
V
Brown-out Voltage
(Falling edge)
VBOD
V
V
V
V
Brown-out Voltage
(Rising edge)
VBOD
2.77
2.25
V
V
7.4.5 Power-on Reset Specification
SYMBOL
TA
PARAMETER
Operating Temperature
Reset Voltage
CONDITION
MIN.
-40
-
TYP.
25
MAX.
UNIT
℃
-
85
-
VPOR
V+
2
V
VDD Start Voltage to
VPOR
-
-
-
-
-
100
-
mV
Ensure Power-on Reset
VDD Raising Rate to
RRVDD
0.025
V/ms
ms
Ensure Power-on Reset
Minimum Time for VDD
Stays at VPOR to Ensure
Power-on Reset
tPOR
-
0.5
-
-
Apr 3, 2019
Page 78 of 102
Rev 1.06
NUC029
VDD
tPOR
RRVDD
VPOR
Time
Figure 7-2 NUC029xAN Power-up Ramp Condition
Apr 3, 2019
Page 79 of 102
Rev 1.06
NUC029
7.4.6 Temperature Sensor Specification
SYMBOL
PARAMETER
Operating Voltage
Operating Temperature
Current Consumption
Gain
CONDITION
MIN.
1.62
-40
TYP.
1.8
MAX.
1.98
85
UNIT
V
[1]
VTEMP
-
℃
TA
-
25
ITEMP
-
-
16
-
μA
mV/℃
-
-
-
-1.65
714
-1.75
724
-1.85
734
TA = 0 ℃
Offset Voltage
mV
Note 1: Operation voltage comes from internal LDO.
Note 2: The temperature sensor formula for the output voltage (Vtemp) is as below equation.
Vtemp (mV) = Gain (mV/℃) x Temperature (℃) + Offset (mV)
7.4.7 Comparator Specification
SYMBOL
VCMP
TA
PARAMETER
Operation Voltage AVDD
Operation Temperature
Operation Current
Input Offset Voltage
Output Swing
CONDITION
MIN.
2.5
-40
-
TYP.
-
MAX.
5.5
UNIT
V
-
℃
-
25
50
10
-
85
ICMP
AVDD = 5 V
100
μA
mV
V
VOFF
VSW
-
-
-
-
-
20
0.1
0.1
40
AVDD-0.1
AVDD-0.1
-
VCOM
-
Input Common Mode Range
DC Gain
-
V
70
dB
VCOM = 1.2 V,
VDIFF = 0.1 V
TPGD
Propagation Delay
-
200
-
ns
VHYS
TSTB
Hysteresis
-
-
-
-
±20
-
±30
1
mV
Stable Time
μs
Apr 3, 2019
Page 80 of 102
Rev 1.06
NUC029
7.5 Flash DC Electrical Characteristics
SYMBOL
PARAMETER
Operation Voltage
Data Retention
Page Erase Time
Program Time
Read Current
CONDITION
MIN.
TYP.
1.8
-
MAX.
UNIT
V
[1]
VFLA
-
1.62
1.98
TA = 25℃
TRET
TERASE
TPROG
IDD1
10
-
-
-
-
-
-
-
year
ms
-
-
-
-
-
3
-
40
0.25
7
μs
-
mA
mA
mA
IDD2
Program Current
Erase Current
-
IDD3
-
20
Note 1: Operation voltage comes from internal LDO.
Note 2: This table is guaranteed by design, not test in production.
Apr 3, 2019
Page 81 of 102
Rev 1.06
NUC029
8
NUC029FAE ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN.
MAX
+7.0
VDD+0.3
24
UNIT
V
DC Power Supply
-0.3
VDDVSS
VIN
Input Voltage
VSS-0.3
V
Oscillator Frequency
1/tCLCL
TA
4
MHz
C
Operating Temperature
-40
+105
+150
120
Storage Temperature
TST
-55
C
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
IDD
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
ISS
120
35
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the life and reliability
of the device.
Apr 3, 2019
Page 82 of 102
Rev 1.06
NUC029
8.2 DC Electrical Characteristics
(VDD-VSS = 5.5 V, TA = 25C)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
VDD = 2.5V ~ 5.5V up to 24 MHz
-
MIN.
TYP.
MAX. UNIT
Operation Voltage
VDD
2.5
-
5.5
-
V
V
VSS
Power Ground
-0.3
1.62
1.20
1.18
-0.3
-
-
AVSS
LDO Output Voltage
VLDO
1.8
1.24
1.24
0
1.98
1.28
1.32
0.3
-
V
VDD ≥ 2.5V
V
VDD = 2.5 V ~ 5.5 V, TA = 25C
Band-gap Voltage
VBG
VDD = 2.5 V ~ 5.5 V,
V
TA = -40C ~ 105C
Allowed Voltage Difference for VDD
and AVDD
VDD
-
V
-
AVDD
All digital
modules
VDD
HXT
HIRC
IDD1
9.2
mA
Operating Current
Normal Run Mode
HCLK = 24 MHz
while(1){}
5.5V 24 MHz
5.5V 24 MHz
X
X
V
X
IDD2
IDD3
IDD4
-
-
-
7.0
7.1
5.0
-
-
-
mA
mA
mA
3.3V 24 MHz
3.3V 24 MHz
X
X
V
X
Excuted from Flash
All digital
modules
VDD
HXT
HIRC
IDD5
-
6.1
-
mA
Operating Current
Normal Run Mode
HCLK = 22.184 MHz
while(1){}
5.5V
5.5V
X
X
V
V
V
X
IDD6
IDD7
IDD8
-
-
-
3.9
6.0
3.9
-
-
-
mA
mA
mA
3.3V
3.3V
X
X
V
V
V
X
Excuted from Flash
All digital
modules
VDD
HXT
HIRC
IDD9
-
5.5
-
mA
Operating Current
Normal Run Mode
HCLK = 12 MHz
while(1){}
5.5V 12 MHz
5.5V 12 MHz
X
X
V
X
IDD10
IDD11
IDD12
-
-
-
4.3
3.9
2.8
-
-
-
mA
mA
mA
3.3V 12 MHz
3.3V 12 MHz
X
X
V
X
Excuted from Flash
All digital
modules
VDD
HXT
HIRC
IDD13
-
3.2
-
mA
Operating Current
Normal Run Mode
HCLK = 4 MHz
while(1){}
5.5V
5.5V
4 MHz
4 MHz
X
X
V
X
IDD14
IDD15
IDD16
-
-
-
2.8
1.8
1.4
-
-
-
mA
mA
mA
3.3V
3.3V
4 MHz
4 MHz
X
X
V
X
Excuted from Flash
Apr 3, 2019
Page 83 of 102
Rev 1.06
NUC029
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
All digital
modules
VDD
HXT HIRC LIRC
IDD17
-
225
-
A
Operating Current
5.5V
5.5V
X
X
X
X
V
V
V[4]
Normal Run Mode
HCLK = 10 kHz
while(1){}
IDD18
IDD19
IDD20
-
-
-
225
200
200
-
-
-
X
V[4]
X
A
A
A
3.3V
3.3V
X
X
X
X
V
V
Excuted from Flash
All digital
modules
VDD
HXT
HIRC
IIDLE1
-
7.1
-
mA
5.5V 24 MHz
5.5V 24MHz
X
X
V
X
Operating Current
Idle Mode
IIDLE2
IIDLE3
IIDLE4
-
-
-
4.9
5.1
2.9
-
-
-
mA
mA
mA
HCLK = 24 MHz
3.3V 24 MHz
3.3V 24 MHz
X
X
V
X
All digital
modules
VDD
HXT
HIRC
IIDLE5
-
4.1
-
mA
5.5V
5.5V
X
X
V
V
V
X
Operating Current
Idle Mode
IIDLE6
IIDLE7
IIDLE8
-
-
-
2.0
4.1
1.9
-
-
-
mA
mA
mA
HCLK= 22.1184 MHz
3.3V
3.3V
X
X
V
V
V
X
All digital
modules
VDD
HXT
HIRC
IIDLE9
-
4.4
-
mA
5.5V 12 MHz
5.5V 12 MHz
X
X
V
X
Operating Current
Idle Mode
IIDLE10
IIDLE11
IIDLE12
-
-
3.3
2.9
-
-
mA
mA
HCLK = 12 MHz
3.3V 12 MHz
3.3V 12 MHz
X
X
V
X
-
-
1.8
2.9
-
-
mA
mA
All digital
modules
VDD
HXT
HIRC
IIDLE13
5.5V
5.5V
4 MHz
4 MHz
X
X
V
X
Operating Current
Idle Mode
IIDLE14
IIDLE15
IIDLE16
-
-
2.5
1.5
-
-
mA
mA
HCLK = 4 MHz
3.3V
3.3V
4 MHz
4 MHz
X
X
V
X
-
-
1.1
-
-
mA
All digital
modules
VDD
5.5V
5.5V
HXT HIRC LIRC
IIDLE17
225
A
X
X
X
X
V
V
V[4]
Operating Current
Idle Mode
IIDLE18
IIDLE19
IIDLE20
-
-
-
225
200
200
-
-
-
X
A
A
A
HCLK = 10 kHz
3.3V
3.3V
X
X
X
X
V
V
V[4]
X
VDD = 5.5V, All oscillators and analog blocks
turned off
Standby Current
IPWD1
-
10
-
A
Apr 3, 2019
Page 84 of 102
Rev 1.06
NUC029
SPECIFICATION
PARAMETER
Power-down Mode
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD = 3.3V, All oscillators and analog blocks
turned off
IPWD2
-
9
-
A
A
(Deep Sleep Mode)
Logic 0 Input Current P0/1/2/3/4
(Quasi-bidirectional mode)
IIL
-
-
-70
-75
VDD = 5.5V, VIN = 0V
VDD = 5.5V, VIN = 2.0V
Logic 1 to 0 Transition Current
P0/1/2/3/4 (Quasi-bidirectional
mode)
[3]
ITL
-690
-750
+1
A
A
V
VDD = 5.5V, 0<VIN<VDD
Input Leakage Current P0/1/2/3/4
ILK
-1
-
Open-drain or input only mode
-0.3
-0.3
2.0
1.5
0
-
-
-
-
-
-
-
-
0.8
0.6
VDD = 4.5V
VDD = 2.5V
VDD = 5.5V
VDD =3.0V
VDD = 4.5V
VDD = 2.5V
VDD = 5.5V
VDD = 3.0V
Input Low Voltage P0/1/2/3/4 (TTL
input)
VIL1
VDD +0.3
VDD +0.3
0.8
Input High Voltage P0/1/2/3/4 (TTL
input)
VIH1
V
V
V
Input Low Voltage XTAL1[*2]
Input High Voltage XTAL1[*2]
VIL3
0
0.4
3.5
2.4
VDD +0.3
VDD +0.3
VIH3
Negative going threshold
(Schmitt input), nRST
VILS
-0.3
-
-
0.2 VDD
V
V
-
-
Positive going threshold
(Schmitt input), nRST
VIHS
RRST
VILS
0.7 VDD
40
VDD +0.3
150
Internal nRST Pin Pull-up Resistor
kΩ VDD = 2.5V ~ 5.5V
Negative going threshold
(Schmitt input), P0/1/2/3/4
-0.3
-
-
0.3 VDD
V
-
-
Positive going threshold
(Schmitt input), P0/1/2/3/4
VIHS
0.7 VDD
VDD +0.3
V
ISR11
ISR12
ISR12
ISR21
ISR22
ISR22
ISK11
ISK12
ISK13
-300
-50
-40
-20
-3
-400
-80
-73
-26
-5
-
-
-
-
-
-
-
-
-
VDD = 4.5V, VS = 2.4V
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
A
A
A
Source Current P0/1/2/3/4 (Quasi-
bidirectional Mode)
mA VDD = 4.5V, VS = 2.4V
mA VDD = 2.7V, VS = 2.2V
mA VDD = 2.5V, VS = 2.0V
Source Current P0/1/2/3/4 (Push-
pull Mode)
-2.5
10
-5
15
9
mA VDD = 4.5V, VS = 0.45V
mA VDD = 2.7V, VS = 0.45V
mA VDD = 2.5V, VS = 0.45V
Sink Current P0/1/2/3/4 (Quasi-
bidirectional and Push-pull Mode)
6
5
8
Note 1: nRST pin is a Schmitt trigger input.
Note 2: XTAL1 is a CMOS input.
Apr 3, 2019
Page 85 of 102
Rev 1.06
NUC029
Note 3: Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1 to 0. In the
condition of VDD = 5.5 V, the transition current reaches its maximum value when VIN approximates to 2 V.
Note 4: Only enable modules which support 10 kHz LIRC clock source.
Apr 3, 2019
Page 86 of 102
Rev 1.06
NUC029
8.3 AC Electrical Characteristics
8.3.1 External Input Clock
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
SYMBOL
tCHCX
PARAMETER
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
CONDITION
MIN.
10
10
2
TYP.
MAX.
UNIT
ns
-
-
-
-
-
-
-
-
-
tCLCX
-
ns
tCLCH
15
15
ns
tCHCL
2
ns
8.3.2 External 4~24 MHz High Speed Crystal (HXT)
SYMBOL
VHXT
PARAMETER
Operation Voltage VDD
Temperature
CONDITION
MIN.
2.5
-40
-
TYP.
MAX.
5.5
105
-
UNIT
V
-
-
-
℃
TA
-
12 MHz at VDD = 5V
12 MHz at VDD = 3.3V
-
2.5
1.0
-
mA
mA
MHz
IHXT
Operating Current
Clock Frequency
-
-
fHXT
4
24
8.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
10~20pF
4 MHz ~ 24 MHz
10~20pF
Apr 3, 2019
Page 87 of 102
Rev 1.06
NUC029
XTAL1
XTAL2
4~24 MHz
Crystal
C1
C2
Vss
Vss
Figure 8-1 NUC029FAE Typical Crystal Application Circuit
8.3.3 Internal 22.1184 MHz High Speed RC Oscillator (HIRC)
SYMBOL
PARAMETER
Operation Voltage VDD
Center Frequency
CONDITION
MIN.
1.62
-
TYP.
1.8
MAX.
1.98
-
UNIT
V
[1]
VHRC
-
-
22.1184
MHz
TA = 25 ℃,
-1
-2
-
-
-
+1
+2
-
%
%
fHRC
VDD = 5 V
Calibrated Internal Oscillator
Frequency
TA = -40 ~ 105 ℃,
VDD = 2.5 V ~ 5.5 V
TA = 25 ℃,
IHRC
Operation Current
700
uA
VDD = 5 V
Note : Operation voltage comes from internal LDO.
Apr 3, 2019
Page 88 of 102
Rev 1.06
NUC029
HIRC oscillator accuracy vs. temperature
1.00
0.80
0.60
0.40
0.20
0.00
-0.20
-0.40
-0.60
-0.80
-1.00
Max
Min
TA ℃
8.3.4 Internal 10 kHz Low Speed RC Oscillator (LIRC)
SYMBOL
PARAMETER
Operation Voltage VDD
Center Frequency
CONDITION
MIN.
2.5
-
TYP.
-
MAX.
UNIT
V
VLRC
-
-
5.5
-
10
kHz
TA = 25 ℃,
-10
-40
-
-
+10
+40
%
%
fLRC
VDD = 2.5 V ~ 5.5 V
Calibrated Internal Oscillator
Frequency
TA = -40 ~ 105 ℃,
VDD = 2.5 V ~ 5.5 V
Apr 3, 2019
Page 89 of 102
Rev 1.06
NUC029
8.4 Analog Characteristics
8.4.1 10-bit SAR ADC Specification
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
10
UNIT
Bit
-
DNL
INL
EO
EG
EA
Resolution
-
-
-
-
-
-
-
Differential nonlinearity error
Integral nonlinearity error
Offset error
-1~1.5
-1~2.5
±2
LSB
LSB
LSB
LSB
LSB
±1
1
2
Gain error (Transfer gain)
Absolute Error
-1
-3
3
4
-
Monotonic
Guaranteed
ADC clock frequency (AVDD = 4.5V ~ 5.5V)
ADC clock frequency (AVDD = 2.5V ~ 5.5V)
Sample rate (FADC/TCONV) (AVDD = 4.5V ~ 5.5V)
Sample rate (FADC/TCONV) (AVDD = 2.5V ~ 5.5V)
Acquisition Time (Sample Stage)
Total Conversion Time
-
-
-
-
-
4.2
2.8
MHz
MHz
FADC
-
-
300
200
kSPS
kSPS
1/ FADC
1/ FADC
V
FS
-
TACQ
TCONV
AVDD
IDDA
N+1[2]
N+14[2]
Supply voltage
2.5
-
600
-
5.5
Supply current (Avg.) (AVDD = 5.5V)
Analog Input voltage
-
0
-
-
μA
VIN
AVDD
V
CIN
Input Capacitance
3.2
6
-
-
pF
RIN
Input Load
-
kΩ
Note 1: ADC voltage reference is same with AVDD
.
Note 2: N is sampling counter, N=0, 1, 2, 4, 8, 16, 32, 4, 128, 256, 1024.
Apr 3, 2019
Page 90 of 102
Rev 1.06
NUC029
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
1023
1022
1021
1020
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
1023
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal
transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve.
8.4.2 LDO and Power Management Specification
SYMBOL
VDD
PARAMETER
Input Voltage VDD
Output Voltage
CONDITION
MIN.
2.5
TYP.
MAX.
5.5
UNIT
V
-
-
-
VLDO
1.62
-40
1.8
25
1.98
105
V
℃
TA
Operating Temperature
Note: It is recommended that a 0.1 uF bypass capacitor is connected between VDD and the closest VSS pin of the device.
Apr 3, 2019
Page 91 of 102
Rev 1.06
NUC029
8.4.3 Low Voltage Reset Specification
SYMBOL
AVDD
TA
PARAMETER
Input Voltage AVDD
Operating Temperature
Capacitor
CONDITION
MIN.
2.5
-40
-
TYP.
-
MAX.
5.5
UNIT
V
-
℃
-
25
105
5
ILVR
AVDD = 5.5 V
TA = 25 ℃
1
F
V
1.90
2.00
2.10
TA = -40 ℃
TA = 105 ℃
VLVR
Threshold Voltage
1.70
2.00
1.90
2.20
2.05
2.45
V
V
8.4.4 Brown-out Detector Specification
SYMBOL
AVDD
TA
PARAMETER
Input Voltage AVDD
Operating Temperature
Quiescent Current
CONDITION
-
MIN.
2.5
-40
-
TYP.
-
MAX.
5.5
UNIT
V
℃
μA
V
-
25
105
IBOD
AVDD = 5.5 V
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
-
140
4.2
3.5
2.5
2.0
4.3
3.5
2.5
2.0
4.38
3.68
2.68
2.18
4.52
3.8
4.55
3.85
2.85
2.35
4.75
4.05
3.05
2.55
V
Brown-out Voltage
(Falling edge)
VBOD
V
V
V
V
Brown-out Voltage
(Rising edge)
VBOD
2.77
2.25
V
V
8.4.5 Power-on Reset Specification
SYMBOL
TA
PARAMETER
Operating Temperature
Reset Voltage
CONDITION
MIN.
-40
TYP.
25
MAX.
85
UNIT
℃
-
VPOR
V+
1.6
2
2.4
V
VDD Start Voltage to
VPOR
-
-
-
-
-
100
-
mV
Ensure Power-on Reset
VDD Raising Rate to
RRVDD
0.025
V/ms
ms
Ensure Power-on Reset
Minimum Time for VDD
Stays at VPOR to Ensure
Power-on Reset
tPOR
-
0.5
-
-
Apr 3, 2019
Page 92 of 102
Rev 1.06
NUC029
VDD
tPOR
RRVDD
VPOR
Time
Figure 8-2 NUC029xAN Power-up Ramp Condition
Apr 3, 2019
Page 93 of 102
Rev 1.06
NUC029
8.4.6 Comparator Specification
SYMBOL
VCMP
TA
PARAMETER
Operation Voltage AVDD
Operation Temperature
Operation Current
Input Offset Voltage
Output Swing
CONDITION
MIN.
2.5
-40
-
TYP.
-
MAX.
5.5
UNIT
V
-
℃
-
25
40
10
-
105
ICMP
AVDD = 5 V
80
μA
mV
V
VOFF
VSW
-
-
-
-
-
20
0.1
0.1
40
AVDD-0.1
AVDD-0.1
-
VCOM
-
Input Common Mode Range
DC Gain
-
V
70
dB
VCOM = 1.2 V,
VDIFF = 0.1 V
TPGD
Propagation Delay
-
200
-
ns
VHYS
TSTB
Hysteresis
VCOM = 1.2 V
-
-
-
±30
-
±60
1
mV
Stable Time
μs
Apr 3, 2019
Page 94 of 102
Rev 1.06
NUC029
8.5 Flash DC Electrical Characteristics
SYMBOL
PARAMETER
Operation Voltage
Endurance
CONDITION
MIN.
TYP.
1.8
-
MAX.
UNIT
[1]
VFLA
-
1.62
1.98
V
NENDUR
TRET
-
20,000
-
-
-
-
-
-
-
cycles[2]
year
ms
TA = 25℃
Data Retention
Page Erase Time
Program Time
Read Current
10
-
-
TERASE
TPROG
IDD1
-
-
-
-
-
20
60
6
-
μs
-
mA
IDD2
Program Current
Erase Current
-
8
mA
IDD3
-
12
mA
Note 1: Operation voltage comes from internal LDO.
Note 2: Number of program/erase cycles.
Note 3: This table is guaranteed by design, not test in production.
Apr 3, 2019
Page 95 of 102
Rev 1.06
NUC029
9
PACKAGE DIMENSIONS
9.1 48-pin LQFP (7x7x1.4 mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Symbol
Dimension in mm
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
L
0.024 0.030
0.45
0
0.039
0.004
7
1
L
Y
0.10
7
0
0
Apr 3, 2019
Page 96 of 102
Rev 1.06
NUC029
9.2 48-pin QFN (7x7x0.8 mm)
Apr 3, 2019
Page 97 of 102
Rev 1.06
NUC029
9.3 33-pin QFN (5x5x0.75 mm)
Apr 3, 2019
Page 98 of 102
Rev 1.06
NUC029
9.4 33-pin QFN (4x4x0.75 mm)
Apr 3, 2019
Page 99 of 102
Rev 1.06
NUC029
9.5 20-pin TSSOP (6.5x4.4x1.2 mm)
Apr 3, 2019
Page 100 of 102
Rev 1.06
NUC029
10 REVISION HISTORY
Date
Revision
Description
2014.05.19
1.00
1.01
1.
1.
Preliminary version.
Modified Figure 4-1 NuMicro® NUC029 Series Selection
2014.08.26
Code.
1.
Changed the order of Chapter 5 FUNCTIONAL
DESCRIPTION.
2.
3.
4.
Fixed typos and obscure description.
Added Chapter 5.2.5 Whole System Memory Mapping.
Fixed the description about Frequency Divider Output of
NUC029xAN series in Chapter 5.3.4.
2015.05.18
1.02
5.
6.
Added clock switching note in Chapter 5.3 and 5.4.
Removed description about ACMP output inverse function
available on NUC029xAN series.
7.
8.
Modified NUC029xDN LVR and BOD specification.
Updated 33-pin QFN (4x4) package dimension in Chapter
9.4.
2017.06.23
2017.12.11
1.03
1.04
1.
1.
1.
Added new part number NUC029ZAN.
Added new part number NUC029NAN.
Modified the figure in section 9.2 48-pin QFN (7x7x0.8
mm).
2019.01.09
1.05
1.
2.
Modified the band-gap characteristic in section 8.2 and the
Flash characteristic in section 8.5.
2019.04.03
1.06
Added the pull-up resistor on SWD interface in the
application circuit schematic in Chapter 6.
Apr 3, 2019
Page 101 of 102
Rev 1.06
NUC029
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Apr 3, 2019
Page 102 of 102
Rev 1.06
相关型号:
©2020 ICPDF网 联系我们和版权申明