W79E8213RAKG [NUVOTON]
The W79E8213 series are an 8-bit 4T-8051 microcontroller which has Flash EPROM which is programmable by ICP (In Circuit Program) or by hardware writer.;
| 型号： | W79E8213RAKG |
| 厂家： | 
NUVOTON |
| 描述： | The W79E8213 series are an 8-bit 4T-8051 microcontroller which has Flash EPROM which is programmable by ICP (In Circuit Program) or by hardware writer. 可编程只读存储器 电动程控只读存储器 时钟 外围集成电路 |
| 文件： | 总96页 (文件大小：2176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W79E8213/W79E8213R Data Sheet
Table of Contents
1.
2.
3.
GENERAL DESCRIPTION ......................................................................................................... 4
FEATURES ................................................................................................................................. 5
PARTS INFORMATION LIST ..................................................................................................... 6
3.1
Lead Free (RoHS) Parts information list......................................................................... 6
4.
5.
6.
PIN CONFIGURATION............................................................................................................... 6
PIN DESCRIPTIONS .................................................................................................................. 7
FUNCTIONAL DESCRIPTION.................................................................................................... 8
6.1
6.2
6.3
6.4
6.5
6.6
On-Chip Flash EPROM .................................................................................................. 8
I/O Ports.......................................................................................................................... 8
Timers............................................................................................................................. 8
Interrupts......................................................................................................................... 8
Data Pointer.................................................................................................................... 8
Architecture..................................................................................................................... 8
6.6.1 ALU ..................................................................................................................................8
6.6.2 Accumulator .....................................................................................................................9
6.6.3 B Register.........................................................................................................................9
6.6.4 Program Status Word.......................................................................................................9
6.6.5 Scratch-pad RAM.............................................................................................................9
6.6.6 Stack Pointer....................................................................................................................9
Power Management........................................................................................................ 9
6.7
7.
MEMORY ORGANIZATION...................................................................................................... 10
7.1
7.2
7.3
7.4
Program Memory (on-chip Flash)................................................................................. 10
Data Flash Memory ...................................................................................................... 10
Data Memory (accessed by MOVX) ............................................................................. 11
Scratch-pad RAM and Register Map............................................................................ 11
7.4.1 Working Registers..........................................................................................................12
7.4.2 Bit addressable Locations ..............................................................................................13
7.4.3 Stack ..............................................................................................................................13
8.
9.
SPECIAL FUNCTION REGISTERS ......................................................................................... 14
INSTRUCTION SET.................................................................................................................. 40
9.1
Instruction Timing ......................................................................................................... 48
10.
11.
POWER MANAGEMENT.......................................................................................................... 51
10.1 Idle Mode ...................................................................................................................... 51
10.2 Power-down Mode........................................................................................................ 51
RESET CONDITIONS............................................................................................................... 52
11.1 Sources of reset............................................................................................................ 52
11.1.1 External Reset..............................................................................................................53
11.1.2 Power-On Reset (POR)................................................................................................53
11.1.3 Watchdog Timer Reset.................................................................................................54
11.2 Reset State ................................................................................................................... 54
12.
INTERRUPTS ........................................................................................................................... 55
-1-
W79E8213/W79E8213R Data Sheet
12.1 Interrupt Sources .......................................................................................................... 55
12.2 Priority Level Structure ................................................................................................. 57
12.3 Response Time............................................................................................................. 58
12.4 Interrupt Inputs.............................................................................................................. 58
PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 60
13.
13.1 Timer/Counters 0 & 1.................................................................................................... 60
13.1.1 Time-Base Selection ....................................................................................................60
13.1.2 Mode 0 .........................................................................................................................60
13.1.3 Mode 1 .........................................................................................................................61
13.1.4 Mode 2 .........................................................................................................................62
13.1.5 Mode 3 .........................................................................................................................62
NVM MEMORY......................................................................................................................... 64
14.
15.
WATCHDOG TIMER................................................................................................................. 65
15.1 WATCHDOG CONTROL.............................................................................................. 66
15.2 CLOCK CONTROL of Watchdog.................................................................................. 66
TIME ACCESS PROCTECTION .............................................................................................. 67
EDGE DETECT INTERRUPT................................................................................................... 69
I/O PORT CONFIGURATION ................................................................................................... 71
18.1 Quasi-Bidirectional Output Configuration ..................................................................... 71
18.2 Open Drain Output Configuration ................................................................................. 72
18.3 Push-Pull Output Configuration .................................................................................... 72
18.4 Input Only Configuration............................................................................................... 73
OSCILLATOR ........................................................................................................................... 74
19.1 Internal RC Oscillator Option........................................................................................ 74
19.2 External Clock Input Option.......................................................................................... 74
BUZZER OUTPUT.................................................................................................................... 75
POWER MONITORING FUNCTION ........................................................................................ 78
21.1 Power On Detect .......................................................................................................... 78
21.2 Brownout Detect ........................................................................................................... 78
PULSE-WIDTH-MODULATED (PWM) OUTPUTS................................................................... 79
ANALOG-TO-DIGITAL CONVERTER...................................................................................... 82
23.1 ADC Resolution and Analog Supply............................................................................. 83
ICP (IN-CIRCUIT PROGRAM) FLASH PROGRAM ................................................................. 85
CONFIG BITS ........................................................................................................................... 86
25.1 CONFIG0...................................................................................................................... 86
25.2 CONFIG1...................................................................................................................... 88
ELECTRICAL CHARACTERISTICS......................................................................................... 89
26.1 Absolute Maximum Ratings.......................................................................................... 89
26.2 DC ELECTRICAL CHARACTERISTICS ...................................................................... 89
26.3 The ADC Converter DC ELECTRICAL CHARACTERISTICS ..................................... 91
26.4 Internal RC Oscillator Accuracy.................................................................................... 92
26.5 AC ELECTRICAL CHARACTERISTICS ...................................................................... 93
26.6 EXTERNAL CLOCK CHARACTERISTICS .................................................................. 93
26.7 AC SPECIFICATION .................................................................................................... 93
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
-2-
W79E8213/W79E8213R Data Sheet
26.8 TYPICAL APPLICATION CIRCUITS............................................................................ 93
PACKAGE DIMENSIONS......................................................................................................... 94
27.1 20-pin SOP-300mil ....................................................................................................... 94
27.2 20-pin PDIP-300mil....................................................................................................... 95
REVISION HISTORY................................................................................................................ 96
27.
28.
-3-
W79E8213/W79E8213R Data Sheet
1. GENERAL DESCRIPTION
The W79E8213 series are an 8-bit 4T-8051 microcontroller which has Flash EPROM which is
programmable by ICP (In Circuit Program) or by hardware writer. The instruction set of the W79E8213
series are fully compatible with the standard 8052. The W79E8213 series contain a 4Kbytes of main
Flash EPROM; a 128bytes of RAM; two 16-bit timer/counters; 4-channel 10-bit PWM; 3 edge detector
inputs; 8-channel multiplexed 10-bit A/D convert. The W79E8213 series supports 128 bytes NVM Data
Flash EPROM. These peripherals are supported by 10 sources four-level interrupt capability. To
facilitate programming and verification, the Flash EPROM inside the W79E8213 series allow the
program memory to be programmed and read electronically. Once the code is confirmed, the user can
protect the code for security.
-4-
W79E8213/W79E8213R Data Sheet
2. FEATURES
Fully static design 8-bit 4T-8051 CMOS microcontroller:
VDD = 4.5V to 5.5V @20MHz
VDD = 2.7V to 5.5V @12MHz
VDD = 2.4V to 5.5V @4MHz
Instruction-set compatible with MSC-51.
Flexible CPU clock source configurable by config bit and software:
High speed external oscillator: upto 20MHz Crystal and resonator (enabled by config bit).
Internal RC oscillator: 20/10MHz selectable by config bit, only W79E8213R supports ±2%
accuracy internal RC oscillator at fixed voltage and temperature condition.
4K bytes of AP Flash EPROM, with ICP and external writer programmable mode.
128 bytes of on-chip RAM.
W79E8213 series supports 128 bytes NVM Data Flash EPROM for customer data storage used
and 10K writer cycles.
8 pages. Page size is 16 bytes.
Two 16-bit timer/counters.
Ten interrupts source with four levels of priority.
Three-edge detect interrupt inputs.
Programmable Watchdog Timer.
Four-channel 10-bit PWM (Pulse Width Modulator).
Internal square wave generator for buzzer.
Up to 18 I/O pins.
The 4 outputs mode and TTL/Schmitt trigger selectable Port.
LED drive capability on all port pins. Sink 20mA; Drive: -15~-20mA @push-pull mode.
Eight high sink capability (40mA) port pins.
Eight-channel multiplexed with 10-bits A/D convert.
Low Voltage Detect interrupt and reset.
Development Tools:
ICP(In Circuit Programming) writer
Packages:
- Lead Free (RoHS) DIP 20:
- Lead Free (RoHS) SOP 20:
- Lead Free (RoHS) DIP 20:
- Lead Free (RoHS) SOP 20:
W79E8213AKG
W79E8213ASG
W79E8213RAKG
W79E8213RASG
-5-
W79E8213/W79E8213R Data Sheet
3. PARTS INFORMATION LIST
3.1 Lead Free (RoHS) Parts information list
INTERNAL RC 1
OSCILLATOR
ACCURACY
NVM FLASH
EPROM
FLASH SIZE
PART NO.
RAM
PACKAGE
EPROM
W79E8213AKG
W79E8213ASG
W79E8213RAKG
W79E8213RASG
4KB
4KB
4KB
4KB
128B
128B
128B
128B
128B
128B
128B
128B
DIP-20 Pin
SOP-20 Pin
DIP-20 Pin
SOP-20 Pin
±30%
±30%
±2%
±2%
Note: 1. Test conditions are VDD = 3.3V, TA = 25°C
Table 3-1: Lead Free (RoHS) Parts information list
4. PIN CONFIGURATION
20-PIN DIP/SOP/SSOP
PWM3/AD6/P0.0
1
2
20 P0.1/AD5/PWM0
19 P0.2/AD4/BRAKE
P0.3/AD0
PWM2/P1.7
PWM1/P1.6
3
18
RST/P1.5
4
17 P0.4/AD1
16 P0.5/AD2
W79E8213AKG
W79E8213ASG
W79E8213RAKG
W79E8213RASG
VSS
5
VDD
15
XTAL1/P2.1
6
XTAL2/CLKOUT/P2.0
STADC/INT1/P1.4
INT0/P1.3
7
14 P0.6/AD3
8
13 P0.7/T1/AD7
P1.0/ED0/BUZ
12
11 P1.1/ED1
9
T0/ED2/P1.2
10
Figure 4-1: Pin Configuration
-6-
W79E8213/W79E8213R Data Sheet
5. PIN DESCRIPTIONS
ALTERNATE
FUNCTION 4
(ICP MODE)
ALTERNATE ALTERNATE ALTERNATE
FUNCTION 1 FUNCTION 2 FUNCTION 3
SYMBOL
TYPE
DESCRIPTION
POWER SUPPLY: Supply voltage
for operation.
VDD
P
VSS
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P
GROUND: Ground potential.
AD6
AD5
AD4
AD0
AD1
AD2
AD3
AD7
BUZ
PWM3
PWM0
BRAKE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port0:
Support 4 output modes and
TTL/Schmitt trigger.
Multifunction pins for T1, PWM0,
PWM3, BRAKE, AD0-7, Data
and Clock (for ICP).
Data
Clock
T1
T0
ED0
ED1
Port1:
Support 4 output modes and
TTL/Schmitt trigger (except for
P1.5 input only).
ED2
/INT0
/INT1
STADC
Multifunction pins for /RST, T0,
/INT0-1, BUZ, PWM1-2, ED0-2,
STADC, and HV (for ICP).
P1.5
P1.6
P1.7
HV
I
RST
PWM1
PWM2
I/O
I/O
P1.0-P1.7 have 40mA high sink
capability.
CRYSTAL2: This is the crystal
oscillator output. It is the
inversion of XTAL1. Also
configurable i/o pin.
When operating as I/O, it
supports 4 output modes and
TTL/Schmitt trigger.
a
P2.0
P2.1
XTAL2/CLKOUT
I/O
I/O
CRYSTAL1: This is the crystal
oscillator input. This pin may be
driven by an external clock or
configurable I/O pin.
XTAL1
When operating as I/O, it
supports 4 output modes and
TTL/Schmitt trigger.
* TYPE: P: power, I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open-drain.
Table 5-1: Pin Description
Note:
On power-on-reset, all port pins will be tri-stated.
After power-on-reset, all port pins state will follow CONFIG0.PRHI bit definition.
-7-
W79E8213/W79E8213R Data Sheet
6. FUNCTIONAL DESCRIPTION
The W79E8213 series architecture consist of a 4T 8051 core controller surrounded by various
registers, 4K bytes Flash EPROM, 128 bytes of RAM, up to 18 general purpose I/O ports, two
timer/counters, 3 edge detector inputs, 4-channel PWM with 10-bits counter, 8-channel multiplexed
with 10-bit ADC analog input, Flash EPROM program by Writer and ICP. W79E8213 series supported
128 bytes NVM Data Flash EPROM.
6.1 On-Chip Flash EPROM
The W79E8213 series include one 4K bytes of main Flash EPROM for application program. A Writer
or ICP programming board is required to program the Flash EPROM or NVM Data Flash EPROM.
This ICP (In-Circuit Programming) feature makes the job easy and efficient when the application’s
firmware needs to be updated frequently. In some applications, the in-circuit programming feature
makes it possible for the end-user to easily update the system firmware without opening the chassis.
6.2 I/O Ports
The W79E8213 series have up to 18 I/O pins using internal RC oscillator & /RST is input only by reset
options. All ports can be used as four outputs mode when it may set by PxM1.y and PxM2.y SFR’s
registers, it has strong pull-ups and pull-downs, and does not need any external pull-ups. Otherwise it
can be used as general I/O port as open drain circuit. All ports can be used bi-directional and these
are as I/O ports. These ports are not true I/O, but rather are pseudo-I/O ports. This is because these
ports have strong pull-downs and weak pull-ups.
6.3 Timers
The W79E8213 series have two 16-bit timers that are functionally and similar to the timers of the 8052
family. When used as timers, the user has a choice of 12 or 4 clocks per count that emulates the
timing of the original 8052.
6.4 Interrupts
The Interrupt structure in the W79E8213 series is slightly different from that of the standard 8052. Due
to the presence of additional features and peripherals, the number of interrupt sources and vectors
has been increased.
6.5 Data Pointer
The data pointer of W79E8213 series is same as standard 8052 which have 16-bit Data Pointer
(DPTR).
6.6 Architecture
The W79E8213 series are based on the standard 8052 device. It is built around an 8-bit ALU that uses
internal registers for temporary storage and control of the peripheral devices. It can execute the
standard 8052 instruction set.
6.6.1 ALU
The ALU is the heart of the W79E8213 series. It is responsible for the arithmetic and logical functions.
It is also used in decision making, in case of jump instructions, and is also used in calculating jump
addresses. The user cannot directly use the ALU, but the Instruction Decoder reads the op-code,
-8-
W79E8213/W79E8213R Data Sheet
decodes it, and sequences the data through the ALU and its associated registers to generate the
required result. The ALU mainly uses the ACC which is a special function register (SFR) on the chip.
Another SFR, namely B register is also used in Multiply and Divide instructions. The ALU generates
several status signals which are stored in the Program Status Word register (PSW).
6.6.2 Accumulator
The Accumulator (ACC) is the primary register used in arithmetic, logical and data transfer operations
in the W79E8213 series. Since the Accumulator is directly accessible by the CPU, most of the high
speed instructions make use of the ACC as one argument.
6.6.3 B Register
This is an 8-bit register that is used as the second argument in the MUL and DIV instructions. For all
other instructions it can be used simply as a general purpose register.
6.6.4 Program Status Word
This is an 8-bit SFR that is used to store the status bits of the ALU. It holds the Carry flag, the Auxiliary
Carry flag, General purpose flags, the Register Bank Select, the Overflow flag, and the Parity flag.
6.6.5 Scratch-pad RAM
The W79E8213 series have a 128 bytes on-chip scratch-pad RAM. These can be used by the user for
temporary storage during program execution. A certain section of this RAM is bit addressable, and can
be directly addressed for this purpose.
6.6.6 Stack Pointer
The W79E8213 series have an 8-bit Stack Pointer which points to the top of the Stack. This stack
resides in the Scratch Pad RAM in the W79E8213 series. Hence the size of the stack is limited by the
size of this RAM.
6.7 Power Management
Power Management like the standard 8052, the W79E8213 series also have the IDLE and POWER
DOWN modes of operation. In the IDLE mode, the clock to the CPU is stopped while the timers, serial
ports and interrupt block continue to operate. In the POWER DOWN mode, all clocks are stopped and
the chip operation is completely stopped. This is the lowest power consumption state.
-9-
W79E8213/W79E8213R Data Sheet
7. MEMORY ORGANIZATION
The W79E8213 series separate the memory into two separate sections, the Program Memory and the
Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory
is used to store data or for memory mapped devices.
FFFFH
(128B NVM, 16bytes/page)
FFFFH
FC7Fh
Page 7
Page 6
Page 5
Page 4
Page 3
Page 2
Page 1
Page 0
CONFIG 1
CONFIG 0
Unused
Code Memory
FC70h
FC6Fh
FC60h
FC5Fh
FC50h
FC4Fh
FC7FH
(16 bytes/page)
128B
NVM
Data Memory
FC40h
FC3Fh
FC00H
FC30h
FC2Fh
Unused
Data Memory
FC20h
FC1Fh
Unused
Code Memory
FC10h
FC0Fh
FC00h
1000H
0FFFH
NVM Data Memory Area
4K Bytes
On-Chip
Code Memory
0000H
0000H
On-Chip Code Memory Space
External Data Memory Space
Figure 7-1: W79E8213 series memory map
7.1 Program Memory (on-chip Flash)
The Program Memory on the W79E8213 series can be up to 4K bytes long. All instructions are
fetched for execution from this memory area. The MOVC instruction can also access this memory
region.
7.2 Data Flash Memory
The NVM Data Memory of Flash EPROM on the W79E8213 series is 128 bytes long, with page size of
16 bytes, respectively. The W79E8213 series’ NVM size is controllable through CONFIG1 register.
The W79E8213 series read the content of data memory by using “MOVC A, @A+DPTR”. To write
data is by NVMADDRL, NVMDATA and NVMCON SFR’s registers.
-10-
W79E8213/W79E8213R Data Sheet
7.3 Data Memory (accessed by MOVX)
Not available in this product series.
7.4 Scratch-pad RAM and Register Map
As mentioned before the W79E8213 series have separate Program and Data Memory areas. The on-
chip 128 bytes scratch pad RAM is in addition to the external memory. There are also several Special
Function Registers (SFRs) which can be accessed by software. The SFRs can be accessed only by
direct addressing, while the on-chip RAM can be accessed by either direct or indirect addressing.
FFH
SFR
Unused
Direct
Indirect
Addressing
RAM
Only
80H
7FH
Direct
&
Indirect
RAM
Addressing
00H
Figure 7-2: W79E8213 RAM and SFR memory map
Since the scratch-pad RAM is only 128 bytes it can be used only when data contents are small. There
are several other special purpose areas within the scratch-pad RAM. These are described as
following.
-11-
W79E8213/W79E8213R Data Sheet
FFH
Indirect RAM
Direct RAM
80H
7FH
30H
2FH 7F 7E 7D 7C 7B 7A 79
2EH 77
76 75 74 73 72 71
2DH 6F 6E 6D 6C 6B 6A 69
2CH 67 66 65 64 63 62 61
2BH 5F 5E 5D 5C 5B 5A 59
2AH 57 56 55 54 53 52 51
29H 4F 4E 4D 4C 4B 4A 49
47 46 45
41
27H 3F 3E 3D 3C 3B 3A 39
26H 34 33
25H 2F 2E 2D 2C 2B 2A 29
24H 27 26 25 24 23 22 21
23H 1F 1E 1D 1C 1B 1A 19
22H 17 16 15 14 13 12 11
21H 0F 0E 0D 0C 0B 0A 09
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
28H
44
43
42
37
36
35
32
31
20H 07
1FH
06
05
04
03
02
01
Bank 3
18H
17H
Bank 2
Bank 1
Bank 0
10H
0FH
08H
07H
00H
Figure 7-3: Scratch pad RAM
7.4.1 Working Registers
There are four sets of working registers, each consisting of eight 8-bit registers. These are termed as
Banks 0, 1, 2, and 3. Individual registers within these banks can be directly accessed by separate
instructions. These individual registers are named as R0, R1, R2, R3, R4, R5, R6 and R7. However, at
one time the W79E8213 series can work with only one particular bank. The bank selection is done by
setting RS1-RS0 bits in the PSW. The R0 and R1 registers are used to store the address for indirect
accessing.
-12-
W79E8213/W79E8213R Data Sheet
7.4.2 Bit addressable Locations
The Scratch-pad RAM area from location 20h to 2Fh is byte as well as bit addressable. This means
that a bit in this area can be individually addressed. In addition some of the SFRs are also bit
addressable. The instruction decoder is able to distinguish a bit access from a byte access by the type
of the instruction itself. In the SFR area, any existing SFR whose address ends in a 0 or 8 is bit
addressable.
7.4.3 Stack
The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP),
which stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the
return address is placed on the stack. There is no restriction as to where the stack can begin in the
RAM. By default however, the Stack Pointer contains 07h at reset. The user can then change this to
any value desired. The SP will point to the last used value. Therefore, the SP will be incremented and
then address saved onto the stack. Conversely, while popping from the stack the contents will be read
first, and then the SP is decreased.
-13-
W79E8213/W79E8213R Data Sheet
8. SPECIAL FUNCTION REGISTERS
The W79E8213 series uses Special Function Registers (SFRs) to control and monitor peripherals and
their Modes. The SFRs reside in the register locations 80-FFh and are accessed by direct addressing
only. Some of the SFRs are bit addressable. This is very useful in cases where users wish to modify a
particular bit without changing the others. The SFRs that are bit addressable are those whose
addresses end in 0 or 8. The W79E8213 series contain all the SFRs present in the standard 8052.
However some additional SFRs are added. In some cases the unused bits in the original 8052, have
been given new functions. The list of the SFRs is as following.
IP1
BUZCON
F8
B
EIE
PADIDS
IP1H
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
ACC
ADCCON
PWMPL
PWMPH
ADCH
PWM0L
PWM0H
ADCCON1
PWM1L
WDCON
PSW
PWMCON1 PWM2L
PWM2H
PWM3L
PWM3H
PWMCON2
PWMCON3
PWM1H
NVMCON NVMDATA
NVMADDRL
P2M2
TA
IP0
P0M1
P0M2
P1M1
EDIC
P1M2
P2M1
IP0H
IE
P2
AUXR1
A0
98
90
88
80
P1
TCON
P0
TMOD
SP
TL0
TL1
TH0
TH1
CKCON
DPL
DPH
PCON
Table 8-1: Special Function Register Location Table
Note: 1. The SFRs in the column with dark borders are bit-addressable
2. The table is condensed with eight locations per row. Empty locations indicate that these are no registers at these
addresses. When a bit or register is not implemented, it will read high.
-14-
W79E8213/W79E8213R Data Sheet
ADD MSB
RESS LSB
BIT_ADDRESS, SYMBOL
RESET
SYMBOL
DEFINITION
BUZDIV. BUZDIV. BUZDIV. BUZDIV. BUZDIV. BUZDIV.
BUZCON
Square wave control register F9H
-
-
xx00 0000B
5
4
3
2
1
0
(FF)
PED
(FE)
PPWM PBK
(FD)
(FC)
PWDI
(FB)
-
(FA)
-
(F9)
-
(F8)
-
IP1
Interrupt priority 1
F8H
0000xxxxB
0000xxxxB
00000000B
00000000B
IP1H
PADIDS
B
Interrupt high priority 1
F7H PEDH
PPWMH PBKH
PWDIH
-
-
-
-
Port ADC digital input
disable
F6H
B register
F0H (F7)
(F6)
(F5)
(F4)
(F3)
(F2)
(F1)
(F0)
(EE)
EPWMU
F
(EF)
E8H
(ED)
EPWM EWDI
(EC)
(EB)
-
(EA)
-
(E9)
-
(E8)
-
EIE
Interrupt enable 1
0000xxxxB
EED
ADCLK. ADCLK.
ADCCON1
ADCH
ADC control register 1
E3H
-
-
-
AADR2
ADC.4
-
-
10xxx0xxB
00000000B
1
0
ADC converter result high
register
E2H ADC.9
ADC.8
ADC.7
ADC.6
ADC.5
ADC.3
ADC.2
ADCCON
ACC
ADC control register
Accumulator
E1H ADC.1
E0H (E7)
ADC.0
(E6)
ADCEX ADCI
ADCS
(E3)
RCCLK AADR1 AADR0 00000000B
(E2) (E1) (E0) 00000000B
(E5)
(E4)
PWMCON2 PWM control register 2
DFH BKCH
BKPS
BPEN
BKEN
PWM3B PWM2B PWM1B PWM0B 00000000B
PWM3L
PWM2L
PWM 3 low bits register
PWM 2 low bits register
DEH PWM3.7 PWM3.6 PWM3.5 PWM3.4 PWM3.3 PWM3.2 PWM3.1 PWM3.0 00000000B
DDH PWM2.7 PWM2.6 PWM2.5 PWM2.4 PWM2.3 PWM2.2 PWM2.1 PWM2.0 00000000B
PWMRU
N
CLRPW
M
PWMCON1 PWM control register 1
DCH
load
PWMF
PWM3I PWM2I PWM1I PWM0I 00000000B
PWM1L
PWM0L
PWM 1 low bits register
PWM 0 low bits register
DBH PWM1.7 PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 PWM1.0 00000000B
DAH PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0 00000000B
PWMP0. PWMP0. PWMP0. PWMP0. PWMP0. PWMP0. PWMP0. PWMP0.
PWMPL
WDCON
PWM counter low register
Watch-Dog control
D9H
D8H
00000000B
7
6
5
4
3
2
1
0
External
reset:
0x00 0000B
Watchdog
reset:
0x00 0100B
Power on
reset
(DF)
WDRUN
(DE)
-
(DD)
WD1
(DC)
WD0
(DB)
WDIF
(DA)
WTRF
(D9)
(D8)
EWRST WDCLR
0x000000B
PWMCON3 PWM control register 3
D7H
D6H
D5H
D3H
D2H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FP1
FP0
-
BKF
xxxx00x0B
PWM3H
PWM2H
PWM1H
PWM0H
PWM 3 high bits register
PWM 2 high bits register
PWM 1 high bits register
PWM 0 high bits register
-
-
-
-
-
-
-
-
PWM3.9 PWM3.8 xxxxxx00B
PWM2.9 PWM2.8 xxxxxx00B
PWM1.9 PWM1.8 xxxxxx00B
PWM0.9 PWM0.8 xxxxxx00B
PWMP0. PWMP0.
00000000B
PWMPH
PSW
PWM counter high register
Program status word
D1H
-
-
-
-
-
-
9
8
(D7)
CY
(D6)
AC
(D5)
F0
(D4)
RS1
(D3)
RS0
(D2)
OV
(D1)
F1
(D0)
P
D0H
CFH
00000000B
NVMDATA
NVMCON
TA
NVM Data
00000000B
00xxxxxxB
11111111B
NVM Control
CEH EER
C7H TA.7
EWR
TA.6
-
-
-
-
-
-
Timed Access Protection
TA.5
TA.4
TA.3
TA.2
TA.1
TA.0
NVMAD NVMAD NVMAD NVMAD NVMAD NVMAD NVMAD
NVMADDRL NVM low byte address
IP0 Interrupt priority
C6H
B8H
-
00000000B
x00x0000B
DR.6
DR.5
DR.4
DR.3
DR.2
DR.1
DR.0
(BF)
-
(BE)
PADC
(BD)
PBO
(BC)
-
(BB)
PT1
(BA)
PX1
(B9)
PT0
(B8)
PX0
-15-
W79E8213/W79E8213R Data Sheet
Continued
ADD MSB
RESS LSB
BIT_ADDRESS, SYMBOL
RESET
SYMBOL
DEFINITION
IP0H
Interrupt high priority
Port 2 output mode 2
Port 2 output mode 1
Port 1 output mode 2
Port 1 output mode 1
Port 0 output mode 2
Port 0 output mode 1
B7H
B6H
-
-
PADCH PBOH
-
-
PT1H
-
PX1H
-
PT0H
PX0H
x00x0000B
P2M2
P2M1
P1M2
P1M1
P0M2
P0M1
-
-
P2M2.1 P2M2.0 xxxxxx 00B
P2M2.1 P2M2.0 00000000B
B5H P2S
P1S
P0S
ENCLK T1OE
T0OE
B4H P1M2.7 P1M2.6
B3H P1M1.7 P1M1.6
-
-
P1M2.4 P1M2.3 P1M2.2 P1M2.1 P1M2.0 00x00000B
P1M1.4 P1M1.3 P1M1.2 P1M1.1 P1M1.0 00x00000B
B2H P0M2.7 P0M2.6 P0M2.5 P0M2.4 P0M2.3 P0M2.2 P0M2.1 P0M2.0 00000000B
B1H P0M1.7 P0M1.6 P0M1.5 P0M1.4 P0M1.3 P0M1.2 P0M1.1 P0M1.0 00000000B
(AF)
EA
(AE)
EADC
(AD)
EBO
(AC)
-
(AB)
ET1
(AA)
EX1
(A9)
ET0
(A8)
EX0
IE
Interrupt enable
A8H
000x0000B
EDIC
Edge detect control register A3H EDFLT.1 EDFLT.0 ED2TRG ED2EN ED1TRG ED1EN ED0TRG ED0EN 00000000B
AUXR1
AUX function register
A2H EDF
BOD
BOI
LPBOV SRST
ADCEN BUZE
-
000X000xB
(A0)
P2.0
XTAL2
CLKOUT
(A1)
(A2)
(A7)
(A6)
-
(A5)
-
(A4)
-
(A3)
P2
P1
Port 2
A0H
-
P2.1
xxxxxxxxB
XTAL1
(94)
P1.4
/INT1
STADC
(92)
(91)
P1.2
P1.1
ED2
ED1
T0
(90)
P1.0
ED0
BUZ
(97)
90H P1.7
(96)
P1.6
PWM1 /RST
(95)
P1.5
(93)
P1.3
/INT0
Port 1
11111111B
PWM2
CKCON
TH1
Clock control
Timer high 1
Timer high 0
Timer low 1
Timer low 0
Timer mode
8EH
8DH
8CH
8BH
8AH
-
-
-
T1M
T0M
-
-
-
xxx00xxxB
00000000B
00000000B
00000000B
00000000B
00000000B
TH0
TL1
TL0
TMOD
89H GATE
C/T
M1
M0
GATE
C/T
M1
M0
(8F)
88H
(8E)
TR1
(8D)
TF0
(8C)
TR0
(8B)
IE1
(8A)
IT1
(89)
IE0
(88)
IT0
TCON
Timer control
00000000B
TF1
PCON
DPH
DPL
SP
Power control
Data pointer high
Data pointer low
Stack pointer
87H
83H
82H
81H
-
-
BOF
POR
GF1
GF0
PD
IDL
xxxx0000B
00000000B
00000000B
00000111B
(87)
P0.7
AD7
T1
(86)
P0.6
AD3
(85)
P0.5
AD2
(84)
P0.4
AD1
(83)
P0.3
AD0
(82)
P0.2
AD4
(81)
P0.1
AD5
(80)
P0.0
AD6
P0
Port 0
80H
11111111B
BRAKE PWM0
PWM3
Table 8-2: Special Function Registers
-16-
W79E8213/W79E8213R Data Sheet
PORT 0
Bit:
7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Mnemonic: P0
Address: 80h
P0.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:
BIT NAME
FUNCTION
7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
AD7 pin or Timer 1 pin by alternative.
AD3 pin by alternative.
AD2 pin by alternative.
AD1 pin by alternative.
AD0 pin by alternative.
AD4 pin or BRAKE pin by alternative.
AD5 pin or PWM0 pin by alternative.
AD6 pin or PWM3 pin by alternative.
Note: During power-on-reset, the port pins are tri-stated. After power-on-reset, the value of the port is set by CONFIG0.PRHI
bit. The default setting for CONFIG0.PRHI =1 which the alternative function output is turned on upon reset. If
CONFIG0.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the alternative function output.
STACK POINTER
Bit:
7
6
5
4
3
2
1
0
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
Mnemonic: SP
BIT NAME
Address: 81h
FUNCTION
The Stack Pointer stores the Scratch-pad RAM address where the stack begins. In
other words it always points to the top of the stack.
7-0 SP.[7:0]
DATA POINTER LOW
Bit:
7
6
5
4
3
2
1
0
DPL.7
DPL.6
DPL.5
DPL.4
DPL.3
DPL.2
DPL.1
DPL.0
Mnemonic: DPL
BIT NAME
Address: 82h
FUNCTION
7-0 DPL.[7:0] This is the low byte of the standard 8052 16-bit data pointer.
-17-
W79E8213/W79E8213R Data Sheet
DATA POINTER HIGH
Bit:
7
6
5
4
3
2
1
0
DPH.7
DPH.6
DPH.5
DPH.4
DPH.3
DPH.2
DPH.1
DPH.0
Mnemonic: DPH
BIT NAME
Address: 83h
FUNCTION
This is the high byte of the standard 8052 16-bit data pointer.
This is the high byte of the DPTR 16-bit data pointer.
7-0 DPH.[7:0]
POWER CONTROL
Bit:
7
-
6
-
5
4
3
2
1
0
BOF
POR
GF1
GF0
PD
IDL
Mnemonic: PCON
Address: 87h
BIT
7
NAME
FUNCTION
-
-
Reserved.
Reserved.
6
0: Cleared by software.
5
4
BOF
POR
1: Set automatically when a brownout reset or interrupt has occurred. Also set at
power on.
0: Cleared by software.
1: Set automatically when a power-on reset has occurred.
3
2
GF1
GF0
General purpose user flags.
General purpose user flags.
1: The CPU goes into the POWER DOWN mode. In this mode, all the clocks are
stopped and program execution is frozen.
1
0
PD
1: The CPU goes into the IDLE mode. In this mode, the clocks CPU clock stopped,
so program execution is frozen. But the clock to the serial, timer and interrupt
blocks is not stopped, and these blocks continue operating.
IDL
TIMER CONTROL
Bit:
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic: TCON
Address: 88h
-18-
W79E8213/W79E8213R Data Sheet
BIT
NAME
FUNCTION
Timer 1 Overflow Flag. This bit is set when Timer 1 overflows. It is cleared
automatically when the program does a timer 1 interrupt service routine. Software
can also set or clear this bit.
7
TF1
Timer 1 Run Control. This bit is set or cleared by software to turn timer/counter on
or off.
6
5
4
TR1
TF0
TR0
Timer 0 Overflow Flag. This bit is set when Timer 0 overflows. It is cleared
automatically when the program does a timer 0 interrupt service routine. Software
can also set or clear this bit.
Timer 0 Run Control. This bit is set or cleared by software to turn timer/counter on
or off.
Interrupt 1 Edge Detect Flag: Set by hardware when an edge/level is detected on
3
2
1
0
IE1
IT1
IE0
IT0
INT1
. This bit is cleared by hardware when the service routine is vectored to only if
the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
Interrupt 1 Type Control. Set/cleared by software to specify falling edge/ low level
triggered external inputs.
Interrupt 0 Edge Detect Flag. Set by hardware when an edge/level is detected on
INT0
. This bit is cleared by hardware when the service routine is vectored to only if
the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
Interrupt 0 Type Control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
TIMER MODE CONTROL
Bit:
7
6
5
4
3
2
1
0
GATE
M1
M0
GATE
M1
M0
C/T
C/T
TIMER1
TIMER0
Mnemonic: TMOD
Address: 89h
BIT NAME
FUNCTION
Gating control: When this bit is set, Timer/counter 1 is enabled only while the INT1
7
GATE
pin is high and the TR1 control bit is set. When cleared, the INT1 pin has no effect,
and Timer 1 is enabled whenever TR1 control bit is set.
Timer or Counter Select: When clear, Timer 1 is incremented by the internal clock.
When set, the timer counts falling edges on the T1 pin.
6
C/T
5
4
M1
M0
Timer 1 mode select bit 1. See table below.
Timer 1 mode select bit 0. See table below.
Gating control: When this bit is set, Timer/counter 0 is enabled only while the INT0
3
GATE
pin is high and the TR0 control bit is set. When cleared, the INT0 pin has no effect,
and Timer 0 is enabled whenever TR0 control bit is set.
Timer or Counter Select: When clear, Timer 0 is incremented by the internal clock.
When set, the timer counts falling edges on the T0 pin.
2
C/T
1
0
M1
M0
Timer 0 mode select bit 1. See table below.
Timer 0 mode select bit 0. See table below.
M1, M0: Mode Select bits:
MODE
M1
M0
Mode 0: 13-bits timer/counter; THx 8 bits and TLx 5 bits which serve as pre-scalar.
-19-
0
0
W79E8213/W79E8213R Data Sheet
Mode 1: 16-bit timer/counter, no pre-scale.
0
1
1
0
Mode 2: 8-bit timer/counter with auto-reload from THx.
Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer0
control bits. TH0 is an 8-bit timer only controlled by Timer1 control bits.
(Timer 1) Timer/Counter 1 is stopped.
1
1
TIMER 0 LSB
Bit:
7
6
5
4
3
2
1
0
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
Mnemonic: TL0
BIT NAME
Address: 8Ah
FUNCTION
7-0 TL0.[7:0] Timer 0 LSB.
TIMER 1 LSB
Bit:
7
6
5
4
3
2
1
0
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
Mnemonic: TL1
BIT NAME
Address: 8Bh
FUNCTION
7-0 TL1.[7:0] Timer 1 LSB.
TIMER 0 MSB
Bit:
7
6
5
4
3
2
1
0
TH0.7
TH0.6
TH0.5
TH0.4
TH0.3
TH0.2
TH0.1
TH0.0
Mnemonic: TH0
BIT NAME
Address: 8Ch
FUNCTION
7-0 TH0.[7:0] Timer 0 MSB.
TIMER 1 MSB
Bit:
7
6
5
4
3
2
1
0
TH1.7
TH1.6
TH1.5
TH1.4
TH1.3
TH1.2
TH1.1
TH1.0
Mnemonic: TH1
BIT NAME
7-0 TH1.[7:0] Timer 1 MSB.
Address: 8Dh
FUNCTION
-20-
W79E8213/W79E8213R Data Sheet
CLOCK CONTROL
Bit:
7
-
6
-
5
-
4
3
2
-
1
-
0
-
T1M
T0M
Mnemonic: CKCON
Address: 8Eh
BIT NAME
FUNCTION
-
Reserved.
Timer 1 clock select:
7-5
T1M
0: Timer 1 uses a divide by 12 clocks.
1: Timer 1 uses a divide by 4 clocks.
4
Timer 0 clock select:
T0M
-
0: Timer 0 uses a divide by 12 clocks.
1: Timer 0 uses a divide by 4 clocks.
3
Reserved.
2-0
PORT 1
Bit:
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Mnemonic: P1
Address: 90h
P1.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:
BIT
7
NAME
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
FUNCTION
PWM2 pin by alternative.
PWM1 pin by alternative.
6
/RST pin or input pin by alternative.
5
STADC pin or /INT1 interrupt pin by alternative.
/INT0 interrupt pin by alternative.
Timer 0 pin or ED2 pin by alternative.
ED1 pin by alternative.
4
3
2
1
BUZ pin or ED0 pin by alternative.
0
Note: During power-on-reset, the port pins are tri-stated. After power-on-reset, the value of the port is set by CONFIG0.PRHI
bit. The default setting for CONFIG0.PRHI =1 which the alternative function output is turned on upon reset. If
CONFIG0.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the alternative function output.
PORT 2
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
P2.1
P2.0
Mnemonic: P2
Address: A0h
BIT
NAME
FUNCTION
7-2
-
Reserved.
-21-
W79E8213/W79E8213R Data Sheet
1
0
P2.1
P2.0
XTAL1 clock input pin.
XTAL2 or CLKOUT pin by alternative.
Note: During power-on-reset, the port pins are tri-stated. After power-on-reset, the value of the port is set by CONFIG0.PRHI
bit. The default setting for CONFIG0.PRHI =1 which the alternative function output is turned on upon reset. If
CONFIG0.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the alternative function output.
AUX FUNCTION REGISTER 1
Bit:
7
6
5
4
3
2
1
0
-
EDF
BOD
BOI
LPBOV
SRST
ADCEN
BUZE
Mnemonic: AUXR1
Address: A2h
BIT
NAME
FUNCTION
Edge detect Interrupt Flag:
1: When any pin of port 1.0-1.2 that is enabled for the Edge Detect Interrupt
function trigger (falling/rising edge trigger configurable). Must be cleared by
software.
7
EDF
Brown Out Disable:
6
5
BOD
BOI
0: Enable Brownout Detect function.
1: Disable Brownout Detect function and save power.
Brown Out Interrupt:
0: Disable Brownout Detect Interrupt function and it will cause chip reset when
BOF is set.
1: This prevents Brownout Detection from causing a chip reset and allows the
Brownout Detect function to be used as an interrupt.
Low Power Brown Out Detect control:
0: When BOD is enable, the Brown Out detect is always turned on by normal run
or Power-down mode.
4
LPBOV
1: When BOD is enable, the Brown Out detect circuit is turned on by Power-
down mode. This control can help save 15/16 of the Brownout circuit power.
When uC is in Power-down mode, the BOD will enable internal RC OSC
(600KHz+/- 50%)
Software reset:
3
2
SRST
1: reset the chip as if a hardware reset occurred.
0: Disable ADC circuit.
1: Enable ADC circuit.
ADCEN
Square-wave enable bit:
1
0
BUZE
-
0: Disable square wave output.
1: The square wave is output to the BUZ (P1.0) pin.
Reserved.
EDGE DETECT CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
0
EDFILT.1
EDFILT.0
ED2TRG
ED2EN
ED1TRG
ED1EN
ED0TRG
ED0EN
Mnemonic: EDIC
Address: A3h
-22-
W79E8213/W79E8213R Data Sheet
BIT
NAME
FUNCTION
Edge detect filter type bits:
00 – Filter clock = Fosc.
01 – Filter clock = Fosc/2.
10 – Filter clock = Fosc/4.
11 – Filter clock = Fosc/8.
7-6
Edge detect 2 (ED2) trigger type bit:
0 – Falling edge on ED2 pin will cause EDF to be set (if ED2EN is enabled).
5
4
3
2
1
0
ED2TRG
ED2EN
1 – Either falling or rising edge on ED2 pin will cause EDF to be set (if ED2EN is
enabled).
Edge detect 2 (ED2) enable bit:
0 – Disabled.
1 – Enable ED2 (P1.2 pin) as a cause of an edge detect interrupt.
Edge detect 1 (ED1) trigger type bit:
0 – Falling edge on ED1 pin will cause EDF to be set (if ED1EN is enabled).
ED1TRG
ED1EN
1 – Either falling or rising edge on ED1 pin will cause EDF to be set (if ED1EN is
enabled).
Edge detect 1 (ED1) enable bit:
0 – Disabled.
1 – Enable ED1 (P1.1 pin) as a cause of an edge detect interrupt.
Edge detect 0 (ED0) trigger type bit:
0 – Falling edge on ED0 pin will cause EDF to be set (if ED0EN is enabled).
ED0TRG
ED0EN
1 – Either falling or rising edge on ED0 pin will cause EDF to be set (if ED0EN is
enabled).
Edge detect 0 (ED0) enable bit:
0 – Disabled.
1 – Enable ED0 (P1.0 pin) as a cause of an edge detect interrupt.
INTERRUPT ENABLE
Bit:
7
6
5
4
-
3
2
1
0
EA
EADC
EBO
ET1
EX1
ET0
EX0
Mnemonic: IE
Address: A8h
-23-
W79E8213/W79E8213R Data Sheet
BIT
7
NAME
EA
FUNCTION
Global enable. Enable/Disable all interrupts.
6
EADC
EBO
-
Enable ADC interrupt.
Enable Brown Out interrupt.
Reserved.
5
4
3
ET1
EX1
ET0
EX0
Enable Timer 1 interrupt.
Enable external interrupt 1.
Enable Timer 0 interrupt.
Enable external interrupt 0.
2
1
0
PORT 0 OUTPUT MODE 1
Bit:
7
6
5
4
3
2
1
0
P0M1.7
P0M1.6
P0M1.5
P0M1.4
P0M1.3
P0M1.2
P0M1.1
P0M1.0
Mnemonic: P0M1
BIT NAME
Address: B1h
FUNCTION
7-0 P0M1.[7:0] To control the output configuration of P0 bits [7:0]
PORT 0 OUTPUT MODE 2
Bit:
7
6
5
4
3
2
1
0
P0M2.7
P0M2.6
P0M2.5
P0M2.4
P0M2.3
P0M2.2
P0M2.1
P0M2.0
Mnemonic: P0M2
BIT NAME
Address: B2h
FUNCTION
7-0 P0M2.[7:0] To control the output configuration of P0 bits [7:0]
PORT 1 OUTPUT MODE 1
Bit:
7
6
5
-
4
3
2
1
0
P1M1.7
P1M1.6
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0
Mnemonic: P1M1
BIT NAME
Address: B3h
FUNCTION
7-0 P1M1.[7:0] To control the output configuration of P1 bits [7:0]
PORT 1 OUTPUT MODE 2
Bit:
7
6
5
-
4
3
2
1
0
P1M2.7
P1M2.6
P1M2.4
P1M2.3
P1M2.2
P1M2.1
P1M2.0
Mnemonic: P1M2
BIT NAME
Address: B4h
FUNCTION
7-0 P1M2.[7:0] To control the output configuration of P1 bits [7:0]
PORT 2 OUTPUT MODE 1
Bit:
7
6
5
4
3
2
1
0
-24-
W79E8213/W79E8213R Data Sheet
P2S
P1S
P0S
ENCLK
T1OE
T0OE
P2M1.1
P2M1.0
Mnemonic: P2M1
Address: B5h
BIT
NAME
FUNCTION
0: Disable Schmitt trigger inputs on port 2 and enable TTL inputs on port 2.
1: Enables Schmitt trigger inputs on Port 2.
7
P2S
0: Disable Schmitt trigger inputs on port 1 and enable TTL inputs on port 1.
1: Enables Schmitt trigger inputs on Port 1.
6
5
P1S
P0S
0: Disable Schmitt trigger inputs on port 0 and enable TTL inputs on port 0
1: Enables Schmitt trigger inputs on Port 0.
4
3
ENCLK 1: Enabled clock output to XTAL2 pin (P2.0).
1: The P0.7 pin is toggled whenever Timer 1 overflows. The output frequency is
T1OE
therefore one half of the Timer 1 overflow rate.
1: The P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is
2
T0OE
therefore one half of the Timer 0 overflow rate.
1
0
P2M1.1 To control the output configuration of P2.1.
P2M1.0 To control the output configuration of P2.0.
PORT 2 OUTPUT MODE 2
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
P2M2.1
P2M2.0
Mnemonic: P2M2
Address: B6h
BIT
NAME
FUNCTION
7-2
-
Reserved.
1-0 P2M2.[1:0] To control the output configuration of P2 bits [1:0]
Port Output Configuration Settings:
PXM1.Y
PXM2.Y
PORT INPUT/OUTPUT MODE
(SEE NOTE)
0
0
0
1
Quasi-bidirectional
Push-Pull
Input Only (High Impedance)
P2M1.PxS=0, TTL input
1
1
0
1
P2M1.PxS=1, Schmitt input
Open Drain
-25-
W79E8213/W79E8213R Data Sheet
INTERRUPT HIGH PRIORITY
Bit:
7
-
6
5
4
-
3
2
1
0
PADCH
PBOH
PT1H
PX1H
PT0H
PX0H
Mnemonic: IP0H
Address: B7h
BIT
7
NAME
FUNCTION
-
This bit is un-implemented and will read high.
1: To set interrupt high priority of ADC is highest priority level.
6
PADCH
PBOH
-
5
1: To set interrupt high priority of Brown Out Detector is highest priority level.
Reserved.
4
3
PT1H
PX1H
PT0H
PX0H
1: To set interrupt high priority of Timer 1 is highest priority level.
1: To set interrupt high priority of External interrupt 1 is highest priority level.
1: To set interrupt high priority of Timer 0 is highest priority level.
1: To set interrupt high priority of External interrupt 0 is highest priority level.
2
1
0
INTERRUPT PRIORITY 0
Bit:
7
-
6
5
4
-
3
2
1
0
PADC
PBO
PT1
PX1
PT0
PX0
Mnemonic: IP
Address: B8h
BIT
7
NAME
FUNCTION
-
This bit is un-implemented and will read high.
1: To set interrupt priority of ADC is higher priority level.
6
PADC
PBO
-
5
1: To set interrupt priority of Brown Out Detector is higher priority level.
Reserved.
4
3
PT1
PX1
PT0
PX0
1: To set interrupt priority of Timer 1 is higher priority level.
1: To set interrupt priority of External interrupt 1 is higher priority level.
1: To set interrupt priority of Timer 0 is higher priority level.
1: To set interrupt priority of External interrupt 0 is higher priority level.
2
1
0
NVM LOW BYTE ADDRESS
Bit:
7
-
6
5
4
3
2
1
0
NVMADDR
.6
NVMADDR
.5
NVMADDR
.4
NVMADDR
.3
NVMADDR
.2
NVMADDR
.1
NVMADDR
.0
Mnemonic: NVMADDRL
Address: C6h
-26-
W79E8213/W79E8213R Data Sheet
BIT
NAME
FUNCTION
7
-
Please Keep it at 0.
The NVM address:
6~0 NVMADDR.[7:0]
The register indicates NVM data memory address on On-Chip code
memory space.
TIMED ACCESS
Bit:
7
6
5
4
3
2
1
0
TA.7
TA.6
TA.5
TA.4
TA.3
TA.2
TA.1
TA.0
Mnemonic: TA
BIT NAME
Address: C7h
FUNCTION
The Timed Access register:
The Timed Access register controls the access to protected bits. To access
protected bits, the user must first write AAH to the TA. This must be immediately
followed by a write of 55H to TA. Now a window is opened in the protected bits
for three machine cycles, during which the user can write to these bits.
7-0 TA.[7:0]
NVM CONTROL
Bit:
7
6
5
-
4
-
3
-
2
-
1
-
0
-
EER
EWR
Mnemonic: NVMCON
Address: CEh
BIT
NAME
FUNCTION
NVM page(n) erase bit:
0: Without erase NVM page(n).
1: Set this bit to erase page(n) of NVM. The NVM has 8 pages and each page
have 16 bytes data memory. Initiate page select by programming NVMADDL
register, which will automaticly enable page area. When user set this bit, the
page erase process will begin and program counter will halt at this instruction.
After the erase process is completed, program counter will continue executing
next instruction.
7
EER
NVM data write bit:
0: Without write NVM data.
6
EWR
-
1: Set this bit to write NVM bytes and program counter will halt at this instruction.
After write is finished, program counter will kept next instruction then executed.
5-0
Reserved
NVM DATA
Bit:
7
6
5
4
3
2
1
0
NVMDAT
A.7
NVMDAT
A.6
NVMDAT
A.5
NVMDAT
A.4
NVMDAT
A3
NVMDAT
A.2
NVMDAT
A.1
NVMDAT
A.0
Mnemonic: NVMDATA
BIT NAME
Address: CFh
FUNCTION
7~0 NVMDATA.[7:0] The NVM data write register. The read NVM data is by MOVC instruction.
-27-
W79E8213/W79E8213R Data Sheet
PROGRAM STATUS WORD
Bit:
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Mnemonic: PSW
Address: D0h
BIT
NAME
FUNCTION
Carry flag:
7
CY
Set for an arithmetic operation which results in a carry being generated from the
ALU. It is also used as the accumulator for the bit operations.
6
Auxiliary carry:
AC
F0
Set when the previous operation resulted in a carry from the high order nibble.
User flag 0:
5
The General purpose flag that can be set or cleared by the user.
4~3 RS1~RS0 Register bank select bits.
Overflow flag:
2
OV
Set when a carry was generated from the seventh bit but not from the 8th bit as
a result of the previous operation, or vice-versa.
User Flag 1:
1
0
F1
P
The General purpose flag that can be set or cleared by the user software.
Parity flag:
Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
RS.1-0: Register Bank Selection Bits:
RS1
RS0
0
REGISTER BANK
ADDRESS
00-07h
0
0
1
1
0
1
2
3
1
08-0Fh
10-17h
0
1
18-1Fh
PWMP COUNTER HIGH BITS REGISTER
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWMP.9
PWMP.8
Mnemonic: PWMPH
Address: D1h
-28-
W79E8213/W79E8213R Data Sheet
BIT
NAME
FUNCTION
7-2
-
Reserved.
1-0 PWMP.[9:8] The PWM Counter Register bits 9~8.
PWM 0 HIGH BITS REGISTER
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM0.9
PWM0.8
Mnemonic: PWM0H
Address: D2h
BIT
NAME
FUNCTION
7~2
-
Reserved.
1~0 PWM0.[9:8] The PWM 0 High Bits Register bit 9~8.
PWM 1 HIGH BITS REGISTER
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM1.9
PWM1.8
Mnemonic: PWM1H
Address: D3h
BIT
NAME
FUNCTION
7~2
-
Reserved.
1~0 PWM1.[9:8] The PWM 1 High Bits Register bit 9~8.
PWM 2 HIGH BITS REGISTER
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM2.9
PWM2.8
Mnemonic: PWM2H
Address: D5h
BIT
NAME
FUNCTION
7~2
-
Reserved.
1~0 PWM2.[9:8] The PWM 2 High Bits Register bit 9~8.
PWM 3 HIGH BITS REGISTER
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
PWM3.9
PWM3.8
Mnemonic: PWM3H
Address: D6h
BIT
NAME
FUNCTION
7~2
-
Reserved.
1~0 PWM3.[9:8] The PWM 3 High Bits Register bit 9~8.
-29-
W79E8213/W79E8213R Data Sheet
PWM CONTROL REGISTER 3
Bit:
7
-
6
-
5
4
3
2
1
-
0
FP1
FP0
BKF
-
-
Mnemonic: PWMCON3
Address: D7h
BIT
NAME
FUNCTION
7-4
-
Reserved.
Select PWM frequency pre-scale select bits. The clock source of pre-scaler,
Fpwm is in phase with Fosc if PWMRUN=1.
FP[1:0]
00
Fpwm
FOSC
3-2
FP[1:0]
01
FOSC/2
FOSC/4
FOSC/16
10
11
1
0
-
Reserved.
The external brake pin flag:
0: The PWM is not brake.
BKF
1: The PWM is brake by external brake pin. It is cleared by software.
WATCHDOG CONTROL
Bit:
7
6
-
5
4
3
2
1
0
WDRUN
WD1
WD0
WDIF
WTRF
EWRST
WDCLR
Mnemonic: WDCON
Address: D8h
BIT
NAME
FUNCTION
0: The Watchdog is stopped.
1: The Watchdog is running.
7
WDRUN
6
5
-
Reserved.
WD1
Watchdog Timer Time-out Select bits. These bits determine the time-out period
of the watchdog timer. The reset time-out period is 512 clocks longer than the
watchdog time-out.
WD1 WD0 Interrupt time-out
Reset time-out
217 + 512
217
220
223
226
4
WD0
0
0
1
1
0
1
0
1
220 + 512
223 + 512
226 + 512
Watchdog Timer Interrupt Flag
0: If the interrupt is not enabled, then this bit indicates that the time-out period
has elapsed. This bit must be cleared by software.
1: If the watchdog interrupt is enabled, hardware will set this bit to indicate that
the watchdog interrupt has occurred.
3
2
WDIF
Watchdog Timer Reset Flag
1: Hardware will set this bit when the watchdog timer causes a reset. Software
can read it but must clear it manually. A power-fail reset will also clear the
bit. This bit helps software in determining the cause of a reset. If EWRST =
WTRF
-30-
W79E8213/W79E8213R Data Sheet
0, the watchdog timer will have no affect on this bit.
0: Disable Watchdog Timer Reset.
1: Enable Watchdog Timer Reset.
Reset Watchdog Timer
This bit helps in putting the watchdog timer into a know state. It also helps in
resetting the watchdog timer before a time-out occurs. Failing to set the
EWRST before time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512
clocks after that a watchdog timer reset will be generated if EWRST is set. This
bit is self-clearing by hardware.
1
0
EWRST
WDCLR
The WDCON SFR is set to 0x000000B on a reset. WTRF (WDCON.2) is set to a 1 on a Watchdog
timer reset, but to a 0 on power on/down resets. WTRF (WDCON.2) is not altered by an external
reset. EWRST (WDCON.1) is set to 0 on a Power-on reset, reset pin reset, and Watch Dog Timer
reset.
All the bits in this SFR have unrestricted read access. WDRUN, WD0, WD1, EWRST, WDIF and
WDCLR require Timed Access procedure to write. The remaining bits have unrestricted write
accesses. Please refer TA register description.
TA
REG
C7H
D8H
WDCON
MOV
MOV
SETB
ORL
REG
TA, #AAH
TA, #55H
WDCON.0
; To access protected bits
; Reset watchdog timer
WDCON, #00110000B
TA, #AAH
; Select 26 bits watchdog timer
MOV
MOV
ORL
TA, #55H
WDCON, #00000010B
; Enable watchdog reset
PWMP COUNTER LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWMP.7
PWMP.6
PWMP.5
PWP.4
PWMP.3
PWMP.2
PWMP.1
PWMP.1
Mnemonic: PWMPL
BIT NAME
Address: D9h
FUNCTION
7~0 PWMP.[7:0] PWM Counter Low Bits Register.
PWM0 LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWM0.7
PWM0.6
PWM0.5
PWM0.4
PWM0.3
PWM0.2
PWM0.1
PWM0.1
Mnemonic: PWM0L
BIT NAME
Address: DAh
FUNCTION
7~0 PWM0.[7:0] PWM 0 Low Bits Register.
PWM1 LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWM1.7
PWM1.6
PWM1.5
PWM1.4
PWM1.3
PWM1.2
PWM1.1
PWM1.0
Mnemonic: PWM1L
BIT NAME
Address: DBh
FUNCTION
-31-
W79E8213/W79E8213R Data Sheet
7~0 PWM1.[7:0] PWM 1 Low Bits Register.
PWM CONTROL REGISTER 1
Bit:
7
6
5
4
3
-
2
-
1
0
PWMRUN Load
Mnemonic: PWMCON1
PWMF
CLRPWM
PWM1I
PWM0I
Address: DCh
BIT
NAME
FUNCTION
0: The PWM is not running.
7
PWMRUN
1: The PWM counter is running.
0: The registers value of PWMP and PWMn are never loaded to counter and
Comparator registers.
6
5
Load
1: The PWMP and PWMn registers load value to counter and compare registers
at the counter underflow. This bit is auto cleared by hardware at next clock
cycle.
PWM underflow flag:
0: The 10-bit counter down count is not underflow.
PWMF
1: The 10-bit counter down count is underflow. (PWM interrupt is requested if
PWM interrupt is enabled).
This bit is Software clear.
4
3
CLRPWM 1: Clear 10-bit PWM counter to 000H. This bit is auto cleared by hardware.
0: PWM3 out is non-inverted.
PWM3I
1: PWM3 output is inverted.
0: PWM2 out is non-inverted.
PWM2I
2
1
0
1: PWM2 output is inverted.
0: PWM1 out is non-inverted.
PWM1I
1: PWM1 output is inverted.
0: PWM0 out is non-inverted.
PWM0I
1: PWM0 output is inverted.
PWM2 LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWM2.7
PWM2.6
PWM2.5
PWM2.4
PWM2.3
PWM2.2
PWM2.1
PWM2.0
Mnemonic: PWM2L
BIT NAME
7~0 PWM2.[7:0] PWM 2 Low Bits Register.
Address: DDh
FUNCTION
-32-
W79E8213/W79E8213R Data Sheet
PWM3 LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWM3.7
PWM3.6
PWM3.5
PWM3.4
PWM3.3
PWM3.2
PWM3.1
PWM3.0
Mnemonic: PWM3L
BIT NAME
Address: DEh
FUNCTION
7~0 PWM3.[7:0] PWM 3 Low Bits Register.
PWM CONTROL REGISTER 2
Bit:
7
6
5
4
3
2
1
0
BKCH
BKPS
BPEN
BKEN
PWM3B
PWM2B
PWM1B
PWM0B
Mnemonic: PWMCON2
Address: DFh
BIT
NAME
BKCH
FUNCTION
7
See the below table, when BKEN is set.
0: Brake is asserted if P0.2 is low.
1: Brake is asserted if P0.2 is high
6
5
4
BKPS
BPEN
BKEN
See the below table, when BKEN is set.
0: The Brake is never asserted.
1: The Brake is enabled, and see the below table.
0: The PWM3 output is low, when Brake is asserted.
1: The PWM3 output is high, when Brake is asserted.
3
2
1
0
PWM3B
PWM2B
PWM1B
PWM0B
0: The PWM2 output is low, when Brake is asserted.
1: The PWM2 output is high, when Brake is asserted.
0: The PWM1 output is low, when Brake is asserted.
1: The PWM1 output is high, when Brake is asserted.
0: The PWM0 output is low, when Brake is asserted.
1: The PWM0 output is high, when Brake is asserted.
-33-
W79E8213/W79E8213R Data Sheet
Brake Condition Table:
BRAKE CONDITION
BPEN
BKCH
Brake On (software brake and keeping brake).
Software brake condition. When active (BPEN=BKCH=0, and BKEN=1), PWM
output follows PWMnB setting. This brake has no effect on PWMRUN bit,
therefore, internal PWM generator continues to run. When the brake is released,
the state of PWM output depends on the current state of PWM generator output
during the release.
0
0
Brake On;
This condition is when BKEN set (BKEN=1) and PWM is not running
(PWMRUN=0), the PWMn output follows PWMnB setting. When the brake is
released (by disabling BKEN = 0), the PWMn output resumes to the state when
PWM generator stop running prior to enabling the brake.
0
1
Brake Off;
This condition is when PWM is running (PWMRUN=1).
Brake On, when Brake Pin asserted.
External pin brake condition. When active (by external pin), PWM output follows
PWMnB setting, PWMRUN will be cleared by hardware, and BKF flag will be set.
When the brake is released (by de-asserting the external pin and disabling
BKEN = 0), the PWM output resumes to the state of the PWM generator output
prior to the brake.
1
1
0
1
This is another brake condition (by Brake Pin) which causes BKF to be set, but
PWM generator continues to run. The PWM output does not follow PWMnB,
instead it output continuously as per normal.
ACCUMULATOR
Bit:
7
6
5
4
3
2
1
0
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
Mnemonic: ACC
BIT NAME
Address: E0h
FUNCTION
7-0 ACC.[7:0] The A or ACC register is the standard 8052 accumulator
ADC CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
0
ADC.1
ADC.0
ADCEX
ADCI
ADCS
RCCLK
AADR1
AADR0
Mnemonic: ADCCON
Address: E1h
-34-
W79E8213/W79E8213R Data Sheet
BIT
NAME
FUNCTION
7-6 ADC.1-0
2 LSB of 10-bit A/D conversion result.
Enable STADC-triggered conversion
0: Conversion can only be started by software (i.e., by setting ADCS).
5
4
ADCEX
ADCI
1: Conversion can be started by software or by a rising edge on STADC (pin
P1.4).
ADC Interrupt flag:
This flag is set when the result of an A/D conversion is ready. This generates an
ADC interrupt, if it is enabled. The flag may be cleared by the ISR. While this flag
is 1, the ADC cannot start a new conversion. ADCI can not be set by software.
ADC Start and Status: Set this bit to start an A/D conversion. It may also be set
by STADC if ADCEX is 1. This signal remains high while the ADC is busy and is
reset right after ADCI is set.
Note:
3
ADCS
1.
It is recommended to clear ADCI before ADCS is set. However, if ADCI
is cleared and ADCS is set at the same time, a new A/D conversion
may start on the same channel.
2.
Software clearing of ADCS will abort conversion in progress.
ADC cannot start a new conversion while ADCS is high.
3.
0: The CPU clock is used as ADC clock source.
1: The internal RC 10MHz/20MHz (selectable by CONFIG1.FS1 bit) clock is
used as ADC clock source.
Note:
2
RCCLK
1. This bit can only be set/cleared when ADCEN=0.
2. The ADC clock source will goes through pre-scalar of /1, /2, /4 or /8,
selectable by ADCLK bits (SFR ADCCON1.6-7).
1
0
AADR1
AADR0
The ADC input select. See table below.
The ADC input select. See table below.
The ADCI and ADCS control the ADC conversion as below:
ADCI
ADCS
ADC STATUS
ADC not busy; A conversion can be started.
0
0
1
1
0
1
0
1
ADC busy; Start of a new conversion is blocked.
Conversion completed; Start of a new conversion requires ADCI = 0.
This is an internal temporary state that user can ignore it.
-35-
W79E8213/W79E8213R Data Sheet
AADR1, AADR0: ADC Analog Input Channel select bits:
These bits can only be changed when ADCI and ADCS are both zero.
AADR2
AADR1
AADR0
SELECTED ANALOG INPUT CHANNEL
AD0 (P0.3)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AD1 (P0.4)
AD2 (P0.5)
AD3 (P0.6)
AD4 (P0.2)
AD5 (P0.1)
AD6 (P0.0)
AD7 (P0.7)
ADC CONVERTER RESULT HIGH REGISTER
Bit:
7
6
5
4
3
2
1
0
ADC.9
ADC.8
ADC.7
ADC.6
ADC.5
ADC.4
ADC.3
ADC.2
Mnemonic: ADCH
BIT NAME
Address: E2h
FUNCTION
7-0 ADC.[9:2] 8 MSB of 10-bit A/D conversion result.
ADC CONTROL REGISTER 1
Bit:
7
6
5
-
4
-
3
-
2
1
-
0
-
ADCLK.1
ADCLK.0
AADR2
Mnemonic: ADCCON1
BIT NAME
Address: E3h
FUNCTION
ADC Clock Prescaler:
The 10-bit ADC needs a clock to drive the converting and the clock frequency
need to be within 200KHz to 5MHz. ADCLK[1:0] controls the frequency of the
clock to ADC block as below table.
ADCLK.1
ADCLK.0
ADC Clock Frequency
ADCCLK/1
0
0
1
1
0
1
0
1
7-6 ADCLK.1~0
ADCCLK/2
ADCCLK/4 (default)
ADCCLK/8
Note: User required to clear ADCEN (ADCEN = 0) when re-configure the
ADC clock prescaler.
5-3
2
-
Reserved.
AADR2
-
The ADC input select. See table in SFR ADCCON.
Reserved.
1-0
INTERRUPT ENABLE REGISTER 1
Bit:
7
6
5
4
3
-
2
-
1
-
0
-
EED
EPWMUF EPWM
EWDI
-36-
W79E8213/W79E8213R Data Sheet
Mnemonic: EIE
Address: E8h
BIT
NAME
FUNCTION
0: Disable Edge Detect Interrupt.
7
EED
1: Enable Edge Detect Interrupt.
0: Disable PWM underflow interrupt.
1: Enable PWM underflow interrupt.
6
5
EPWMUF
EPWM
0: Disable PWM Interrupt when external brake pin was brake.
1: Enable PWM Interrupt when external brake pin was brake.
0: Disable Watchdog Timer Interrupt.
1: Enable Watchdog Timer Interrupt.
4
EWDI
-
3-0
Reserved.
B REGISTER
Bit:
7
6
5
4
3
2
1
0
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
Mnemonic: B
Address: F0h
BIT
NAME
FUNCTION
7-0 B.[7:0]
The B register is the standard 8052 register that serves as a second accumulator.
PORT ADC DIGITAL INPUT DISABLE
Bit:
7
6
5
4
3
2
1
0
PADIDS.7 PADIDS.6 PADIDS.5 PADIDS.4 PADIDS.3 PADIDS.2 PADIDS.1 PADIDS.0
Mnemonic: PADIDS Address: F6h
BIT
NAME
FUNCTION
P0.7 digital input disable bit.
7
PADIDS.7
0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 7.
P0.6 digital input disable bit.
6
5
PADIDS.6
PADIDS.5
0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 3.
P0.5 digital input disable bit.
0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 2.
-37-
W79E8213/W79E8213R Data Sheet
Continued
BIT
NAME
FUNCTION
P0.4 digital input disable bit.
4
3
2
1
0
PADIDS.4
0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 1.
P0.3 digital input disable bit.
PADIDS.3
PADIDS.2
PADIDS.1
PADIDS.0
0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 0.
P0.2 digital input disable bit.
0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 4.
P0.1 digital input disable bit.
0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 5.
P0.0 digital input disable bit.
0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 6.
Note: Port 0 (ADC input pins) should also be set to Input Only (High Impedance) during when
using the port for ADC application. Please see I/O Port Configuration section.
INTERRUPT HIGH PRIORITY 1
Bit:
7
6
5
4
3
-
2
-
1
-
0
PEDH
PPWMH
PBKH
PWDIH
-
Mnemonic: IP1H
Address: F7h
BIT
7
NAME
PEDH
FUNCTION
1: To set interrupt high priority of edge detect is highest priority level.
1: To set interrupt priority of PWM underflow is highest priority level.
1: To set interrupt priority of PWM’s external brake is highest priority level.
1: To set interrupt high priority of Watchdog is highest priority level.
Reserved.
6
PPWMH
PBKH
PWDIH
-
5
4
3-0
EXTENDED INTERRUPT PRIORITY
Bit:
7
6
5
4
3
-
2
-
1
-
0
PED
PPWM
PBK
PWDI
-
Mnemonic: IP1
Address: F8h
-38-
W79E8213/W79E8213R Data Sheet
BIT
7
NAME
PED
FUNCTION
1: To set interrupt priority of Edge Detect is higher priority level.
6
1: To set interrupt priority of PWM underflow is higher priority level.
1: To set interrupt priority of PWM’s external brake is higher priority level.
1: To set interrupt priority of Watchdog is higher priority level.
Reserved.
PPWM
PBK
PWDI
-
5
4
3-0
BUZZER CONTROL REGISTER
Bit:
7
-
6
-
5
4
3
2
1
0
BUZDIV.5 BUZDIV.4 BUZDIV.3 BUZDIV.2 BUZDIV.1 BUZDIV.0
Address: F9h
Mnemonic: BUZCON
BIT
NAME
FUNCTION
7-6
Reserved.
-
Buzzer division select bits:
These bits are division selector. User may configure these bits to further divide
the cpu clock in order to generate the desired buzzer output frequency.
The following shows the equation for the buzzer output rate;
Fbuz = Fcpu x 1/[(256)x(BUZDIV + 1)]
5-0
BUZDIV
-39-
W79E8213/W79E8213R Data Sheet
9. INSTRUCTION SET
The W79E8213 series execute all the instructions of the standard 8052 family. The operations of
these instructions, as well as their effects on flag and status bits, are exactly the same. However, the
timing of these instructions is different in two ways. Firstly, the machine cycle is four clock periods,
while the standard-8051/52 machine cycle is twelve clock periods. Secondly, it can fetch only once per
machine cycle (i.e., four clocks per fetch), while the standard 8051/52 can fetch twice per machine
cycle (i.e., six clocks per fetch).
The timing differences create an advantage for the W79E8213 series. There is only one fetch per
machine cycle, so the number of machine cycles is usually equal to the number of operands in the
instruction. (Jumps and calls do require an additional cycle to calculate the new address.) As a result,
the W79E8213 series reduces the number of dummy fetches and wasted cycles, and therefore
improves overall efficiency, compared to the standard 8051/52.
W79E8213 W79E8213
W79E8213
series v.s.
8032 Speed
Ratio
8032
Clock
cycles
series
Machine
Cycle
series
Clock
cycles
Op-code
HEX Code
Bytes
NOP
00
28
29
2A
2B
2C
2D
2E
2F
26
27
25
24
38
39
3A
3B
3C
3D
3E
3F
36
37
35
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
2
4
4
4
4
4
4
4
4
4
4
4
8
8
4
4
4
4
4
4
4
4
4
4
8
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
3
ADD A, R0
3
ADD A, R1
3
ADD A, R2
3
ADD A, R3
3
ADD A, R4
3
ADD A, R5
3
ADD A, R6
3
ADD A, R7
3
ADD A, @R0
ADD A, @R1
ADD A, direct
ADD A, #data
ADDC A, R0
ADDC A, R1
ADDC A, R2
ADDC A, R3
ADDC A, R4
ADDC A, R5
ADDC A, R6
ADDC A, R7
ADDC A, @R0
ADDC A, @R1
ADDC A, direct
3
3
1.5
1.5
3
3
3
3
3
3
3
3
3
3
1.5
-40-
W79E8213/W79E8213R Data Sheet
INSTRUCTION SET, continued
W79E8213 W79E8213
W79E8213
series v.s.
8032 Speed
Ratio
8032
Clock
cycles
series
Machine
Cycle
series
Clock
cycles
Op-code
HEX Code
Bytes
ADDC A, #data
SUBB A, R0
SUBB A, R1
SUBB A, R2
SUBB A, R3
SUBB A, R4
SUBB A, R5
SUBB A, R6
SUBB A, R7
SUBB A, @R0
SUBB A, @R1
SUBB A, direct
SUBB A, #data
INC A
34
2
2
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
8
4
4
4
4
4
4
4
4
4
4
8
8
4
4
4
4
4
4
4
4
4
4
4
8
8
4
4
4
4
4
4
4
4
12
1.5
98
99
9A
9B
9C
9D
9E
9F
96
97
95
94
04
08
09
0A
0B
0C
0D
0E
0F
06
07
05
A3
14
18
19
1A
1B
1C
1D
1E
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
12
12
3
3
3
3
3
3
3
3
3
3
1.5
1.5
3
INC R0
3
INC R1
3
INC R2
3
INC R3
3
INC R4
3
INC R5
3
INC R6
3
INC R7
3
INC @R0
INC @R1
INC direct
INC DPTR
DEC A
3
3
1.5
3
3
DEC R0
3
DEC R1
3
DEC R2
3
DEC R3
3
DEC R4
3
DEC R5
3
DEC R6
3
-41-
W79E8213/W79E8213R Data Sheet
INSTRUCTION SET, continued
W79E8213 W79E8213
8032
Clock
cycles
W79E8213
series v.s 8032
Speed Ratio
series
Machine
Cycle
series
Clock
cycles
Op-code
HEX Code
Bytes
DEC R7
1F
1
1
1
1
2
2
5
5
1
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
2
2
4
4
4
8
8
12
3
DEC @R0
DEC @R1
DEC direct
DEC DPTR
MUL AB
16
17
15
A5
A4
84
D4
58
59
5A
5B
5C
5D
5E
5F
56
57
55
54
52
53
48
49
4A
4B
4C
4D
4E
4F
46
47
45
44
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
2
2
12
12
12
24
48
48
12
12
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
12
12
12
12
12
12
3
3
1.5
3
20
20
4
2.4
2.4
3
DIV AB
DA A
ANL A, R0
ANL A, R1
ANL A, R2
ANL A, R3
ANL A, R4
ANL A, R5
ANL A, R6
ANL A, R7
ANL A, @R0
ANL A, @R1
ANL A, direct
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, R0
ORL A, R1
ORL A, R2
ORL A, R3
ORL A, R4
ORL A, R5
ORL A, R6
ORL A, R7
ORL A, @R0
ORL A, @R1
ORL A, direct
ORL A, #data
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
8
1.5
1.5
1.5
2
8
8
12
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
8
1.5
1.5
8
-42-
W79E8213/W79E8213R Data Sheet
INSTRUCTION SET, continued
W79E8213 W79E8213
8032
Clock
cycles
W79E8213
series v.s 8032
Speed Ratio
series
Machine
Cycle
series
Clock
cycles
Op-code
HEX Code
Bytes
ORL direct, A
ORL direct, #data
XRL A, R0
XRL A, R1
XRL A, R2
XRL A, R3
XRL A, R4
XRL A, R5
XRL A, R6
XRL A, R7
XRL A, @R0
XRL A, @R1
XRL A, direct
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
42
2
2
3
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
8
12
1.5
2
43
68
69
6A
6B
6C
6D
6E
6F
66
67
65
64
62
63
E4
F4
23
33
03
13
C4
E8
E9
EA
EB
EC
ED
EE
EF
E6
E7
E5
3
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
12
4
4
4
4
4
4
4
4
4
4
8
8
8
12
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
24
12
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
3
3
3
3
3
3
3
3
3
3
1.5
1.5
1.5
2
3
CPL A
3
RL A
3
RLC A
3
RR A
3
RRC A
3
SWAP A
3
MOV A, R0
MOV A, R1
MOV A, R2
MOV A, R3
MOV A, R4
MOV A, R5
MOV A, R6
MOV A, R7
MOV A, @R0
MOV A, @R1
MOV A, direct
3
3
3
3
3
3
3
3
3
3
1.5
-43-
W79E8213/W79E8213R Data Sheet
INSTRUCTION SET, continued
W79E8213 W79E8213
8032
Clock
cycles
W79E8213
series v.s 8032
Speed Ratio
series
Machine
Cycle
series
Clock
cycles
Op-code
HEX Code
Bytes
MOV A, #data
MOV R0, A
74
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
2
2
2
2
2
2
8
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
8
8
8
8
8
8
8
12
1.5
3
F8
F9
FA
FB
FC
FD
FE
FF
A8
A9
AA
AB
AC
AD
AE
AF
78
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
2
2
2
2
2
2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
MOV R1, A
3
MOV R2, A
3
MOV R3, A
3
MOV R4, A
3
MOV R5, A
3
MOV R6, A
3
MOV R7, A
3
MOV R0, direct
MOV R1, direct
MOV R2, direct
MOV R3, direct
MOV R4, direct
MOV R5, direct
MOV R6, direct
MOV R7, direct
MOV R0, #data
MOV R1, #data
MOV R2, #data
MOV R3, #data
MOV R4, #data
MOV R5, #data
MOV R6, #data
MOV R7, #data
MOV @R0, A
MOV @R1, A
MOV @R0, direct
MOV @R1, direct
MOV @R0, #data
MOV @R1, #data
MOV direct, A
MOV direct, R0
MOV direct, R1
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3
79
7A
7B
7C
7D
7E
7F
F6
F7
A6
A7
76
3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
77
F5
88
89
-44-
W79E8213/W79E8213R Data Sheet
INSTRUCTION SET, continued
W79E8213 W79E8213
8032
Clock
cycles
W79E8213
series v.s 8032
Speed Ratio
series
Machine
Cycle
series
Clock
cycles
Op-code
HEX Code
Bytes
MOV direct, R2
MOV direct, R3
MOV direct, R4
MOV direct, R5
MOV direct, R6
MOV direct, R7
MOV direct, @R0
MOV direct, @R1
MOV direct, direct
MOV direct, #data
MOV DPTR, #data 16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @R0
MOVX A, @R1
MOVX A, @DPTR
MOVX @R0, A
MOVX @R1, A
MOVX @DPTR, A
PUSH direct
8A
8B
8C
8D
8E
8F
86
2
2
2
2
2
2
2
2
2
3
3
3
2
2
8
8
8
8
8
8
8
8
12
1.5
2
2
2
2
2
2
2
3
3
3
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
12
12
12
12
12
12
12
24
24
24
24
24
24
24
24
24
24
24
24
24
12
12
12
12
12
12
12
12
12
12
12
12
12
1.5
1.5
1.5
1.5
1.5
1.5
87
1.5
85
12
2
75
12
2
90
12
2
93
8
3
83
8
3
E2
E3
E0
F2
F3
F0
C0
D0
C8
C9
CA
CB
CC
CD
CE
CF
C6
C7
D6
D7
C5
2 - 9
8 - 36
3 - 0.66
2 - 9
8 - 36
3 - 0.66
2 - 9
8 - 36
3 - 0.66
2 - 9
8 - 36
3 - 0.66
2 - 9
2 - 9
2
8 - 36
3 - 0.66
8 - 36
3 - 0.66
8
8
4
4
4
4
4
4
4
4
4
4
4
4
8
3
3
POP direct
2
XCH A, R0
1
3
XCH A, R1
1
3
XCH A, R2
1
3
XCH A, R3
1
3
XCH A, R4
1
3
XCH A, R5
1
3
XCH A, R6
1
3
XCH A, R7
1
3
XCH A, @R0
1
3
XCH A, @R1
1
3
XCHD A, @R0
XCHD A, @R1
XCH A, direct
1
3
1
3
2
1.5
-45-
W79E8213/W79E8213R Data Sheet
INSTRUCTION SET, continued
W79E8213 W79E8213
8032
Clock
cycles
W79E8213
series v.s 8032
Speed Ratio
series
Machine
Cycle
series
Clock
cycles
Op-code
HEX Code
Bytes
CLR C
C3
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
1
1
2
1
2
1
2
2
2
2
2
2
2
4
8
4
8
4
8
8
6
8
6
8
8
12
3
CLR bit
2
1
2
1
2
2
2
2
2
2
2
12
12
12
12
12
24
24
24
24
12
24
1.5
3
SETB C
SETB bit
CPL C
1.5
3
CPL bit
1.5
3
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
3
3
3
1.5
3
71, 91, B1,
11, 31, 51,
D1, F1
ACALL addr11
2
3
12
24
2
LCALL addr16
RET
12
22
32
3
1
1
4
2
2
16
8
24
24
24
1.5
3
RETI
8
3
01, 21, 41,
61, 81, A1,
C1, E1
AJMP ADDR11
2
3
12
24
2
LJMP addr16
JMP @A+DPTR
SJMP rel
02
73
80
60
70
40
50
20
30
10
B5
B4
B6
B7
3
1
2
2
2
2
2
3
3
3
3
3
3
3
4
2
3
3
3
3
3
4
4
4
4
4
4
4
16
6
24
24
24
24
24
24
24
24
24
24
24
24
24
24
1.5
3
12
12
12
12
12
16
16
16
16
16
16
16
2
JZ rel
2
JNZ rel
2
JC rel
2
JNC rel
2
JB bit, rel
1.5
1.5
1.5
1.5
1.5
1.5
1.5
JNB bit, rel
JBC bit, rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE @R0, #data, rel
CJNE @R1, #data, rel
-46-
W79E8213/W79E8213R Data Sheet
INSTRUCTION SET, continued
W79E8213 W79E8213
8032
Clock
cycles
W79E8213
series v.s 8032
Speed Ratio
series
Machine
Cycle
series
Clock
cycles
Op-code
HEX Code
Bytes
CJNE R0, #data, rel
CJNE R1, #data, rel
CJNE R2, #data, rel
CJNE R3, #data, rel
CJNE R4, #data, rel
CJNE R5, #data, rel
CJNE R6, #data, rel
CJNE R7, #data, rel
DJNZ R0, rel
B8
B9
BA
BB
BC
BD
BE
BF
D8
D9
DD
DA
DB
DC
DE
DF
D5
3
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
4
16
24
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
3
16
16
16
16
16
16
16
12
12
12
12
12
12
12
12
16
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
DJNZ R1, rel
2
DJNZ R5, rel
2
DJNZ R2, rel
2
DJNZ R3, rel
2
DJNZ R4, rel
2
DJNZ R6, rel
2
DJNZ R7, rel
2
DJNZ direct, rel
1.5
Table 9-1: Instruction Set for W79E8213
-47-
W79E8213/W79E8213R Data Sheet
9.1 Instruction Timing
This section is important because some applications use software instructions to generate timing
delays. It also provides more information about timing differences between the W79E8213 series and
the standard 8051/52.
In W79E8213 series, each machine cycle is four clock periods long. Each clock period is called a
state, and each machine cycle consists of four states: C1, C2 C3 and C4, in order. Both clock edges
are used for internal timing, so the duty cycle of the clock should be as close to 50% as possible to
avoid timing conflicts.
The W79E8213 series does one op-code fetch per machine cycle, so, in most instructions, the number
of machine cycles required is equal to the number of bytes in the instruction. There are 256 available
op-codes. 128 of them are single-cycle instructions, so many op-codes are executed in just four clocks
period. Some of the other op-codes are two-cycle instructions, and most of these have two-byte op-
codes. However, there are some instructions that have one-byte instructions yet take two cycles to
execute. One important example is the MOVX instruction.
In the standard 8052, the MOVX instruction is always two machine cycles long. However, in the
W79E8213 series each machine cycle is made of only 4 clock periods compared to the 12 clock
periods for the standard 8052. Therefore, even though the number of categories has increased, each
instruction is at least 1.5 to 3 times faster than the standard 8052 in terms of clock periods.
Single Cycle
C4
C1
C2
C3
CPU CLK
ALE
PSEN
A7-0
Data_ in D7-0
AD<7:0>
Address A15-8
Address <15:0>
Figure 9-1: Single Cycle Instruction Timing
-48-
W79E8213/W79E8213R Data Sheet
Operand Fetch
Instruction Fetch
C1
C2
C3
C4
C1
C2
C3
C4
CPU CLK
ALE
PSEN
PC
OP-CODE
PC+1
OPERAND
AD<7:0>
Address A15-8
Address A15-8
Address<15:0>
Figure 9-2: Two Cycles Instruction Timing
Instruction Fetch
Operand Fetch
Operand Fetch
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
CPU CLK
ALE
PSEN
A7-0
OP-CODE
A7-0
OPERAND
A7-0
OPERAND
AD<7:0>
Address<15:0>
Address A15-8
Address A15-8
Address A15-8
Figure 9-3: Three Cycles Instruction Timing
-49-
W79E8213/W79E8213R Data Sheet
Instruction Fetch
Operand Fetch
Operand Fetch
Operand Fetch
C1
C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CPU CLK
ALE
PSEN
OP-CODE
A7-0
OPERAND
A7-0
AD<7:0>
A7-0
OPERAND
A7-0
OPERAND
Address<15:0>
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Figure 9-4: Four Cycles Instruction Timing
Operand Fetch
Instruction Fetch
Operand Fetch
Operand Fetch
Operand Fetch
C1
C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CPU CLK
ALE
PSEN
OPERAND
AD<7:0>
OP-CODE
OPERAND
OPERAND
OPERAND
A7-0
A7-0
A7-0
A7-0
A7-0
Address<15:0>
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Figure 9-5: Five Cycles Instruction Timing
-50-
W79E8213/W79E8213R Data Sheet
10. POWER MANAGEMENT
The W79E8213 series has several features that help the user to control the power consumption of the
device. These modes are discussed in the next two sections.
10.1 Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the
idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle
mode, the clock to the CPU is halted, but not to the Interrupt, Timer, PWM and Watchdog timer blocks.
This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program Status
Word, the Accumulator and the other registers hold their contents. The port pins hold the logical states
they had at the time Idle was activated. The Idle mode can be terminated in two ways. Since the
interrupt controller is still active, the activation of any enabled interrupt can wake up the processor.
This will automatically clear the Idle bit, terminate the Idle mode, and the Interrupt Service Routine
(ISR) will be executed. After the ISR, execution of the program will continue from the instruction which
put the device into Idle Mode.
The Idle mode can also be exited by activating the reset. The device can put into reset either by
applying a low on the external /RST pin, a Power on reset condition or a Watchdog timer reset. The
external reset pin has to be held low for at least two machine cycles i.e. 8 clock periods to be
recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the
SFRs are set to the reset condition. Since the clock is already running there is no delay and execution
starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out
will cause a watchdog timer interrupt which will wake up the device. The software must reset the
Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out.
When the W79E8213 series are exiting from an Idle Mode with a reset, the instruction following the
one which put the device into Idle Mode is not executed. So there is no danger of unexpected writes.
10.2 Power-down Mode
The device can be put into Power-down mode by writing 1 to bit PCON.1. The instruction that does
this will be the last instruction to be executed before the device goes into Power-down mode. In the
Power-down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. The port pins output the
values held by their respective SFRs.
The W79E8213 series will exit the Power-down mode with a reset or by an external interrupt pin
enabled as level detected. An external reset can be used to exit the Power down state. The low on
/RST pin terminates the Power-down mode, and restarts the clock. The program execution will restart
from 0000h. In the Power-down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power-down mode when its clock source is external OSC or crystal.
The sources that can wake up from the power-down mode are external interrupts, brownout reset
(BOR) and ADC. Note that for ADC waking up from powerdown, the device need to run on internal rc
and software perform start ADC prior to powerdown.
The W79E8213 series can be waken up from the Power-down mode by forcing an external interrupt
pin activation, provided the corresponding interrupt is enabled, while the global enable (EA) bit is set.
If these conditions are met, then either a low-level or a falling-edge at external interrupt pin will re-start
the oscillator. The device will then execute the interrupt service routine for the corresponding external
interrupt. After the interrupt service routine is completed, the program execution returns to the
instruction after one which put the device into Power-down mode and continues from there. During
Power-down mode, if AUXR1.LPBOV = 1 and AUXR1.BOD = 0, the internal RC clock will be enabled
and hence save power.
-51-
W79E8213/W79E8213R Data Sheet
11. RESET CONDITIONS
The user has several hardware related options for placing the W79E8213 series into reset condition.
In general, most register bits go to their reset value irrespective of the reset condition, but there are a
few flags whose state depends on the source of reset. The user can use these flags to determine the
cause of reset using software.
11.1 Sources of reset
VDD = 5.0V, Disable /RST pin
V
BO3.8 (BOR Enable)
VBO3.8
VBO3.8 (BOR Enable)
VDD Power
Internal RST
WDT Normal Run
WDT RST
WDT Stop
System Normal Run
System Status
System Stop
2 Watchdog
timer clocks
Crystal 65536 clocks
Internal RC 256 clocks
Crystal 65536 clocks
Internal RC 256 clocks
512 Watchdog
timer clocks
Figure 11-1: Reset and Vdd monitor timing diagram, disable /RST pin.
-52-
W79E8213/W79E8213R Data Sheet
VDD = 5.0V, Enable /RST pin
V
BO3.8 (BOR Enable)
VDD Power
0.7VDD
External RST Pin
0.3VDD
At least 4 clocks
System Normal Run
System Status
System within Power Down Mode
System Stop
System not in Power Down Mode
Crystal 65536 clocks
Internal RC 256 clocks
Crystal 65536 clocks
Internal RC 256 clocks
Figure 11-2: Reset and Vdd monitor timing diagram, enable /RST pin.
11.1.1 External Reset
The device samples the /RST pin every machine cycle during state C4. The /RST pin must be held
low for at least two machine cycles before the reset circuitry applies an internal reset signal. Thus, this
reset is a synchronous operation and requires the clock to be running.
The device remains in the reset state as long as /RST is low and remains low up to two machine
cycles after /RST is deactivated. Then, the device begins program execution at 0000h. There are no
flags associated with the external reset, but, since the other two reset sources do have flags, the
external reset is the cause if those flags are clear.
11.1.2 Power-On Reset (POR)
When power up, the device performs a power-on reset and sets the POR flag. The software should
clear the POR flag, or it will be difficult to determine the source of future resets. During power-on-
reset, all port pins will be tri-stated. After power-on-reset, the port pins state will determined by PRHI
value.
-53-
W79E8213/W79E8213R Data Sheet
11.1.3 Watchdog Timer Reset
The Watchdog Timer is a free-running timer with programmable time-out intervals. The program must
clear the Watchdog Timer before the time-out interval is reached to restart the count. If the time-out
interval is reached, an interrupt flag is set. 512 clocks later, if the Watchdog Reset is enabled and the
Watchdog Timer has not been cleared, the Watchdog Timer generates a reset. The reset condition is
maintained by the hardware for two machine cycles, and the WTRF bit in WDCON is set. Afterwards,
the device begins program execution at 0000h.
11.2 Reset State
When the device is reset, most registers return to their initial state. The Watchdog Timer is disabled if
the reset source was a power-on reset. The port registers are set to FFh, which puts most of the port
pins in a high state. The Program Counter is set to 0000h, and the stack pointer is reset to 07h. After
this, the device remains in the reset state as long as the reset conditions are satisfied.
Reset does not affect the on-chip RAM, however, so RAM is preserved as long as VDD remains
above approximately 2V, the minimum operating voltage for the RAM. If VDD falls below 2V, the RAM
contents are also lost. In either case, the stack pointer is always reset, so the stack contents are lost.
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset. The
WDCON SFR is set to a 0x00 0000B on the reset. WTRF (WDCON.2) is set to a 1 on a Watchdog timer
reset, but to a 0 on power on/down resets. WTRF (WDCON.2) is not altered by external reset. EWRST
(WDCON.1) is cleared by any reset. Software or any reset will clear WDIF (WDCON.3) bit.
Some of the bits in the WDCON SFR (WDRUN, WDCLR, EWRST, WDIF, WD0 and WD1) have
unrestricted read access which required Timed Access procedure to write. The remaining bits have
unrestricted write accesses. Please refer TA register description.
For all SFR reset state values, please refer to Table 8-2: Special Function Registers.
-54-
W79E8213/W79E8213R Data Sheet
12. INTERRUPTS
The W79E8213 series have four priority level interrupts structure with 10 interrupt sources. Each of
the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
12.1 Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, programmable
through bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the
external interrupts are sampled every machine cycle, they have to be held high or low for at least one
complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the
level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is
serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the
interrupt continues to be held low even after the service routine is completed, then the processor may
acknowledge another interrupt request from the same source.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware
when the timer interrupt is serviced.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-
out count is reached, the Watchdog Timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is
enabled by the enable bit EIE.4, then an interrupt will occur.
PWM interrupt is generated when its’ 10-bit down counter underflows. PWMF flag is set and PWM
interrupt is generated if enabled. PWMF is set by hardware and can only be cleared by software.
Alternatively, PWM function can also generate interrupt by BKF flag, after external brake pin has brake
occurred. This bit will be cleared by software.
The ADC can generate interrupt after finished ADC converter. There is one interrupt source, which is
obtained by the ADCI bit in the ADCCON SFR. This bit is not automatically cleared by the hardware,
and the user will have to clear this bit using software.
Edge detect interrupt is generated when any of the keypad connected to P1.0-P1.2 pins is pressed.
Each edge detect interrupt can be individually enabled/disabled. User will have to software clear the
flag bit. The ED pins have edge type and filter type control, configurable through EDIC SFR.
Brownout detect can cause brownout flag, BOF, to be asserted if power voltage drop below brownout
voltage level. Interrupt will occur if BOI (AUXR1.5), EBO (IE.5) and global interrupt enable are set.
All the bits that generate interrupts can be set or reset by software, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to
disable all interrupts.
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are;
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being execute.
3. The current instruction does not involve a write to IE, EIE, IP0, IP0H, IP1 or IPH1 registers and is
not a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt
-55-
W79E8213/W79E8213R Data Sheet
flag is active in one cycle but not responded to, and is not active when the above conditions are met,
the denied interrupt will not be serviced. This means that active interrupts are not remembered; every
polling cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate
service routine. This may or may not clear the flag which caused the interrupt. In case of Timer
interrupts, the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the
appropriate timer service routine. In case of external interrupt, INT0 and INT1, the flags are cleared
only if they are edge triggered. In case of Serial interrupts, the flags are not cleared by hardware. The
Watchdog timer interrupt flag WDIF has to be cleared by software. The hardware LCALL behaves
exactly like the software LCALL instruction. This instruction saves the Program Counter contents onto
the Stack, but does not save the Program Status Word PSW. The PC is reloaded with the vector
address of that interrupt which caused the LCALL. These address of vector for the different sources
are as following:
VECTOR LOCATIONS FOR INTERRUPT SOURCES
VECTOR
ADDRESS
VECTOR
ADDRESS
SOURCE
SOURCE
External Interrupt 0
0003h
Timer 0 Overflow
Timer 1 Overflow
Brownout Interrupt
Edge Detect Interrupt
-
000Bh
External Interrupt 1
0013h
0023h
0033h
0043h
0053h
0063h
006Bh
001Bh
002Bh
003Bh
004Bh
005Bh
0073h
007Bh
-
-
-
Watchdog Timer
ADC Interrupt
PWM Brake Interrupt
-
-
PWM Underflow Interrupt
Table 12-1: Vector locations for interrupt sources
Execution continues from the vectored address till an RETI instruction is executed. On execution of
the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the
stack. The user must take care that the status of the stack is restored to what it was after the hardware
LCALL, if the execution is return to the interrupted program. The processor does not notice anything if
the stack contents are modified and will proceed with execution from the address put back into PC.
Note that a RET instruction would perform exactly the same process as a RETI instruction, but it
would not inform the Interrupt Controller that the interrupt service routine is completed, and would
leave the controller still thinking that the service routine is underway.
-56-
W79E8213/W79E8213R Data Sheet
12.2 Priority Level Structure
The W79E8213 series uses a four priority level interrupt structure (highest, high, low and lowest) and
supports up to 10 interrupt sources. The interrupt sources can be individually set to either high or low
levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. However
there exists a pre-defined hierarchy amongst the interrupts themselves. This hierarchy comes into play
when the interrupt controller has to resolve simultaneous requests having the same priority level. This
hierarchy is defined as table below. This allows great flexibility in controlling and handling many
interrupt sources.
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPXH
IPX
0
0
0
1
1
Level 0 (lowest priority)
Level 1
1
0
Level 2
1
Level 3 (highest priority)
Table 12-2: Four-level interrupt priority
Each interrupt source can be individually programmed to one of four priority levels by setting or
clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service routine in progress can be
interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The
highest priority interrupt service cannot be interrupted by any other interrupt source. So, if two
requests of different priority levels are received simultaneously, the request of higher priority level is
serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. This is called the arbitration ranking. Note that the arbitration
ranking is only used to resolve simultaneous requests of the same priority level.
As below Table summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,
arbitration ranking, and whether each interrupt may wake up the CPU from Power-down mode.
Power-
Down
Wakeup
Vector
Interrupt
Interrupt
Priority
Arbitration
Ranking
Flag
cleared by
Source
Flag
address
Enable Bits
Hardware,
Follow the
inverse of pin
External
Interrupt 0
IE0
0003H
002BH
EX0 (IE0.0)
IP0H.0, IP0.0
1(highest)
Yes
Brownout
Detect
BOF
EBO (IE.5)
IP0H.5, IP0.5
2
3
4
Yes
No
Software
EWDI (EIE.4) IP1H.4, IP1.4
Software
Watchdog Timer WDIF 0053H
Hardware,
software
Timer 0
Interrupt
TF0
000BH
ET0 (IE.1)
IP0H.1, IP0.1
No
-57-
W79E8213/W79E8213R Data Sheet
Continued
Power-
Down
Wakeup
Vector
Interrupt
Interrupt
Priority
Arbitration
Ranking
Flag
cleared by
Source
Flag
address
Enable Bits
ADC Converter ADCI 005BH
EAD (IE.6)
EX1 (IE.2)
IP0H.6, IP0.6
IP0H.2, IP0.2
5
6
Yes(1)
Hardware
Hardware,
Follow the
inverse of pin
External
IE1
0013H
Yes
Interrupt 1
Edge Detect
Interrupt
EDF
TF1
003BH
001BH
EED (EIE.7)
ET1 (IE.3)
IP1H.7, IP1.7
IP0H.3, IP0.3
IP1H.6, IP1.6
7
No
No
No
No
Software
Hardware,
software
Timer 1
Interrupt
8
PWM Period
Interrupt
EPWMUF
(EIE.6)
PWMF 006BH
BKF 0073H
9
Software
Software
PWM Brake
Interrupt
EPWM (EIE.5) IP1H.5, IP1.5
10 (lowest)
Note: 1. ADC Converter can wake up Power-down Mode when its clock source is from internal RC.
Table 12-3: Vector location for Interrupt sources and power-down wakeup
12.3 Response Time
The response time for each interrupt source depends on several factors, such as the nature of the
interrupt and the instruction underway. In the case of external interrupts INT0 and INT1 , they are
sampled at C3 of every machine cycle and then their corresponding interrupt flags IEx will be set or
reset. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has
occurred. These flag values are polled only in the next machine cycle. If a request is active and all
three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes
four machine cycles to be completed. Thus there is a minimum time of five machine cycles between
the interrupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the
instruction being executed, then an additional delay is introduced. The maximum response time (if no
other interrupt is in service) occurs if the W79E8213 series are performing a write to IE, EIE, IP0,
IP0H, IP1 or IP1H and then executes a MUL or DIV instruction. From the time an interrupt source is
activated, the longest reaction time is 12 machine cycles. This includes 1 machine cycle to detect the
interrupt, 2 machine cycles to complete the IE, EIE, IP0, IP0H, IP1 or IP1H access, 5 machine cycles
to complete the MUL or DIV instruction and 4 machine cycles to complete the hardware LCALL to the
interrupt vector location.
Thus in a single-interrupt system the interrupt response time will always be more than 5 machine
cycles and not more than 12 machine cycles. The maximum latency of 12 machine cycles is 48 clock
cycles. Note that in the standard 8051 the maximum latency is 8 machine cycles which equals 96
machine cycles. This is a 50% reduction in terms of clock periods.
12.4 Interrupt Inputs
The W79E8213 series have total 10 interrupt sources with two individual interrupt inputs sources.
-58-
W79E8213/W79E8213R Data Sheet
They are IE0, IE1, BOF, EDF, WDT, TF0, TF1, BKF and ADC. Two interrupt inputs are identical to
those present on the standard 80C51 microcontroller as show in below figures.
If an external interrupt is enabled when the W79E8213 series are put into Power-down or Idle mode,
the interrupt will cause the processor to wake up and resume operation.
IE0
EX0
IE1
EX1
BOF
EBO
Wakeup
(If in Power Down)
ADCI
EADC
EA
Interrupt
To CPU
Figure 12-1: Interrupt sources that can wake up from power-down mode
TF0
ET0
TF1
ET1
PWMF
Interrupt
To CPU
EPWMUF
EA
BKF
EPWM
EDF
EED
WDT
EWDI
Figure 12-2: Interrupt Sources that cannot wake up from power-down mode
-59-
W79E8213/W79E8213R Data Sheet
13. PROGRAMMABLE TIMERS/COUNTERS
The W79E8213 series have two 16-bit programmable timer/counters and one programmable
Watchdog Timer. The Watchdog Timer is operationally quite different from the other two timers. Its’
timer/counters have additional timer 0 or timer 1 overflow toggle output enable feature as compare to
conventional timer/counters. This timer overflow toggle output can be configured to automatically
toggle T0 or T1 pin output whenever a timer overflow occurs.
13.1 Timer/Counters 0 & 1
The W79E8213 series have two 16-bit Timer/Counters. Each of these Timer/Counters has two 8 bit
registers which form the 16 bit counting register. For Timer/Counter 0 they are TH0, the upper 8 bits
register, and TL0, the lower 8 bit register. Similarly Timer/Counter 1 has two 8 bit registers, TH1 and
TL1. The two can be configured to operate either as timers, counting machine cycles or as counters
counting external inputs.
When configured as a "Timer", the timer counts clock cycles. The timer clock can be programmed to
be thought of as 1/12 of the system clock or 1/4 of the system clock. In the "Counter" mode, the
register is incremented on the falling edge of the external input pin, T0 for Timer 0, and T1 for Timer 1.
The T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high in one
machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the
count register is incremented. Since it takes two machine cycles to recognize a negative transition on
the pin, the maximum rate at which counting will take place is 1/8 of the master clock frequency. In
either the "Timer" or "Counter" mode, the count register will be updated at C3. Therefore, in the
"Timer" mode, the recognized negative transition on pin T0 and T1 can cause the count register value
to be updated only in the machine cycle following the one in which the negative edge was detected.
The "Timer" or "Counter" function is selected by the " C/T " bit in the TMOD Special Function Register.
Each Timer/Counter has one selection bit for its own; bit 2 of TMOD selects the function for
Timer/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each
Timer/Counter can be set to operate in any one of four possible modes. The mode selection is done
by bits M0 and M1 in the TMOD SFR.
13.1.1 Time-Base Selection
The W79E8213 series can operate like the standard 8051/52 family, counting at the rate of 1/12 of the
clock speed, or in turbo mode, counting at the rate of 1/4 clock speed. The speed is controlled by the
T0M and T1M bits in CKCON, and the default value is zero, which uses the standard 8051/52 speed.
13.1.2 Mode 0
In Mode 0, the timer/counter is a 13-bit counter. The 13-bit counter consists of THx (8 MSB) and the
five lower bits of TLx (5 LSB). The upper three bits of TLx are ignored. The timer/counter is enabled
when TRx is set and either GATE is 0 or INTx is 1. When C/T is 0, the timer/counter counts clock
cycles; when C/T is 1, it counts falling edges on T0 (P1.2 for Timer 0) or T1 (P0.7 for Timer 1). For
clock cycles, the time base may be 1/12 or 1/4 clock speed, and the falling edge of the clock
increments the counter. When the 13-bit value moves from 1FFFh to 0000h, the timer overflow flag
TFx is set, and an interrupt occurs if enabled. This is illustrated in next figure below.
In “Timer” mode, if output toggled enable bit of P2M1.T0OE or P2M1.T1OE is enable, T0 or T1 output
pin will toggle whenever a timer overflow occurs.
-60-
W79E8213/W79E8213R Data Sheet
T0M=CKCON.3
(T1M=CKCON.4)
1/4
1
C/T=TMOD.2
(C/T=TMOD.6)
0
TL0
Fcpu
(TL1)
0
1/12
0
0
4
7
7
1
T0=P1.2
TF0
T1=(P0.7)
(TF1)
TR0=TCON.4
Interrupt
TFx
TR1=TCON.6
GATE=TMOD.3
(GATE=TMOD.7)
TH0
(TH1)
P1.2
INT0=P1.3
(P0.7)
(INT1=P1.4)
T0OE
(T1OE)
Figure 13-1: Timer/Counters 0 & 1 in Mode 0
13.1.3 Mode 1
Mode 1 is similar to Mode 0 except that the counting register forms a 16-bit counter, rather than a 13-
bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer
moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if
enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in
Mode 0. The gate function operates similarly to that in Mode 0.
T0M=CKCON.3
(T1M=CKCON.4)
1/4
1
0
C/T=TMOD.2
(C/T=TMOD.6)
0
TL0
Fcpu
(TL1)
1/12
0
0
4
7
7
1
T0=P1.2
TF0
T1=(P0.7)
(TF1)
TR0=TCON.4
Interrupt
TFx
TR1=TCON.6
GATE=TMOD.3
(GATE=TMOD.7)
TH0
(TH1)
P1.2
INT0=P1.3
(P0.7)
(INT1=P1.4)
T0OE
(T1OE)
Figure 13-2: Timer/Counters 0 & 1 in Mode 1
-61-
W79E8213/W79E8213R Data Sheet
13.1.4 Mode 2
In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as 8-bit count register,
while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx bit in
TCON is set and TLx is reloaded with the contents of THx, and the counting process continues from
here. The reload operation leaves the contents of the THx register unchanged. Counting is enabled by
the TRx bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1 mode 2
allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin Tn.
In “Timer” mode, if output toggled enable bit of P2M1.T0OE or P2M1.T1OE is enable, T0 or T1 output
pin will toggle whenever a timer overflow occurs.
T0M=CKCON.3
(T1M=CKCON.4)
1/4
1
0
C/T=TMOD.2
(C/T=TMOD.6)
0
TL0
Fcpu
TF0
(TL1)
(TF1)
1/12
0
0
7
7
Interrupt
TFx
1
T0=P1.2
T1=(P0.7)
TR0=TCON.4
TR1=TCON.6
GATE=TMOD.3
(GATE=TMOD.7)
P1.2
(P0.7)
TH0
INT0=P1.3
T0OE
(TH1)
(INT1=P1.4)
(T1OE)
Figure 13-3: Timer/Counter 0 & 1 in Mode 2
13.1.5 Mode 3
Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3 simply
freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count
registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer/Counter 0
control bits C/T , GATE, TR0, INT0 and TF0. The TL0 can be used to count clock cycles (clock/12 or
clock/4) or 1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle
counter (clock/12 or clock/4) and takes over the use of TR1 and TF1 from Timer/Counter 1. Mode 3 is
used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still be used
in Modes 0, 1 and 2, but its flexibility is somewhat limited. While its basic functionality is maintained, it
no longer has control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a
timer/counter and retains the use of GATE and INT1 pin. In this condition it can be turned on and off
by switching it out of and into its own Mode 3. It can also be used as a baud rate generator for the
serial port.
In “Timer” mode, if output toggled enable bit of P2M1.T0OE or P2M1.T1OE is enable, T0 or T1 output
pin will toggle whenever a timer overflow occurs.
-62-
W79E8213/W79E8213R Data Sheet
T0M=CKCON.3
(T1M=CKCON.4)
1
1/4
C/T=TMOD.2
Fcpu
0
0
TL0
1/12
0
7
Interrupt
T0OE
TF0
TF1
1
T0=P1.2
TR0=TCON.4
GATE=TMOD.3
INT0=P1.3
P1.2
TH0
0
7
Interrupt
T1OE
TR1=TCON.6
P0.7
Figure 13-4: Timer/Counter Mode 3
-63-
W79E8213/W79E8213R Data Sheet
14. NVM MEMORY
The W79E8213 series have NVM data memory of 128 bytes for customer’s data store used. The NVM
data memory has 8 pages area and each page of 16 bytes.
The NVM memory can be read/write by customer program to access. Read NVM data is by MOVC
A,@A+DPTR instruction, and write data is by SFR of NVMADDRL, NVMDATA and NVMCON. Before
write data to NVM memory, the page must be erased by providing page address on NVMADDRL,
which address of On-Chip Code Memory space will decode, then set EER of NVMCON.7. This will
automatically hold fetch program code and PC Counter, and execute page erase. After finished, this
bit will be cleared by hardware. The erase time is ~ 5ms.
For writing data to NVM memory, user must set address and data to NVMADDRL and NVMDATA,
then set EWR of NVMCON.6 to initiate nvm data write. The uC will hold program code and PC
Counter, and then write data to mapping address. Upon write completion, the EWR bit will be cleared
by hardware, the uC will continue execute next instruction. The program time is ~50us.
FFFFH
(128B NVM, 16bytes/page)
FFFFH
FC7Fh
Page 7
Page 6
Page 5
Page 4
Page 3
Page 2
Page 1
Page 0
CONFIG 1
CONFIG 0
Unused
Code Memory
FC70h
FC6Fh
FC60h
FC5Fh
FC50h
FC4Fh
FC7FH
(16 bytes/page)
128B
NVM
Data Memory
FC40h
FC3Fh
FC00H
FC30h
FC2Fh
Unused
Data Memory
FC20h
FC1Fh
Unused
Code Memory
FC10h
FC0Fh
FC00h
1000H
0FFFH
NVM Data Memory Area
4K Bytes
On-Chip
Code Memory
0000H
0000H
On-Chip Code Memory Space
External Data Memory Space
Figure 14-1: W79E8213 Memory Map
-64-
W79E8213/W79E8213R Data Sheet
15. WATCHDOG TIMER
The Watchdog Timer is a free-running Timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be caused if
it is enabled. The interrupt will occur if the individual interrupt enable and the global enable are set.
The interrupt and reset functions are independent of each other and may be used separately or
together depending on the user’s software.
Time-Out
26-bits Counter
(WDCON.3)
WDIF
Selector
00
01
10
11
0
16
19
22
25
Interrupt
17
20
23
Fcpu
EWDI
(EIE.4)
MUX
(WDCON.2)
WTRF
WDRUN
(WDCON.7)
512 clock
delay
Reset
WDCLR
(Reset Watchdog)
(WDCON.0)
WD1,WD0
(WDCON.5/4)
EWRST
(WDCON.1)
Figure 15-1: Watchdog Timer
The Watchdog Timer should first be restarted by using WDCLR. This ensures that the timer starts
from a known state. The WDCLR bit is used to restart the Watchdog Timer. This bit is self clearing, i.e.
after writing a 1 to this bit the software will automatically clear it. The Watchdog Timer will now count
clock cycles. The time-out interval is selected by the two bits WD1 and WD0 (WDCON.5 and
WDCON.4). When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set.
After the time-out has occurred, the Watchdog Timer waits for an additional 512 clock cycles. If the
Watchdog Reset EWRST (WDCON.1) is enabled, then 512 clocks after the time-out, if there is no
WDCLR, a system reset due to Watchdog Timer will occur. This will last for two machine cycles, and
the Watchdog Timer reset flag WTRF (WDCON.2) will be set. This indicates to the software that the
Watchdog was the cause of the reset.
When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the
WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a
time-out and the WDCLR allows software to restart the timer. The Watchdog Timer can also be used
as a very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an
interrupt will occur if the global interrupt enable EA is set.
The main use of the Watchdog Timer is as a system monitor. This is important in real-time control
applications. In case of some power glitches or electro-magnetic interference, the processor may
begin to execute errant code. If this is left unchecked the entire system may crash. Using the
watchdog timer interrupt during software development will allow the user to select ideal watchdog
reset locations. The code is first written without the watchdog interrupt or reset. Then the Watchdog
interrupt is enabled to identify code locations where interrupt occurs. The user can now insert
instructions to reset the Watchdog Timer, which will allow the code to run without any Watchdog Timer
interrupts. Now the Watchdog Timer reset is enabled and the Watchdog interrupt may be disabled. If
any errant code is executed now, then the reset Watchdog Timer instructions will not be executed at
the required instants and Watchdog reset will occur.
The Watchdog Timer time-out selection will result in different time-out values depending on the clock
-65-
W79E8213/W79E8213R Data Sheet
speed. The reset, when enabled, will occur when 512 clocks after time-out has occurred.
RESET
INTERRUPT
TIME-OUT
NUMBER OF
CLOCKS
TIME
@ 10 MHZ
WD1
WD0
TIME-OUT
0
0
1
1
0
1
0
1
217
217 + 512
131072
13.11 mS
220
223
226
220 + 512
223 + 512
226 + 512
1048576
8388608
67108864
104.86 mS
838.86 mS
6710.89 mS
Table 15-1: Time-out values for the Watchdog Timer
The Watchdog Timer will be disabled by a power-on/fail reset. The Watchdog Timer reset does not
disable the Watchdog Timer, but will restart it. In general, software should restart the timer to put it into
a known state. The control bits that support the Watchdog Timer are discussed below.
15.1 WATCHDOG CONTROL
WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the
Watchdog Timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur (if the global
interrupt enable is set and other interrupt requirements are met). Software or any reset can clear this
bit.
WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.
This bit is useful for determined the cause of a reset. Software must read it, and clear it manually. A
Power-fail reset will clear this bit. If EWRST = 0, then this bit will not be affected by the Watchdog
Timer.
EWRST: WDCON.1 - Enable Watchdog Timer Reset. This bit when set to 1 will enable the Watchdog
Timer reset function. Setting this bit to 0 will disable the Watchdog Timer reset function, but will leave
the timer running.
WDCLR: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog Timer and to
restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will automatically
clear it. If the Watchdog Timer reset is enabled, then the WDCLR has to be set by the user within 512
clocks of the time-out. If this is not done then a Watchdog Timer reset will occur.
15.2 CLOCK CONTROL of Watchdog
WD1, WD0: WDCON.5, WDCON.4 - Watchdog Timer Mode select bits. These two bits select the
time-out interval for the watchdog timer. The reset time is 512 clocks longer than the interrupt time-out
value.
The default Watchdog time-out is 217 clocks, which is the shortest time-out period. The WDRUN, WD0,
WD1, EWRST, WDIF and WDCLR bits are protected by the Timed Access procedure. This prevents
software from accidentally enabling or disabling the watchdog timer. More importantly, it makes it
highly improbable that errant code can enable or disable the Watchdog Timer.
-66-
W79E8213/W79E8213R Data Sheet
16. TIME ACCESS PROCTECTION
The W79E8213 series have a new feature, like the Watchdog Timer which is a crucial to proper
operation of the system. If left unprotected, errant code may write to the Watchdog control bits
resulting in incorrect operation and loss of control. In order to prevent this, the W79E8213 series have
a protection scheme which controls the write access to critical bits. This protection scheme is done
using a timed access.
In this method, the bits which are to be protected have a timed write enable window. A write is
successful only if this window is active, otherwise the write will be discarded. This write enable window
is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window
automatically closes. The window is opened by writing AAh and immediately 55h to the Timed Access
(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed access
window is
TA
REG
MOV
MOV
0C7h
; Define new register TA, @0C7h
TA, #0AAh
TA, #055h
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine
cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the
first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles,
during which the user may write to the protected bits. Once the window closes the procedure must be
repeated to access the other protected bits.
Examples of Timed Assessing are shown below.
Example 1: Valid access
MOV
TA, #0AAh
; 3 M/C Note: M/C = Machine Cycles
MOV
TA, #055h
; 3 M/C
; 3 M/C
MOV
WDCON, #00h
Example 2: Valid access
MOV
TA, #0AAh
TA, #055h
; 3 M/C
; 3 M/C
; 1 M/C
; 2 M/C
MOV
NOP
SETB
EWRST
Example 3: Valid access
MOV
MOV
ORL
TA, #0AAh
; 3 M/C
; 3 M/C
; 3M/C
TA, #055h
WDCON, #00000010B
Example 4: Invalid access
MOV
MOV
NOP
NOP
CLR
TA, #0AAh
; 3 M/C
; 3 M/C
; 1 M/C
; 1 M/C
; 2 M/C
TA, #055h
EWT
-67-
W79E8213/W79E8213R Data Sheet
Example 5: Invalid Access
MOV
NOP
MOV
SETB
TA, #0AAh
; 3 M/C
; 1 M/C
; 3 M/C
; 2 M/C
TA, #055h
EWT
In the first three examples, the writing to the protected bits is done before the 3 machine cycles
window closes. In Example 4, however, the writing to the protected bit occurs after the window has
closed, and so there is effectively no change in the status of the protected bit. In Example 5, the
second write to TA occurs 4 machine cycles after the first write, therefore the timed access window is
not opened at all, and the write to the protected bit fails.
-68-
W79E8213/W79E8213R Data Sheet
17. EDGE DETECT INTERRUPT
The W79E8213 series are provided edge detect interrupt function to detect keypad status which key is
acted, and allow a single interrupt to be generated when any key is pressed on a keyboard or keypad
connected to specific pins of the W79E8213 series, as shown below Figure. This interrupt may be
used to wake up the CPU from Idle, after chip is in Idle Mode.
Edge detect function is supported through Port 1.0-1.2. It can allow any or all pins of P1.0-P1.2 to be
enabled to cause this interrupt. Port pins are enabled by the setting of bits of ED0EN ~ ED2EN in the
EDIC register, as shown below Figure.
The edge detect trigger option is programmable through EDxTRG bits (EDIC). It supports falling
edge, and either falling edge or rising edge triggers. It also has a global digital noise filter type control
which can filter noisy edge detect inputs. The trigger pulse must be over 1 machine cycle (for Clk =
Fosc filter type), 2 machine cycles (for Clk = Fosc/2 filter type), 4 machine cycles (for Fosc/4 filter type)
and 8 machine cycles (for Fosc/8 filter type).
The Edge Detect Interrupt Flag (EDF) in the AUXR1 register is set when any enabled pin is triggered
while the ED interrupt function is active. An interrupt will be generated if it has been enabled. The EDF
bit set by hardware and must be cleared by software. Due to human time scales and the mechanical
delay associated with key-switch closures, the edge detect feature will typically allow the interrupt
service routine to poll P1.0-P1.2 in order to determine which key was pressed.
Note:
As this device support falling and rising edge triggers, user has to ensure the Edge
Detection pins at high initial state when using edge detection. This is necessary to avoid
false detection. It applies to both trigger types.
EDFILT.1-0
[0]
Noise Filter
P1.2 (ED2)
Fosc/1,2,4,8
[1]
ED2TRG
ED2EN
[0]
EDF (Edge Detect
Interrupt)
Noise Filter
P1.1 (ED1)
ED1TRG
Fosc/1,2,4,8
[1]
ED1EN
ED0EN
EED
(From EIE Register)
[0]
[1]
Noise Filter
P1.0 (ED0)
ED0TRG
Fosc/1,2,4,8
Figure 17-1: Edge Detect Interrupt
-69-
W79E8213/W79E8213R Data Sheet
SET
Tx filtered
J
Q
Q
SET
CLR
SET
CLR
SET
CLR
SET
CLR
D
Q
Q
Tx
D
Q
Q
D
Q
Q
D
Q
Q
K
CLR
Divider
/1,/2,/4,/8
Clk
2
EDFILT.1-0
Figure 17-2: Edge Detect Noise Filter
-70-
W79E8213/W79E8213R Data Sheet
18. I/O PORT CONFIGURATION
The W79E8213 series have three I/O ports, port 0, port 1 and port 2. All pins of I/O ports can be
configured to one of four types by software except P1.5 is only input pin. When P1.5 is configured
reset pin by RPD=0 in the CONFIG 1 register, the W79E8213 series can support 17 I/O pins by use
Crystal. If used internal RC oscillator the P1.5 is configured input pin, the W79E8213 series can be
supported up to 18 I/O pins. The I/O ports configuration setting as below table.
PXM1.Y
PXM2.Y
PORT INPUT/OUTPUT MODE
Quasi-bidirectional
Push-Pull
0
0
0
1
Input Only (High Impedance)
P2M1.PxS=0, TTL input
1
1
0
P2M1.PxS=1, Schmitt input
1
Open Drain
Table 18-1: I/O port Configuration Table
All port pins can be determined to high or low after reset by configure PRHI bit in the CONFIG0
register. During power-on-reset, all port pins will be tri-stated. After reset, these pins are in quasi-
bidirectional mode. The port pin of P1.5 only is a Schmitt trigger input.
Enabled toggle outputs from Timer 0 and Timer 1 by T0OE and T1OE on P2M1 register, the output
frequency of Timer 0 or Timer 1 is by Timer overflow.
Each I/O port of the W79E8213 series may be selected to use TTL level inputs or Schmitt inputs by
P(n)S bit on P2M1 register, where n is 0, 1 or 2. When P(n)S is set to 1, Ports are selected Schmitt
trigger inputs on Port(n). The P2.0 (XTAL2) can be configured clock output when used internal RC or
external Oscillator is clock source, and the frequency of clock output is divided by 4 on internal RC
clock or external Oscillator.
Note: During power-on-reset, all port pins will be tri-stated. However, PWM pins will be tr-
stated longer until cpu clock is stable.
18.1 Quasi-Bidirectional Output Configuration
After chip was power on or reset, the all ports output are this mode, and output is common with the
8051. This mode can be used as both an input and output without the need to reconfigure the port.
When the pin is pulled low, it is driven strongly and able to sink a fairly large current. These features
are somewhat similar to an open drain output except that there are three pull-up transistors in the
quasi-bidirectional output that serve different purposes.
This mode has three pull-up resisters that are “strong” pull-up, “weak” pull-up and “very weak” pull-up.
The “strong” pull-up is used fast transition from logic “0” change to logic “1”, and it is fast latch and
transition. When port pins is occur from logic “0” to logic “1”, the strong pull-up will quickly turn on two
CPU clocks to pull high then turn off.
The “weak” pull-up is turned on when the input port pin is logic “1” level or itself is logic “1”, and it
-71-
W79E8213/W79E8213R Data Sheet
provides the most source current for a quasi-bidirectional pin that output is “1” or port latch is logic “0”’.
The “very weak” pull-up is turned on when the port latch is logic “1”. If port latch is logic “0”, it will be
turned off. The very weak pull-up is support a very small current that will pull the pin high if it is left
floating. And the quasi-bidirectional port configuration is shown as below figure.
If port pin is low, it can drives large sink current for output, and it is similar with push-pull and open
drain on sink current output.
VDD
2 CPU
Clock Delay
Very
Weak
P
N
P
P
Strong
Weak
Port Pin
Port Latch
Data
Input Data
Figure 18-1: Quasi-Bidirectional Output
18.2 Open Drain Output Configuration
To configure this mode is turned off all pull-ups. If used similar as a logic output, the port must has an
external pull-up resister. The open drain port configuration is shown as below.
Port Pin
Port Latch
Data
N
Input Data
Figure 18-2: Open Drain Output
18.3 Push-Pull Output Configuration
The push-pull output mode has two strong pull-up and pull-down structure that support large source
and sink current output. It removes “weak” pull-up and “very weak” pull-up resister and remains
“strong pull-up resister on quasi-bidirectional output mode. The “strong” pull-up is always turns on
when port latch is logic “1” to support source current. The push-pull port configuration is shown in
below Figure.
-72-
W79E8213/W79E8213R Data Sheet
VDD
P
Port Pin
Port Latch
Data
N
Input Data
Figure 18-3: Push-Pull Output
18.4 Input Only Configuration
By configure this mode, the ports are only digital input and disable digital output. The W79E8213
series can select input pin to Schmitt trigger or TTL level input by PxM1.y and PxM2.y registers.
-73-
W79E8213/W79E8213R Data Sheet
19. OSCILLATOR
The W79E8213 series provides three oscillator input option. These are configured at CONFIG register
(CONFIG0) that include Internal RC Oscillator Option, External Clock Input Option and Crystal
Oscillator Input Option. The Crystal Oscillator Input frequency may be supported from 4MHz to
20MHz, and without capacitor or resister.
Crystal Oscillator
Internal RC Oscillator
External Clock input
00B
01B
11B
16 bits Ripple
Counter
CPU Clock
FOSC1 FOSC0
Peripheral
Clock
To ADC Block
Power Monitor Reset
Power Down
Figure 19-1: Oscillator
19.1 Internal RC Oscillator Option
The internal RC Oscillator is configurable to 10MHz/20MHz (through CONFIG1.FS1 bit) frequency to
support clock source. When FOSC1, FOSC0 = 01b, the internal RC oscillator is enabled. A clock
output on P2.0 (XTAL2) may be enabled when internal RC oscillator is used.
19.2 External Clock Input Option
The clock source pin (XTAL1) is from External Clock Input by FOSC1, FOSC0 = 11b, and frequency
range is form 4MHz up to 20MHz. A clock output on P2.0 (XTAL2) may be enabled when External
Clock Input is used.
The W79E8213 series supports a clock output function when either the internal RC oscillator or the
external clock input options is selected. This allows external devices to synchronize to the W79E8213
serial. When enabled, via the ENCLK bit in the P2M1 register, the clock output appears on the
XTAL2/CLKOUT pin whenever the internal RC oscillator is running, including in Idle Mode. The
frequency of the clock output is 1/4 of the CPU clock rate. If the clock output is not needed in Idle
Mode, it may be turned off prior to entering Idle mode, saving additional power. The clock output may
also be enabled when the external clock input option is selected.
-74-
W79E8213/W79E8213R Data Sheet
20. BUZZER OUTPUT
The W79E8213 series support square wave output capability. The square wave is output through P1.0
(BUZ) pin. The square wave can be enabled through bit BUZE (SFR AUXR1.1). Depending on Fcpu
clock input to the buzzer output block, user is able to control the output frequency by configure the 6-
bit Divider through BUZDIV bits in BUZCON SFR. The following shows the block diagram of square
wave output generator.
P1.0
BUZ pin
(P1.0)
Fcpu clock
1
0
1/256
6-bit Divider
Buz Output
6
1
BUZDIV.5-0
BUZE, buzzer enable bit
BUZE
Figure 20-1: Square wave output
Buzzer output frequency equation:
Fbuz = Fcpu x 1/[256x(BUZDIV+1)]
The following table tabulates examples of the BUZDIV setting needed in order to generate buzzer
output at rate of 1953Hz and 3906Hz, for each cpu clock frequency.
-75-
W79E8213/W79E8213R Data Sheet
Frequency, Fcpu (Hz)
Division
/256
1
4000000
15625
6000000
23437.5
8000000 10000000 11000000
31250 39062.5 42968.75
12000000 20000000
46875
78125
.
4
3906.25
5
6
3906.25
7
8
1953.125
3906.25
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
.
3906.25
3906.25
1953.125
3906.25
1953.125
1953.125
3906.25
1953.125
1953.125
40
.
1953.125
64
-76-
W79E8213/W79E8213R Data Sheet
For supporting active low buzzer, this buzzer output is implemented with an off-state of high. The
following pseudo code shows the operating procedure when working with active high and low buzzer;
(Assume PRHI=1):
1) During power on, P1.0/BUZ will be high;
<For active high buzzer>
Clear SFR P1.0
; user has to take care to output this pin low
; at the top of s/w code to avoid initial beep sound.
<For active low buzzer>
No action needed.
2) To turn-on buzzer;
<For active high buzzer>
Set BUZE bit
Set SFR P1.0 bit
<For active low buzzer>
Set BUZE bit
; to push out the buzout.
3) To turn-off buzzer;
<For active high buzzer>
Clear SFR P1.0
; user has to take care to output this pin low.
Clear BUZE bit
<For active low buzzer>
Set BUZE bit
-77-
W79E8213/W79E8213R Data Sheet
21. POWER MONITORING FUNCTION
Power-On Detect and Brownout are two additional power monitoring functions implemented in
W79E8213 series to prevent incorrect operation during power up and power drop or loss.
21.1 Power On Detect
The Power–On Detect function is a designed to detect power up after power voltage reaches to a level
where Brownout Detect can work. After power on detect, the POR (PCON.4) will be set to “1” to
indicate an initial power up condition. The POR flag will be cleared by software.
21.2 Brownout Detect
The Brownout Detect function is detect power voltage is drops to brownout voltage level, and allows
preventing some process work or indicate power warming. The W79E8213 series have two brownout
voltage levels to select by BOV (CONFIG0.4). If BOV =0 that brownout voltage level is 3.8V, If BOV =
1 that brownout voltage level is 2.5V. When the Brownout voltage is drop to select level, the brownout
detector will detect and keeps this active until VDD is returns to above brownout Detect voltage. The
Brownout Detect block is as follow.
To Reset
0
1
Brownout
Detect
Circuit
BOF
To Brownout interrupt
BOD
(Enable Brownout Detect)
BOI
Figure 21-1: Brownout Detect Block
When Brownout Detect is enabled by BOD (AUXR1.6), the BOF (PCON.5) flag will be set and
brownout reset will occur. If BOI (AUXR1.5) is set to “1”, the brownout detect will cause interrupt via
the EA (IE.7) and EBO (IE.5) bits is set. BOF is cleared by software.
In order to guarantee a correct detection of Brownout, The VDD fail time must be slower than
50mV/us, and rise time is slower than 2mV/us to ensure a proper reset.
-78-
W79E8213/W79E8213R Data Sheet
22. PULSE-WIDTH-MODULATED (PWM) OUTPUTS
The W79E8213 series have 4 Pulse Width Modulated (PWM) channels, and the PWM outputs are
PWM0(P0.1), PWM1(P1.6), PWM2(P1.7), PWM3(P0.0). The initial PWM outputs level
correspondingly depend on the PRHI level set prior to the chip reset. When PRHI set to high, PWM
output will initialize to high after chip reset; if PRHI set to low, PWM output will be initialize to low after
chip reset.
The W79E8213 series support 10-bits down counter with cpu clock as its input. The PWM counter
clock, has the frequency as FCPWM = FOSC/Prescaler. The two pre-scaler selectable bits FP[1:0] are
located at PWMCON3[3:2].
When the counter reaches underflow it will automatic reloaded from counter register. The PWM
frequency is given by: fPWM = FCPWM / (PWMP+1), where PWMP is 10-bits register of PWMPH.1,
PWMPH.0 and PWMPL.7~PWMPL.0.
The counter register will be loaded with the PWMP register value when PWMRUN, load and PWMF
are equal to 1; the load bit will be automatically cleared to zero on the next clock cycle, and at the
same time the counter register value will be loaded to the 10 bits down counter. PWMF flag is set
when 10-bits down counter underflow, the PWMF flag can only be cleared by software.
The pulse width of each PWM output is determined by the Compare registers of PWM0L through
PWM3L and PWM0H through PWM3H. When PWM compare register is greater than 10-bits counter
register, the PWM output is low. Load bit has to be set to 1 for alteration of PWMn width. After the
new values are written to the PWMn registers, and if load bit is set to 1, the new PWMn values will be
loaded to the PWMn registers upon the next underflow. The PWM output high pulses width is given
by:
tHI = (PWMP – PWMn+1).
The following equations show the formula for period and duty:
Period
Duty
= (pwmp +1) * ioclock period * 1/prescaler
= duty * ioclock period
Note:
1. If compare register is set to 000H, the PWMn output will stay at high, and if compare register is
set to 3FFH, the PWMn output will stuck at low until there is a change in the compare register.
[n = 0-3].
2. During ICP mode, PWM pins will be tri-stated. PWM operation will be stop. When exit from ICP
mode, the PWM pins will follow the last SFR port values.
-79-
W79E8213/W79E8213R Data Sheet
0
1
P0.2=0
P0.2=1
BKF
BKCH
BPEN
BKEN
Brake
Control
Block
Brake Pin
(P0.2)
Enable External Brake Pin
(BPEN,BKCH)=(1,X)
PWMP Register
Counter Register
10-bit Down Counter
BKPS
load
PWMRUN
Fosc
SET
CLR
D
Q
Q
PWMF
Posc
Fcpwm
S/W Clear
X
P0.1
Underflow
Prescaler
(1/1, 1/2, 1/4, 1/16)
PWM0I
+
Clear
Counter
0
1
PWM0
(P0.1)
(FP1, FP0)
>
Y
CLRPWM
-
PWM0B
Compare Register
P1.6
PWM1I
X
Y
PWM0 register
+
-
0
PWM1
(P1.6)
>
1
PWM1B
Compare Register
PWM1 register
P1.7
X
Y
PWM2I
+
-
0
PWM2
(P1.7)
>
PWM2B
1
Compare Register
PWM2 register
P0.0
X
Y
PWM3I
+
-
0
PWM3
(P0.0)
>
PWM3B
1
Compare Register
PWM3 register
Figure 22-1: PWM Block Diagram
The W79E8213 series devices support brake function which can be activated by software or external
pin (P0.2). The Brake function is controlled by the PWMCON2 register. The setting and details
description of software brake and external pin brake can be found at the brake condition table at the
SFR section.
As for external brake, the user program can poll the brake flag (BKF) or enable PWM’s brake interrupt
to determine when the external Brake Pin is asserted and causes a brake to occur. The brake pin
(P0.2) can be set to trigger the brake function by either low or high level, by clearing or setting the
PWMCON2.6 (BKPS) bit respectively. The details description of varies brake functions can be found
in the brake condition table.
-80-
W79E8213/W79E8213R Data Sheet
Since the Brake Pin being asserted will automatically clear the Run bit of PWMCON1.7 and BKF
(PWMCON3.0) flag will be set, the user program can poll this bit or enable PWM’s brake interrupt to
determine when the Brake Pin causes a brake to occur. The other method for detecting a brake
caused by the Brake Pin would be to tie the Brake Pin to one of the external interrupt pins. This latter
approach is needed if the Brake signal is of insufficient length to ensure that it can be captured by a
polling routine. When, after being asserted, the condition causing the brake is removed, the PWM
outputs go to whatever state that had immediately prior to the brake. This means that in order to go
from brake being asserted to having the PWM run without going through an indeterminate state, care
must be taken. If the Brake Pin causes brake to be asserted, the following prototype code will allow
the PWM to go from brake and then run smoothly after brake is released.
Start
1. Clear 10-bit PWM counter
Initialize PWM function
CLRPWM=1
2. Reload PWMP & PWM registers
3. Enable brake function
1. Set PWM Control Regs
2. Set PWM brake output pattern(PWMnB)
3. Enable brake function
(BKEN,BPEN,BKCH)=(1,1,0)
(BKEN,BPEN,BKCH)=(1,1,0)
PWM starts running
Yes
Brake pin is
asserted?
No
No
Brake occurs?
Yes
1. Clear BKF
PWM output=PWM comparator output
2. Re-start PWM Running by setting
PWMRUN=1; load bit=1
1. PWMn output=PWMnB
2. H/W set BKF=1 & PWMRUN=0
3. S/W switch to S/W Brake
(BKEN,BPEN,BKCH)=(1,0,0)
4. Set PWMn comparator output =
PWMnB or a given pattern
End
Figure 22-2: PWM Brake Function
-81-
W79E8213/W79E8213R Data Sheet
23. ANALOG-TO-DIGITAL CONVERTER
The ADC contains a DAC which converts the contents of a successive approximation register to a
voltage (VDAC) which is compared to the analog input voltage (Vin). The output of the comparator is
fed to the successive approximation control logic which controls the successive approximation
register. A conversion is initiated by setting ADCS in the ADCCON register. There are two triggering
methods by ADC to start conversion, either by purely software start or external pin STADC triggering.
The software start mode is used to trigger ADC conversion regardless of ADCCON.5 (ADCEX) bit is
set or cleared. A conversion will start simply by setting the ADCCON.3 (ADCS) bit. As for the
external STADC pin triggering mode, ADCCON.5 (ADCEX) bit has to be set and a rise edge pulse has
to apply to STADC pin to trigger the ADC conversion. For the rising edge triggering method, a
minimum of at least 2 machine cycles symmetrical pulse is required.
The low-to-high transition of STADC is recognized at the end of a machine cycle, and the conversion
commences at the beginning of the next cycle. When a conversion is initiated by software, the
conversion starts at the beginning of the machine cycle which follows the instruction that sets ADCS.
ADCS is actually implemented with tpw flip-flops: a command flip-flop which is affected by set
operations, and a status flag which is accessed during read operations.
The next two machine cycles are used to initiate the converter. At the end of the first cycle, the ADCS
status flag is set end a value of “1” will be returned if the ADCS flag is read while the conversion is in
progress. Sampling of the analog input commences at the end of the second cycle.
During the next eight machine cycles, the voltage at the previously selected pin of one of analog input
pin is sampled, and this input voltage should be stable in order to obtain a useful sample. In any event,
the input voltage slew rate must be less than 10V/ms in order to prevent an undefined result.
The successive approximation control logic first sets the most significant bit and clears all other bits in
the successive approximation register (10 0000 0000b). The output of the DAC (50% full scale) is
compared to the input voltage Vin. If the input voltage is greater than VDAC, then the bit remains set;
otherwise if is cleared.
The successive approximation control logic now sets the next most significant bit (11 0000 0000b or
01 0000 0000b, depending on the previous result), and the VDAC is compared to Vin again. If the
input voltage is greater then VDAC, then the bit remains set; otherwise it is cleared. This process is
repeated until all ten bits have been tested, at which stage the result of the conversion is held in the
successive approximation register. The conversion takes four machine cycles per bit.
The end of the 10-bit conversion is flagged by control bit ADCCON.4 (ADCI). The upper 8 bits of the
result are held in special function register ADCH, and the two remaining bits are held in ADCCON.7
(ADC.1) and ADCCON.6 (ADC.0). The user may ignore the two least significant bits in ADCCON and
use the ADC as an 8-bit converter (8 upper bits in ADCH). In any event, the total actual conversion
time is 52 ADC clock cycles. ADCI will be set and the ADCS status flag will be reset 52 cycles after
the ADCS is set. Control bits ADCCON.0~1 and ADCCON1.2 are used to control an analog
multiplexer which selects one of 8 analog channels. An ADC conversion in progress is unaffected by
an external or software ADC start. The result of a completed conversion remains unaffected provided
ADCI = logic 1; a new ADC conversion already in progress is aborted when the idle or power-down
mode is entered. The result of a completed conversion (ADCI = logic 1) remains unaffected when
entering the idle mode.
-82-
W79E8213/W79E8213R Data Sheet
MSB
Start
Successive
Approximation
Register
Successive
Approximation
Control Logic
DAC
Ready
(Stop)
LSB
Comparator
-
V
DAC
Vin
+
Figure 23-1: Successive Approximation ADC
23.1 ADC Resolution and Analog Supply
The ADC circuit has its own supply pins (AVDD and AVSS) and one pins (Vref+) connected to each
end of the DAC’s resistance-ladder that the AVDD and Vref+ are connected to VDD and AVSS is
connected to VSS. The ladder has 1023 equally spaced taps, separated by a resistance of “R”. The
first tap is located 0.5×R above AVSS, and the last tap is located 0.5×R below Vref+. This gives a total
ladder resistance of 1024×R. This structure ensures that the DAC is monotonic and results in a
symmetrical quantization error.
For input voltages between VSS and [(Vref+) + ½ LSB], the 10-bit result of an A/D conversion will be
0000000000B = 000H. For input voltages between [(Vref+) – 3/2 LSB] and Vref+, the result of a
conversion will be 1111111111B = 3FFH. Vref+ and AVSS may be between AVDD + 0.2V and VSS –
0.2 V. Vref+ should be positive with respect to VSS, and the input voltage (Vin) should be between
Vref+ and VSS.
The result can always be calculated from the following formula:
Vin
Vin
Result = 1024 ×
or Result = 1024 ×
Vref +
VDD
-83-
W79E8213/W79E8213R Data Sheet
VDD
ADC Conversion Block
ADC0(P0.3)
ADC1(P0.4)
ADC2(P0.5)
ADC3(P0.6)
ADC4(P0.2)
ADC5(P0.1)
ADC6(P0.0)
ADC7(P0.7)
Analog
Input
Multiplexer
8
Vref+
AVDD
ADC[9:0]
ADCI
AADR[2:0]
ADCS
P1.4
0
10-bits
ADC Block
1
ADCEX
Fcpu
0
Prescaler
/8,/4,/2,/1
ADC Clock = 200KHz to 5MHz
RC_CLK (Internal RC
10MHz or 20MHz, selectable
by CONFIG1.FS1 bit)
1
AVSS
VSS
RCCLK
ADCLK1, ADCLK0 bits
(SFR ADCCON1)
default: divided by 4.
ADCEN
Figure 23-2: ADC block diagram
Note:
As Port 0 is multi-function port, when configuring Port0 for ADC application, user should configure Input Only
(High Impedance) and Disable Digital Input on port 0. This is done using P1Mx and PADIDS SFRs.
-84-
W79E8213/W79E8213R Data Sheet
24. ICP (IN-CIRCUIT PROGRAM) FLASH PROGRAM
The contexts of flash in W79E8213 series are empty by default. At the first use, you must program the
flash EPROM by external Writer device or by ICP (In-Circuit Program) tool.
Vcc
ICP Power
Jumper
ICP Connector
Vdd
Jumper
Vdd
Vpp
RST
P0.4
P0.5
To Reset or Input Pin
To I/O pin
Data
Clock
Vss
To I/O pin
Vss
ICP Program Tool
W79E8213 Series
System Board
Note:
1.
When using ICP to upgrade code, the P1.5, P0.4 and P0.5 must be taken within design system board.
2.
After program finished by ICP, to suggest system power must power off and remove ICP connector then power on.
3.
It is recommended that user performs erase function and programming configure bits continuously without any
interruption.
4.
During ICP mode, all PWM pins will be tri-stated.
-85-
W79E8213/W79E8213R Data Sheet
25. CONFIG BITS
The W79E8213 series has two CONFIG bits that must be defined at power up and can not be set the
program after start of execution. Those features are configured through the use of two flash EPROM
bytes, and the flash EPROM can be programmed and verified repeatedly. Until the code inside the
Flash EPROM is confirmed OK, the code can be protected. The protection of flash EPROM
(CONFIG1) and those operations on it are described below. The data of these bytes may be read by
the MOVX instruction at the addresses.
25.1 CONFIG0
7
6
0
5
4
3
2
1
Fos
Fos
“1”
RPD
PRHI BOV “1”
1
0
BPFR
c
c
RPD
PRHI
BOV
: Reset Pin Disable Bit.
: Port Reset High Bit.
: Brownout Voltage Select Bit.
BPFR : Bypass Clock Filter Bit.
Fosc1 : CPU Oscillator Type Select
Fosc0 : CPU Oscillator Type Select
Bit 1.
Figure 25-1: Config0 register bits
BIT NAME
FUNCTION
7
-
Must be “1”
Reset Pin Disable bit:
6
RPD 0: Enable Reset function of Pin 1.5.
1: Disable Reset function of Pin 1.5, and it to be used as an input port pin.
Port Reset High or Low bit:
PRHI 0: Port reset to low state.
1: Port reset to high state.
5
Brownout Voltage Select bit:
BOV 0: Brownout detect voltage is 3.8V.
1: Brownout detect voltage is 2.5V.
4
3
2
-
Must be “1”
Bypass Clock Filter.
BPFR 0: Disable Clock Filter.
1: Enable Clock Filter.
1
0
Fosc1 CPU Oscillator Type Select bit 1.
Fosc0 CPU Oscillator Type Select bit 0.
-86-
W79E8213/W79E8213R Data Sheet
Oscillator Configuration bits:
Fosc1
Fosc0
OSC source
0
0
4MHz ~ 20MHz crystal
Internal RC Oscillator (FS1 bit in CONFIG1.5 will determine either 10MHz or
20MHZ)
0
1
1
1
0
1
Reserved
External Oscillator in XTAL1
-87-
W79E8213/W79E8213R Data Sheet
25.2 CONFIG1
7
6
5
4
3
2
1
0
C7
C6
FS1
“1”
“1”
“1”
“1”
“1”
Bit7: C7
Bit6: C6
Bit5: FS1
Bit4~0:
: 4K Flash EPROM Code Lock Bit
: 128 byte Data Lock Bit
: Internal RC 10MHz/20MHz Selection Bit
: Must be “1”
Figure 25-2: Config1 register bits (W79E8213 series)
C7: 4K Flash EPROM Lock bit
This bit is used to protect the customer’s program code. It may be set after the programmer finishes
the programming and verifies sequence. Once this bit is set to logic 0, both the Flash EPROM data
and CONFIG Registers can not be accessed again.
C6: 128 byte Data Flash EPROM Lock bit
This bit is used to protect the customer’s 128 bytes of data code. It may be set after the programmer
finishes the programming and verifies sequence. Once this bit is set to logic 0, both the 128 bytes of
Flash EPROM data and CONFIG Registers can not be accessed again.
BIT 7 BIT 6
FUNCTION DESCRIPTION
Both security of 4KB program code and 128 Bytes data area are not locked. They
can be erased, programmed or read by Writer or ICP.
1
0
1
1
The 4KB program code area is locked. It can’t be read by Writer or ICP. The 128
Bytes data area can be program or read. The bank erase is invalid.
1
0
0
0
Not supported.
Both security of 4KB program code and 128 Bytes data area are locked. They can’t
be read by Writer or ICP.
FS1: Internal RC Oscillator 10MHz/20MHz selection bit
This bit is used to select 10MHz or 20MHz internal RC oscillator.
FS1
0
Internal RC Oscillator Output
10MHz
1
20MHz (default)
Internal Oscillator Selection Table
-88-
W79E8213/W79E8213R Data Sheet
26. ELECTRICAL CHARACTERISTICS
26.1 Absolute Maximum Ratings
PARAMETER
DC Power Supply
Input Voltage
SYMBOL
VDD−VSS
VIN
MIN
-0.3
MAX
+7.0
UNIT
V
VSS-0.3
-40
VDD+0.3
+85
V
Operating Temperature
Storage Temperature
P1 Sink current
TA
°C
°C
mA
Tst
-55
+150
90
ISK
-
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
26.2 DC ELECTRICAL CHARACTERISTICS
(TA = -40~85°C, unless otherwise specified.)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD=4.5V ~ 5.5V @ 20MHz
VDD=2.7V ~ 5.5V @ 12MHz
VDD1
2.4
-
5.5
VDD=2.4V ~ 5.5V @ 4MHz
Operating Voltage
V
NVM program and erase
operation.
VDD2
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
3.0
-
5.5
12
6
No load, /RST = VSS, VDD
5.0V @ 20MHz
=
=
-
-
-
-
-
-
-
-
8.30
4.20
14.50
5.20
3.60
1.86
8.60
2.20
No load, /RST = VSS, VDD
3.0V @ 20MHz
Operating Current (20MHz)
mA
No load, /RST = VDD, VDD
5.0V @ 20MHz, RUN NOP
=
20
7
No load, /RST = VDD, VDD
3.0V @ 20MHz, RUN NOP
=
No load, /RST = VSS, VDD
5.0V @ 4MHz
=
5
No load, /RST = VSS, VDD
3.0V @ 4MHz
=
3
Operating Current (4MHz)
mA
mA
No load, /RST = VDD, VDD
5.0V @ 4MHz, RUN NOP
=
12
3.5
No load, /RST = VDD, VDD
3.0V @ 4MHz, RUN NOP
=
No load, VDD = 5.0V
@ 20MHz
IIDLE1
-
-
5.70
2.48
8
Idle Current
No load, VDD = 3.0V
@ 20MHz
IIDLE2
3.5
-89-
W79E8213/W79E8213R Data Sheet
DC ELECTRICAL CHARACTERISTICS, continued
SPECIFICATION
PARAMETER
SYM.
IPWDN1
IPWDN2
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
No load, VDD = 5.5V
-
1
10
µA
@ Disable BOV function
Power-down Current
No load, VDD = 3.0V
-
1
10
uA
@ Disable BOV function
Input / Output
VDD = 5.5V, VIN = 0V or
VIN=VDD
Input Current P0, P1, P2
IIN1
IIN2
ILK
-50
-30
-
+10
-55
µA
µA
µA
µA
V
Input Current P1.5(RST
pin)[1]
-45
0.1
-
VDD = 5.5V, VIN = 0.45V
VDD = 5.5V, 0<VIN<VDD
VDD = 5.5V, VIN<2.0V
Input Leakage Current P0,
P1, P2 (Open Drain)
-10
+10
-500
Logic 1 to 0 Transition
Current P0, P1, P2
[*3]
ITL
-200
0
0
-
-
0.8
0.5
VDD = 4.5V
VDD = 2.4V
Input Low Voltage P0, P1,
P2 (TTL input)
VIL1
VIH1
VIL3
VIH3
VILS
VDD
+0.2
2.4
1.7
-
-
V
V
DD = 5.5V
DD = 2.4V
Input High Voltage P0, P1,
P2 (TTL input)
V
V
V
V
VDD
+0.2
0
0
-
-
0.8
0.4
VDD = 4.5V
VDD = 3.0V
Input Low Voltage XTAL1[*2]
Input High Voltage XTAL1[*2]
VDD
+0.2
3.5
2.4
-
-
-
-
V
V
DD = 5.5V
DD = 3.0V
VDD
+0.2
Negative going threshold
(Schmitt input)
-0.5
0.3VDD
VDD = 2.4V~5.5V
VDD = 2.4V~5.5V
Positive going threshold
(Schmitt input)
VIHS
VHY
ISR1
0.7VDD
VDD+0.5
V
V
Hysteresis voltage
-
0.2VDD
-25
-
-
-
-16
-2
VDD = 4.5V, VS = 2.4V
VDD = 2.4V, VS = 2.0V
Source Current P0, P1, P2
(PUSH-PULL Mode)
mA
-3.8
-150
-18
13
-225
-28.5
21.5
-360
-69
-
VDD = 4.5V, VS = 2.4V
VDD = 2.4V, VS = 2.0V
VDD = 4.5V, VS = 0.45V
Source Current P0, P1, P2
(Quasi-bidirectional Mode)
ISR2
µA
Sink Current P0, P2
(Quasi-bidirectional, Open
drain and PUSH-PULL
Mode) [*4]
ISK1
mA
9
13.7
42.5
28.7
-
-
-
VDD = 2.4V, VS = 0.45V
VDD = 4.5V, VS = 0.45V
VDD = 2.4V, VS = 0.45V
Sink Current P1
35
22
(Quasi-bidirectional, Open
drain and PUSH-PULL
Mode) [*4]
ISK2
mA
-90-
W79E8213/W79E8213R Data Sheet
DC ELECTRICAL CHARACTERISTICS, continued
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Brownout voltage with
BOV=1
VBO2.5
VBO3.8
IADC
2.4
-
2.7
V
TA = -0 to 70°C
TA = -0 to 70°C
Brownout voltage with
BOV=0
3.5
-
4
V
-
-
0.4
0.8
0.5
VDD = 5.0V, ADCCLK = 4MHz
VDD = 3.0V, ADCCLK = 4MHz
ADC current consumption
mA
0.25
-
-
1.2
0.8
1.8
1.2
VDD = 5.0V
VDD = 3.0V
Brownout voltage detect
current
IBOD
mA
*1. /RST pin is a Schmitt trigger input.
*2. XTAL1 is a CMOS input.
*3. Pins of P0, P1 and P2 can source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when Vin approximates to 2V.
*4. Only one of the 8 pins sinks high current at a time.
26.3 The ADC Converter DC ELECTRICAL CHARACTERISTICS
(VDD−VSS = 3.0~5V, TA = -40~85°C, Fosc = 4MHz, unless otherwise specified.)
SPECIFICATION
TEST
PARAMETER
Analog input
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
AVin
VSS-0.2
VDD+0.2
V
ADC block circuit
input clock
ADC clock
ADCCLK 200KHz
tC
-
5MHz
Hz
1
Conversion time
Differential non-linearity
Integral non-linearity
Offset error
52tADC
us
DNL
INL
Ofe
Ge
-1
-2
-1
-1
-3
-
-
-
-
-
+1
+2
+1
+1
+3
LSB
LSB
LSB
%
Gain error
Absolute voltage error
Notes:
Ae
LSB
1. tADC: The period time of ADC input clock.
-91-
W79E8213/W79E8213R Data Sheet
26.4 Internal RC Oscillator Accuracy
Parameter
Specification (Reference)
Test Conditions
Min.
-
Typ.
±30
Max.
-
Unit
%
VDD = 3.3V, TA = 25°C
W79E8213
Frequency accuracy of On-
chip RC oscillator
(Fosc = 20/10MHz without
calibration)
VDD = 5.0V, TA = 25°C
W79E8213R
-2
-5
-7
-9
2
5
7
7
%
%
On-chip RC oscillator with
calibration1,2
VDD = 2.7V~5.5V, TA = 0~85°C
VDD = 2.7V~5.5V, TA = -20~85°C
VDD = 2.7V~5.5V, TA = -40~85°C
%
(Fosc = 20/10MHz with
factory calibration)
%
Wakeup time
Note:
256
clk
1. These values are for design guidance only and are not tested.
2. RC frequency deviation v.s VDD and Temperature is shown below
6
3
T=85C
T=50C
T=25C
T=0C
0
-3
-6
-9
-12
T=-20C
T=-40C
2.2
2.7
3.2
3.7
4.2
4.7
5.2
Supply Voltage (V)
-92-
W79E8213/W79E8213R Data Sheet
26.5 AC ELECTRICAL CHARACTERISTICS
tCLCL
tCLCH
tCLCX
tCHCL
tCHCX
Note: Duty cycle is 50%.
26.6 EXTERNAL CLOCK CHARACTERISTICS
PARAMETER
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
SYMBOL
tCHCX
MIN.
12.5
12.5
-
TYP.
MAX.
UNITS
nS
NOTES
-
-
-
-
-
tCLCX
-
nS
tCLCH
10
10
nS
tCHCL
-
nS
26.7 AC SPECIFICATION
VARIABLE CLOCK
MIN.
VARIABLE CLOCK
MAX.
PARAMETER
SYMBOL
1/tCLCL
UNITS
Oscillator Frequency
0
20
MHz
26.8 TYPICAL APPLICATION CIRCUITS
CRYSTAL
C1
C2
R
4MHz ~ 20 MHz
without
without
without
The above table shows the reference values for crystal applications.
C1
XTAL1
R
XTAL2
C2
W79E8213
Series
-93-
W79E8213/W79E8213R Data Sheet
27. PACKAGE DIMENSIONS
27.1 20-pin SOP-300mil
11
c
20
E
H
E
L
1
10
O
D
0.25
A
Y
SEATING PLANE
e
GAUGE P
A1
b
Control demensions are in milmeters .
DIMENSION IN MM DIMENSION IN INCH
SYMBOL
MIN.
2.35
0.10
0.33
0.23
MAX.
2.65
MIN.
0.093
MAX.
0.104
0.012
0.020
A
A1
b
0.30
0.51
0.004
0.013
c
0.32
0.009
0.291
0.496
0.013
0.299
7.40
E
D
7.60
13.00
0.512
12.60
e
0.050 BSC
1.27 BSC
H
Y
10.00
10.65
0.10
1.27
8
0.394
0.419
0.004
0.050
8
E
0.40
0
0.016
0
L
θ
-94-
W79E8213/W79E8213R Data Sheet
27.2 20-pin PDIP-300mil
D
20
11
1
E
1
10
E
S
c
1
2
A
A
A
Base Plane
Seating Plane
L
B
e1
eA
α
B 1
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Min
Max Min
0.175
Max
4.45
A
0.010
0.125
0.25
1
A
0.130 0.135
3.18
0.41
1.47
0.20
3.30
0.46
1.52
0.25
20.06
7.62
6.35
2.54
3.30
3.43
0.56
1.63
0.36
26.42
7.87
6.48
2.79
2
A
0.016 0.018
0.022
0.064
B
0.060
0.058
0.008
1
B
0.010 0.014
1.026 1.040
c
D
E
0.310
0.255
0.110
0.290
0.245
0.300
0.250
7.37
6.22
2.29
1
E
e
1
0.090 0.100
3.05
0
0.140
15
0.120
0
0.130
3.56
15
L
α
A
e
9.53
1.91
0.335
0.375
0.075
8.51
0.355
9.02
S
-95-
W79E8213/W79E8213R Data Sheet
28. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
May 20,
2008
A1
-
Initial Issued
5
Add VDD = 2.7V to 5.5V @12MHz CPU operation condition
Revise ADC current consumption specification
A2
July 11, 2008
92
August 5,
2008
A3
A4
A5
91
Revise Power down current to typical 1uA, max.10uA
6
Revise Lead Free (RoHS) Parts information list
Revise Internal RC Oscillator Accuracy table
September
1, 2008
93
November
12, 2008
30
Remove duplicate description about SFR WDCON register
Remove the “prelimanry”
November
21, 2009
A6
A7
87
91
Add defaule value for the reserved bit of CONFIG0
Add defaule value for the reserved bit of CONFIG1
Revise chapter 26.4 “Internal RC ± 2% with VDD = 5.0V, TA
= 25C”.
November
12, 2012
92
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
-96-
相关型号：
W79E8213RASG
The W79E8213 series are an 8-bit 4T-8051 microcontroller which has Flash EPROM which is programmable by ICP (In Circuit Program) or by hardware writer.
NUVOTON
W79E821ADG
Microcontroller, 8-Bit, FLASH, 8051 CPU, 20MHz, CMOS, PDIP20, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-20
WINBOND
W79E823ASG
Microcontroller, 8-Bit, FLASH, 8051 CPU, 20MHz, CMOS, PDSO20, 0.300 INCH, ROHS COMPLIANT, SOP-20
WINBOND
©2020 ICPDF网 联系我们和版权申明