W83628AG [NUVOTON]
PCI TO ISA BRIDGE;
| 型号： | W83628AG |
| 厂家： | 
NUVOTON |
| 描述： | PCI TO ISA BRIDGE PC 外围集成电路 |
| 文件： | 总65页 (文件大小：857K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nuvoton
PCI TO ISA BRIDGE
W83628AG
W83629AG
Revision: 1.2
Date: January, 2008
W83628AG & W83629AG
W83628AG & W83629AG Datasheet Revision History
PAGES
DATES
VERSION
MAIN CONTENTS
N.A.
07/30/2007
0.5
1. First published version.
1
2
1. Update the information of Chapter 10 Absolute
Maximum Ratings.
34, 38
08/02/2007
0.51
2. Modify the description of Chapter 12 AC
Characteristics.
1. All versions before 1.0 are preliminary versions.
1. Add the ordering information
N.A.
1
11/01/2007
11/28/2007
31/1/2008
1.0
1.1
1.2
3
4
5
11
1. Modify DC characteristics
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Nuvoton
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales.
Publication Release Date: January, 2008
- I -
Revision 1.2
W83628AG & W83629AG
Table of Contents –
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 1
FEATURES................................................................................................................................. 1
PACKAGE................................................................................................................................... 1
ORDERING INFORMATION ...................................................................................................... 1
BLOCK DIAGRAM OF W83628AG ............................................................................................ 2
BLOCK DIAGRAM OF W83629AG ............................................................................................ 3
FUNCTION DESCRIPTION........................................................................................................ 4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
PCI Interface................................................................................................................... 4
ISA Interface ................................................................................................................... 5
Serial IRQ Interface ........................................................................................................ 5
PC/PCI DMA Interface.................................................................................................... 7
ISA Bus SYSCLK Clock Generation............................................................................... 8
ISA Bus I/O Recovery Time............................................................................................ 8
NOGO............................................................................................................................. 8
8.
9.
PIN CONFIGURATION............................................................................................................... 9
8.1
8.2
PIN CONFIGURATION FOR W83628AG ...................................................................... 9
PIN CONFIGURATION FOR W83629AG .................................................................... 10
PIN DESCRIPTION................................................................................................................... 11
9.1
9.2
W83628AG PIN DESCRIPTION .................................................................................. 11
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
PCI Interface .............................................................................................................11
Control Logic and Handshaking Signals....................................................................13
ISA Interface Signals.................................................................................................13
Power Signals ...........................................................................................................16
NC Pins.....................................................................................................................16
W83629AG PIN DESCRIPTION .................................................................................. 17
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Control Logic and Handshaking Signals....................................................................17
PC/PCI Interface .......................................................................................................17
IRQ Serializer Interface.............................................................................................18
Power Signals ...........................................................................................................18
NC Pins.....................................................................................................................18
10.
PCI CONFIGURATION REGISTERS....................................................................................... 19
10.1 VID-VENDOR IDENTIFICATION REGISTER.............................................................. 19
10.2 DID-DEVICE IDENTIFICATION REGISTER................................................................ 19
10.3 PCICMD-PCI COMMAND REGISTER......................................................................... 19
Publication Release Date: January, 2008
- I -
Revision 1.2
W83628AG & W83629AG
10.4 PCISTS-PCI STATUS REGISTER............................................................................... 20
10.5 REVID-REVISION IDENTIFICATION REGISTER ....................................................... 21
10.6 CCODE-CALSS CODE REGISTER............................................................................. 21
10.7 HEADT-HEAD TYPE REGISTER ................................................................................ 22
10.8 IO_RCVR-IO RECOVERY REGISTER........................................................................ 22
10.9 WISA_STS-ISA BRIDGE ERROR STATUS REGISTER............................................. 23
10.10 BRIDGE FAST MEMORY DECODER #0 CONTROL REGISTERS ........................... 24
10.11 BRIDGE FAST MEMORY DECODER #1 CONTROL REGISTERS ........................... 25
10.12 BRIDGE FAST MEMEORY DECODER #2 CONTROL REGISTERS......................... 26
10.13 WISA_FADC-ISA BRIDGE FAST IO DECODERS CONTROL REGISTERS ............. 27
10.14 ISA_FAD0MC-ISA BRIDGE FAST DECODERS # 0 MASK CONTROL REGISTER.. 29
10.15 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 1 MASK CONTROL REGISTER
29
10.16 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 2 MASK CONTROL REGISTER
29
10.17 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 3 MASK CONTROL REGISTER
29
10.18 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 4 MASK CONTROL REGISTER
30
10.19 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 5 MASK CONTROL REGISTER
30
10.20 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 6 MASK CONTROL REGISTER
30
10.21 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 7 MASK CONTROL REGISTER
30
10.22 WISA_FADCB0-ISA BRIDGE FAST DECODERS # 0 BASE ADDRESS REGISTER 31
10.23 WISA_FADCB1-ISA BRIDGE FAST DECODERS # 1 BASE ADDRESS REGISTER 31
10.24 WISA_FADCB2-ISA BRIDGE FAST DECODERS # 2 BASE ADDRESS REGISTER 31
10.25 WISA_FADCB3-ISA BRIDGE FAST DECODERS # 3 BASE ADDRESS REGISTER 31
10.26 WISA_FADCB4-ISA BRIDGE FAST DECODERS # 4 BASE ADDRESS REGISTER 31
10.27 WISA_FADCB5-ISA BRIDGE FAST DECODERS # 5 BASE ADDRESS REGISTER 32
10.28 WISA_FADCB6-ISA BRIDGE FAST DECODERS # 6 BASE ADDRESS REGISTER 32
10.29 WISA_FADCB7-ISA BRIDGE FAST DECODERS # 7 BASE ADDRESS REGISTER 32
10.30 WISA_CTRLREG1-ISA BRIDGE CONTROL REGISTER 1........................................ 33
10.31 WISA_CTRLREG2-ISA BRIDGE CONTROL REGISTER 2........................................ 34
10.32 WISA_CTRLREG3-ISA BRIDGE CONTROL REGISTER 3........................................ 34
10.33 WISA_CTRLREG4-ISA BRIDGE CONTROL REGISTER 4........................................ 35
Publication Release Date: January, 2008
- II -
Revision 1.2
W83628AG & W83629AG
10.34 BRIDGE FAST MEMORY DECODER #3 CONTROL REGISTERS ........................... 35
10.35 WISA_TSTREG-ISA BRIDGE TEST REGISTER ........................................................ 36
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 37
DC CHARACTERISTICS.......................................................................................................... 37
AC CHARACTERISTICS.......................................................................................................... 40
WAVEFORMS........................................................................................................................... 43
TOP MARKING SPECIFICATION ........................................................................................... 58
PACKAGE DIMENSIONS 1 FOR W83628AG (128-PIN PQFP).............................................. 59
PACKAGE DIMENSIONS 2 FOR W83629AG (48-PIN LQFP) ................................................ 59
11.
12.
13.
14.
15.
16.
17.
Publication Release Date: January, 2008
- III -
Revision 1.2
W83628AG & W83629AG
1. GENERAL DESCRIPTION
The W83628AG is a PCI-to-ISA bus conversion IC. The W83629AG is a condensed centralizer IC for
IRQ and DMA control. W83628AG and W83629AG together form a complete set for the PCI-to-ISA
bridge.
For the new generation Intel chipsets featuring LPC bus but not supporting ISA bus and slots, the
W83628AG plus the W83629AG are the best companion solution for the non-ISA chipset. Also the
packages of the W83628AG (128-QFP) and the W83629AG (48-LQFP) are the most cost-effective
solution that minimizes the M/B board layout size and cost.
For the new generation chipsets featuring LPC interface but not supporting ISA bus, the best and the
most complete solution will be the combination of the W83627 (Nuvoton LPC I/O) family and the set of
the W83628AG and the W83629AG.
2. FEATURES
PCI to ISA Bridge
•
•
•
•
•
•
•
•
•
Full ISA Bus Support, including ISA Masters
5V ISA and 3.3V PCI interfaces
PC/PCI DMA protocol for Software Transparent
IRQ Serializer for ISA Parallel IRQ transfer to Serial IRQ
Supports 3 fully ISA Compatible Slots without Buffering
PCI Bus at 25MHz, 33MHz and up to 40MHz
Supports Programmable ISA Bus Divide the PCI Bus Clock into 3 or 4
All ISA Signals can be Isolated
Supports Configuration registers for performance programming
3. PACKAGE
•
•
128-pin QFP for the W83628AG
48-pin LQFP for the W83629AG
4. ORDERING INFORMATION
PART NUMBER
DESCRIPTION
PRODUCTION FLOW
Commercial, 0oC to +70oC
Commercial, 0oC to +70oC
W83628AG
128-PIN QFP, Pb-free
W83629AG
48-PIN LQFP, Pb-free
W83628AGEVB
W83628/629AG Evaluation board
Publication Release Date: January, 2008
Revision 1.2
- 1 -
W83628AG & W83629AG
5. BLOCK DIAGRAM OF W83628AG
AD[31:0]
C/BE[3:0]#
PAR
SA[19:0]
SD[15:0]
BALE
FRAME#
TRDY#
IRDY#
STOP#
AEN
PCI
IOCHRDY
IOCS16#
IOCHK#
Interface
DEVSEL#
IOR#
IOW#
LA[23:17]
SBHE#
MEMCS16#
MEMR#
MEMW#
SMEMR#
SMEMW#
ZEROWS#
MASTER#
REFRESH#
ROMCS#
RSTDRV
SYSCLK
ISA
IDSEL
SERR#
Interface
NOGO
PCIRST#
PCICLK
Signal
Isolation
Control
ISOLATE#
3.3V
5V
Power
SuppIy
Handshaking
HS[2:0]
Publication Release Date: January, 2008
Revision 1.2
- 2 -
W83628AG & W83629AG
6. BLOCK DIAGRAM OF W83629AG
PCIRST#
PCI Host &
PCICLK
Bridge Set
NOGO
Handshaking Logic
HS[2:0]
DREQ[7:5, 3:0]
ISAREQ#
PC/PCI DMA
ISAGNT#
DACK[7:5, 3:0]#
TC
Interface
Parallel
To
IRQ[15,14,12:9,7:3]
IOCHK#
SERIRQ
3.3V
Serial
IRQ
Power
5V
Supply
Publication Release Date: January, 2008
Revision 1.2
- 3 -
W83628AG & W83629AG
7. FUNCTION DESCRIPTION
The W83628AG and W83629AG support the functional sub-block interfaces described below:
7.1
PCI Interface
The W83628AG provides a PCI slave/master interface. The slave mode means the PCI cycles are
initiated by the PCI Host Bridge or South Bridge chipset. Default is PCI bus cycle information from PCI
Host Bridge being received in PCI slave mode. When ISA bus’s MASTER# signal is asserted, the
W83628A’s PCI interface as slave mode will be switched to PCI master mode to drive/initiate PCI bus
cycles to PCI bus. The W83628AG supports some positive decodes and implements subtractive
decodes for unclaimed PCI accesses.
The PCI slave interface supports the positive decodes as below:
z
z
z
z
z
PCI configuration register spaces which are positively decode with medium DEVSEL#
timing speed on the Type0 PCI configuration cycle.
Eight IO positively decode space which can be programmed to claim PCI I/O cycle with
Fast/Medium/Slow/Subtractive DEVSEL# timing speed.
Four Memory positively decode spaces which can be programmed to claim PCI Memory
cycle with Fast/Medium/Slow/Substractive DEVSEL# timing speed.
PC/PCI DMA (PPDMA) cycle space:The I/O portion of the DMA cycle generates a PCI I/O
cycle to one of the four I/O addresses of 0000h/0004h/00C0h/00C4h
ISA BIOS ROM boot up scheme: upload boot ROM on ISA bus during system boot up.
Enable/disbale optionally the function through the external pull-up resistor on signal
ROMCS# of the W83628AG. When PCIRST# is asserted, the signal ROMCS# will be
detected and latched. After PCIRST# is released, the latched signal High(1)/Low(0)
means to enable(1)/disable(0) the ISA BIOS ROM boot up function, respectively. The
latched bit can also be disabled/enabled through Type0 PCI configuration cycle.
The PCI master interface will issue PCI cycle for ISA bus master cycle.
The W83628AG and the W83629AG together support PC/PCI DMA. The W83629AG uses dedicated
ISAREQ# and ISAGNT# signals to permit ISA devices’ transfer requests associated with specific DMA
channels. Upon receiving a request and getting control of the PCI bus, South Bridge chipset performs
a two-cycle transfer. For example, if data is to be moved from the peripheral to the main memory, the
chipset will first read data from the peripheral and then write it to the main memory.
When in PC/PCI DMA cycle, the W83629AG DACKn# is decoded from ISAGNT#. As long as the
ISAGNT# and MASTER# signals are asserted and are with an ISA command issued by ISA master,
then the W83628AG PCI master interface will issues a PCI cycle for ISA master.
Publication Release Date: January, 2008
- 4 -
Revision 1.2
W83628AG & W83629AG
7.2
ISA Interface
The W83628AG provides an ISA bus interface for the subtractive decoded memory and I/O cycles on
PCI. Default is driving/issuing relative legacy ISA bus cycle to ISA bus in ISA master mode. Generally
if a valid PCI memory or I/O cycle is received by the W83628AG PCI slave interface, it will be passed
to the internal ISA interface and the ISA interface will convert it to correspond to the ISA bus cycle.
When ISA bus’s MASTER# signal is asserted, the W83628AG ISA interface as master mode will be
switched to ISA slave mode to receive legacy ISA bus cycles from the ISA bus. That means there is
an ISA command issued by ISA master. The related ISA bus cycle will be passed to PCI master
interface to drive/issue corresponding PCI bus cycle.
7.3
Serial IRQ Interface
The W83629AG supports a serialized IRQ slave which conforms to the specification of “Serialized
IRQ Support for PCI system, rev. 6.0, September 1, 1995”. Two modes, continuous and quiet, are
supported.
The serial IRQ interface provides signal filtering and encoding logic for all legacy parallel ISA IRQ
channels (IRQ15-14, 12-9, 7-3 and IOCHK#) to convert them to serial IRQ on the SERIRQ line. The
IRQ/Data serializer is a Wired-OR structure that simply passes the state of one or more device’s
IRQ(s) and/or Data to the host controller. The transfer can be initiated by either a device or the host
controller. A transfer, called an IRQSER Cycle, consists of three frame types: one Start Frame,
several IRQ/Data Frames, and one Stop Frame.
This protocol uses the PCI Clock as its clock source and conforms to the PCI bus electrical
specification.
z
Start Frame timing with source sampled a low pulse on IRQ1
START FRAME
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
SL
or
H
R
T
S
R
T
S
R
T
S
R
T
H
PCICLK
IRQSER
1
START
IRQ1 Host Controller
None
IRQ1
None
Drive Source
H=Host Control
SL=Slave Control
R=Recovery
T=Turn-around S=Sample
Start Frame pulse can be 4-8 clocks wide
Publication Release Date: January, 2008
Revision 1.2
- 5 -
W83628AG & W83629AG
z
Stop Frame Timing with Host using 17 IRQSER sampling period
IRQ14
FRAME
R
IRQ15
FRAME
R
IOCHCK#
FRAME
STOP FRAME
NEXT CYCLE
START
I 2
S
T
S
T
S
R
T
H
R
T
PCICLK
IRQSER
Driver
1
3
STOP
None
IRQ15
None
Host Controller
S=Sample
H=Host Control
R=Recovery
T=Turn-around
I= Idle.
1. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
2. There may be none, one or more Idle states during the Stop Frame.
3. The next IRQSER cycle’s Start Frame pulse may or may not start immediately after the turn-around
clock of the Stop Frame.
The main difference between the quite mode and the continuous mode for the IRQSER Frame is:
z Quiet (Active) Mode: Any device may initiate a Start Frame by driving the IRQSER
low for one clock, while the IRQSER is Idle.
z Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update
IRQ/Data line information.
Publication Release Date: January, 2008
- 6 -
Revision 1.2
W83628AG & W83629AG
7.4
PC/PCI DMA Interface
The W83629AG supports PC/PCI DMA Serial Channel Passing Protocol interface as shown in Figure
6-1.
Figure 6-1: PC/PCI DMA Serial Channel Passing Protocol
When the W83629AG receives the legacy ISA DMA requesting DRQn, the DMA interface must
encode the channel request information, where CH0-CH7 will be active high, depending on which is
requested as the DMA channel.
The South Bridge chipset encodes the granted channel on the ISAGNT# line, where the bits have the
same meaning. For example, the sequence [start, bit0, bit1, bit2] = [0, 1, 0, 0] grants DMA channel 1
to the requesting device, and the sequence [start, bit0, bit1, bit2] = [0, 0, 1, 1] grants DMA channel 6 to
the requesting device.
After receiving a valid grant and detecting ISAGN# start bit, the W83629AG will decode and convert
the ISAGNT# signal information to corresponding legacy ISA DMA acknowledge DACKn# signal.
Table 6-1 below shows the I/O portion of the DMA cycle generates a PCI I/O cycle to one of the four
I/O addresses. The W83628AG will recognize the PCI I/O cycle with the DMA I/O address. These
cycles must be qualified by an active ISAGNT# signal to the requesting device. A2 of DMA I/O
address bit 2 is used to indicate DMA Terminal Count cycle.
DMA CYCLE TYPE
Normal
DMA I/O ADDRESS
00h
TC(A2)
PCI CYCLE TYPE
I/O Read/Write
0
Normal TC
Verify
04h
1
0
1
I/O Read/Write
I/O Read
0C0h
0C4h
Verify TC
I/O Read
Table 6-1: DMA Cycle Type and I/O Address
Publication Release Date: January, 2008
Revision 1.2
- 7 -
W83628AG & W83629AG
7.5
ISA Bus SYSCLK Clock Generation
The W83628AG generates the ISA SYSCLK clock using PCI clock signal. A PCICLK divisor (3, 4) is
programmable through PCI configuration register to generate the ISA SYSCLK clock signal. This
provides ISA SYSCLK frequencies 8.33MHz and 11MHz of a typical 33MHz PCICLK.
7.6
ISA Bus I/O Recovery Time
The W83628AG supports 8-bit/16-bit I/O recovery time for back-to-back ISA I/O cycles. The register
can be programmed through Type0 PCI configuration cycle.
7.7
NOGO
The W83628AG and W83629AG also support NOGO function. The NOGO signal generally connected
to South Bridge chipset’s NOGO signal is used to disable the subtractive decode function when
NOGO signal is asserted high during system boot-up, since there is only one subtractive decode
device presented on the PCI bus .
Publication Release Date: January, 2008
- 8 -
Revision 1.2
W83628AG & W83629AG
8. PIN CONFIGURATION
8.1
PIN CONFIGURATION FOR W83628AG
Publication Release Date: January, 2008
Revision 1.2
- 9 -
W83628AG & W83629AG
8.2
PIN CONFIGURATION FOR W83629AG
Publication Release Date: January, 2008
Revision 1.2
- 10 -
W83628AG & W83629AG
9. PIN DESCRIPTION
Note: Please refer to Section 10 DC CHARACTERISTICS for details.
I/O
I/O
I/O
I/O
- TTL level bi-directional pin with 10 mA source-sink capability
- TTL level bi-directional pin with 18 mA source-sink capability
- 3.3V TTL level bi-directional pin with 10 mA source-sink capability
- 3.3V TTL level bi-directional pin with 18 mA source-sink capability
- TTL level bi-directional pin open drain output with 10 mA sink capability
- TTL level bi-directional pin open drain output with 18 mA sink capability
- TTL level output pin with 10 mA source-sink capability
- TTL level output pin with 18 mA source-sink capability
- Open-drain output pin with 10 mA sink capability
10t
18t
10tp3
18tp3
I/OD
I/OD
OUT
OUT
10t
18t
10t
18t
OD
10
IN
IN
- TTL level input pin
t
- TTL level Schmitt-trigger input pin
ts
9.1
W83628AG PIN DESCRIPTION
9.1.1 PCI Interface
SYMBOL
PIN
I/O
FUNCTION
LEVEL
19-26
30-37
52-59
61-63
66-70
PCI Bus Address and Data Signals. The standard
PCI address and data lines. The address is driven
with FRAME# assertion; the data is driven or
received in following clocks.
I/O
AD[31:0]
3.3V
18tp3
18tp3
PCI Bus Command and Byte Enables. During the
address phase of a transaction, C/BE[3:0]# define
the bus command. During the data phase,
C/BE[3:0]# are used as Byte Enables.
28,44
51,60
I/O
C/BE[3:0]#
PCICLK
3.3V
3.3V
PCI Bus System Clock. PCICLK provides timing
for all transactions on the PCI bus. All the other PCI
signals are sampled on the rising edge of PCICLK,
and all timing parameters are defined with respect
to this edge.
IN
47
ts
Publication Release Date: January, 2008
Revision 1.2
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W83628AG & W83629AG
8.1.1 PCI Interface, contiuned
SYMBOL
PIN
I/O
I/O
FUNCTION
LEVEL
Frame Signal. FRAME# is driven by the current
PCI bus master to indicate the beginning and
duration of an access.
FRAME#
40
3.3V
18tp3
Initialization Device Select. IDSEL is used as a
chip select during configuration read and write
transactions. This signal should be externally tied to
one of the upper 21 address signals.
IN
IDSEL
29
3.3V
ts
Bus Stop#. STOP# indicates the current target is
requesting the master to stop the current PCI bus
transaction.
I/O
I/O
I/O
STOP#
IRDY#
TRDY#
39
41
42
3.3V
3.3V
3.3V
10tp3
10tp3
10tp3
Initiator Ready. IRDY# indicates the initiating
agent’s ability to complete the current data phase of
the PCI bus transaction.
Target Ready. TRDY# indicates the target agent’s
ability to complete the current data phase of the
PCI bus transaction.
Device Select. The W83628AG drives DEVSEL#
to indicate that it is the target of the current PCI bus
transaction. The W83628AG uses subtractive
decoding and the NOGO protocol to claim PCI
transactions.
I/O
DEVSEL#
43
3.3V
10tp3
System Error. SERR# can be pulsed active by any
PCI agent that detects a system error condition.
OD
SERR#
PAR
45
49
71
3.3V
3.3V
3.3V
10
Parity Signal. The W83628AG generates even
parity across AD[31:0] and C/BE[3:0]#.
I/O
10tp3
PCI Reset. The W83628AG receives PCIRST# as
a reset from the PCI Bus.
IN
PCIRST#
ts
Publication Release Date: January, 2008
Revision 1.2
- 12 -
W83628AG & W83629AG
9.1.2 Control Logic and Handshaking Signals
SYMBOL
PIN
I/O
FUNCTION
LEVEL
Handshaking Signals. HS[2:0] are connected to
the W83629AG for PCI to ISA SET handshaking
signals.
I/O
10t
HS[2:0]
112-114
5V
HS1 is handshaking Signal 1; this pin is weak
pulled-down while PCIRST# is asserted.
Applying a pull-up resistor (4.7Kohm) to this pin
disables ISA bridge subtraction decoder.
Isolation Control Input. Isolate# is an active low
signal by user programming to control all of the
output signals of the W83628AG to Isolation and
Tri-state.
IN
ISOLATE#
NOGO
72
76
3.3V
5V
ts
NOGO, This signal indicates which master initiates
the current transaction and whether or not the
current bus cycle is targeted for the ISA bus. This
signal is a point-to-point connection between PCI
HOST Bridge and the W83628AG.
IN
t
9.1.3 ISA Interface Signals
SYMBOL
PIN
I/O
FUNCTION
LEVEL
System Address Bus. These are the upper
address lines that define the ISA’s byte granular
address space (up to 1 Mbyte). SA[19:17] are at an
unknown state upon PCIRST#.
SA[19:17]
98-96
I/O18t
5V
System Address Bus. These are the bi-directional
lower address lines that define the ISA’s byte
granular address space (up to 1 Mbyte). SA[16:0]
are at an unknown state upon PCIRST#.
94-83
81-77
I/O
18t
SA[16:0]
SD[15:0]
5V
5V
110-107,
104,103,
101,100,
8-15
System Data. SD[15:0] provide the 16-bit data path
for devices residing on the ISA Bus. The
W83628AG tri-states SD[15:0] during PCIRST#.
I/O
18t
Address Enable. AEN is asserted during DMA
cycles. This signal is also driven high when the
W83628AG initiates refresh cycles. AEN is driven
low upon PCIRST#.
OUT
AEN
118
120
5V
5V
18t
I/O Read. IOR# is the command to an ISA I/O slave
device that the slave may drive data on to the ISA
data bus (SD[15:0]).
I/O
18t
IOR#
Publication Release Date: January, 2008
Revision 1.2
- 13 -
W83628AG & W83629AG
SYMBOL
IOW#
PIN
I/O
FUNCTION
LEVEL
I/O Write. IOW# is the command to an ISA I/O
slave device that the slave may latch data from the
ISA data bus (SD[15:0]).
I/O
121
5V
18t
I/O Channel Ready. Resources on the ISA Bus
negate IOCHRDY to indicate that additional time
(wait states) is required to complete the cycle.
I/O
IOCHRDY
SYSCLK
116
99
5V
18t
ISA System Clock. SYSCLK is the reference clock
for the ISA bus. The SYSCLK is generated by
dividing PCICLK by 3 or 4.
OUT
OUT
IN
5V
5V
18t
18t
t
Reset Drive. The W83628AG asserts RSTDRV to
reset devices that reside on the ISA Bus. The
W83628AG asserts this signal while the PCIRST#
is asserted.
RSTDRV
IOCS16#
SBHE#
74
124
18
16-bit I/O Chip Select. This signal is driven by I/O
devices on the ISA Bus to indicate that they support
16-bit I/O bus cycles.
5V
5V
System Byte High Enable. SBHE# asserted
indicates that a byte is being transferred on the
upper byte (SD[15:8]) of the data bus. SBHE# is at
an unknown state upon PCIRST#.
I/O
18t
I/O Channel Check. IOCHK# can be driven by any
resource on the ISA bus during the detection of an
error.
IN
IOCHK#
MEMR#
105
6
5V
5V
5V
5V
t
Memory Read. MEMR# asserted indicates the
current ISA bus cycle is a memory read.
I/O
18t
Memory Write. MEMW# asserted indicates the
current ISA bus cycle is a memory write.
I/O
18t
MEMW#
MASTER#
7
MASTER#. This signal is used with a DREQ line by
an ISA master to gain control over the ISA Bus.
IN
17
t
Unlatched Address. The LA[23:17] address lines
are bi-directional. These address lines allow
accesses to physical memory on the ISA Bus up to
16 Mbytes. LA[23:17] are outputs when the
W83628AG owns the ISA Bus.
5-2
127-125
I/O
LA[23:17]
5V
18t
Publication Release Date: January, 2008
Revision 1.2
- 14 -
W83628AG & W83629AG
SYMBOL
PIN
I/O
FUNCTION
LEVEL
ROMCS#. This pin is weak pulled-down while
PCIRST is asserted. Applying a pull-up resistor
(4.7K ohm) to this pin enables positive decoder
of BIOS address range (depending on Configure
register 70, bit 3,2). When the BIOS access
range is enabled, the pin is BIOS ROMCS#
output.
I/O
ROMCS#
73
5V
10t
Refresh. REFRESH# asserted indicates that a
refresh cycle is in progress, or that an ISA master is
requesting the W83628AG to generate a refresh
cycle. Upon PCIRST#, this signal is tri-stated.
I/O
REFRESH#
ZEROWS#
75
5V
5V
18t
Zero Wait States. An ISA slave asserts ZEROWS#
after its address and command signals are decoded
to indicate that the current cycle can be executed
as an ISA zero wait state cycle. ZEROWS# has no
effect during 16-bit I/O cycles.
IN
106
t
Standard Memory Read. SMEMR# asserted
indicates the current ISA bus cycle is a memory
read cycle to an address below 1 Mbyte.
OUT
OUT
SMEMR#
SMEMW#
117
119
5V
5V
18t
18t
Standard Memory Write. SMEMW# asserted
indicates the current ISA bus cycle is a memory
write cycle to an address below 1 Mbyte.
Bus Address Latch Enable. BALE is an active
high signal asserted by the W83628AG to indicate
that the address (SA[19:0], LA[23:17]) and SBHE#
signal lines are valid.
The LA[23:17] address lines are latched on the
trailing edge of BALE. BALE remains asserted
throughout DMA and ISA master cycles. BALE is
driven low upon PCIRST#.
OUT
BALE
122
123
5V
5V
18t
18t
Memory Chip Select 16. MEMCS16# asserted
indicates that the memory slave supports 16-bit
accesses.
I/OD
MEMCS16#
Publication Release Date: January, 2008
Revision 1.2
- 15 -
W83628AG & W83629AG
9.1.4 Power Signals
SYMBOL
PIN
I/O
FUNCTION
LEVEL
VCC
3VCC
GND
1, 82, 102, 115
27, 46, 64
PWR
5V Supply.
3.3V Supply.
Ground.
5V
PWR
PWR
3.3V
0V
16, 38, 50, 65, 95,
111, 128
9.1.5 NC Pins
SYMBOL
PIN
I/O
FUNCTION
No Connection.
LEVEL
NC
48
Publication Release Date: January, 2008
Revision 1.2
- 16 -
W83628AG & W83629AG
9.2
W83629AG PIN DESCRIPTION
9.2.1 Control Logic and Handshaking Signals
SYMBOL
HS[2:0]
PIN
I/O
FUNCTION
LEVEL
5V
Handshaking Signals. HS[2:0] are connected to
the W83628AG for PCI to ISA SET handshaking
signals.
I/O
10t
17-15
5V
NO GO. This signal indicates which master
initiates the current transaction and whether or not
the current bus cycle is targeted for the ISA bus.
This signal is a point-to-point connection between
PCI HOST Bridge and the W83628AG.
IN
NOGO
40
ts
3.3V
3.3V
PCI Bus System Clock. PCICLK provides timing
for all transactions on the PCI bus. All the other
PCI signals are sampled on the rising edge of
PCICLK, and all timing parameters are defined
with respect to this edge.
IN
IN
PCICLK
44
47
ts
ts
PCI Reset. The W83628AG receives PCIRST# as
a reset from the PCI Bus.
PCIRST#
9.2.2 PC/PCI Interface
SYMBOL
PIN
I/O
FUNCTION
LEVEL
3.3V
ISA Bus Request. This signal is a point-to-point
signal between the W83629AG and a PCI HOST
arbiter. The W83629AG asserts this signal
according to the PC/PCI protocol.
OUT
ISAREQ#
41
18t
3.3V
5V
ISA Bus Grant. This signal is a point-to-point
signal between the W83629AG and a PCI HOST
Bridge’s secondary bus PCPCIGNT# signal. The
W83629AG asserts this signal according to the
PC/PCI protocol.
IN
ISAGNT#
42
ts
DMA Request. The DREQ signal indicates that
either a slave DMA device is requesting DMA
services, or an ISA bus master is requesting to
use the ISA bus.
35,33,31,
28,26,23,
21
DRQ
IN
t
[7:5,3:0]
Publication Release Date: January, 2008
Revision 1.2
- 17 -
W83628AG & W83629AG
SYMBOL
DACK
PIN
I/O
FUNCTION
LEVEL
5V
34,32,30,
27,24,22,
20
DMA Acknowledge. The DACK# signal indicates
that either a DMA channel or an ISA bus master is
granted to the ISA bus.
OUT
18t
[7:5,3:0]#
5V
Terminal Count. The W83628AG asserts TC to
OUT
TC
19
18t
DMA slaves as a terminal count indicator.
9.2.3 IRQ Serializer Interface
SYMBOL
PIN
I/O
FUNCTION
LEVEL
3.3V
Serial Interrupt Requested Signals. This
signal is to transfer IRQ from the parallel
IRQ mode to the serial IRQ mode.
I/OD
SERIRQ
46
10t
2-6
5V
5V
IN
IN
IRQ[3:7,9:12,14,15]
IOCHK#
Parallel Interrupt Requested Input.
t
t
8-13
I/O Channel Check. IOCHK# can be driven
by any resource on the ISA bus with the
detection of an error.
36
9.2.4 Power Signals
SYMBOL
VCC
PIN
7, 14, 25
48
I/O
FUNCTION
LEVEL
5V
PWR
PWR
PWR
5V Supply.
3.3V Supply.
Ground.
3VCC
3.3V
0V
GND
1, 18, 29, 43
9.2.5 NC Pins
SYMBOL
PIN
I/O
FUNCTION
No Connection
LEVEL
NC
37, 38, 39, 45
Publication Release Date: January, 2008
Revision 1.2
- 18 -
W83628AG & W83629AG
10. PCI CONFIGURATION REGISTERS
10.1
VID-VENDOR IDENTIFICATION REGISTER
Address Offset:
Default Value:
Attribute:
01h_00h
10h_50h
Read only
This register is read-only and contains Nuvoton vendor identification number (1050h).
10.2
DID-DEVICE IDENTIFICATION REGISTER
Address Offset:
Default Value:
Attribute:
03h_02h
06h_28h
Read only
This register is read-only and contains the device identification number (0628h).
10.3
PCICMD-PCI COMMAND REGISTER
Address Offset:
Default Value:
Attribute:
05h_04h
00h_07h
Read/Write
This register provides control over the ISA bridge to generate and respond to PCI cycles properly.
When a 0 is written to this register, the ISA bridge is to be disconnected from the PCI bus for all
accesses except configuration accesses.
Bit 15:10
Bit 9
Reserved.
Fast Back to Back. This bit always returns a zero.
Bit 8
SERR# Enable.
=1
=0
Enable.
Disable.
Bit 7
Bit 6
Bit 5
Wait Cycle Control (Not supported).
Hardwired to zero.
Parity Error Response (Not supported).
Hardwired to zero.
VGA Palette Snoop Enable (Not supported).
Hardwired to zero.
Publication Release Date: January, 2008
Revision 1.2
- 19 -
W83628AG & W83629AG
Bit 4
Bit 3
Bit 2
Memory Write and Invalidate Enable (Not supported).
Hardwired to zero.
Parity Error Response (Not supported).
Hardwired to zero.
Bus Master Enable
Hardwired to one. The ISA bridge Bus Masters are always supported to generate a
PCI Bus master cycle.
Bit 1
Bit 0
Memory Space Enable
Hardwired to one. The ISA bridge Memory space is always enabled.
I/O Space Enable
Hardwired to one. The ISA bridge I/O space is always enabled.
10.4
PCISTS-PCI STATUS REGISTER
Address Offset:
Default Value:
Attribute:
07h_06h
02h_00h
Read/Write
This register shows status information for PCI bus related events.
Bit 15
Bit 14
Bit 13
Detected Parity Error
Hardwired to zero. The ISA bridge does not check bus parity.
Signaled System Error
This bit is set when ISA bridge asserts SERR# on PCI bus.
Received Master Abort Status
This bit is set when the ISA bridge is target aborted as a master on the PCI bus.
Software sets this bit to 0 by writing a 1 to it.
Bit 12
Bit 11
Received Target Abort Status
This bit is set when the ISA bridge target aborts a PCI transaction as a target.
Software sets this bit to 0 by writing a 1 to it.
Signaled Target Abort Status
This bit is set when the ISA bridge signals a target abortion for a PCI transaction.
Software sets this bit to 0 by writing a 1 to it.
Bit 10:9
Bit 8
DEVSEL# Timing. This 2 bits always return a 01b (medium decode).
Data Parity Detected (Not supported)
Hardwired to zero.
Publication Release Date: January, 2008
- 20 -
Revision 1.2
W83628AG & W83629AG
Bit 7
Fast Back-to-Back (Not supported)
Hardwired to zero.
Bit 6
66 MHz/ 33 MHz (Only support 33 MHz).
Hardwired to zero.
Bit 5
User Defineable Features (Not supported).
Hardwired to zero.
Bit 4:0
Reserved.
Reserved and will return zero when reading this register.
10.5
REVID-REVISION IDENTIFICATION REGISTER
Address Offset:
Default Value:
Attribute:
08h
See the lastest stepping information
Read Only
This register shows status information for PCI bus related events.
Bit 7:0
Revision Identification Number.
10.6
CCODE-CALSS CODE REGISTER
0Bh_0Ah_09h
Address Offset:
Default Value:
Attribute:
06h_01h_00h
Read Only
The class code register is a read-only register and used to identify the ISA bridge.
Bit 23:16
Bit 15:8
Bit 7:0
Base Class Code.
06h = Bus Bridge
Sub-Class Code.
01h = PCI to ISA Bridge
Programming Interface.
00h
Publication Release Date: January, 2008
Revision 1.2
- 21 -
W83628AG & W83629AG
10.7
HEADT-HEAD TYPE REGISTER
Address Offset:
Default Value:
Attribute:
0Eh
00h
Read Only
The register is a read-only register and used to indicate that the ISA bridge configuration space
adheres to PCI local bus specification. It also indicates that ISA bridge is not a multifunction device.
Bit 7
Multifunction Indicator.
0 = Not a multifunction device.
Layout Code.
Bit 6:0
00h = PCI layout type.
10.8
IO_RCVR-IO RECOVERY REGISTER
Address Offset:
Default Value:
Attribute:
40h
4Dh
Read/Write
Bit 7
SYSCLK Divider.
0 = SYSCLK is equal to PCICLK divided by 4.
1 = SYSCLK is equal to PCICLK divided by 3.
Bit 6
8-bit I/O Recovery Enable
0 = Disable bits 5:3 setting and use 3.5 SYSCLKs for 8 bit I/O recovery time.
1 = Enable bits 5:3 setting.
Bit 5:3
8-bit I/O RecoveryTimes.
When bit 6=1, this 3-bit field defines the additional number of SYSCLKs added to
standard 3.5 SYSCLK recovery time for 8 bit I/O
000 =0 SYSCLK
001 =1 SYSCLK
010 =2 SYSCLKs
011 =3 SYSCLKs
100 =4 SYSCLKs
101 =5 SYSCLKs
110 =6 SYSCLKs
111 = 7 SYSCLKs
Publication Release Date: January, 2008
- 22 -
Revision 1.2
W83628AG & W83629AG
Bit 2
16-bit I/O Recovery Enable.
= 0 Ignore bits 1:0 setting and uses 3.5 SYSCLKs for 16-bit I/O recovery time.
= 1 The 16-bit I/O recovery time is decided by bits 1:0.
Bit 1:0
16-bit I/O Recovery Times.
When bit 2=1, this 2-bit field defines the additional number of SYSCLKs added to
standard 3.5 SYSCLK recovery time for 16 bit I/O
= 01
= 10
= 11
= 00
1 SYSCLK
2 SYSCLKs
3 SYSCLKs
4 SYSCLKs
10.9
WISA_STS-ISA BRIDGE ERROR STATUS REGISTER
Address Offset:
Default Value:
Attribute:
42h
00h
Read/Write
Bit 7:3
Bit 2
Reserved.
IOCHK# Pin State.
This bit reflects the inverse state of the IOCHK# pin on the ISA bus.
Bit 1
Bit 0
Reserved.
Byte Lane Error.
This bit is set if the ISA bridge detects an illegal byte lane combination for a
PCI I/O cycles.
Publication Release Date: January, 2008
Revision 1.2
- 23 -
W83628AG & W83629AG
10.10
BRIDGE FAST MEMORY DECODER #0 CONTROL REGISTERS
Address Offset:
Default Value:
Attribute:
47h_46h_45h_44h
00h_00h_02h_00h
Read/Write
Bit [31:24] High Page Base Address of Fast Memory Decoder #0:
PCI A[31:24]. W83628AG will relocate the access within Fast Memory Decoder to ISA
bus, but the A[31:24] will be ignored since ISA has SA[23:0] only.
Bit [23:14] Low Base Address of Fast Memory Decoder #0:PCI A[23:14]
Bit [13:12] Reserved.
Bit 11
Enable/Disable Fast Memory Decoder #0
1=Enable, 0=Disable
Bit 10
Enable Fast Memory Decoder #0 High Page Address A[31:24] Comparison
Function.
1=Enable, 0=Disable
Bit [9:8]
Bit[7:0]
Fast Memory Decoder #0
00=Subtractive speed, 01= Slow speed, 10=Medium speed, 11=Fast speed
Fast Memory Decoder#0 Mask Control
Bit[7:0] is used to mask PCI address bits of A[23:14], respectively. If the corresponding
bit of the register is set to 1 (one), the corresponding address bits [23:14] are ignored by
the Fast Memory Address Decoder #0. The following example will show the Fast
Memory Decoder #0 size setting. If bit[7:0] = 00h, the size is 16K bytes. If bit[7:0]=01h,
the size is 32K bytes. If bit[7:0]=7fh, the size is 2M bytes. If bit[7:0]=ffh, the size is 4M
bytes.
Publication Release Date: January, 2008
- 24 -
Revision 1.2
W83628AG & W83629AG
10.11
BRIDGE FAST MEMORY DECODER #1 CONTROL REGISTERS
Address Offset:
Default Value:
Attribute:
4Bh_4Ah_49h_48h
00h_00h_02h_00h
Read/Write
Bit [31:24] High Page Base Address of Fast Memory Decoder #1: PCI A[31:24].
W83628AG will relocate the access within Fast Memory Decoder to ISA bus, but the
A[31:24] will be ignored since ISA has SA[23:0] only.
Bit [23:14] Low Base Address of Fast Memory Decoder #1:PCI A[23:14]
Bit [13:12] Reserved.
Bit 11
Enable/Disable Fast Memory Decoder #1
1=Enable, 0=Disable
Bit 10
Enable Fast Memory Decoder #1 High Page Address A[31:24] Comparison
Function.
1=Enable, 0=Disable
Bit [9:8]
Bit [7:0]
Fast Memory Decoder #1
00=Subtractive speed, 01= Slow speed, 10=Medium speed,11=Fast speed
Fast Memory Decoder#1 Mask Control
Bit[7:0] is used to mask PCI address bits of A[23:14], respectively. If the corresponding
bit of the register is set to 1 (one), the corresponding address bits [23:14] are ignored by
Fast Memory Address Decoder #1. The following example will show the Fast Memory
Decoder #1 size setting. If bit[7:0] = 00h, the size is 16K bytes. If bit[7:0]=01h, the size is
32K bytes. If bit[7:0]=7fh, the size is 2M bytes. If bit[7:0]=ffh, the size is 4M bytes.
Publication Release Date: January, 2008
- 25 -
Revision 1.2
W83628AG & W83629AG
10.12
BRIDGE FAST MEMEORY DECODER #2 CONTROL REGISTERS
Address Offset:
Default Value:
Attribute:
4Fh_4Eh_4Dh_4Ch
00h_00h_02h_00h
Read/Write
Bit [31:24] High Page Base Address of Fast Memory Decoder #2: PCI A[31:24].
W83628AG will relocate the access within Fast Memory Decoder to ISA bus, but the
A[31:24] will be ignored, since ISA has SA[23:0] only.
Bit [23:14] Low Base Address of Fast Memory Decoder #2:PCI A[23:14]
Bit [13:12] Reserved.
Bit 11
Enable/Disable Fast Memory Decoder #2.
1=Enable, 0=Disable
Bit 10
Enable Fast Memory Decoder #2 High Page Address A[31:24] Comparison
Function.
1=Enable, 0=Disable
Bit [9:8]
Bit [7:0]
Fast Memory Decoder #2.
00=Subtractive speed, 01= Slow speed, 10=Medium speed, 11=Fast speed
Fast Memory Decoder#2 Mask Control
Bit[7:0] is used to mask PCI address bits of A[23:14], respectively. If the corresponding
bit of the register is set to 1 (one), the corresponding address bits [23:14] are ignored by
Fast Memory Address Decoder #2. The following example will show the Fast Memory
Decoder #2 size setting. If bit[7:0] = 00h, the size is 16K bytes. If bit[7:0]=01h, the size is
32K bytes. If bit[7:0]=7fh, the size is 2M bytes. If bit[7:0]=ffh, the size is 4M bytes.
Publication Release Date: January, 2008
- 26 -
Revision 1.2
W83628AG & W83629AG
10.13
WISA_FADC-ISA BRIDGE FAST IO DECODERS CONTROL REGISTERS
Address Offset:
Default Value:
Attribute:
53h_52h_51h_50h
AAh_AAh_00h_00h
Read/Write
Bit [31:30] IO Decoder #7.
00=Subtractive speed, 01=Slow speed, 10=Medium speed, 11=Fast speed
Bit [29:28] IO Decoder #6.
00=Subtractive speed, 01=Slow speed, 10=Medium speed, 11=Fast speed
Bit [27:26] IO Decoder #5.
00=Subtractive speed, 01=Slow speed, 10=Medium speed, 11=Fast speed
Bit [25:24] IO Decoder #4.
00=Subtractive speed, 01=Slow speed, 10=Medium speed, 11=Fast speed
Bit [23:22] IO Decoder #3.
00=Subtractive speed, 01=Slow speed, 10=Medium speed, 11=Fast speed
Bit [21:20] IO Decoder #2.
00=Subtractive speed, 01=Slow speed, 10=Medium speed, 11=Fast speed
Bit[19:18] IO Decoder #1.
00=Subtractive speed, 01=Slow speed, 10=Medium speed, 11=Fast speed
Bit [17:16] IO Decoder #0.
00=Subtractive speed, 01=Slow speed, 10=Medium speed, 11=Fast speed
Bit 15
Enable IO Decoder #7 Address A[15:12] comparison
1=Enable, 0=Disable
Bit 14
Enable IO Decoder #6 Address A[15:12] comparison
1=Enable, 0=Disable
Publication Release Date: January, 2008
Revision 1.2
- 27 -
W83628AG & W83629AG
Bit 13
Bit 12
Bit 11
Bit10
Bit 9
Enable IO Decoder #5 Address A[15:12] comparison
1=Enable, 0=Disable
Enable IO Decoder #4 Address A[15:12] comparison
1=Enable, 0=Disable
Enable IO Decoder #3 Address A[15:12] comparison
1=Enable, 0=Disable
Enable IO Decoder #2 Address A[15:12] comparison
1=Enable, 0=Disable
Enable IO Decoder #1 Address A[15:12] comparison
1=Enable, 0=Disable
Bit 8
Enable IO Decoder #0 Address A[15:12] comparison
1=Enable, 0=Disable
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Enable/Disable Fast I/O Address Decoder # 7.
Enable/Disable Fast I/O Address Decoder # 6.
Enable/Disable Fast I/O Address Decoder # 5.
Enable/Disable Fast I/O Address Decoder # 4.
Enable/Disable Fast I/O Address Decoder # 3.
Enable/Disable Fast I/O Address Decoder # 2.
Enable/Disable Fast I/O Address Decoder # 1.
Enable/Disable Fast I/O Address Decoder # 0.
Publication Release Date: January, 2008
Revision 1.2
- 28 -
W83628AG & W83629AG
10.14
ISA_FAD0MC-ISA BRIDGE FAST DECODERS # 0 MASK CONTROL
REGISTER
Address Offset:
Default Value:
Attribute:
58h
00h
Read/Write
This register is used to mask address bits (A7~A0) for fast address decoder # 0. If the corresponding
bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address
decoder # 0.
10.15
WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 1 MASK CONTROL
REGISTER
Address Offset:
Default Value:
Attribute:
59h
00h
Read/Write
This register is used to mask address bits (A7~A0) for fast address decoder # 1. If the corresponding
bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address
decoder # 1.
10.16
WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 2 MASK CONTROL
REGISTER
Address Offset:
Default Value:
Attribute:
5Ah
00h
Read/Write
This register is used to mask address bits (A7~A0) for fast address decoder # 2. If the corresponding
bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address
decoder # 2.
10.17
WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 3 MASK CONTROL
REGISTER
Address Offset:
Default Value:
Attribute:
5Bh
00h
Read/Write
This register is used to mask address bits (A7~A0) for fast address decoder # 3. If the corresponding
bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address
decoder # 3.
Publication Release Date: January, 2008
- 29 -
Revision 1.2
W83628AG & W83629AG
10.18
WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 4 MASK CONTROL
REGISTER
Address Offset:
Default Value:
Attribute:
5Ch
00h
Read/Write
This register is used to mask address bits (A7~A0) for fast address decoder # 4. If the corresponding
bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address
decoder # 4.
10.19
WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 5 MASK CONTROL
REGISTER
Address Offset:
Default Value:
Attribute:
5Dh
00h
Read/Write
This register is used to mask address bits (A7~A0) for fast address decoder # 5. If the corresponding
bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address
decoder # 5.
10.20
WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 6 MASK CONTROL
REGISTER
Address Offset:
Default Value:
Attribute:
5Eh
00h
Read/Write
This register is used to mask address bits (A7~A0) for fast address decoder # 6. If the corresponding
bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address
decoder # 6.
10.21
WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 7 MASK CONTROL
REGISTER
Address Offset:
Default Value:
Attribute:
5Fh
00h
Read/Write
This register is used to mask address bits (A7~A0) for fast address decoder # 7. If the corresponding
bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address
decoder # 7.
Publication Release Date: January, 2008
- 30 -
Revision 1.2
W83628AG & W83629AG
10.22
WISA_FADCB0-ISA BRIDGE FAST DECODERS # 0 BASE ADDRESS
REGISTER
Address Offset:
Default Value:
Attribute:
61h_60h**
00h_00h
Read/Write
This register contains the base address for fast address decoder # 0.
**Note: 60h is the lower byte and 61h is the upper byte.
10.23
WISA_FADCB1-ISA BRIDGE FAST DECODERS # 1 BASE ADDRESS
REGISTER
Address Offset:
Default Value:
Attribute:
63h_62h
00h_00h
Read/Write
This register contains the base address for fast address decoder # 1.
10.24
WISA_FADCB2-ISA BRIDGE FAST DECODERS # 2 BASE ADDRESS
REGISTER
Address Offset:
Default Value:
Attribute:
65h_64h
00h_00h
Read/Write
This register contains the base address for fast address decoder # 2.
10.25
WISA_FADCB3-ISA BRIDGE FAST DECODERS # 3 BASE ADDRESS
REGISTER
Address Offset:
Default Value:
Attribute:
67h_66h
00h_00h
Read/Write
This register contains the base address for fast address decoder # 3.
10.26 WISA_FADCB4-ISA BRIDGE FAST DECODERS # 4 BASE ADDRESS
REGISTER
Address Offset:
Default Value:
Attribute:
69h_68h
00h_00h
Read/Write
This register contains the base address for fast address decoder # 4.
Publication Release Date: January, 2008
Revision 1.2
- 31 -
W83628AG & W83629AG
10.27
WISA_FADCB5-ISA BRIDGE FAST DECODERS # 5 BASE ADDRESS
REGISTER
Address Offset:
Default Value:
Attribute:
6Bh_6Ah
00h_00h
Read/Write
This register contains the base address for fast address decoder # 5.
10.28
WISA_FADCB6-ISA BRIDGE FAST DECODERS # 6 BASE ADDRESS
REGISTER
Address Offset:
Default Value:
Attribute:
6Dh_6Ch
00h_00h
Read/Write
This register contains the base address for fast address decoder # 6.
10.29
WISA_FADCB7-ISA BRIDGE FAST DECODERS # 7 BASE ADDRESS
REGISTER
Address Offset:
Default Value:
Attribute:
6Fh_6Eh
00h_00h
Read/Write
This register contains the base address for fast address decoder # 7.
Publication Release Date: January, 2008
Revision 1.2
- 32 -
W83628AG & W83629AG
10.30
WISA_CTRLREG1-ISA BRIDGE CONTROL REGISTER 1
Address Offset:
Default Value:
Attribute:
70h
000010ssb
Read/Write
Power-on setting bits
bit 1:0 are power-on set by ROMCS# and HS1.
Default voltage level will be internal pull-down resistance 47K ohm to logical 0 level during
PCIRST# reset cycle.
Bit 7-6
Bit 5-4
Reserved.
= 00 Send AD Bus with no STEP
= 01 Send AD Bus with 2 STEP
= 10 Send AD Bus with 4 STEP
= 11 Reverse
Bit 3-2
= 00 1MB BIOS ROM positive decode.
= 01 2MB BIOS ROM positive decode.
= 10 4MB BIOS ROM positive decode.
= 11 8MB BIOS ROM positive decode.
=0 Disable High-Address BIOS ROM decoder.
=1 Enable High-Address BIOS ROM decoder.
Bit 1
Bit 0
This bit can be set/reset by ROMCS# power-on setting during PCIRST#
assertion.
=0 Normal mode.
=1 Disable ISA Bridge subtraction decoder.
This bit can be set/reset by HS1 power-on setting during PCIRST# assertion.
Publication Release Date: January, 2008
- 33 -
Revision 1.2
W83628AG & W83629AG
10.31
WISA_CTRLREG2-ISA BRIDGE CONTROL REGISTER 2
Address Offset:
Default Value:
Attribute:
71h
00h
Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
=0 Enable IRQ11.
=0 Enable IRQ10.
=0 Enable IRQ9.
=0 Enable IRQ7
=0 Enable IRQ6.
=0 Enable IRQ5.
=0 Enable IRQ4.
=0 Enable IRQ3.
=1 Disable IRQ11.
=1 Disable IRQ10.
=1 Disable IRQ9.
=1 Disable IRQ7.
=1 Disable IRQ6.
=1 Disable IRQ5.
=1 Disable IRQ4.
=1 Disable IRQ3.
10.32
WISA_CTRLREG3-ISA BRIDGE CONTROL REGISTER 3
Address Offset:
Default Value:
Attribute:
72h
00h
Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved. Always write 0 to this bit.
Reserved. Always write 0 to this bit.
Reserved. Always write 0 to this bit.
Reserved. Always write 0 to this bit.
1=Enable IOCHK#, 0=Disable IOCHK#
0=Enable IRQ15, 1=Disable IRQ15
0=Enable IRQ14, 1=Disable IRQ14
0=Enable IRQ12, 1=Disable IRQ12
Publication Release Date: January, 2008
Revision 1.2
- 34 -
W83628AG & W83629AG
10.33
WISA_CTRLREG4-ISA BRIDGE CONTROL REGISTER 4
Address Offset:
Default Value:
Attribute:
73h
00h
Read/Write
Bit 7
Bit 6
Bit 5
=0 Enable DRQ 7. =1 Disable DRQ 7.
=0 Enable DRQ6. =1 Disable DRQ6.
=0 Enable DRQ5. =1 Disable DRQ5.
Bit 4
Reserevd. Always write 0 to this bit.
Bit 3
Bit 2
Bit 1
Bit 0
=0 Enable DRQ 3. =1 Disable DRQ 3.
=0 Enable DRQ 2. =1 Disable DRQ 2.
=0 Enable DRQ 1. =1 Disable DRQ 1.
=0 Enable DRQ 0. =1 Disable DRQ 0.
10.34
BRIDGE FAST MEMORY DECODER #3 CONTROL REGISTERS
77h_76h_75h_74h
Address Offset:
Default Value:
Bit [31:24]
00h_00h_02h_00h
High Page Base Address of Fast Memory Decoder #3: PCI A[31:24].
W83628AG will relocate the access within Fast Memory Decoder to ISA bus, but the
A[31:24] will be ignored, since ISA has SA[23:0] only.
Bit [23:14] Low Base Address of Fast Memory Decoder #3:PCI A[23:14]
Bit [13:12] Reserved.
Bit 11
Bit 10
Enable/Disable Fast Memory Decoder #3.
1=Enable, 0=Disable
Enable Fast Memory Decoder #3 High Page Address A[31:24] Comparison
Function.
1=Enable, 0=Disable
Bit [9:8]
Fast Memory Decoder #3.
00=Subtractive speed,01= Slow speed, 10=Medium speed, 11=Fast speed
Publication Release Date: January, 2008
- 35 -
Revision 1.2
W83628AG & W83629AG
Bit [7:0]
Fast Memory Decoder#3 Mask Control
Bit[7:0] is used to mask PCI address bits of A[23:14], respectively. If the corresponding
bit of the register is set to 1 (one), the corresponding address bits [23:14] are ignored by
the Fast Memory Address Decoder #3. The following example shows the Fast Memory
Decoder #3 size setting. If bit[7:0] = 00h, the size is 16K bytes. If bit[7:0]=01h, the size is
32K bytes. If bit[7:0]=7fh, the size is 2M bytes. If bit[7:0]=ffh, the size is 4M bytes.
10.35
WISA_TSTREG-ISA BRIDGE TEST REGISTER
Address Offset:
Default Value:
Attribute:
82h_81h_80h
3Fh_00h_08h
Read/Write
Bit 23
Bit 22
Reserved. No data should be written to this register.
Reserved. No data should be written to this register.
Bit [21:16] Reserved. No data should be written to this register.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit [10:8]
Bit 7
Reserved. No data should be written to this register.
Reserved
Reserved
Reserved
Reserved
Reserved. Always write 0 to the bits.
Reserved. No data should be written to this register.
Reserved. No data should be written to this register.
Reserved. No data should be written to this register.
0= 80h port decoding on subtractive cycles of LPC I/F
1= 80h port decoding on positive cycles of LPC I/F
Bit 6
Bit 5
Bit 4
This bit must be set to 1 when LPC I/F is only decoding on positive cycles, but
when the bridge is used in PIIX4 for test, set the bit to 0.
Bit 3
Bit 2
Bit 1
Bit 0
Reserved. No data should be written to this register.
Reserved. No data should be written to this register.
Reserved. No data should be written to this register.
Reserved. No data should be written to this register.
Publication Release Date: January, 2008
- 36 -
Revision 1.2
W83628AG & W83629AG
11. ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
Power Supply Voltage
-0.5 to 6.0
V
Input Voltage
-0.5 to Vcc+0.5
0 to +70
V
Operating Temperature
Storage Temperature
° C
° C
-55 to+ 150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life
and reliability of the device.
12. DC CHARACTERISTICS
(Ta = 0° C to 70° C, VCC = 5V ± 10%, 3Vcc=3.3V± 5% , GND = 0V)
PARAMETER
INt – TTL level input pin
Input Low Voltage
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
VIL
VIH
ILIH
ILIL
0.8
V
V
Input High Voltage
Input High Leakage
Input Low Leakage
2.0
+10
-10
VIN = 5 V
μA
μA
VIN = 0 V
INts - TTL level Schmitt-triggered input pin
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
Vt-
Vt+
VTH
ILIH
ILIL
0.8
1.8
0.8
0.9
1.9
1.0
1.0
2.0
V
V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VIN = 5 V
VIN = 0 V
V
Input High Leakage
Input Low Leakage
+10
-10
μA
μA
I/O10t - TTL level bi-directional pin with source-sink capability of 10 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
2.0
2.4
0.4
V
IOL = 10 mA
IOH = -10 mA
VIN = 5 V
V
+10
-10
μA
μA
VIN = 0 V
Publication Release Date: January, 2008
Revision 1.2
- 37 -
W83628AG & W83629AG
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O10tp3 – 3.3 V TTL level bi-directional pin with source-sink capability of 10 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
0.4
V
V
2.0
2.4
V
IOL = 10 mA
IOH = -10 mA
VIN = 3.3 V
VIN = 0 V
V
+10
-10
μA
μA
I/O18t - TTL level bi-directional pin with source-sink capability of 18 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
2.0
2.4
0.4
V
IOL = 18 mA
IOH = -18 mA
VIN = 5 V
V
+10
-10
μA
μA
VIN = 0 V
I/O18tp3 – 3.3 V TTL level bi-directional pin with source-sink capability of 18 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
0.4
V
V
2.0
2.4
V
IOL = 18 mA
IOH = -18 mA
VIN = 3.3 V
VIN = 0 V
V
+10
-10
μA
μA
I/OD10t – TTL level bi-directional pin. Open-drain output with 10 mA sink capability
Input Low Voltage
Input High Voltage
Output Low Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
ILIH
ILIL
0.8
V
V
2.0
0.4
+10
-10
V
IOL = 10 mA
VIN = 5V
μA
μA
VIN = 0V
I/OD18t – TTL level bi-directional pin. Open-drain output with 18 mA sink capability
Input Low Voltage
Input High Voltage
VIL
VIH
0.8
V
V
2.0
Publication Release Date: January, 2008
Revision 1.2
- 38 -
W83628AG & W83629AG
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
IOL = 18 mA
Output Low Voltage
VOL
0.4
V
Input High Leakage
Input Low Leakage
ILIH
ILIL
+10
-10
VIN = 5V
VIN = 0V
μA
μA
OD10 – Open-drain output pin with sink capability of 10 mA
Output Low Voltage VOL 0.4
OUT10t - TTL level output pin with source-sink capability of 10 mA
V
IOL = 10 mA
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
V
V
IOL = 10 mA
IOH = -10mA
2.4
OUT18t - TTL level output pin with source-sink capability of 18mA
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
V
V
IOL = 18 mA
IOH = -18 mA
2.4
Publication Release Date: January, 2008
Revision 1.2
- 39 -
W83628AG & W83629AG
13. AC CHARACTERISTICS
The PCI Bus Interface Signals are compliant with PCI Bus Specification, Rev 2.1
The ISA Bus Interface Signals conform with Abide Industry Standards.
(Ta = 0° C to 70° C, VCC = 5V ± 10%, 3Vcc=3.3V± 5% , GND = 0V
PARAMETER
PCICLK
SYM.
MIN.
TYP. MAX.
UNIT
COMMENTS
PCICLK Period
T_cyc
30
ns
PCICLK High Time
PCICLK Low Time
PCICLK Slew time
T_high
T_low
--
11
11
1
Ns
ns
4
mV/ns
Unit: 1T = 1 PCICLK period
PARAMETER SYM.
SYSCLK
MIN.
TYP. MAX. UNIT
COMMENTS
SYSCLK Period
SYSCLK High Time tSYSCLK_H
SYSCLK Low Time tSYSCLK_L
tSYSCLK
4T
3T
ns
ns
ns
ns
ns
ns
SYSCLK freq. = PCICLK freq. /4
SYSCLK freq. = PCICLK freq. /3
SYSCLK freq. = PCICLK freq. /4
SYSCLK freq. = PCICLK freq. /3
SYSCLK freq. = PCICLK freq. /4
SYSCLK freq. = PCICLK freq. /3
2T
1.5T
2T
1.5T
The following table values are measured in design simulation. The SYSCLK frequency is equal to
PCICLK frequency divided by 4.
PARAMETER
BALE
SYM.
MIN.
TYP. MAX. UNIT
COMMENTS
BALE Pulse Width
t1a
2T
6T
ns
LA[23:17]
LA[23:17] Valid Setup
to BALE Inactive
t2a
t2b
t2c
t2d
ns
ns
ns
ns
LA[23:17] Valid Hold
from BALE Inactive
6T
10.5
T
LA[23:17] Valid Setup
to MEMx# Active
1.5T
2T
LA[23:17] Valid Setuip
to IOx# Active
2T
Publication Release Date: January, 2008
Revision 1.2
- 40 -
W83628AG & W83629AG
PARAMETER
SYM.
MIN.
TYP. MAX. UNIT
COMMENTS
8-bit memory cycle
LA[23:17] Invalid from
MEMx# Active
t2e
11T
9T
ns
ns
ns
ns
16-bit memory cycle
8-bit I/O cycle
LA[23:17] Invalid from
IOx# Active
t2f
30T
18T
16-bit I/O cycle
SA[19:0], SBHE#
SA[19:0], SBHE# Valid
Setup to BALE
Inactive
t3a
t3b
2T
4T
4T
ns
ns
ns
SA[19:0], SBHE# Valid
Setup to MEMx#
Active
2T
4T
SA[19:0], SBHE# Valid
Setup to IOx# Active
t3c
t3d
SA[19:0], SBHE# Valid
Hold from MEMx#
Inactive
20T
10T
ns
ns
8-bit memory cycle
16-bit memory cycle
SA[19:0], SBHE# Valid
Hold from IOx#
Inactive
t3e
32T
20T
ns
ns
8-bit I/O cycle
16-bit I/O cycle
MEMR#, MEMW#, IOR#, and IOW#
MEMx# Active Pulse
Width (std)
t4a
t4b
t4c
t4d
t4e
t4f
18T
8T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8-bit memory cycle
16-bit memory cycle
8-bit memory cycle
16-bit memory cycle
8-bit I/O cycle
MEMx# Active Pulse
Width (nws)
6T
4T
IOx# Active Pulse (std)
18T
6T
16-bit I/O cycle
IOx# Active Pulse
(nws)
6T
8-bit I/O cycle
6T
16-bit I/O cycle
MEMx# Inactive Pulse
Width
6T
4T
6T
8-bit memory cycle
16-bit memory cycle
8-bit I/O cycle
4T
IOX# Inactive Pulse
Width
18T
18T
18T
18T
16-bit I/O cycle
SD[15:0]
SD[15:0] Read Data
Valid Setup to MEMR#
t5a
t5b
2T
2T
2T
2T
ns
ns
SD[15:0] Read Data
Valid Setup to IOR#
Publication Release Date: January, 2008
Revision 1.2
- 41 -
W83628AG & W83629AG
PARAMETER
SYM.
MIN.
TYP. MAX. UNIT
COMMENTS
SD[15:0] Read Data
Valid Hold from
MEMR# Inactive
t5c
2T
2T
2T
4T
4T
2T
ns
ns
ns
ns
ns
SD[15:0] Read Data
Valid Hold from IOR#
Inactive
t5d
t6a
t6b
t6c
2T
2T
4T
2T
SD[15:0] Write Data
Valid Setup to
MEMW# Active
SD[15:0] Write Data
Valid setup to IOW#
Active
SD[15:0] Write Data
Valid Hold from
MEMW# Inactive
SD[15:0] Write Data
Valid Hold from IOW#
Inactive
t6d
2T
2T
ns
Publication Release Date: January, 2008
Revision 1.2
- 42 -
W83628AG & W83629AG
14. WAVEFORMS
Figure 13-1: PCICLK Waveform
Figure 13-2: PCI DEVSEL# Timing Speed with Master Abort Termination
Publication Release Date: January, 2008
Revision 1.2
- 43 -
W83628AG & W83629AG
tSYSCLK
SYSCLK
tSYSCLK_H
tSYSCLK_L
Figure 13-3: SYSCLK Waveform
Figure 13-4: ISA Memory/I/O Read/Write Access Waveform
Publication Release Date: January, 2008
Revision 1.2
- 44 -
W83628AG & W83629AG
PCI Configuration Read Cycle
PCI Configuration Write Cycle
Medium DEVSEL# Speed
Medium DEVSEL# Speed
Figure 13-5: PCI Configuration Read/Write Cycle
Figure 13-6: PCI I/O Read from 8-bit ISA Device
with SA=3f8h and BE#=0000b
Publication Release Date: January, 2008
Revision 1.2
- 45 -
W83628AG & W83629AG
Figure 13-7: PCI I/O Read from 16-bit ISA Device
with SA=210h and BE#=0000b
Publication Release Date: January, 2008
Revision 1.2
- 46 -
W83628AG & W83629AG
Figure 13-8: PCI I/O Write to 8-bit ISA Device
with Write Data = 1234_5678h, SA=3f8h, and BE#=0000b
Publication Release Date: January, 2008
Revision 1.2
- 47 -
W83628AG & W83629AG
Figure 13-9: PCI I/O Write to 16-bit ISA Device
with Write Data = 1234_5678h, SA = 3f8h, and BE#=0000b
Publication Release Date: January, 2008
Revision 1.2
- 48 -
W83628AG & W83629AG
Figure 13-10: PCI Memory Read from 8-bit ISA Device
with SA=55_5558h and BE#=0000b
Publication Release Date: January, 2008
Revision 1.2
- 49 -
W83628AG & W83629AG
Figure 13-11: PCI Memory Read from 16-bit ISA Device
with SA=33ch and BE#=0000b
Publication Release Date: January, 2008
Revision 1.2
- 50 -
W83628AG & W83629AG
Figure 13-12: PCI Memory Write to 8-bit ISA Device
with Write Data=1234_5678h, SA=778h and BE#=0000b
Publication Release Date: January, 2008
Revision 1.2
- 51 -
W83628AG & W83629AG
Figure 13-13: PCI Memory Write to 16-bit ISA Device
with Write Data = 1234_5678h, SA=1778h, and BE#=0000b
Publication Release Date: January, 2008
Revision 1.2
- 52 -
W83628AG & W83629AG
Figure 13-14: ISA Master Memory Read from PCI
with Even Address SA and SBHE#=0b
Publication Release Date: January, 2008
Revision 1.2
- 53 -
W83628AG & W83629AG
Figure 13-15: ISA Master Memory Read from PCI
with Even Address SA and SBHE#=1b
Publication Release Date: January, 2008
Revision 1.2
- 54 -
W83628AG & W83629AG
Figure 13-16: ISA Master Memory Write to PCI
with Even Address SA and SBHE#=0b
Publication Release Date: January, 2008
Revision 1.2
- 55 -
W83628AG & W83629AG
Figure 13-17: ISA Master Memory Write to PCI
with Even Address SA and SBHE#=1b
Figure 13-18: DRQn/DACKn# Coding in PC/PCI DMA Function
Publication Release Date: January, 2008
Revision 1.2
- 56 -
W83628AG & W83629AG
Figure 13-19: DRQn/DACKn# Coding in PC/PCI DMA Function
with Drive ISAREQ# Inactive for One Clock to Signal New Request Information
Figure 13-20: DRQn/DACKn# Coding in PC/PCI DMA Function
with Drive ISAREQ# Inactive for Two Clocks to Signal New Request Information (Previous DRQn had
been granted the bus)
Publication Release Date: January, 2008
- 57 -
Revision 1.2
W83628AG & W83629AG
15. TOP MARKING SPECIFICATION
inbond
W83628AG
131AE211113302SA
1st line: Chip logo
2nd line: The type number: W83628AG （the “G” means Pb-free package）
3th line: The tracking code 131 A E 211113302SA
131: Packages made in '01, week 31
A: Assembly house ID;
E: IC revision. A means version A; B means version B
21111330: Wafer production series lot number
2SA: Nuvoton internal use.
W83629AG
131AD
1nd line: The type number: W83629AG （the “G” means Pb-free package）
2th line: The tracking code 131 AD
131: Packages made in '01, week 31
A: Assembly house ID.
D: IC revision. A means version A; B means version B.
Publication Release Date: January, 2008
Revision 1.2
- 58 -
W83628AG & W83629AG
16. PACKAGE DIMENSIONS 1 FOR W83628AG (128-PIN PQFP)
Dimension in mm
Dimension in inch
HE
E
Symbol
Min
0.25
2.57
Nom
0.35
Max
0.45
2.87
Min Nom Max
65
102
1
A
0.010
0.101
0.014
0.107
0.018
0.113
2.72
A
2
64
103
0.10
0.10
0.20
0.15
0.30
0.20
0.004 0.008 0.012
0.004 0.006 0.008
0.547 0.551 0.555
b
c
D
E
e
13.90
19.90
14.00
20.00
0.50
14.10
20.10
0.783 0.787
0.020
0.791
HD
D
H
D
17.20
23.20
0.669
0.677 0.685
0.921
17.40
23.40
0.95
17.00
23.00
0.905 0.913
HE
L
0.80
1.60
0.025 0.031 0.037
0.063
0.65
39
128
1
L
0.08
7
y
0.003
1
38
e
b
0
7
0
0
c
Note:
A
1.Dimension D & E do not include interlead
flash.
2
A
2.Dimension b does not include dambar
protrusion/intrusion
.
3.Controlling dimension : Millimeter
4.General appearance spec. should be based
on final visual inspection spec.
1
A
See Detail F
Seating Plane
L
y
L 1
Detail F
5. PCB layout please use the "mm".
17. PACKAGE DIMENSIONS 2 FOR W83629AG (48-PIN LQFP)
H
D
D
25
36
Dimension in inch
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
1.60
0.15
1.45
---
---
---
0.05
1.35
1
A
24
37
1.40
0.20
---
2
A
0.17
0.09
0.27
0.20
b
c
E
E
7.00
7.00
H
D
E
e
0.50
9.00
9.00
D
H
HE
L
L
y
48
13
0.45
0.75
0.60
1.00
0.08
3.5
1
---
0
---
7
1
12
e
b
0
Notes:
c
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
2
A
A
A1
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
See Detail F
L
y
Seating Plane
L
1
Detail F
Publication Release Date: January, 2008
Revision 1.2
- 59 -
W83628AG & W83629AG
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of
Nuvoton products could result or lead to a situation wherein personal injury, death or severe
property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper
use or sales.
Publication Release Date: January, 2008
- 60 -
Revision 1.2
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