10020EV8-4A [NXP]
ECL programmable array logic; ECL可编程阵列逻辑
| 型号： | 10020EV8-4A |
| 厂家： | 
NXP |
| 描述： | ECL programmable array logic |
| 文件： | 总17页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
The 10H20EV8/10020EV8 also features the
ability to Preload the registers to any desired
state during testing. The Preload is not
affected by the pattern within the device, so
can be performed at any step in the testing
sequence. This permits full logical verification
even after the device has been patterned.
DESCRIPTION
PIN CONFIGURATIONS
The 10H20EV8/10020EV8 is an ultra
F Package
high-speed universal ECL PAL device.
Combining versatile output macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user’s custom logic. The use of Philips
Semiconductors state-of-the-art bipolar oxide
isolation process enables the
10H20EV8/10020EV8 to achieve optimum
speed in any design. The SNAP design
software package from Philips
1
2
24
23
22
21
20
19
18
17
16
15
14
13
I
I
V
I
1
CC
2
11
3
CLK/I
I
10
12
4
F
F
F
1
2
8
7
FEATURES
5
F
• Ultra high speed ECL device
6
V
V
F
CO1
CO2
– t = 4.5ns (max)
PD
7
F
3
6
5
Semiconductors simplifies design entry
based upon Boolean or state equations.
– t = 2.6ns (max)
IS
8
F
4
F
I
– t
– f
= 2.3ns (max)
= 208MHz
CKO
MAX
9
I
3
9
The 10H20EV8/10020EV8 is a two-level logic
element comprised of 11 fixed inputs, an
input pin that can either be used as a clock or
12th input, 90 AND gates, and 8 Output Logic
Macrocells. Each Output Macrocell can be
individually configured as a dedicated input,
dedicated output with polarity control, a
bidirectional I/O, or as a registered output
that has both output polarity control and
feedback to the AND array. This gives the
part the capability of having up to 20 inputs
and eight outputs.
10
11
12
I
I
I
I
4
8
• Universal ECL Programmable Array Logic
– 8 user programmable output macrocells
– Up to 20 inputs and 8 outputs
I
5
7
6
V
EE
F = Ceramic DIP (300mil-wide)
– Individual user programmable output
polarity
• Variable product term distribution allows
A Package
increased design capability
NC
1
CLK/I
I
I
V
I
I
12
2
1
CC 11 10
28 27 26
• Asynchronous Preset and Reset capability
• 10KH and 100K options
4
3
2
5
6
25
24
23
22
21
20
19
F
F
F
F
The 10H20EV8/10020EV8 has a variable
number of product terms that can be OR’d
per output. Four of the outputs have 12 AND
terms available and the other four have 8
terms per output. This allows the designer the
extra flexibility to implement those functions
that he couldn’t in a standard PAL device.
Asynchronous Preset and Reset product
terms are also included for system design
ease. Each output has a separate output
enable product term. Another feature added
for the system designer is a power-up Reset
on all registered outputs.
1
2
8
7
• Power-up Reset and Preload function to
enhance state machine design and testing
7
V
V
CO2
CO1
NC
NC
8
• Design support provided via SNAP and
other CAD tools
9
F
3
F
6
• Security fuse for preventing design
10
11
F
4
F
5
duplication
I
I
3
9
• Available in 24-Pin 300mil-wide DIP and
12 13 14 15 16 17 18
NC
28-Pin PLCC.
I
I
I
I
I
8
V
4
5
6
7
EE
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
DRAWING NUMBER
10H20EV8–4F
10020EV8–4F
24-Pin Ceramic Dual In-Line (300mil-wide)
28-Pin Plastic Leaded Chip Carrier
0586B
10H20EV8–4A
10020EV8–4A
0401F
PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
113
October 22, 1993
853–1423 11164
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
LOGIC DIAGRAM
INPUT LINES
16 20
3
0
4
8
12
24
28
32
36
D
0
OUTPUT
LOGIC
MACRO
CELL
4
7
D
0
OUTPUT
LOGIC
MACRO
CELL
21
7
1
D
0
OUTPUT
LOGIC
MACRO
CELL
5
20
7
11
2
D
0
OUTPUT
LOGIC
MACRO
CELL
11
9
D
0
OUTPUT
LOGIC
MACRO
CELL
11
10
D
0
OUTPUT
LOGIC
MACRO
CELL
18
11
11
D
0
OUTPUT
LOGIC
MACRO
CELL
8
7
13
D
0
OUTPUT
LOGIC
MACRO
CELL
17
7
14
15
16
23
22
ASYNCHRONOUS RESET
ASYNCHRONOUS PRESET
NOTES:
1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”
2. Programmable connections
3. Pinout for F Package
114
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
FUNCTIONAL DIAGRAM
CLK/I
I
1
11
PROGRAMMABLE AND ARRAY
(90 × 40)
12
12
8
8
8
8
12
12
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
RESET
PRESET
F
F
F
F
F
F
F
F
As can be seen in the Logic Diagram, the
device is a two-level logic element with a
programmable AND array. The 20EV8 can
have up to 20 inputs and 8 outputs. Each
output has a versatile Macrocell whereby the
output can either be configured as a
dedicated input, a dedicated combinatorial
output with polarity control, a bidirectional I/O,
or as a registered output that has both output
polarity control and feedback into the AND
array.
The device also features 90 product terms.
Two of the product terms can be used for a
global asynchronous preset and/or reset.
Eight of the product terms can be used for
individual output enable control of each
Macrocell. The other 80 product terms are
distributed among the outputs. Four of the
outputs have eight product terms, while the
other four have 12. This arrangement allows
the utmost in flexibility when implementing
user patterns.
FUNCTIONAL DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL-type device.
Combining versatile Output Macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user’s custom logic.
Output Logic Macrocell
The 10H20EV8/10020EV8 incorporates an
extremely versatile Output Logic Macrocell
that allows the user complete flexibility when
configuring outputs.
F
n
AP
As seen in Figure 1, the 10H20EV8/
OUTPUT
SELECT
MUX
D
Q
Q
10020EV8 Output Logic Macrocell consists of
an edge-triggered D-type flip-flop, an output
select MUX, and a feedback select MUX.
S
S
0
CLK
1
V
CC
Fuses S and S allow the user to select
0
1
AR
between the various cells. S controls
1
whether the output will be either registered
with internal feedback or combinatorial I/O.
FEEDBACK
MUX
S controls the polarity of the output (Active-
HIGH or Active-LOW). This allows the user to
achieve the following configurations:
0
S
1
V
CC
Registered Active-HIGH output, Registered
Active-LOW output, Combinatorial Active-
HIGH output, and Combinatorial Active-LOW
output. With the output enable product term,
this list can be extended by adding the
configurations of a Combinatorial I/O with
Polarity or another input.
Figure 1. Output Logic Macrocell
115
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
V
V
EE
V
IN
Supply voltage
–8.0
Input voltage (V should never be more negative than V
)
0 to V
EE
V
IN
EE
I
Output source current
–50
–55 to +150
+165
mA
°C
°C
°C
O
T
Operating Temperature range
Storage Temperature range
S
J
T
Ceramic Package
Plastic Package
+150
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.
DC OPERATING CONDITIONS 10H20EV8
TEST
LIMITS
NOM
0
SYMBOL
, V , V
CO2
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
V
V
Circuit ground
0
0
CC
CO1
Supply voltage (negative)
High level input voltage
–5.2
V
EE
T
= 0°C
–1170
–1130
–1070
–1950
–1950
–1980
0
–840
–810
–735
–1480
–1480
–1450
+75
mV
mV
mV
mV
mV
mV
°C
amb
V
V
T
amb
= +25°C
= +75°C
IH
T
amb
T
amb
= 0°C
Low level input voltage
T
amb
= +25°C
= +75°C
IL
T
amb
T
Operating ambient temperature range
+25
amb
NOTE:
When operating at other than the specified V voltage (–5.2V), the DC and AC Electrical Characteristics will vary slightly from specified values.
EE
DC OPERATING CONDITIONS 10020EV8
TEST
LIMITS
NOM
0
SYMBOL
, V , V
CO2
PARAMETER
CONDITIONS
MIN
0
MAX
0
UNIT
V
CC
V
EE
V
EE
Circuit ground
Supply voltage
V
V
V
CO1
–4.8
–5.7
–4.5
–4.2
Supply voltage when opetating with the 10K
or 10KH ECL family
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
= –4.2V
= –4.5V
= –4.8V
= –4.2V
= –4.5V
= –4.8V
–1150
–1165
–1165
V
V
High level input voltage
–880
mV
IH
IL
–1475
–1475
–1490
+85
mV
mV
mV
°C
Low level input voltage
–1810
0
T
amb
Operating ambient temperature range
+25
NOTE:
When operating at other than the specified V voltages (–4.2V, –4.5V, –4.8V), the DC and AC Electrical Characteristics will vary slightly from
EE
their specified values.
116
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
D
D
AP
AP
D
Q
Q
D
Q
Q
CK
CK
AR
AR
Registered Active-HIGH
Registered Active-LOW
D
D
Combinatorial Active-HIGH
Combinatorial Active-LOW
Figure 2. Output Macro Cell Configurations
controlled by a programmed pattern. A HIGH
on the D term enables the output, while a
LOW performs the disable function. Output
enable control can be achieved by
Active-HIGH and Active-LOW, a Preset
signal will force the Active-HIGH outputs
HIGH while the Active-LOW outputs would go
LOW, even though the Q output of all
flip-flops would go HIGH. A Reset signal
would force the opposite conditions.
OUTPUT MACRO CELL
CONFIGURATION
Shown in Figure 2 are the four possible
configurations of the output macrocell using
programming a pattern on the D term.
fuses S and S . As seen, the output can
0
1
either be registered Active-HIGH/LOW with
feedback or combinatorial Active-HIGH/LOW
with feedback. If the registered mode is
chosen, the feedback from the Q output to
the AND array enables one to make state
machines or shift registers without having to
tie the output to one of the inputs. If a
combinatorial output is chosen, the feedback
gate is enabled from the pin and allows one
to create permanent outputs, permanent
inputs, or I/O pins through the use of the
output enable (D) product term.
The output enable control can also be used
to expand a designer’s possibilities once a
combinatorial output has been chosen. If the
D term is always HIGH, the pin becomes a
permanent Active-HIGH/LOW output. If the
D term is always LOW (all fuses left intact),
the pin now becomes an extra input.
PRELOAD
To simplify testing, the 10H20EV8/10020EV8
has also included PRELOAD circuitry. This
allows a user to load any particular data
desired into the registers regardless of the
programmed pattern. This means that the
PRELOAD can be done on a blank part and
after that same part has been programmed to
facilitate any post-fuse testing desired.
PRESET AND RESET
The 10H20EV8/10020EV8 also includes a
separate product term for asynchronous
Preset and asynchronous Reset. These lines
are common for all registers and are asserted
when the specific product term goes HIGH.
Being asynchronous, they are independent of
the clock. It should be noted that the actual
state of the output is dependent on how the
polarity of the particular output has been
chosen. If the outputs are a mix of
It can also be used by a designer to help
debug a circuit. This could be important if a
state machine was implemented in the
10H20EV8/ 10020EV8. The PRELOAD
would allow the entry of any state in the
sequence desired and start clocking from that
particular point. Any or all transitions could be
verified.
OUTPUT ENABLE
Each output on the 10H20EV8/10020EV8
has its own individual product term for output
enable. The use of the D product term
(direction control) allows the user three
possible configurations of the outputs. They
are: always enabled, always disabled, and
117
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
DC ELECTRICAL CHARACTERISTICS 10H20EV8
0°C ≤ T
≤ +75°C, V = –5.2V ± 5%, V = V
= V = GND
amb
EE
CC
CO1
CO2
4
LIMITS
1
2
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
MIN
MAX
UNITS
V
High level output voltage
V
V
= V MIN or V MAX
0°C
+25°C
+75°C
–1020
–980
–920
–840
–810
–735
OH
IN
IH
IL
mV
V
OL
Low level output voltage
= V MIN or V MAX
0°C
+25°C
+75°C
–1950
–1950
–1950
–1630
–1630
–1600
IN
IH
IL
mV
I
I
High level input current
Low level input current
Supply current
V
V
= V MAX
0°C
+75°C
IH
IN
IH
220
µA
µA
= V MIN
0°C
+75°C
IL
IN
IL
Except I/O Pins
0.3
–I
V
EE
= MAX
0°C to +75°C
EE
All inputs = V MAX
250
mA
IH
DC ELECTRICAL CHARACTERISTICS 10020EV8
0°C ≤ T
≤ +85°C, –4.8V ≤ V ≤ –4.2V, V = V
= V
= GND
amb
EE
CC
CO1
CO2
4
LIMITS
1
2
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
V
V
V
V
V
V
V
V
V
V
V
V
= –4.2V –1020
= –4.5V –1025
= –4.8V –1035
= –4.2V –1030
= –4.5V –1035
= –4.8V –1045
= –4.2V
–870
–880
–880
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
µA
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
V
V
V
V
High level output voltage
V
= V MAX or V MIN
–955
OH
IN
IH
IL
Outputs
Loaded
Apply V
or V
to
IHMIN
ILMAX
High level output threshold voltage
one input at a time, other
or V
OHT
OLT
OL
with 50Ω inuts at V
IHMAX
ILMIN.
to –2.0V
Apply V
or V
to
–1595
–1610
–1610
–1605
IHMIN
ILMAX
Low level output threshold voltage ± 0.010V one input at a time, other
= –4.5V
inuts at V
Inuts at V
or V
or V
= –4.8V
IHMAX
ILMIN.
= –4.2V –1810
Low level output voltage
= –4.5V –1810 –1705 –1620
IHMAX
ILMIN.
= –4.8V –1830
–1620
220
I
I
High level input current
Low level input current
One input under test at V
. Other inputs at
IH
IHMAX
V
ILMIN
.
One input under test at V
. Other inputs at
0.5
µA
IL
ILMIN
V
IHMAX
.
–I
EE
V
EE
supply current
All inputs at V .
IHMAX
230
mA
NOTES:
1. All voltage measurements are referenced to the ground terminal.
2. Each ECL 10KH/100K series device has been designed to meet the DC specification after thermal equilibrium has been established.
Thermal equilibrium is established by applying power for at least 2 minutes, while maintaining transverse airflow of 2.5 meters/sec (500
linear feet/min.) over the device, mounted either in a test socket or on a printed circuit board. Test voltage values are given in the DC
operating conditions table. Conditions for testing shown in the tables are not necessarily worst case. For worst case testing guidelines, refer
to DC Testing, Chapter 1, Section 3, of the Philips Semiconductors 10/100K ECL Data Handbook.
3. Terminals not specifically referenced can be left electrically open. Open inputs assume a logic LOW state. Any unused pins can be
terminated to –2V. If tied to V , it must be through a resistor > 10K. It is recommended that pins that have been programmed as RESET,
EE
PRESET, or CLOCK inputs not be left open due to the possibility of false triggering from internally and externally generated switching
transients.
4. The specified limits represent the worst case values for the parameter. Since these worst case values normally occur at the supply voltage
and temperature extremes, additional noise immunity can be achieved by decreasing the allowable operating condition ranges.
118
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
AC ELECTRICAL CHARACTERISTICS (for Ceramic Dual In-Line Package)
10H20EV8: 0°C ≤ T
≤ +75°C, V = –5.2V ± 5%, V = V
= V
= GND
amb
EE
CC
CO1
CO2
10020EV8: 0°C ≤ T
≤ +85°C, –4.8V ≤ V ≤ –4.2V, V = V
= V
= GND
amb
EE
CC
CO1
CO2
1
LIMITS
SYMBOL
PARAMETER
FROM
TO
0°C
+25°C
+75°C/+85°C
UNIT
MAX
MAX
MAX
2
3
2
3
2
3
MIN
TYP
MIN
TYP
MIN
TYP
2
2
2
Pulse Width
t
t
t
t
Clock High
CLK +
CLK –
CLK –
CLK +
2.0
2.0
4.0
4.5
0.6
0.9
2.0
2.0
4.0
4.5
0.6
0.9
2.0
2.0
4.0
4.5
0.6
0.9
ns
ns
ns
ns
CKH
CKL
CKP
PRH
Clock Low
Clock Period
Preset/Reset Pulse
CLK +
CLK +
(I, I/O) ±
(I, I/O) ±
—
—
—
Setup and Hold Time
t
t
t
Input
Input
(I, I/O) ±
CLK +
CLK +
(I, I/O) ±
CLK +
2.6
0.1
4.6
1.0
< 0
1.0
2.6
0.1
4.6
1.1
< 0
0.9
2.7
0.1
4.6
1.4
< 0
0.8
ns
ns
ns
IS
IH
Clock Resume after
Preset/Reset
(I, I/O) ±
PRS
Propagation Delay
t
t
t
t
t
t
f
Input
(I, I/O) ±
CLK +
I/O ±
I/O ±
I/O
2.85
1.65
2.0
4.7
2.4
4.2
4.2
4.7
10
2.95
1.7
2.1
2.1
3.0
—
4.7
2.4
4.2
4.2
4.7
10
3.35
2.0
2.2
2.2
3.5
—
4.7
2.5
4.2
4.2
4.7
10
ns
ns
PD
Clock
CKO
OE
Output Enable
Output Disable
Preset/Reset
Power-on Reset
(I, I/O) ±
(I, I/O) ±
(I, I/O) ±
ns
I/O
2.0
ns
OD
I/O ±
I/O
2.8
ns
PRO
PPR
MAX
V
EE
—
ns
212
377
212
357
204
294
MHz
NOTES:
1. Refer to AC Test Circuit and Voltage Wafeforms diagrams.
2. Maximum loading conditions: 89 fuses intact per row.
3. Typical loading conditions: 15 fuses intact per row. (All “inactive” fuses, except those necessary for correct functionality, are removed.)
119
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
AC ELECTRICAL CHARACTERISTICS (for Plastic Leaded Chip Carrier)
10H20EV8: 0°C ≤ T
≤ +75°C, V = –5.2V ± 5%, V = V
= V
= GND
amb
EE
CC
CO1
CO2
10020EV8: 0°C ≤ T
≤ +85°C, –4.8V ≤ V ≤ –4.2V, V = V
= V
= GND
amb
EE
CC
CO1
CO2
1
LIMITS
SYMBOL
PARAMETER
FROM
TO
0°C
+25°C
+75°C/+85°C
UNIT
MAX
MAX
MAX
3
3
3
MIN
TYP
MIN
TYP
MIN
TYP
2
2
2
Pulse Width
t
t
t
t
Clock High
CLK +
CLK –
CLK –
CLK +
2.0
2.0
4.0
4.5
0.6
0.9
2.0
2.0
4.0
4.5
0.6
0.9
2.0
2.0
4.0
4.5
0.6
0.9
ns
ns
ns
ns
CKH
CKL
CKP
PRH
Clock Low
Clock Period
Preset/Reset Pulse
CLK +
CLK +
(I, I/O) ±
(I, I/O) ±
—
—
—
Setup and Hold Time
t
t
t
Input
Input
(I, I/O) ±
CLK +
CLK +
(I, I/O) ±
CLK +
2.5
0
1.0
< 0
1.0
2.5
0
1.1
< 0
0.9
2.6
0
1.4
< 0
0.8
ns
ns
ns
IS
IH
Clock Resume after
Preset/Reset
(I, I/O) ±
4.5
4.5
4.5
PRS
Propagation Delay
t
t
t
t
t
t
f
Input
(I, I/O) ±
CLK +
I/O ±
I/O ±
I/O
2.85
1.65
2.0
4.5
2.2
4.0
4.0
4.5
10
2.95
1.7
2.1
2.1
3.0
—
4.5
2.2
4.0
4.0
4.5
10
3.35
2.0
2.2
2.2
3.5
—
4.5
2.3
4.0
4.0
4.5
10
ns
ns
PD
Clock
CKO
OE
Output Enable
Output Disable
Preset/Reset
Power-on Reset
(I, I/O) ±
(I, I/O) ±
(I, I/O) ±
ns
I/O
2.0
ns
OD
I/O ±
I/O
2.8
ns
PRO
PPR
MAX
V
EE
—
ns
212
377
212
357
204
294
MHz
NOTES:
1. Refer to AC Test Circuit and Voltage Wafeforms diagrams.
2. Maximum loading conditions: 89 fuses intact per row.
3. Typical loading conditions: 15 fuses intact per row. (All “inactive” fuses, except those necessary for correct functionality, are removed.)
120
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
AC TEST CIRCUIT
+2.0V + 0.010V
25µF
0.1µF
V
I
V
V
CO2
CO1
CC
L
L
L
3
2
1
PULSE
GENERATOR
SCOPE
F
X
1
C
L
R
T
I
DUT
11
CLK/I
12
SCOPE
F
Y
F
M
R
T
F
N
V
EE
25µF
0.01µF
–2.5V + 0.010V FOR 10020EV8
–3.2V + 0.010V FOR 10H20EV8
NOTES:
1. Use decoupling capacitors of 0.1µF and 25µF from GND to V , and 0.01µF and 25µF from GND to V (0.01 and 0.1µF capacitors
CC
EE
should be NPO Ceramic or MLC type). Decoupling capacitors should be placed as close as physically possible to the DUT and lead
1
length should be kept to less than / inch (6mm).
4
2. All unused inputs should be connected to either HIGH or LOW state consistent with the LOGIC function required.
3. All unused outputs are loaded with 50Ω to GND.
4. L and L are equal length 50Ω impedance lines. L , the distance from the DUT pin to the junction of the cable from the Pulse
1
2
3
1
Generator and the cable to the Scope, should not exceed / inch (6mm).
4
5. R = 50Ω terminator internal to Scope.
6. The unmatched wire stub between coaxial cable and pins under test must be less than / inch (6mm) long for proper test.
T
1
4
7. C = Fixture and stray capacitance ≤ 3pF.
L
8. Any unterminated stubs connected anywhere along the transmission line between the Pulse Generator and the DUT or between the
1
DUT and the Scope should not exceed / inch (6mm) in length (refer to section on AC setup procedure).
4
9. All 50Ω resistors should have tolerance of ± 1% or better.
10.Test procedures are shown for only one input or set of input conditions. Other inputs are tested in the same manner.
121
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
VOLTAGE WAVEFORMS
t
t
TLH
THL
+1110mV (10H20EV8)
+1050mV (10020EV8)
80%
50%
80%
50%
NEGATIVE
PULSE
20%
80%
20%
80%
+310mV
t
t
(L)
(H)
W
W
+1110mV (10H20EV8)
+1050mV (10020EV8)
POSITIVE
PULSE
50%
20%
50%
20%
+310mV
t
t
THL
TLH
INPUT PULSE REQUIREMENTS
= +2.0V +0.010V, V = –3.2V + 0.010V, V = GND (0V)
V
= V
CO1
= V
CO2
CC
EE
REP RATE PULSE WIDTH
T
t
t
FAMILY
AMPLITUDE
TLH
THL
800mV
P–P
10KH ECL
1MHz
INPUT PULSE REQUIREMENTS
= +2.0V +0.010V, V = –2.5V + 0.010V, V = GND (0V)
500ns
1.3 + 0.2ns
1.3 + 0.2ns
V
= V
CO1
= V
CC
CO2
EE
REP RATE PULSE WIDTH
T
t
t
FAMILY
AMPLITUDE
TLH
THL
740mV
P–P
100K ECL
1MHz
500ns
0.7 + 0.1ns
0.7 + 0.1ns
Input Pulse Definition
122
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
TIMING DIAGRAMS
I, I/O
(INPUT)
50%
50%
t
IH
t
IS
50%
50%
50%
CLK
t
t
t
CKL
CKH
t
CK
P
CKO
I/O
(REGISTERED
OUTPUT)
50%
t
PD
I/O
(COMBINATORIAL
OUTPUT)
50%
Flip-Flop and Gate Outputs
0V
V
= –4.94 10H20EV8
= –4.2 10020EV8
EE
EE
V
V
EE
t
PPR
REGISTERED
ACTIVE-LOW
OUTPUT
I, I/O
(INPUT)
50%
t
IS
t
CLK
50%
50%
Power-On Reset
123
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
TIMING DIAGRAMS (Continued)
I, I/O
50%
50%
(INPUT)
t
t
OE
OD
I/O
(OUTPUT)
50%
50%
Output Enable/Disable
50%
CLK
t
PRS
ASYNCHRONOUS
PRESET/RESET
50%
50%
t
PRH
t
PRO
I/O
(OUTPUT)
50%
Asynchronous Preset/Reset
124
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
REGISTER PRELOAD
The 10H20EV8/10020EV8 has included
circuitry that allows a user to load data into
the output registers. Register PRELOAD can
be done at any time and is not dependent on
any particular pattern programmed into the
device. This simplifies the ability to fully verify
logic states and sequences even after the
device has been patterned.
The pin levels and sequence necessary to
perform the register PRELOAD are shown
below.
V
IH
PIN 3
V
PP
PIN 23
V
V
IH
OH
OUTPUTS
V
V
IL
OL
DISABLE OUTPUTS
ENABLE PRELOAD
APPLY EXTERNAL
INPUTS TO BE
PRELOADED
DATA PRELOADED
AND PRELOAD
DISABLED
REMOVE EXTERNAL
INPUTS
LIMITS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Input HIGH level during
PRELOAD and Verify
V
V
V
–1.1
–0.9
–0.7
V
IH
Input LOW level during
PRELOAD and Verify
–1.85
1.45
–1.65
1.6
–1.45
1.75
V
V
IL
PRELOAD enable voltage
PP
applied to I
11
NOTE:
1. Unused inputs should be handled as follows:
–
–
–
–
Set at V or V
Terminated to –2V
IH IL
Tied to V through a resistor > 10K
EE
Open
125
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
All packages allow Boolean and state
program table entry format is supported by
SNAP only.
LOGIC PROGRAMMING
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.
The 10H20EV8/10020EV8 is fully supported
by industry standard (JEDEC compatible)
PLD CAD tools, including Philips
Semiconductors SNAP design software
package. ABEL and CUPL design
software packages also support the
10H20EV8/10020EV8.
To implement the desired logic functions, the
state of each logic variable from logic
equations (I, F, Q, etc.) is assigned a symbol.
The symbols for TRUE, COMPLEMENT,
INACTIVE, PRESET, etc., are defined below.
10H20EV8/10020EV8 logic designs can also
be generated using the program table entry
format detailed on the following page. This
“AND” ARRAY – (I), (F), (Q )
p
I, F, Q
I, F, Q
I, F, Q
I, F, Q
I, F, Q
I, F, Q
I, F, Q
I, F, Q
I, F, Q
I, F, Q
I, F, Q
I, F, Q
P, D, AP, AR
P, D, AP, AR
P, D, AP, AR
CODE
P, D, AP, AR
STATE
1, 2
CODE
O
STATE
I, F, Q
CODE
H
STATE
I, F, Q
STATE
CODE
–
L
DON’T CARE
INACTIVE
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (P, D, AP, AR) will be unconditionally inhibited if any one of the I, F or Q link pairs is left intact.
OUTPUT MACROCELL CONFIGURATIONS
CONTROL WORD
OUTPUT MACROCELL CONFIGURATION
POLARITY FUSE
FUSE
Registered Output, Active-HIGH
Registered Output, Active-LOW
Combinatorial I/O, Active-HIGH
Combinatorial I/O, Acitve-LOW
D
H
1
1
D
L
B
B
H
L
NOTE:
1. This is the initial (unprogrammed) state of the device.
PROGRAMMING AND
SOFTWARE SUPPORT
Refer to Section 9 (Development Software)
and Section 10 (Third-party Programmer/
Software Support) of the 1992 PLD Data
Handbook for additional information.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
126
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
PROGRAM TABLE
CONTROL WORD
POLARITY
T
E
R
M
AND
2
OR (FIXED)
F(O)
I
F(I)
4
12 11 10
9
8
7
6
5
4
3
1
8
7
6
5
3
2
1
8
7
6
5
4
3
2
1
0
D
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
D
A
A
A
A
A
A
A
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
AR
AP
D
A
A
A
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
PIN
3
23 22 16 15 14 13 11 10
9
2
1
21 20 18 17
8
7
5
4
127
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
SNAP’s simulator uses a synthetic logic
analyzer format to display and set the nodes
of the design. The SNAP simulator provides
complete timing information, setup and
hold-time checking, plus toggle and fault
grading analysis.
SNAP
• JEDEC fuse map generated from netlist
Features
SNAP (Synthesis, Netlist, Analysis and
Program) is a versatile development tool that
speeds the design and testing of PML. SNAP
combines a user-friendly environment and
powerful modules that make designing with
PML simple. The SNAP environment gives
the user the freedom to design independent
of the device architecture.
• Schematic entry using DASH 4.0 or
above or OrCAD SDT III
• State Equation Entry
SNAP operates on an IBM PC/XT, PC/AT,
PS/2, or any compatible system with DOS
2.1 or higher. A minimum of 640K bytes of
RAM is required together with a hard disk.
• Boolean Equation Entry
• Allows design entry in any combination of
above formats
The flexibility in the variations of design entry
methodologies allows design entry in the
most appropriate terms. SNAP merges the
inputs, regardless of the type, into a high-
level netlist for simulation or compilation into
a JEDEC fuse map. The JEDEC fuse map
can then be transferred from the host
• Simulator
– Logic and fault simulation
DESIGN SECURITY
– Timing model generation for device
timing simulation
The 10H20EV8/10020EV8 has a
programmable security fuse that controls the
access to the data programmed in the device.
By using this programmable feature,
proprietary designs implemented in the
device cannot be copied or retrieved.
– Synthetic logic analyzer format
• Macro library for standard TTL and user
computer to the device programer.
defined functions
• Device independent netlist generation
128
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
SNAP RESOURCE SUMMARY DESIGNATIONS
CLK/I
I
CKEV8
1
11
NINEV8
DINEV8
NINEV8
AND
DINEV8
PROGRAMMABLE AND ARRAY
(90 × 40)
12
12
8
8
8
8
12
12
OR
OR
OR
OR
OR
OR
OR
OR
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
RESET
CLK
PRESET
DFFEV8,
OLMDIR,
OLMINV,
OLMREG
OUTEV8
OUTEV8
OUTEV8
OUTEV8
OUTEV8
OUTEV8
OUTEV8
OUTEV8
F
F
F
F
F
F
F
F
OUTEV8
F
n
AP
OLMDIR
OLMINV
D
Q
Q
OUTPUT
SELECT
MUX
OLMREG
S
S
0
CLK
1
V
CC
AR
FEEDBACK
MUX
S
1
V
CC
Output Logic Macrocell
129
October 22, 1993
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