33996EK [NXP]
SPECIALTY ANALOG CIRCUIT, PDSO32, 11 X 7.50 MM, 0.65 MM PITCH, LEAD FREE, SOICW-32;
| 型号： | 33996EK |
| 厂家： | 
NXP |
| 描述： | SPECIALTY ANALOG CIRCUIT, PDSO32, 11 X 7.50 MM, 0.65 MM PITCH, LEAD FREE, SOICW-32 光电二极管 |
| 文件： | 总4页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33996DWBTAD
Rev. 2.0, 3/2007
Freescale Semiconductor
Technical Data
16-Output Switch with SPI Control
33996EK
Thermal Addendum
Introduction
This thermal addendum is provided as a supplement to the MC33996 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
32-PIN
SOICW-EP
Packaging and Thermal Considerations
The MC33996 is offered in a 32 pin SOICW exposed pad, single die package.
There is a single heat source (P), a single junction temperature (TJ), and thermal
resistance (RθJA).
TJ
.
=
RθJA
P
EK (PB-FREE) SUFFIX
98ARL10543D
32-PIN SOICW-EP
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant
to and will not predict the performance of a package in an application-specific
environment. Stated values were obtained by measurement and simulation
according to the standards listed below.
Note For package dimensions, refer to
the 33996 data sheet.
Standards
Table 1. Thermal Performance Comparisons
Thermal Resistance
[°C/W]
29
*All Measurements
are in Millimeters
,
(1) (2)
RθJA
RθJB
RθJA
RθJC
1.0
,
(2) (3)
1.0
9.0
0.2
,
(1) (4)
69
0.2
(5)
2.0
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-5 and
JESD51-7.
32 Pin SOICW-EP
0.65 Pitch
11.0 mm x 7.5mm Body
4.6 mm x 5.7 mm Exposed Pad
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the center lead.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad surface; cold plate attached to the package
bottom side, remaining surfaces insulated.
Figure 1. Surface Mount for SOICW Exposed Pad
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Document Number: MC33996DWBTAD
Rev. 2.0, 3/2007
Freescale Semiconductor
Technical Data
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OUT0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OUT15
OUT14
PWM
OUT13
OUT12
RST
OUT1
SOPWR
OUT2
OUT3
VPWR
GND
GND
GND
GND
GND
GND
GND
GND
SCLK
SO
OUT4
OUT11
OUT10
SI
OUT5
CS
OUT6
OUT9
OUT8
OUT7
33996 Pin Connections
32-Pin SOICW EP
0.65 mm Pitch
11.0 mm x 7.5 mm Body
4.6 x 5.7 mm exposed pad
Figure 2. Thermal Test Board
Table 2. Thermal Resistance Performance
Device on Thermal Test Board
A [mm2]
RθJA [°C/W]
Material:
Single layer printed circuit board
FR4, 1.6 mm thickness
0
70
49
47
Cu traces, 0.07 mm thickness
300
Outline:
Area A:
80 mm x 100 mm board area,
including edge connector for
thermal testing
600
RθJA is the thermal resistance between die junction and
ambient air.
Cu heat-spreading areas on board
surface
Ambient Conditions: Natural convection, still air
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Document Number: MC33996DWBTAD
Rev. 2.0, 3/2007
Freescale Semiconductor
Technical Data
80
70
60
50
40
30
20
10
0
R
[°C/W]
JA
x
θ
0
300
Heat Spreading Area A [mm²]
600
Figure 3. Device on Thermal Test Board RθJA
100
10
1
R
x
θJA [°C/W]
0.1
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 4. Transient Thermal Resistance RθJA,
1 W Step response, Device on Thermal Test Board Area A = 600 (mm2)
© Freescale Semiconductor, Inc., 2007. All rights reserved.
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MC33996DWBTAD
Rev. 2.0
3/2007
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