4071B [NXP]
Quadruple 2-input OR gate; 四路2输入或门
| 型号： | 4071B |
| 厂家： | 
NXP |
| 描述： | Quadruple 2-input OR gate |
| 文件： | 总3页 (文件大小：29K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4071B
gates
Quadruple 2-input OR gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4071B
gates
Quadruple 2-input OR gate
DESCRIPTION
The HEF4071B is a positive logic quadruple 2-input OR
gate. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.2 Pinning diagram.
HEF4071BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4071BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4071BT(D): 14-lead SO; plastic
(SOT108-1)
Fig.1 Functional diagram.
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
Fig.3 Logic diagram (one gfate).
January 1995
2
Philips Semiconductors
Product specification
HEF4071B
gates
Quadruple 2-input OR gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP.
MAX.
Propagation delays
In → On
HIGH to LOW
5
55
25
20
45
20
15
60
30
20
60
30
20
115
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
28 ns
15 ns
12 ns
18 ns
9 ns
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
10
15
5
tPHL
35
90
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
45
30
7 ns
Output transition times
HIGH to LOW
120
60
10 ns
9 ns
10
15
5
40
6 ns
120
60
10 ns
9 ns
LOW to HIGH
10
15
40
6 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
1150 fi + ∑ (foCL) × VDD
where
2
10
15
4800 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
19 700 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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