74ABT16240ADGG,112 [NXP]
74ABT16240A - 16-bit inverting buffer/line driver; 3-state TSSOP 48-Pin;
| 型号： | 74ABT16240ADGG,112 |
| 厂家： | 
NXP |
| 描述： | 74ABT16240A - 16-bit inverting buffer/line driver; 3-state TSSOP 48-Pin |
| 文件： | 总14页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ABT16240A
16-bit inverting buffer/line driver; 3-state
Rev. 6 — 3 November 2011
Product data sheet
1. General description
The 74ABT16240A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT16240A is an inverting 16-bit buffer that is ideal for driving bus lines. The
device features four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling four of
the 3-state outputs.
2. Features and benefits
16-bit bus interface
Multiple VCC and GND pins minimize switching noise
Power-up 3-state
3-state buffers
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Output capability: +64 mA and 32 mA
Live insertion and extraction permitted
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
HBM JESD-A114E exceeds 2000 V
CDM JESD22-C101-C exceeds 1000 V
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74ABT16240ADGG
74ABT16240ADL
40 C to +85 C
TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
40 C to +85 C
SSOP48
plastic shrink small outline package; 48 leads; body SOT370-1
width 7.5 mm
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
4. Functional diagram
1
1OE
2OE
3OE
4OE
EN1
EN2
EN3
EN4
1A0
1A1
1A2
1A3
1OE
2A0
2A1
2A2
2A3
2OE
1Y0
1Y1
1Y2
1Y3
3A0
3A1
3A2
3A3
3OE
4A0
4A1
4A2
4A3
4OE
3Y0
3Y1
3Y2
3Y3
47
46
44
43
1
2
3
5
6
36
35
33
32
25
30
29
27
26
24
13
14
16
17
48
25
24
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
3A0
3A1
3A2
3A3
4A0
4A1
4A2
4A3
1
1
1
1
1
2
3
4
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
2Y0
2Y1
2Y2
2Y3
4Y0
4Y1
4Y2
4Y3
41
40
38
37
48
8
9
19
20
22
23
11
12
001aad261
001aad262
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74ABT16240A
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
2 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
2OE
1A0
1A1
GND
1A2
1A3
1Y0
1Y1
GND
1Y2
1Y3
3
4
5
6
7
V
V
CC
CC
8
2Y0
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
3Y2
3Y3
2A0
2A1
GND
2A2
2A3
3A0
3A1
GND
3A2
3A3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
74ABT16240A
V
V
CC
CC
4Y0
4Y1
4A0
4A1
GND
4A2
4A3
3OE
GND
4Y2
4Y3
4OE
001aaj891
Fig 3. Pin configuration
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
1OE, 2OE, 3OE, 4OE 1, 48, 25, 24
output enable (LOW active)
1 data output
1Y0, 1Y1, 1Y2, 1Y3
GND
2, 3, 5, 6
4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
VCC
7, 18, 31, 42
8, 9, 11, 12
supply voltage
2 data output
3 data output
4 data output
4 data input
3 data input
2 data input
1 data input
2Y0, 2Y1, 2Y2, 2Y3
3Y0, 3Y1, 3Y2, 3Y3
4Y0, 4Y1, 4Y2, 4Y3
4A0, 4A1, 4A2, 4A3
3A0, 3A1, 3A2, 3A3
2A0, 2A1, 2A2, 2A3
1A0, 1A1, 1A2, 1A3
13, 14, 16, 17
19, 20, 22, 23
30, 29, 27, 26
36, 35, 33, 32
41, 40, 38, 37
47, 46, 44, 43
74ABT16240A
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
3 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
6. Functional description
Table 3.
Function table[1]
Control
Input
nAn
L
Output
nOE
L
nYn
H
L
H
L
H
X
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
VI
Parameter
Conditions
Min
Max Unit
supply voltage
0.5 +7.0
1.2 +7.0
0.5 +5.5
V
[1]
[1]
input voltage
V
VO
output voltage
output in OFF-state or HIGH-state
VI < 0 V
V
IIK
input clamping current
output clamping current
output current
18
-
mA
mA
mA
mA
C
IOK
VO < 0 V
50
-
IO
output in LOW-state
output in HIGH-state
-
128
64
150
-
[2]
Tj
junction temperature
storage temperature
-
Tstg
65
+150 C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
8. Recommended operating conditions
Table 5.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
4.5
0
Typ
Max Unit
supply voltage
-
-
-
-
-
-
-
-
-
5.5
VCC
-
V
input voltage
V
VIH
HIGH-level input voltage
LOW-level Input voltage
HIGH-level output current
LOW-level output current
2.0
-
V
VIL
0.8
-
V
IOH
32
-
mA
mA
mA
ns/V
C
IOL
32
64
10
+85
duty cycle 50 %; fi 1 kHz
-
t/V
input transition rise and fall rate
ambient temperature
-
Tamb
in free air
40
74ABT16240A
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
4 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
9. Static characteristics
Table 6.
Static characteristics
Symbol Parameter
Conditions
25 C
40 C to +85 C Unit
Min Typ Max
Min
Max
VIK
input clamping voltage VCC = 4.5 V; IIK = 18 mA
1.2 0.9
-
1.2
-
V
VOH
HIGH-level output
voltage
VI = VIL or VIH
VCC = 4.5 V; IOH = 3 mA
VCC = 5.0 V; IOH = 3 mA
VCC = 4.5 V; IOH = 32 mA
2.5
3.0
2.0
-
2.9
3.4
2.4
-
-
-
2.5
3.0
2.0
-
-
V
V
V
V
-
-
VOL
LOW-level output
voltage
VCC = 4.5 V; IOL = 64 mA;
VI = VIL or VIH
0.42 0.55
0.55
II
input leakage current VCC = 5.5 V; VI = VCC or GND
-
-
0.01 1.0
5.0 100
-
-
1.0 A
100 A
IOFF
power-off leakage
current
VCC = 0 V; VI or VO 4.5 V
[1]
IO(pu/pd)
IOZ
power-up/power-down VCC = 2.0 V; VO = 0.5 V;
-
5.0 50
-
50
A
output current
VI = GND or VCC; nOE = HIGH
OFF-state output
current
VCC = 5.5 V; VI = VIL or VIH
output HIGH-state at VO = 5.5 V
output LOW-state at VO = 0.5 V
-
-
-
1.0
10
-
-
-
10
10
50
A
A
A
1.0 10
ILO
output leakage current HIGH-state; VO = 5.5 V;
VCC = 5.5 V; VI = GND or VCC
1.0
50
[2]
IO
output current
supply current
VCC = 5.5 V; VO = 2.5 V
VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state
180 70
50
180
50
mA
ICC
-
-
-
-
0.5
8
1.0
19
-
-
-
-
1.0
19
mA
mA
mA
A
outputs LOW-state
outputs 3-state
0.5
10
1.0
200
1.0
200
[3][4]
ICC
additional supply
current
per input pin; VCC = 5.5 V; one input
at 3.4 V and other inputs at VCC or
GND
CI
input capacitance
VI = 0 V or VCC
-
-
4
6
-
-
-
-
-
-
pF
pF
CI/O
input/output
capacitance
outputs disabled; VO = 0 V or VCC
[1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V 10 %,
a transition time of up to 100 s is permitted.
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[3] This is the increase in supply current for each input at 3.4 V.
[4] This data sheet limit may vary among suppliers.
74ABT16240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
5 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V. For test circuit, see Figure 6.
Symbol Parameter Conditions
25 C; VCC = 5.0 V 40 C to +85 C; Unit
VCC = 5.0 V 0.5 V
Min
Typ Max
Min
Max
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
LOW to HIGH
propagation delay
nAn to nYn, see Figure 4
nAn to nYn, see Figure 4
1.0
2.0
1.5
2.4
2.3
2.7
2.5
3.0
3.0
3.3
3.2
4.1
3.6
1.0
3.7
ns
ns
ns
ns
ns
ns
HIGH to LOW
propagation delay
1.0
1.2
1.2
1.3
1.3
1.0
1.2
1.0
1.6
1.4
3.5
4.2
4.2
4.7
4.1
OFF-state to HIGH nOE to nYn; see Figure 5
propagation delay
OFF-state to LOW nOE to nYn; see Figure 5
propagation delay
HIGH to OFF-state nOE to nYn; see Figure 5
propagation delay
LOW to OFF-state nOE to nYn; see Figure 5
propagation delay
74ABT16240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
6 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
11. Waveforms
V
I
input nAn
V
M
V
M
0 V
t
t
PHL
PLH
V
OH
output nYn
V
V
M
M
V
OL
001aaj028
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 4. Input (nAn) to output (nYn) propagation delay
V
I
V
M
nOE input
GND
3.5 V
t
t
PLZ
PZL
V
nYn output
M
V
+ 0.3 V
OL
V
OL
t
t
PHZ
PZH
V
OH
V
− 0.3 V
OH
V
M
nYn output
0 V
001aaj892
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. 3-state output enable and disable times
74ABT16240A
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
7 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
12. Test information
t
W
V
I
90 %
90 %
negative
pulse
V
V
M
M
10 %
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
90 %
positive
pulse
V
M
V
M
10 %
10 %
0 V
t
W
001aai298
VM = 1.5 V
a. Input pulse definition
V
EXT
V
CC
R
L
L
V
V
O
I
PULSE
GENERATOR
DUT
C
R
L
R
T
001aac764
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
b. Test circuit for 3-state outputs
Fig 6. Load circuitry for switching times
Table 8.
Input
VI
Test data
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH
open
tPLZ, tPZL
tPLH, tPHL
3.0 V
1 MHz
500 ns
2.5 ns
50 pF
500
7.0 V
open
74ABT16240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
8 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
13. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
Fig 7. Package outline SOT362-1 (TSSOP48)
74ABT16240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
9 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
Fig 8. Package outline SOT370-1 (SSOP48)
74ABT16240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
10 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
14. Abbreviations
Table 9.
Acronym
BiCMOS
DUT
Abbreviations
Description
Bipolar CMOS
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Charged Device Model
Transistor-Transistor Logic
HBM
CDM
TTL
15. Revision history
Table 10. Revision history
Document ID
Release date
20111103
Data sheet status
Change notice
Supersedes
74ABT16240A v.6
Modifications:
Product data sheet
-
74ABT16240A v.5
• Legal pages updated
74ABT16240A v.5
74ABT16240A v.4
74ABT16240A v.3
20100525
20090325
20040212
Product data sheet
-
74ABT16240A v.4
74ABT16240A v.3
74ABT_H16240A v.2
74ABT_H16240A
-
Product data sheet
Product specification
Product specification
Product specification
-
01-A15420
74ABT_H16240A v.2 19980225
853-1880 19019
-
74ABT_H16240A
19961001
74ABT16240A
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
11 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74ABT16240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
12 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74ABT16240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
13 of 14
74ABT16240A
NXP Semiconductors
16-bit inverting buffer/line driver; 3-state
18. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Test information. . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
7
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 November 2011
Document identifier: 74ABT16240A
相关型号：
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