74ABT16823ADGG,112 [NXP]
74ABT16823A - 18-bit bus interface D-type flip-flop with reset and enable (3-State) TSSOP 56-Pin;
| 型号： | 74ABT16823ADGG,112 |
| 厂家： | 
NXP |
| 描述： | 74ABT16823A - 18-bit bus interface D-type flip-flop with reset and enable (3-State) TSSOP 56-Pin 驱动 信息通信管理 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT16823A
18-bit bus interface D-type flip-flop
with reset and enable (3-State)
Product data
2004 Feb 02
Replaces data sheet 74ABT16823A/ABTH16823A of 1998 Feb 27
Philips
Semiconductors
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
FEATURES
DESCRIPTION
The 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
• Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
• Live insertion/extraction permitted
• Power-up 3-State
The registers are fully edge-triggered. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.
• Power-up Reset
• Output capability: +64 mA/–32 mA
• Latch-up protection exceeds 500 mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
CONDITIONS
= 25 °C; GND = 0 V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
nCP to nQx
2.3
1.9
PLH
PHL
C = 50 pF; V = 5 V
ns
L
CC
C
Input capacitance
Output capacitance
V = 0 V or V
CC
4
6
pF
pF
IN
I
C
V = 0 V or V ; 3-State
O CC
OUT
CCZ
I
Outputs disabled; V = 5.5 V
500
9
µA
mA
CC
Quiescent supply current
I
Outputs low; V = 5.5 V
CC
CCL
ORDERING INFORMATION
T
amb
= –40 °C to +85 °C
Package
Name
Type number
Description
Version
74ABT16823ADL
SSOP56
TSSOP56
plastic shrink small outline package; 56 leads; body width 7.5 mm
plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT371-1
SOT364-1
74ABT16823ADGG
PIN DESCRIPTION
PIN NUMBER
2, 27
SYMBOL
FUNCTION
Output enable input (active-LOW)
1OE, 2OE
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
1D0-1D8
2D0-2D8
Data inputs
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
1Q0-1Q8
2Q0-2Q8
Data outputs
56, 29
55, 30
1CP, 2CP
1CE, 2CE
1MR, 2MR
GND
Clock pulse input (active rising edge)
Clock enable input (active-LOW)
Master reset input (active-LOW)
Ground (0 V)
1, 28
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
V
CC
Positive supply voltage
2
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
1MR
1OE
1Q0
GND
1Q1
1Q2
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CP
1CE
1D0
GND
1D1
1D2
2
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
EN1
R2
1
55
56
27
28
30
29
3
G3
4
3C4
5
EN5
R6
6
V
7
V
G7
CC
CC
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
8
1D3
1D4
1D5
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D3
2D4
2D5
7C8
9
54
52
51
49
48
47
45
44
43
42
3
4D
1, 2
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
25
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
8D
5, 6
41
40
38
37
36
34
33
31
V
V
CC
CC
2Q6
2Q7
GND
2Q8
2OE
2MR
2D6
2D7
GND
2D8
2CE
2CP
SH00015
SH00014
3
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
LOGIC DIAGRAM
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP
CP
Q
CP
Q
CP
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
nD
R
nD
R
nD
R
nD
nD
R
nD
R
nD
R
nD
R
nD
R
R
Q
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
SH00016
n = 1 or 2
FUNCTION TABLE
INPUTS
nCE
OUTPUTS
nQ0 – nQ8
OPERATING MODE
nOE
nMR
nCP
nDx
L
L
L
L
H
L
H
H
H
X
X
L
X
↑
X
h
l
L
H
Clear
Load and read data
L
↑
L
H
X
↑
X
X
NC
Z
Hold
X
High impedance
H = High voltage level
h
L
l
=
=
=
High voltage level one set-up time prior to the LOW-to-HIGH clock transition
Low voltage level
Low voltage level one set-up time prior to the LOW-to-HIGH clock transition
NC= No change
X
Z
↑
=
=
=
=
Don’t care
High impedance “off” state
LOW-to-HIGH clock transition
Not a LOW-to-HIGH clock transition
↑
4
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
–0.5 to +7.0
–18
CC
IK
I
DC input diode current
V < 0 V
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0 V
mA
V
OK
3
V
OUT
DC output voltage
output in Off or HIGH state
output in LOW state
–0.5 to +5.5
128
I
DC output current
mA
OUT
output in HIGH state
–64
T
stg
Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
0
MAX
V
CC
DC supply voltage
5.5
V
V
V
I
Input voltage
V
CC
V
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
Input transition rise or fall rate
2.0
–
–
V
IH
V
0.8
–32
64
V
IL
I
–
mA
mA
ns/V
°C
OH
I
OL
–
∆t/∆v
0
10
T
amb
Operating free-air temperature range
–40
+85
5
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= –40 °C to
+85 °C
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25 °C
UNIT
MIN
TYP
–0.9
2.9
MAX
–1.2
–
MIN
–
MAX
–1.2
–
V
Input clamp voltage
V
V
V
V
V
= 4.5 V; I = –18 mA
–
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5 V; I = –3 mA; V = V or V
2.5
3.0
2.0
–
2.5
3.0
2.0
–
OH
I
IL
IH
IH
V
OH
HIGH-level output voltage
= 5.0 V; I = –3 mA; V = V or V
3.4
–
–
OH
I
IL
= 4.5 V; I = –32 mA; V = V or V
2.4
–
–
OH
I
IL
IH
V
OL
LOW-level output voltage
Power-up output LOW
= 4.5 V; I = 64 mA; V = V or V
IH
0.42
0.55
0.55
OL
I
IL
V
RST
V
= 5.5 V; I = 1 mA; V = GND or V
–
0.13
0.55
–
0.55
V
CC
CC
OL
I
CC
3
voltage
I
Input leakage curent
V
V
= 5.5 V; V = V or GND
–
–
±0.01
±5.0
±1
–
–
±1
µA
µA
I
I
CC
I
Power-off leakage current
Power-up/down 3-State
= 0.0 V; V or V ≤ 4.5 V
±100
±100
OFF
CC
O
I
V
CC
= 2.1 V; V = 0.5 V; V = GND or V
;
CC
O
I
I
–
±5.0
±50
–
±50
µA
PU/PD
4
output current
V
= Don’t care
OE
CC
I
3-State output HIGH current
3-State output LOW current
V
= 5.5 V; V = 2.7 V; V = V or V
IH
–
–
1.0
10
–
–
10
µA
µA
OZH
O
I
IL
I
V
= 5.5 V; V = 0.5 V; V = V or V
IH
–1.0
–10
–10
OZL
CC
CC
O
I
IL
Output HIGH leakage
current
I
V
= 5.5 V; V = 5.5 V; V = GND or V
CC
–
–50
–
50
–80
0.5
50
–180
1
–
–50
–
50
–180
1
µA
mA
mA
CEX
O
I
1
I
O
Output current
V
V
= 5.5 V; V = 2.5 V
O
CC
= 5.5 V; Outputs HIGH;
CC
I
CCH
V = GND or V
I
CC
V
= 5.5V; Outputs LOW;
CC
I
Quiescent supply current
Additional supply current
–
–
–
9.0
0.5
0.2
19
1
–
–
–
19
1
mA
mA
mA
CCL
V = GND or V
I
CC
V
CC
= 5.5V; Outputs 3–State;
I
CCZ
V = GND or V
I
CC
V
CC
= 5.5V; one input at 3.4 V,
∆I
1
1
CC
2
per input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10% a
CC
CC
CC
transition time of up to 100µsec is permitted.
6
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
AC CHARACTERISTICS
GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω
R
F
L
L
LIMITS
T
V
= +25 °C
= + 5.0 V
T
= –40 °C to +85 °C
amb
CC
amb
V
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0 V ± 0.5 V
CC
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
1
1
140
190
–
140
MHz
ns
MAX
t
t
Propagation delay
nCP to nQx
1.4
1.2
2.3
1.9
3.2
2.6
1.4
1.2
3.7
2.9
PLH
PHL
Propagation delay
nMR to nQx
t
2
2.0
3.3
4.3
2.0
5.0
ns
ns
ns
PHL
t
t
Output enable time
to HIGH and LOW level
4
5
1.3
1.2
2.4
2.1
3.2
2.9
1.3
1.2
3.9
3.4
PZH
PZL
t
t
Output disable time
from HIGH and LOW level
4
5
1.7
1.6
2.9
2.3
4.0
3.2
1.7
1.6
4.7
3.4
PHZ
PLZ
AC SET-UP REQUIREMENTS
GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω
R
F
L
L
LIMITS
T
V
= +25 °C
= + 5.0 V
T
= –40 °C to +85 °C
amb
CC
amb
V
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0 V ± 0.5V
CC
MIN
TYP
MIN
t (H)
t (L)
s
Set-up time, HIGH or LOW
nDx to nCP
2.0
1.5
1.3
0.9
2.0
1.5
s
3
3
1
3
ns
ns
ns
ns
t (H)
Hold time, HIGH or LOW
nDx to nCP
1.5
1.5
–0.9
–1.2
1.5
1.5
h
t (L)
h
t (H)
nCP pulse width
HIGH or LOW
3.3
3.3
1.7
1.7
3.3
3.3
w
t (L)
w
t (H)
Set-up time, HIGH or LOW
nCE to nCP
1.5
2.0
0.9
0.9
1.5
2.0
s
t (L)
s
t (H)
t (L)
h
Hold time, HIGH or LOW
nCE to nCP
1.5
1.5
–0.8
–0.9
1.5
1.5
h
3
2
2
ns
ns
ns
t (L)
w
nMR pulse width, LOW
3.0
2.5
1.7
1.0
3.0
2.5
Recovery time
nMR to nCP
t
rec
7
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
AC WAVEFORMS
For all waveforms, V = 1.5 V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
3.0V or V
whichever
is less
CC
1/f
MAX
nOE
3.0V or V
whichever
is less
CC
V
V
M
M
t
nCP
nQn
0V
V
t
V
M
M
t
PHZ
0V
t
PZH
w
t
PLH
V
V
OH
–0.3V
PHL
V
OH
OH
V
M
V
V
nQx
M
M
0V
0V
SH00020
SH00017
Waveform 4. 3-State Output Enable Time to HIGH Level
and Output Disable Time from HIGH Level
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
3.0V or V
CC
whichever
is less
3.0V or V
whichever
is less
CC
V
V
M
M
nOE
nQx
V
V
M
nMR
M
0V
3.0V or V
0V
3.0V or V
whichever
is less
t
t
PLZ
PZL
t
CC
REC
t
w
whichever
is less
CC
V
V
M
nCP
nQn
M
V
V
+0.3V
OL
OL
0V
t
PHL
V
OH
SH00021
V
M
Waveform 5. 3-State Output Enable Time to LOW Level
and Output Disable Time from LOW Level
0V
SH00018
Waveform 2. Master Reset Pulse WIdth, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
3.0V or V
CC
whichever
is less
nDx,
nCE
V
V
V
V
V
M
M
M
M
0V
3.0V or V
t (H)
t
(H)
t (L)
t (L)
h
CC
s
h
s
whichever
is less
nCP
V
M
M
0V
SH00019
Waveform 3. Data Set-up and Hold Times
8
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
TEST CIRCUIT AND WAVEFORM
V
CC
t
W
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
R
L
M
M
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
SWITCH POSITION
TEST SWITCH
V = 1.5V
M
Input Pulse Definition
t
t
closed
closed
open
PLZ
PZL
All other
DEFINITIONS:
R
C
=
=
Load resistor; see AC CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
L
L
INPUT PULSE REQUIREMENTS
FAMILY
Rep. Rate
t
w
t
R
t
Amplitude
F
R
T
=
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns
2.5ns
74ABT16
3.0V
1MHz
500ns
SH00022
9
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
10
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
11
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
REVISION HISTORY
Rev
Date
Description
_3
20040202
Product data (9397 750 12833); 853-1791 ECN 01-A15432 of 27 January 2004.
Replaces data sheet 74ABT_H16823A_2 of 1998 February 27 (9397 750 03502).
Modifications:
• Delete all references to 74ABTH16823A (product discontinued).
_2
19980227
Product specification (9397 750 03502); ECN 853-1791 19025 of 27 February 1998.
Supersedes data of 1995 Sep 28.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 02-04
9397 750 12833
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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