74ABT16899DL,512 [NXP]
74ABT16899DL;
| 型号： | 74ABT16899DL,512 |
| 厂家： | 
NXP |
| 描述： | 74ABT16899DL 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总20页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT16899
74ABTH16899
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
Product specification
1998 Feb 25
Supersedes data of 1997 Mar 28
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
Parity error checking of the A and B bus latches is continuously
provided with ERRA and ERRB, even with both buses in 3-State.
FEATURES
• Symmetrical (A and B bus functions are identical)
The 74ABT/H16899 features independent latch enables for the A
and B bus latches, a select pin for ODD/EVEN parity, and separate
error signal output pins for checking parity.
• Selectable generate parity or ”feed-through” parity for A-to-B and
B-to-A directions
• Independent transparent latches for A-to-B and B-to-A directions
• Selectable ODD/EVEN parity
FUNCTIONAL DESCRIPTION
The 74ABT/H16899 has three principal modes of operation which
are outlined below. All modes apply to both the A-to-B and B-to-A
directions.
• Continuously checks parity of both A bus and B bus latches as
ERRA and ERRB
• Open-collector ERR output
Transparent latch, Generate parity, Check A and B bus parity:
Bus A (B) communicates to Bus B (A), parity is generated and
passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are
High and the Mode Select (SEL) is Low, the parity generated from
A0-A7 and B0-B7 can be checked and monitored by ERRA and
ERRB. (Fault detection on both input and output buses.)
• Ability to simultaneously generate and check parity
• Can simultaneously read/latch A and B bus data
• Output capability: +64 mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
Transparent latch, Feed-through parity, Check A and B bus
parity:
and 200 V per Machine Model
Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL
is High. Parity is still generated and checked as ERRA and ERRB
and can be used as an interrupt to signal a data/parity bit error to the
CPU.
• Power up 3-State
• Power-up reset
• Live insertion/extraction permitted
Latched input, Generate/Feed-through parity, Check A (and B)
bus parity:
• Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Independent latch enables (LEA and LEB) allow other permutations
of:
DESCRIPTION
The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with
separate transparent latches for the A bus and B bus. Either bus
can generate or check parity. The parity bit can be fed-through with
no change or the generated parity can be substituted with the SEL
input.
• Transparent latch / 1 bus latched / both buses latched
• Feed-through parity / generate parity
• Check in bus parity / check out bus parity / check in and out bus
parity
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
2.7
UNIT
ns
T
amb
t
t
Propagation delay
An to Bn or Bn to An
PLH
PHL
C = 50pF; V = 5V
L
CC
t
t
Propagation delay
An to ERRA
PLH
PHL
C = 50pF; V = 5V
5.0
ns
L
CC
C
Input capacitance
Output capacitance
V = 0V or V
CC
4
7
pF
pF
IN
I
C
Outputs disabled; V = 0V or V
O CC
I/O
I
Outputs disabled; V =5.5V
500
10.5
µA
mA
CCZ
CC
Quiescent supply current
I
Output Low; V = 5.5V
CCL
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
BT16899 DL
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT16899 DL
74ABT16899 DGG
74ABTH16899 DL
74ABTH16899 DGG
BT16899 DGG
BH16899 DL
SOT364-1
SOT371-1
BH16899 DGG
SOT364-1
2
1998 Feb 25
853-1960 19018
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
PIN CONFIGURATION
ODD/EVEN
OEA
1A0
1
2
56
55
54
53
52
SEL
LEA
1B0
GND
1B1
3
GND
1A1
4
5
1A2
6
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1B2
1B3
1B4
1A3
7
1A4
8
V
9
V
CC
CC
1A5
1A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1B5
1B6
1A7
1B7
1APAR
1ERRA
GND
1BPAR
1ERRB
GND
2ERRB
2BPAR
2B7
2ERRA
2APAR
2A7
2A6
2B6
2A5
2B5
V
V
CC
CC
2A4
2A3
2A2
2A1
GND
2A0
LEB
2B4
2B3
2B2
2B1
GND
2B0
OEB
SH00082
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
NAME AND FUNCTION
1A0 - 1A7
2A0 - 2A7
3, 5, 6, 7, 8, 10, 11, 12
27, 25, 24, 23, 22, 20, 19, 18
Latched A bus 3-State inputs/outputs
Latched B bus 3-State inputs/outputs
A bus parity 3-State input
1B0 - 1B7
2B0 - 2B7
54, 52, 51, 50, 49, 47, 46, 45
30, 32, 33, 34, 35, 37, 38, 39
1APAR
2APAR
13, 17
1BPAR
2BPAR
44, 40
1
B bus parity 3-State input
ODD/EVEN
OEA, OEB
Parity select input (Low for EVEN parity)
Output enable inputs (gate A to B,
B to A)
2, 29
SEL
56
Mode select input (Low for generate)
Latch enable inputs (transparent High)
LEA, LEB
55, 28
1ERRA, 1ERRB
2ERRA, 2ERRB
14, 43,
16, 41
Error signal outputs (active-Low)
GND
4, 15, 26, 31, 42, 53
9, 21, 36, 48
Ground (0V)
V
CC
Positive supply voltage
3
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
LOGIC SYMBOL
3
5
6
7
8
10 11 12
13
27 25 24 23
22 20 19 18
17
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1APAR
LEA
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2APAR
LEA
55
28
55
28
LEB
LEB
56
1
SEL
56
1
SEL
1ERRA
14
43
2ERRA
16
41
ODD/EVEN
1ERRB
ODD/EVEN
2ERRB
2
OEA
2
OEA
OEB
29
OEB
29
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1BPAR
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2BPAR
54 52 51 50 49 47 46 45
44
30 32 33 34 35 37 38 39
40
SH00083
PARITY AND ERROR FUNCTION TABLE
INPUTS
OUTPUTS
ERRt
xPAR
Σ of High
Inputs
xPAR
(B or A)
SEL
ODD/EVEN
ERRr*
(A or B)
PARITY MODES
Even
Odd
H
H
H
L
H
L
H
H
H
H
L
H
H
L
H
L
Odd
Even
Odd
L
L
L
H
L
H
Mode
Feed-through/check parity
Even
Odd
H
H
L
H
L
H
H
L
Even
Mode
Even
Odd
L
L
H
L
H
L
L
Even
Odd
H
L
H
L
H
H
H
H
L
H
L
Odd
Even
Odd
H
L
L
H
H
H
Mode
L
Generate parity
Even
Odd
L
H
L
H
H
H
L
H
L
Even
Mode
Even
Odd
L
H
H
L
H
H
L
L
H
L
t
=
=
=
=
High voltage level
Low voltage level
Transmit–if the data path is from A→B then ERRt is ERRA
Receive–if the data path is from A→B then ERRr is ERRB
r
*
Blocked if latch is not transparent
4
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
BLOCK DIAGRAM
OEB
OE
9–bit
Transparent
Latch
9–bit
Output
Buffer
LEA
LE
1
mux
A0
A1
B0
Parity
Generator
B1
0
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
APAR
BPAR
9–bit
Transparent
Latch
9–bit
Output
Buffer
OEA
SEL
LEB
OE
LE
1
mux
Parity
Generator
ERRA
0
ERRB
ODD/
EVEN
(1 of 2 parity blocks)
SH00084
FUNCTION TABLE
INPUTS
OPERATING MODE
OEB OEA SEL LEA LEB
H
H
H
H
H
H
L
H
L
X
L
X
L
X
H
H
L
3-State A bus and B bus (input A & B simultaneously)
B → A, transparent B latch, generate parity from B0 - B7, check B bus parity
B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
B → A, transparent B latch, parity feed-through, check B bus parity
B → A, transparent A & B latch, parity feed-through, check A & B bus parity
A → B, transparent A latch, generate parity from A0 - A7, check A bus parity
A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
A → B, transparent A latch, parity feed-through, check A bus parity
A → B, transparent A & B latch, parity feed-through, check A & B bus parity
Output to A bus and B bus (NOT ALLOWED)
L
L
H
X
X
H
H
H
L
L
L
L
H
H
L
H
H
X
H
X
L
L
H
H
H
H
H
L
L
L
L
L
L
H
H
X
H
H
X
L
H
X
L
H
L
X
=
=
=
High voltage level
Low voltage level
Don’t care
5
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
–0.5 to +7.0
–18
CC
IK
I
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
I
DC output current
mA
OUT
output in High state
–64
T
stg
Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
5
T
amb
Operating free-air temperature range
–40
+85
6
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.7
3.1
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
3.6
OH
I
IL
= 4.5V; I = –32mA; V = V or V
IH
2.7
OH
I
IL
V
OL
Low-level output voltage
Power-up output low
= 4.5V; I = 64mA; V = V or V
IH
0.36
0.55
0.55
0.55
0.55
OL
I
IL
V
RST
V
CC
= 5.5V; I = 1mA; V = GND or V
CC
0.13
V
O
I
3
voltage
I
I
Input leakage Control pins
V
V
= 5.5V; V = GND or 5.5V
±0.2
±1.0
±1.0
±1.0
µA
µA
CC
I
current
Data pins
= 5.5V; V = GND or 5.5V
±100
±100
CC
I
V
V
= 4.5V; V = 0.8V
75
75
CC
I
Bushold current A or B
inputs
5
= 4.5V; V = 2.0V
–75
–75
I
µA
CC
I
HOLD
74ABTH16899
V
= 5.5V; V = 0 to 5.5V
±500
CC
CC
I
I
Power-off leakage current
Power-up/down 3-State
V
= 0.0V; V or V 4.5V
±2.0
±5.0
±100
±50
±100
±50
µA
µA
≤
I
OFF
O
I
/I
V
= 2.1V; V = 0.5V; V = GND or V
PU PD
CC O I
CC
CC
4
output current
I
+ I
+ I
3-State output High current
3-State output Low current
Output High leakage current
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5V; V = 2.7V; V = V or V
2.0
–2.0
2.0
50
–50
50
50
–50
50
µA
µA
IH
OZH
OZL
O
I
IL
IH
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
IL
I
= 5.5V; V = 5.5V; V = GND or V
µA
CEX
O
I
1
I
Output current
= 5.5V; V = 2.5V
–50
–100
0.5
–180
1
–50
–180
1
mA
mA
mA
O
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
10.5
19
19
CCL
I
CC
= 5.5V; Outputs 3-State;
I
0.5
0.2
1
1
mA
mA
CCZ
V = GND or V
I
CC
Additional supply current per
input pin
V
CC
= 5.5V; one input at 3.4V,
∆I
1.5
1.5
CC
2
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V, with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
7
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
o
o
T
V
= +25 C
T
V
= –40 to +85 C
amb
CC
amb
CC
= +5.0V
= 50pF
= 500Ω
= +5.0V ±10%
SYMBOL
PARAMETER
WAVEFORM
UNIT
C
C
R
= 50pF
= 500Ω
L
L
L
L
R
Min
Typ
Min
Max
t
t
Propagation delay
An to Bn or Bn to An
1.0
1.0
2.7
2.2
4.5
3.5
1.0
1.0
5.5
6.9
PLH
PHL
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
An to BPAR or Bn to APAR
2.5
2.5
4.9
5.0
7.2
7.4
2.5
2.5
8.8
8.7
PLH
PHL
2
t
t
Propagation delay
An to ERRA or Bn to ERRB
2.8
2.8
5.0
4.9
9.3
8.0
2.8
2.8
11.0
10.2
PLH
PHL
3
t
t
Propagation delay
APAR to BPAR or BPAR to APAR
1.5
1.5
3.1
2.5
3.9
3.1
1.5
1.5
4.8
3.9
PLH
PHL
1
t
t
Propagation delay
APAR to ERRA or BPAR to ERRB
1.0
1.0
2.5
2.5
3.3
3.3
1.0
1.0
4.3
3.9
PLH
PHL
6
t
t
Propagation delay
ODD/EVEN to APAR or BPAR
2.5
2.5
4.1
3.9
5.1
5.0
2.5
2.5
6.1
5.7
PLH
PHL
5
t
t
Propagation delay
ODD/EVEN to ERRA or ERRB
2.5
2.5
4.1
4.0
6.1
5.5
2.5
2.5
7.1
6.6
PLH
PHL
4
t
t
Propagation delay
SEL to APAR or BPAR
1.5
1.5
3.1
2.6
4.0
3.4
1.5
1.5
5.0
4.2
PLH
PHL
8
t
t
Propagation delay
SEL to ERRA or ERRB
2.5
2.5
5.0
4.4
7.5
5.9
2.5
2.5
8.3
7.1
PLH
PHL
8
t
t
Propagation delay
LEA to Bn or LEB to An
1.0
1.0
3.1
2.8
4.2
4.3
1.0
1.0
5.2
4.7
PLH
PHL
9
9
t
t
Propagation delay
LEA to BPAR or LEB to APAR
2.8
2.8
5.5
5.1
8.0
7.7
2.8
2.8
9.7
9.1
PLH
PHL
t
t
Propagation delay
LEA to ERRA or LEB to ERRB
1.1
1.2
5.4
5.8
8.0
8.0
1.1
1.2
9.2
9.6
PLH
PHL
7
t
Output enable time
OEA to An, APAR or OEB to Bn, BPAR
1.0
1.0
2.6
2.3
3.6
3.2
1.0
1.0
5.1
4.5
PZH
11, 12
11, 12
t
PZL
t
Output disable time
OEA to An, APAR or OEB to Bn, BPAR
2.5
1.5
3.9
2.8
5.6
4.1
2.5
1.5
6.0
4.4
PHZ
t
PLZ
AC SETUP REQUIREMENTS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
= +5.0V
= 50pF
= 500Ω
T
V
= –40 to +85 C
amb
CC
amb
CC
= +5.0V ±10%
SYMBOL
PARAMETER
WAVEFORM
UNIT
C
C
= 50pF
= 500Ω
L
L
L
L
R
R
Min
Typ
Min
t (H)
t (L)
s
Setup time, High or Low
An, APAR to LEA or Bn, BPAR to LEB
1.5
1.0
0.3
–0.1
1.5
1.0
s
10
10
10
ns
ns
ns
t (H)
Hold time, High or Low
An, APAR to LEA or Bn, BPAR to LEB
1.5
1.0
0.1
–0.2
1.5
1.0
h
t (L)
h
Pulse width, High
LEA or LEB
t (H)
w
3.0
1.0
3.0
8
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
1
SEL
An, APAR
(Bn, BPAR)
INPUT
V
V
M
M
t
t
PLH
PHL
Bn, BPAR
(An, APAR)
OUTPUT
SA00293
V
V
M
M
Waveform 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR
SEL
0
ODD/EVEN
0
1
LEA
(LEB)
An
(Bn)
ODD PARITY
INPUT
EVEN PARITY
ODD PARITY
V
V
M
M
t
t
PLH
PHL
BPAR
(APAR)
OUTPUT
SA00294
V
V
M
M
NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1
Waveform 2. Propagation Delay, An to BPAR or Bn to APAR
ODD/EVEN
0
APAR
(BPAR)
0
1
LEA
(LEB)
An
(Bn)
SEL
ODD PARITY
INPUT
EVEN PARITY
ODD PARITY
V
V
M
M
t
t
PHL
PLH
ERRA
(ERRB)
OUTPUT
SA00295
V
V
M
M
NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1
Waveform 3. Propagation Delay, An to ERRA or Bn to ERRB
9
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
1
APAR
(BPAR)
An
(Bn)
INPUT
INPUT
EVEN PARITY
ODD/EVEN
V
V
M
M
t
t
PLH
PHL
ERRA
(ERRB)
OUTPUT
V
V
M
M
NOTE: Only even parity mode is shown, odd parity mode would cause inverted output
SA00296
Waveform 4. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB
SEL
0
APAR
(BPAR)
0
An
(Bn)
EVEN PARITY
INPUT
INPUT
ODD/EVEN
V
V
M
M
V
t
t
PLH
PHL
BPAR
(APAR)
OUTPUT
SA00297
V
M
M
NOTE: Only even parity mode is shown, odd parity mode would cause inverted output
Waveform 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR
10
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
ODD/EVEN
0
An
(Bn)
EVEN PARITY
INPUT
INPUT
APAR
(BPAR)
V
V
M
M
V
t
t
PLH
PHL
ERRA
(ERRB)
OUTPUT
V
M
M
NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output
and odd parity mode would be with ODD/EVEN = 1
SA00298
Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB
1
ODD/EVEN
APAR
(BPAR)
0
An
(Bn)
EVEN PARITY
INPUT
INPUT
ODD PARITY
EVEN PARITY
LEA
(LEB)
V
V
M
M
t
t
PLH
PHL
ERRA
(ERRB)
OUTPUT
SA00299
V
V
M
M
NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o
Waveform 7. Propagation Delay, LEA to ERRA or LEB to ERRB
11
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
1
ODD/EVEN
APAR
(BPAR)
0
An
(Bn)
EVEN PARITY
INPUT
INPUT
SEL
V
V
M
M
V
t
t
PLH
PHL
BPAR
(APAR)
OUTPUT
V
M
M
NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output
and odd parity mode would be with ODD/EVEN = 1
SA00300
Waveform 8. Propagation Delay, SEL to BPAR or SEL to APAR
1
SEL
APAR, An]
(BPAR, Bn)
INPUT
LEA
(LEB)
INPUT
V
V
M
M
t
t
PHL
PLH
Bn, BPAR
(An, APAR)
OUTPUT
V
V
M
M
SA00301
Waveform 9. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An
APAR, BPAR,
An, Bn
V
V
V
V
M
M
M
M
t
(H)
t (L)
s
t
(H)
V
t (L)
h
s
h
LEA, LEB
V
V
M
M
M
t
(H)
w
The shaded areas indicate when the input is permitted to change for predictable output performance.
SA00302
Waveform 10. Data Setup and Hold Times, Pulse Width High
12
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
OEA,
OEB
V
V
M
M
t
t
PHZ
PZH
V
–0.3V
OH
An, APAR,
Bn, BPAR
V
M
0V
SA00303
Waveform 11. 3-State Output Enable Time to High Level and Output Disable Time from High Level
OEA,
OEB
V
V
M
M
t
t
PZL
PLZ
An, APAR,
Bn, BPAR
V
M
V
+0.3V
OL
SA00304
Waveform 12. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
V
CC
t
W
AMP (V)
0V
V
X
90%
90%
NEGATIVE
PULSE
V
V
M
R
M
X
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Open Collector Outputs
SWITCH POSITION LOAD VALUES
10%
10%
t
W
OUTPUT
ERROR
All other
R
100
500
V
X
V
CC
7.0V
TEST
SWITCH
closed
closed
open
X
Input Pulse Definition
Ω
Ω
t
PLZ
t
PZL
All other
DEFINITIONS:
R
C
=
=
Load resistor; see AC CHARACTERISTICS for value.
L
L
INPUT PULSE REQUIREMENTS
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
FAMILY
74ABT/H16
Rep. Rate
t
w
t
t
F
Amplitude
R
R
T
=
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns
2.5ns
3.0V
1MHz
500ns
SH00009
13
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
14
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
15
1998 Feb 25
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
74ABT16899
74ABTH16899
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03507
Document order number:
Philips
Semiconductors
it Q
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74ABT16899;
74ABTH16899; 18-
bit latched
download datasheet
Download datasheet
Products
transceiver with 16-
bit parity
generator/checker
(3-State)
MultiMarket
Semiconductors
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General description
The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either
bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted
with the SEL input.
Models
•
•
SoC solutions
Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-
State.
The 74ABT/H16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and
separate error signal output pins for checking parity.
Features
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Symmetrical (A and B bus functions are identical)
Selectable generate parity or 'feed-through' parity for A-to-B and B-to-A directions
Independent transparent latches for A-to-B and B-to-A directions
Selectable ODD/EVEN parity
Continuously checks parity of both A bus and B bus latches as ERRA and ERRB
Open-collector ERR output
Ability to simultaneously generate and check parity
Can simultaneously read/latch A and B bus data
Output capability: +64 mA/-32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
Power up 3-State
Power-up reset
Live insertion/extraction permitted
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
Applications
AN203_2: Test Fixtures for High Speed Logic (date 02-Apr-98)
AN2301: Simulation Support for Philips' Advanced BiCMOS Products
Datasheet
Type number
Title
Publication
release date
Datasheet status Page
File
Datasheet
count size
(kB)
74ABT16899;
74ABTH16899
18-bit latched transceiver 2/25/1998
with 16-bit parity
Product
specification
16
116
Download
generator/checker (3-
State)
Blockdiagram(s)
Block diagram of
74ABTH16899DL
Parametrics
Type number
Package
Description
Propagation Voltage No. Power
Logic
Switching Drive
Pins Considerations Levels Capability
Output
Delay(ns)
of Dissipation
18-Bit Latched
Transceiver with
Parity
Generator/Checker
(3-State)
SOT364-1
(TSSOP56)
5 Volts
+
74ABT16899DGG
74ABT16899DL
4~6
56 None
56 None
TTL
TTL
High
18-Bit Latched
Transceiver with
Parity
Generator/Checker
(3-State)
SOT371-1
(SSOP56)
5 Volts
+
4~6
4~6
High
High
18-Bit Latched
Transceiver with
Parity
Generator/Checker
with Bus Hold (3-
State)
SOT364-1
(TSSOP56)
5 Volts
+
74ABTH16899DGG
74ABTH16899DL
56 None
TTL
TTL
18-Bit Latched
Transceiver with
Parity
Generator/Checker
with Bus Hold (3-
State)
SOT371-1
(SSOP56)
5 Volts
+
4~6
56 None
High
Products, packages, availability and ordering
Type number
North American Ordering code Marking/Packing Package Device
Buy online
IC packing info
type number
(12NC)
status
SOT364-1
Standard Marking
* Tube
Full production
74ABT16899DGG 74ABT16899DG 9352 155 30112
(TSSOP56)
Standard Marking
SMD, 13"
SOT364-1
74ABT16899DG-
T
Full production
Full production
Full production
9352 155 30118 * Reel Pack,
(TSSOP56)
SOT371-1
(SSOP56)
Standard Marking
* Tube
74ABT16899DL
74ABT16899DL
9352 155 10112
Standard Marking
9352 155 10118 * Reel Pack,
SMD, 13"
SOT371-1
(SSOP56)
74ABT16899DL-
T
SOT364-1
Standard Marking
* Tube
Full production
74ABTH16899DGG 74ABTH16899DG 9352 089 70112
(TSSOP56)
Standard Marking
SMD, 13"
SOT364-1
74ABTH16899DG-
T
Full production
Full production
Full production
9352 089 70118 * Reel Pack,
(TSSOP56)
-
SOT371-1
(SSOP56)
Standard Marking
* Tube
74ABTH16899DL 74ABTH16899DL 9352 089 30112
74ABTH16899DL-
Standard Marking
9352 089 30118 * Reel Pack,
SOT371-1
(SSOP56)
T
SMD, 13"
Products in the above table are all in production. Some variants are discontinued; click here for information on these
variants.
Similar products
74ABT16899; 74ABTH16899 links to the similar products page containing an overview of products that are similar in
function or related to the type number(s) as listed on this page. The similar products page includes products from the same
catalog tree(s), relevant selection guides and products from the same functional category.
Support & tools
Introduction to Advanced BiCMOS Logic Products(date 01-Mar-98)
Family specifications ABT/H16, family characteristics(date 01-Mar-98)
Advanced BiCMOS features(date 01-Jan-98)
Family specifications MULTIBYTE(TM), family characteristics(date 01-Mar-98)
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