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74ABT543ADB,112 [NXP]

74ABT543A - Octal latched transceiver with dual enable; 3-state SSOP2 24-Pin;
74ABT543ADB,112
型号： 74ABT543ADB,112
厂家： NXP    NXP
描述：

74ABT543A - Octal latched transceiver with dual enable; 3-state SSOP2 24-Pin

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Important notice  
Dear Customer,  
On 7 February 2017 the former NXP Standard Product business became a new company with the  
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS  
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable  
application markets  
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use  
the references to Nexperia, as shown below.  
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,  
use http://www.nexperia.com  
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Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on  
the version, as shown below:  
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights  
reserved  
Should be replaced with:  
- © Nexperia B.V. (year). All rights reserved.  
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail  
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understanding,  
Kind regards,  
Team Nexperia  
74ABT543A  
Octal latched transceiver with dual enable; 3-state  
Rev. 5 — 3 November 2011  
Product data sheet  
1. General description  
The 74ABT543A high performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT543A octal registered transceiver contains two sets of D-type latches for  
temporary storage of data flowing in either direction. Separate latch enable (LEAB, LEBA)  
and output enable (OEAB, OEBA) inputs are provided for each register to permit  
independent control of data transfer in either direction. The outputs are guaranteed to sink  
64 mA.  
2. Features and benefits  
Combines 74ABT245 and 74ABT373 type functions in one device  
8-bit octal transceiver with D-type latch  
Back-to-back registers for storage  
Separate controls for data flow in each direction  
Live insertion and extraction permitted  
Output capability: +64 mA to 32 mA  
Power-up 3-state  
Power-up reset  
Latch-up protection exceeds 500 mA per JESD78B class II level A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74ABT543AD  
40 C to +85 C  
SO24  
plastic small outline package; 24 leads;  
body width 7.5 mm  
SOT137-1  
74ABT543ADB 40 C to +85 C  
74ABT543APW 40 C to +85 C  
SSOP24  
plastic shrink small outline package; 24 leads;  
body width 5.3 mm  
SOT340-1  
SOT355-1  
TSSOP24 plastic thin shrink small outline package; 24 leads;  
body width 4.4 mm  
 
 
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
4. Functional diagram  
2
1EN3 (BA)  
23  
G1  
1
1C5  
3
4
5
6
7
8
9
10  
13  
2EN4 (AB)  
11  
G2  
14  
A0 A1 A2 A3 A4 A5 A6 A7  
EAB  
2C6  
11  
23  
14  
1
3
22  
EBA  
OEAB  
OEBA  
13  
2
3
5D  
4
5
21  
20  
19  
18  
17  
16  
15  
LEAB  
LEBA  
2
6D  
6
B0 B1 B2 B3 B4 B5 B6 B7  
7
22 21 20 19 18 17 16 15  
8
001aae900  
9
10  
001aae901  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
2
OEBA  
13  
OEAB  
23  
1
EBA  
11  
14  
LEBA  
EAB  
LEAB  
DETAIL A  
22  
D
Q
B0  
LE  
3
A0  
Q
D
LE  
4
5
21  
20  
19  
18  
17  
16  
15  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
6
7
DETAIL A × 7  
8
9
10  
001aae902  
Fig 3. Logic diagram  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
2 of 16  
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
5. Pinning information  
5.1 Pinning  
74ABT543A  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
LEBA  
OEBA  
A0  
V
CC  
EBA  
B0  
3
4
A1  
B1  
5
A2  
B2  
6
A3  
B3  
7
A4  
B4  
8
A5  
B5  
9
A6  
B6  
10  
11  
12  
A7  
B7  
EAB  
GND  
LEAB  
OEAB  
001aae899  
Fig 4. Pin configuration  
5.2 Pin description  
Table 2.  
Symbol  
LEBA  
OEBA  
A0 to A7  
EAB  
Pin description  
Pin  
1
Description  
B-to-A latch enable input (active LOW)  
B-to-A output enable input (active LOW)  
data input or output  
2
3, 4, 5, 6, 7, 8, 9, 10  
11  
12  
13  
14  
A-to-B enable input (active LOW)  
ground (0 V)  
GND  
OEAB  
LEAB  
B0 to B7  
EBA  
A-to-B output enable input (active LOW)  
A-to-B latch enable input (active LOW)  
22, 21, 20, 19, 18, 17, 16, 15 data input or output  
23  
24  
B-to-A enable input (active LOW)  
VCC  
positive supply voltage  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
3 of 16  
 
 
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
6. Functional description  
6.1 Function table  
Table 3.  
Function selection[1]  
Input  
Output  
Status  
OEXX  
EXX  
X
LEXX  
An or Bn  
Bn or An  
H
X
L
X
X
L
X
X
h
l
Z
disabled  
H
Z
Z
disabled + latch  
latch + display  
transparent  
hold  
Z
L
L
L
L
L
L
L
h
l
H
L
H
L
X
H
L
H
NC  
[1] H = HIGH voltage level;  
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);  
L = LOW voltage level;  
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);  
= LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);  
NC = no change;  
X = don’t care;  
Z = high-impedance OFF-state.  
6.2 Description  
The 74ABT543A contains two sets of eight D-type latches, with separate control pins for  
each set.  
Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the  
A-to-B latch enable (LEAB) input and the A-to-B output enable (OEAB) input are all LOW,  
the A-to-B path is transparent.  
A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches  
where it is stored and the B outputs no longer change with the A inputs. With EAB and  
OEAB both LOW, the 3-state B output buffers are active and display the data present at  
the outputs of the A latches.  
Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs.  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
4 of 16  
 
 
 
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VCC  
VI  
Parameter  
Conditions  
Min  
0.5  
1.2  
0.5  
18  
50  
-
Max  
+7.0  
+7.0  
+5.5  
-
Unit  
V
supply voltage  
[1]  
[1]  
input voltage  
V
VO  
output voltage  
output in OFF-state or HIGH-state  
VI < 0 V  
V
IIK  
input clamping current  
output clamping current  
output current  
mA  
mA  
mA  
C  
C  
IOK  
IO  
VO < 0 V  
-
output in LOW-state  
128  
150  
+150  
[2]  
Tj  
junction temperature  
storage temperature  
-
Tstg  
65  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction  
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.  
8. Recommended operating conditions  
Table 5.  
Symbol  
VCC  
Recommended operating conditions  
Parameter  
Conditions  
Min  
4.5  
0
Typ  
Max  
5.5  
VCC  
-
Unit  
V
supply voltage  
-
-
-
-
-
-
-
-
VI  
input voltage  
V
VIH  
HIGH-level input voltage  
LOW-level input voltage  
HIGH-level output current  
LOW-level output current  
input transition rise and fall rate  
ambient temperature  
2.0  
-
V
VIL  
0.8  
-
V
IOH  
32  
-
mA  
mA  
ns/V  
C  
IOL  
64  
t/V  
Tamb  
0
10  
in free air  
40  
+85  
9. Static characteristics  
Table 6.  
Static characteristics  
Symbol Parameter  
Conditions  
25 C  
Typ Max  
40 C to +85 C Unit  
Min  
1.2 0.9  
Min  
Max  
VIK  
input clamping voltage VCC = 4.5 V; IIK = 18 mA  
-
1.2  
-
V
VOH  
HIGH-level output  
voltage  
VI = VIL or VIH  
VCC = 4.5 V; IOH = 3 mA  
VCC = 5.0 V; IOH = 3 mA  
VCC = 4.5 V; IOH = 32 mA  
2.5  
3.0  
2.0  
-
3.2  
3.7  
2.3  
0.3  
-
2.5  
3.0  
2.0  
-
-
V
V
V
V
-
-
-
-
VOL  
LOW-level output  
voltage  
VCC = 4.5 V; IOL = 64 mA;  
VI = VIL or VIH  
0.55  
0.55  
VOL(pu)  
power-up LOW-level  
output voltage  
VCC = 5.5 V; IO = 1 mA;  
VI = GND or VCC  
-
0.13 0.55  
-
0.55  
V
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
5 of 16  
 
 
 
 
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
Table 6.  
Static characteristics …continued  
Symbol Parameter  
Conditions  
25 C  
40 C to +85 C Unit  
Min  
Typ Max  
Min  
Max  
II  
input leakage current VCC = 5.5 V; VI = GND or 5.5 V  
OEAB, OEBA  
An, Bn  
-
-
-
0.01 1.0  
5.0 100  
5.0 100  
-
-
-
1.0 A  
100 A  
100 A  
IOFF  
power-off leakage  
current  
VCC = 0.0 V; VI or VO 4.5 V  
[1]  
IO(pu/pd)  
power-up/power-down VCC = 2.1 V; VO = 0.5 V;  
-
5.0 50  
-
50  
A  
output current  
VI = GND or VCC;  
OEAB, OEBA don’t care  
VCC = 5.5 V; VI = VIL or VIH  
VO = 2.7 V  
IOZ  
OFF-state output  
current  
-
-
-
5.0  
50  
-
-
-
50  
50  
50  
A  
A  
A  
VO = 0.5 V  
5.0 50  
ILO  
output leakage current HIGH-state; VO = 5.5 V;  
VCC = 5.5 V; VI = GND or VCC  
5.0  
50  
[2]  
IO  
output current  
supply current  
VCC = 5.5 V; VO = 2.5 V  
VCC = 5.5 V; VI = GND or VCC  
outputs HIGH-state  
180 65  
40  
180  
40  
mA  
ICC  
-
-
-
-
110  
20  
250  
30  
-
-
-
-
250  
30  
A  
mA  
A  
mA  
outputs LOW-state  
outputs disabled  
110  
0.3  
250  
1.5  
250  
1.5  
[3]  
ICC  
additional supply  
current  
per input pin; VCC = 5.5 V; one input  
pin at 3.4 V, other inputs at VCC or  
GND  
CI  
input capacitance  
VI = 0 V or VCC  
-
-
4
7
-
-
-
-
-
-
pF  
pF  
CI/O  
input/output  
capacitance  
outputs disabled; VO = 0 V or VCC  
[1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V 10 %,  
a transition time of up to 100 s is permitted.  
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
[3] This is the increase in supply current for each input at 3.4 V.  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
GND = 0 V; for test circuit, see Figure 10.  
Symbol Parameter  
Conditions  
25 C; VCC = 5.0 V 40 C to +85 C; Unit  
CC = 5.0 V 0.5 V  
V
Min Typ Max  
Min  
1.0  
1.0  
1.9  
2.1  
1.0  
1.0  
Max  
5.2  
6.2  
5.7  
6.7  
6.2  
6.2  
tPLH  
tPHL  
tPZH  
LOW to HIGH  
propagation delay  
An to Bn or Bn to An; see Figure 5  
LEBA to An or LEAB to Bn; see Figure 6  
An to Bn or Bn to An; see Figure 5  
LEBA to An or LEAB to Bn; see Figure 6  
1.0  
1.0  
1.9  
2.1  
1.0  
1.0  
2.9  
3.4  
3.6  
4.3  
3.2  
3.4  
4.5  
5.1  
5.2  
6.0  
5.1  
5.1  
ns  
ns  
ns  
ns  
ns  
ns  
HIGH to LOW  
propagation delay  
OFF-state to HIGH OEBA to An, OEAB to Bn; see Figure 7  
propagation delay  
EBA to An, EAB to Bn; see Figure 7  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
6 of 16  
 
 
 
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
Table 7.  
Dynamic characteristics …continued  
GND = 0 V; for test circuit, see Figure 10.  
Symbol Parameter  
Conditions  
25 C; VCC = 5.0 V 40 C to +85 C; Unit  
VCC = 5.0 V 0.5 V  
Min Typ Max  
Min  
2.0  
2.0  
2.0  
2.0  
1.0  
1.0  
2.5  
3.5  
3.0  
3.0  
0.5  
0.5  
0.5  
0.5  
3.5  
Max  
tPZL  
tPHZ  
tPLZ  
tsu(H)  
tsu(L)  
th(H)  
th(L)  
tWL  
OFF-state to LOW OEBA to An, OEAB to Bn; see Figure 8  
2.0  
2.0  
2.0  
2.0  
1.0  
1.0  
2.5  
3.5  
3.0  
3.0  
4.3  
4.4  
4.0  
3.6  
3.0  
3.0  
1.0  
1.3  
1.4  
1.4  
5.9  
6.6  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
propagation delay  
EBA to An, EAB to Bn; see Figure 8  
6.1  
6.8  
HIGH to OFF-state OEBA to An, OEAB to Bn; see Figure 7  
5.7  
6.2  
propagation delay  
EBA to An, EAB to Bn; see Figure 7  
5.4  
5.9  
LOW to OFF-state OEBA to An, OEAB to Bn; see Figure 8  
4.6  
5.0  
propagation delay  
EBA to An, EAB to Bn; see Figure 8  
4.6  
5.0  
set-up time HIGH  
set-up time LOW  
hold time HIGH  
hold time LOW  
pulse width LOW  
An to LEAB, Bn to LEBA; see Figure 9  
An to EAB, Bn to EBA; see Figure 9  
An to LEAB, Bn to LEBA; see Figure 9  
An to EAB, Bn to EBA; see Figure 9  
LEAB to An, LEBA to Bn; see Figure 9  
EAB to An, EBA to Bn; see Figure 9  
LEAB to An, LEBA to Bn; see Figure 9  
EAB to An, EBA to Bn; see Figure 9  
latch enable; see Figure 9  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+0.5 0.8  
+0.5 0.8  
+0.5 0.6  
+0.5 0.6  
3.5  
1.0  
11. Waveforms  
V
I
An or Bn  
GND  
V
V
M
M
t
t
PHL  
PLH  
V
OH  
Bn or An  
V
V
M
M
V
OL  
001aae904  
VM = 1.5 V.  
VOL and VOH are typical voltage output levels that occur with the output load.  
Fig 5. Propagation delay input (An, Bn) to output (Bn, An)  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
7 of 16  
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
V
I
LEAB or LEBA  
GND  
V
V
M
M
t
t
PLH  
PHL  
V
OH  
An or Bn  
V
V
M
M
V
OL  
001aae903  
VM = 1.5 V.  
V
OL and VOH are typical voltage output levels that occur with the output load.  
Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn)  
V
I
OEAB, OEBA,  
EAB, EBA  
V
V
M
M
GND  
t
t
PHZ  
PZH  
V
OH  
V
− 0.3 V  
OH  
An, Bn  
GND  
V
M
001aae907  
VM = 1.5 V.  
VOH is a typical voltage output level that occurs with the output load.  
Fig 7. Propagation delay 3-state output enable to HIGH-level and output disable from HIGH-level  
V
I
OEAB, OEBA,  
EAB, EBA  
V
V
M
M
GND  
t
t
PLZ  
PZL  
3.5 V  
An, Bn  
V
M
V
OL  
+ 0.3 V  
V
OL  
001aae906  
VM = 1.5 V.  
OL is a typical voltage output level that occurs with the output load.  
V
Fig 8. Propagation delay 3-state output enable to LOW-level and output disable from LOW-level  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
8 of 16  
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
V
I
V
V
V
V
M
An, Bn  
GND  
M
M
M
t
t
t
t
h(L)  
su(H)  
h(H)  
su(L)  
t
WL  
V
I
LEAB, LEBA,  
V
V
M
M
EAB, EBA  
GND  
001aae905  
VM = 1.5 V.  
The shaded areas indicate when the input is permitted to change for predictable output performance.  
Fig 9. Data set-up and hold times and latch enable pulse width  
t
W
V
I
90 %  
90 %  
negative  
pulse  
V
EXT  
V
V
M
M
V
CC  
10 %  
10 %  
0 V  
R
L
V
V
O
I
t
t
r
f
G
DUT  
t
t
f
r
V
I
R
T
C
L
R
L
90 %  
90 %  
positive  
pulse  
V
M
V
M
mna616  
10 %  
10 %  
0 V  
t
W
001aai298  
a. Input pulse definition  
b. Test circuit  
Test data is given in Table 8.  
Test circuit definitions:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
EXT = Test voltage for switching times.  
V
Fig 10. Load circuitry for switching times  
Table 8.  
Input  
VI  
Test data  
Load  
CL  
VEXT  
fI  
tW  
tr, tf  
RL  
tPHL, tPLH  
open  
tPZH, tPHZ  
tPZL, tPLZ  
7.0 V  
3.0 V  
1 MHz  
500 ns  
2.5 ns  
50 pF  
500   
open  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
9 of 16  
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
12. Package outline  
SO24: plastic small outline package; 24 leads; body width 7.5 mm  
SOT137-1  
D
E
A
X
c
H
v
M
A
E
y
Z
24  
13  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
12  
w
detail X  
e
M
b
p
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
max.  
(1)  
(1)  
(1)  
UNIT  
mm  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3  
0.1  
2.45  
2.25  
0.49  
0.36  
0.32  
0.23  
15.6  
15.2  
7.6  
7.4  
10.65  
10.00  
1.1  
0.4  
1.1  
1.0  
0.9  
0.4  
2.65  
0.1  
0.25  
0.01  
1.27  
0.05  
1.4  
0.25 0.25  
0.01  
0.1  
8o  
0o  
0.012 0.096  
0.004 0.089  
0.019 0.013 0.61  
0.014 0.009 0.60  
0.30  
0.29  
0.419  
0.394  
0.043 0.043  
0.016 0.039  
0.035  
0.016  
inches  
0.055  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT137-1  
075E05  
MS-013  
Fig 11. Package outline SOT137-1 (SO24)  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
10 of 16  
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm  
SOT340-1  
D
E
A
X
v
c
H
M
A
y
E
Z
24  
13  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
12  
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
8.4  
8.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
0.8  
0.4  
mm  
2
0.65  
1.25  
0.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT340-1  
MO-150  
Fig 12. Package outline SOT340-1 (SSOP24)  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
11 of 16  
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm  
SOT355-1  
D
E
A
X
c
H
v
M
A
y
E
Z
13  
24  
Q
A
2
(A )  
3
A
A
1
pin 1 index  
θ
L
p
L
1
12  
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
7.9  
7.7  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.5  
0.2  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT355-1  
MO-153  
Fig 13. Package outline SOT355-1 (TSSOP24)  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
12 of 16  
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
13. Abbreviations  
Table 9.  
Acronym  
BiCMOS  
DUT  
Abbreviations  
Description  
Bipolar Complementary Metal-Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
HBM  
Human Body Model  
MM  
Machine Model  
14. Revision history  
Table 10. Revision history  
Document ID  
74ABT543A v.5  
Modifications:  
74ABT543A v.4  
74ABT543A v.3  
74ABT543A v.2  
74ABT543A v.1  
Release date  
20111103  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
74ABT543A v.4  
• Legal pages updated  
20100507  
20100126  
19980924  
19950419  
Product data sheet  
-
-
-
-
74ABT543A v.3  
74ABT543A v.2  
74ABT543A v.1  
-
Product data sheet  
Product specification  
Product specification  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
13 of 16  
 
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
15.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
15.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
14 of 16  
 
 
 
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74ABT543A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 5 — 3 November 2011  
15 of 16  
 
 
74ABT543A  
NXP Semiconductors  
Octal latched transceiver with dual enable; 3-state  
17. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 1  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
6
6.1  
6.2  
Functional description . . . . . . . . . . . . . . . . . . . 4  
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Recommended operating conditions. . . . . . . . 5  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13  
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 15  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 3 November 2011  
Document identifier: 74ABT543A  
 

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