74ABT651D-T [NXP]
Single 8-Bit Inverting Bus Transceiver ; 一个8位反相总线收发器\n
| 型号： | 74ABT651D-T |
| 厂家： | 
NXP |
| 描述： | Single 8-Bit Inverting Bus Transceiver
|
| 文件： | 总7页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
FEATURES
• Independent registers for A and B buses
DESCRIPTION
The 74ABT651 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
• The 74ABT651 is the inverting version of the 74ABT652
• Multiplexed real-time and stored data
• 3-State outputs
The 74ABT651 transceiver/register consists of bus transceiver
circuits with 3-State outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from the input
bus or the internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes High. Output
Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for
bus management.
• Live insertion/extraction permitted.
• Power-up 3-State
• Power-up reset
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ABT651.
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
The select pins determine whether data is stored or transferred
through the device in real time.
and 200 V per Machine Model
The output enable pins determine the direction of the data flow.
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
3.8
4.4
PLH
PHL
C = 50pF; V = 5V
ns
L
CC
CPBA to An or CPAB to Bn
Input capacitance
C
V = 0V or V
I CC
4
7
pF
pF
µA
IN
C
I/O capacitance
Outputs disabled; V = 0V or V
O CC
I/O
I
Total supply current
Outputs disabled; V =5.5V
110
CCZ
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT651 N
DWG NUMBER
SOT222-1
24-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT651 N
74ABT651 D
74ABT651 DB
74ABT651 PW
24-Pin plastic SO
74ABT651 D
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT651 DB
74ABT651PW DH
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN
SYMBOL
NUMBER
FUNCTION
CPAB
SAB
OEAB
A0
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CPAB /
1, 23
CPBA
SBA
OEBA
B0
A to B clock input / B to A clock input
A to B select input / B to A select input
CPBA
SAB /
2, 22
SBA
A1
A to B Output Enable input /
B to A Output Enable input
(active–Low)
OEAB /
3, 21
A2
B1
OEBA
A3
B2
4, 5, 6, 7, 8,
9, 10, 11
A0 – A7 Data inputs/outputs (A side)
A4
B3
A5
B4
20, 19, 18,
17, 16, 15,
14, 13
B0 – B7 Data inputs/outputs (B side)
A6 10
A7 11
B5
B6
12
24
GND
Ground (0V)
GND 12
B7
V
CC
Positive supply voltage
SA00094
1
1995 Sep 06
853-1783 15703
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
LOGIC SYMBOL (IEEE/IEC)
LOGIC SYMBOL
4
5
6
7
8
9
10 11
21
EN1 [BA]
3
23
22
1
EN2 [AB]
C4
A0 A1 A2 A3 A4 A5 A6 A7
G5
C6
23
22
2
CPBA
2
G7
SBA
OEAB
OEBA
3
SAB
21
5
5
4D
20
4
w1
ʼn1
1
CPAB
1
6D
1
7
7
w1
2ʼn
B0 B1 B2 B3 B4 B5 B6 B7
20 19 18 17 16 15 14 13
5
6
19
18
17
16
15
14
13
SA00095
7
8
9
10
11
SA00125
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A OR B
A
B
A
B
A
B
A
B
OEABOEBACPAB CPBA SAB SBA
OEABOEBACPAB CPBA SAB SBA
OEABOEBACPAB CPBA SAB SBA
OEABOEBACPAB CPBA SAB SBA
L
L
X
X
X
L
H
H
X
X
L
X
X
L
L
H
X
H
↑
X
↑
X
↑
X
X
X
X
X
X
H
L
H | L H | L
H
H
↑
SA00097
2
1995 Sep 06
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
FUNCTION TABLE
INPUTS
CPAB
DATA I/O
OPERATING MODE
OEAB
OEBA
CPBA
SAB
SBA
An
Bn
L
L
H
H
H or L
↑
H or L
↑
X
X
X
X
Isolation
Store A and B data
Input
Input
X
H
H
H
↑
↑
H or L
↑
X
**
X
X
Unspecified
output*
Store A, Hold B
Store A in both registers
Input
L
L
X
L
H or L
↑
↑
↑
X
X
X
**
Unspecified
output*
Hold A, Store B
Store B in both registers
Input
Input
L
L
L
L
X
X
X
X
X
L
H
Real time B data to A bus
Stored B data to A bus
Output
Input
H or L
H
H
H
H
X
X
X
L
H
X
X
Real time A data to B bus
Store A data to B bus
Output
Output
H or L
Stored A data to B bus
Stored B data to A bus
H
L
H or L
H or L
H
H
Output
H
L
X
↑
=
=
=
=
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
*
The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be
staggered in order to load both registers.
**
LOGIC DIAGRAM
21
3
OEBA
OEAB
CPBA
SBA
23
22
1
CPAB
SAB
2
1of 8 Channels
1D
C1
Q
4
20
A0
B0
1D
C1
Q
5
6
19
18
17
16
15
14
13
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
7
8
DETAIL A X 7
9
10
11
SA00098
3
1995 Sep 06
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. 1Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
Min
4.5
0
Max
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
10
T
amb
Operating free-air temperature range
–40
+85
4
1995 Sep 06
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
DC ELECTRICAL CHARACTERISTICS
LIMITS
= +25°C
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
V
V
V
V
V
= 4.5V; I = –18mA
–0.9
3.2
–1.2
–1.2
V
V
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
V
OH
High–level output voltage
= 5.0V; I = –3mA; V = V or V
3.7
V
OH
I
IL
IH
= 4.5V; I = –32mA; V = V or V
IH
2.30
0.42
0.13
±0.01
±5
V
OH
I
IL
V
OL
Low–level output voltage
= 4.5V; I = 64mA; V = V or V
IH
0.55
0.55
±1.0
±100
±100
0.55
0.55
±1.0
±100
±100
V
OL
I
IL
3
V
RST
Power-up output low voltage
= 5.5V; I = 1mA; V = GND or V
V
O
I
CC
Control pins
= 5.5V; V = GND or 5.5V
µA
µA
µA
I
Input leakage
I
I
current
Data pins
= 5.5V; V = GND or 5.5V
I
I
Power-off leakage current
= 0.0V; V or V ≤ 4.5V
±5.0
OFF
O
I
Power-up/down 3-State
= 2.1V; V = 0.5V; V
= Don’t Care;
OE
O
I
/I
±5.0
±50
±50
µA
PU PD
4
output current
V = GND or V
I CC
I
+ I
+ I
3–State output High current
3–State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
IH
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
IL
OZL
IH
I
= 5.5V; V = 5.5V; V = GND or V
O I CC
CEX
1
I
O
Output current
= 5.5V; V = 2.5V
–40
–65
110
20
–180
250
30
–40
–180
250
30
O
I
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
= 5.5V; Outputs Low, V = GND or V
CCL
I
CC
Quiescent supply current
= 5.5V; Outputs 3–State;
110
0.3
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
CC
mA
2
input pin
other inputs at V or GND; V = 5.5V
CC CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V, with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
T
= -40 to
+85 C
= +5.0V ±0.5V
amb
o
T
V
= +25 C
amb
CC
o
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
V
CC
Min
Typ
Min
Max
f
Maximum clock frequency
1
1
125
300
125
MHz
ns
MAX
t
t
Propagation delay
CPAB to Bn or CPBA to An
2.2
1.7
3.8
4.4
5.1
5.1
2.2
1.7
5.6
5.6
PLH
PHL
t
t
Propagation delay
An to Bn or Bn to An
1.5
1.5
3.2
3.7
5.1
4.6
1.5
1.5
6.2
5.4
PLH
PHL
2
3
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
SAB to Bn or SBA to An
1.5
1.5
3.8
4.4
5.1
4.9
1.5
1.5
6.5
5.9
PLH
PHL
t
Output enable time
OEBA to An
5
6
1.3
2.5
3.7
4.7
4.6
6.8
1.3
2.5
5.8
8.5
PZH
t
PZL
t
Output disable time
OEBA to An
5
6
1.5
1.5
4.0
3.2
4.5
3.8
1.5
1.5
5.0
4.1
PHZ
t
PLZ
t
Output enable time
OEAB to Bn
5
6
1.8
2.9
3.4
4.5
6.1
6.5
1.8
2.9
6.5
7.4
PZH
t
PZL
t
Output disable time
OEAB to Bn
5
6
1.5
1.5
3.8
3.1
4.5
4.4
1.5
1.5
5.5
5.1
PHZ
t
PLZ
5
1995 Sep 06
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
Min
Typ
Min
t (H)
t (L)
s
Setup time
An to CPAB, Bn to CPBA
3.0
3.0
1.2
0.8
3.0
3.0
s
4
4
1
ns
ns
ns
t (H)
Hold time
An to CPAB, Bn to CPBA
0.0
0.0
–0.8
–0.9
0.0
0.0
h
t (L)
h
t (H)
Pulse width, High or Low
CPAB or CPBA
4.0
4.0
1.2
1.1
4.0
4.0
w
t (L)
w
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
1/f
MAX
An or Bn
V
V
V
V
V
M
M
M
M
CPBA or
CPAB
V
V
V
t
M
t
M
M
t (H)
s
t (L)
s
t
(H)
t (L)
h
h
(H)
t (L)
w
w
t
W
(L)
CPBA or
CPAB
t
PHL
PLH
V
M
M
An or Bn
V
V
M
M
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00087
SA00090
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
Waveform 4. Data Setup and Hold Times
OEBA
An or Bn
V
V
M
M
t
V
V
M
t
M
t
OEAB
t
PZH
PHZ
PLH
PHL
V
–0.3V
0V
An or Bn
OH
V
M
V
M
V
Bn or An
M
SA00100
SA00016
Waveform 5. 3–State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 2. Propagation Delay, An to Bn or Bn to An
OEBA
SBA or SAB
An or Bn
V
V
V
V
M
M
t
M
M
t
OEAB
t
t
PLZ
PHL
PLH
PZL
V
V
M
M
V
M
An or Bn
V
+0.3V
OL
0V
SA00089
SA00101
Waveform 3. Propagation Delay, SBA to An or SAB to Bn
Waveform 6. 3–State Output Enable Time to Low Level and
Output Disable Time from Low Level
6
1995 Sep 06
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
TEST CIRCUIT AND WAVEFORM
V
t
W
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
R
L
L
0V
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
(t )
R
THL
F
TLH
)
(t )
F
R
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00012
7
1995 Sep 06
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