74ABT823N [NXP]
9-bit D-type flip-flop with reset and enable 3-State; 9位D型触发器与复位和使能三态
| 型号： | 74ABT823N |
| 厂家： | 
NXP |
| 描述： | 9-bit D-type flip-flop with reset and enable 3-State |
| 文件： | 总7页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
FEATURES
DESCRIPTION
The 74ABT823 Bus interface Register is designed to eliminate the
extra packages required to buffer existing registers and provide
extra data width for wider data/address paths of buses carrying
parity.
• High speed parallel registers with positive edge-triggered D-type
flip-flops
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
The 74ABT823 is a 9-bit wide buffered register with Clock Enable
(CE) and Master Reset (MR) which are ideal for parity bus
interfacing in high microprogrammed systems.
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
The register is fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power-up 3-State
• Power-up Reset
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
CP to Qn
PLH
PHL
C = 50pF; V = 5V
4.4
4
ns
pF
pF
nA
L
CC
C
Input capacitance
V = 0V or V
I CC
IN
Outputs disabled;
= 0V or V
C
Output capacitance
Total supply current
7
OUT
CCZ
V
O
CC
I
Outputs disabled; V =5.5V
500
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT823 N
DWG NUMBER
SOT222-1
24-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT823 N
74ABT823 D
74ABT823 DB
74ABT823 PW
24-Pin plastic SO
74ABT823 D
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT823 DB
74ABT823PW DH
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
Output enable input
(active-Low)
1
OE
D0-D8
Q0-Q8
CP
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
2, 3, 4, 5, 6,
7, 8, 9, 10
Data inputs
23, 22, 21, 20,
19,18, 17, 16, 15
Data outputs
Clock pulse input (active
rising edge)
13
14
11
Clock enable input
(active-Low)
CE
Master reset input
(active-Low)
MR
D8 10
MR 11
15
14
13
Q8
CE
CP
12
24
GND
Ground (0V)
GND 12
V
CC
Positive supply voltage
TOP VIEW
SA00227
1
1995 Sep 06
853–1617 15703
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1
EN
11
R
2
3
4
5
6
7
8
9
10
14
G1
13
1C2
D0 D1 D2 D3 D4 D5 D6 D7 D8
13
14
CP
CE
2
23
22
21
20
19
18
17
16
15
2D
3
11
1
MR
4
5
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
6
7
23 22 21 20 19 18 17 16 15
8
9
10
SA00228
SA00229
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
OE
L
MR
L
CE
X
CP
X
↑
Dn
X
h
Q0 – Q8
L
H
Clear
L
H
L
Load and read data
L
H
L
↑
l
L
L
H
H
X
↑
X
X
NC
Z
Hold
H
X
X
High impedance
H
h
=
=
High voltage level
High voltage level one set-up time prior to the Low-to-High
clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High
clock transition
NC
X
Z
↑
↑
=
=
=
=
=
No change
Don’t care
High impedance “off” state
Low to High clock transition
Not a Low-to-High clock transition
L
l
=
=
LOGIC DIAGRAM
14
CE
D0
D1
D2
D3
D4
D5
D6
D7
D8
10
2
3
4
5
6
7
8
9
13
CP
CP
Q
CP
Q
CP
Q
CP
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
D
D
D
R
D
D
D
D
D
R
D
R
R
R
RR
Q
R
R
R
11
MR
OE
1
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
SA00230
2
1995 Sep 06
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
5
T
amb
Operating free-air temperature range
–40
+85
3
1995 Sep 06
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.9
2.9
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
IH
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
Low-level output voltage
Power-up output low
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
0.55
0.55
OL
I
IL
V
RST
V
CC
= 5.5V; I = 1mA; V = GND or V
CC
0.13
V
O
I
3
voltage
I
Input leakage current
V
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5.0
±1.0
±1.0
µA
µA
I
CC
CC
CC
I
I
Power-off leakage current
Power-up/down 3-State
= 0.0V; V or V ≤ 4.5V
±100
±100
OFF
O
I
= 2.0V; V = 0.5V; V
= V
;
O
OE
CC
I
/I
±5.0
±50
±50
µA
PU PD
4
output current
V = GND or V
I CC
I
3-State output High current
3-State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
IH
5.0
–5.0
5.0
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
I
= 5.5V; V = 0.5V; V = V or V
O I IL IH
OZL
I
= 5.5V; V = 5.5V; V = GND or V
O I CC
CEX
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–100
0.5
–180
250
34
–50
–180
250
34
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
27
CCL
I
CC
= 5.5V; Outputs 3-State;
I
0.5
0.5
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
mA
CC
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. For V = 2.1V to V = 5V " 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
T
= -40 to
+85 C
= +5.0V ±0.5V
amb
o
T
V
= +25 C
amb
CC
o
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
V
CC
Min
Typ
Min
Max
f
Maximum clock frequency
1
1
125
200
125
MHz
ns
MAX
t
t
Propagation delay
CP to Qn
2.1
2.2
4.3
4.4
5.9
6.1
2.1
2.2
6.8
6.7
PLH
PHL
Propagation delay
MR to Qn
t
2
2.0
4.1
6.3
2.0
7.1
ns
ns
ns
PHL
t
t
Output enable time
to High and Low level
4
5
1.0
2.2
3.0
4.1
4.5
5.6
1.0
2.2
5.3
6.3
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
2.7
2.8
4.8
5.0
6.2
6.4
2.7
2.8
6.9
6.9
PHZ
PLZ
4
1995 Sep 06
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
Min
Typ
Min
t (H)
t (L)
s
Setup time, High or Low
Dn to CP
2.1
2.1
0.5
0.2
2.1
2.1
s
3
3
1
3
ns
ns
ns
ns
t (H)
Hold time, High or Low
Dn to CP
1.3
1.3
0.0
–0.3
1.3
1.3
h
t (L)
h
t (H)
CP pulse width
High or Low
2.9
3.8
1.9
2.8
2.9
3.8
w
t (L)
w
t (H)
Setup time, High or Low
CE to CP
2.0
3.3
–0.5
1.5
2.0
3.3
s
t (L)
s
t (H)
t (L)
h
Hold time, High or Low
CE to CP
1.0
2.0
–1.4
0.7
1.0
2.0
h
3
2
2
ns
ns
ns
t (L)
w
MR pulse width, Low
5.5
2.5
4.0
0.6
5.5
2.5
Recovery time
MR to CP
t
rec
5
1995 Sep 06
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
MR
V
V
M
M
1/f
MAX
t
(L)
t
w
REC
CP
V
V
M
M
t
CP
Qn
V
M
(H)
t
(L)
W
W
t
t
PLH
PHL
t
PHL
V
Q
n
V
M
M
V
M
SA00232
Waveform 2. Master Reset Pulse WIdth, Master Reset to Output
Delay and Master Reset to Clock Recovery Time
SA00159
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
V
V
M
OE
Qn
M
Dn, CE
V
V
V
V
M
M
M
M
t
t
PHZ
PZH
t (H)
t
(H)
t (L)
t (L)
h
s
h
s
V
–0.3V
0V
OH
V
M
CP
V
V
M
M
NOTE: The shaded areas indicate when the input is permitted to change for
predictable output performance.
SA00066
SA00231
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 3. Data Setup and Hold Times
OE
V
V
M
M
t
t
PLZ
PZL
V
M
Qn
V
+0.3V
OL
0V
SA00067
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
6
1995 Sep 06
Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
TEST CIRCUIT AND WAVEFORM
V
t
W
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
L
0V
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
(t
)
R
THL
F
TLH
)
(t )
F
R
R
L
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00012
7
1995 Sep 06
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