74ABT843D [NXP]
9-bit interface latch with set and reset 3-State; 9位锁存器的接口与置位和复位三态
| 型号： | 74ABT843D |
| 厂家： | 
NXP |
| 描述： | 9-bit interface latch with set and reset 3-State |
| 文件： | 总14页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT843
9-bit interface latch with set and reset
(3-State)
Product specification
Supersedes data of 1995 Sep 06
IC23 Data Handbook
1998 Jan 16
Philips
Semiconductors
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
FEATURES
• High speed parallel latches
DESCRIPTION
The 74ABT843 Bus interface latch is designed to eliminate the extra
packages required to buffer existing registers and provide extra data
width for wider data/address paths of buses carrying parity.
• Extra data width for wide address/data paths or buses carrying
parity
The 74ABT843 consists of nine D-type latches with 3-State outputs.
In addition to the LE and OE pins, it has a Master Reset (MR) pin
and Preset (PRE) pin. These pins are ideal for parity bus interfacing
in high performance systems. When MR is Low, the outputs are Low
if OE is Low. When MR is High, data can be entered into the latch.
When PRE is Low, the outputs are High, if OE is Low. PRE
overrides MR.
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Slim DIP 300 mil package
• Broadside pinout
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
• Power-up 3-State
• Power-up reset
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
Dn to Qn
PLH
PHL
C = 50pF; V = 5V
5.0
4
ns
pF
pF
nA
L
CC
C
Input capacitance
V = 0V or V
I CC
IN
Outputs disabled;
= 0V or V
C
Output capacitance
Total supply current
7
OUT
CCZ
V
O
CC
I
Outputs disabled; V = 5.5V
500
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT843 N
DWG NUMBER
SOT222-1
24-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT843 N
74ABT843 D
74ABT843 DB
74ABT843 PW
24-Pin plastic SO
74ABT843 D
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT843 DB
74ABT843PW DH
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
24
V
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
CC
Output enable input
(active-Low)
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
1
OE
2, 3, 4, 5, 6,
7, 8, 9, 10
D0-D8
Data inputs
23, 22, 21, 20,
19,18, 17, 16, 15
Q0-Q8
MR
Data outputs
TOP VIEW
11
13
Master reset input (active-Low)
Latch enable input (active rising
edge)
LE
14
12
24
PRE
GND
Preset input (active-Low)
Ground (0V)
D8 10
MR 11
15
14
13
Q8
PRE
LE
GND 12
V
CC
Positive supply voltage
SA00250
2
1998 Jan 16
853-1620 18864
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1
EN
11
R
14
S2
13
C1
2
3
4
5
6
7
8
9
10
D0 D1 D2 D3 D4 D5 D6 D7 D8
13
14
LE
2
23
22
21
20
19
18
17
16
15
1D
PRE
3
4
5
11
1
MR
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
6
7
8
23 22 21 20 19 18 17 16 15
SA00251
9
10
SA00252
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
OE
L
PRE
L
MR
X
LE
X
Dn
X
Qn
H
Preset
L
H
L
X
X
L
Clear
L
L
H
H
H
H
H
H
L
H
L
H
Transparent
L
L
H
H
H
H
↓
↓
l
h
L
H
Latched
H
L
X
H
X
H
X
L
X
X
Z
High impedance
Hold
NC
H
h
L
l
=
=
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low LE transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low LE transition
NC= No change
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-Low transition
3
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
10
2
3
4
5
6
7
8
9
14
PRE
P
P
P
P
P
P
P
P
P
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
C
C
C
C
C
C
C
C
C
11
MR
13
1
LE
OE
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
SA00253
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +7.0
–18
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
5.5
V
DC supply voltage
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
10
T
amb
Operating free-air temperature range
–40
+85
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.9
2.9
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
IH
V
OH
High–level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
Low–level output voltage
Power–up output low
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
0.55
0.55
OL
I
IL
V
RST
V
CC
= 5.5V; I = 1mA; V = V or GND
0.13
V
O
I
CC
3
voltage
I
Input leakage current
V
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5.0
±1.0
±1.0
µA
µA
I
CC
CC
CC
I
I
Power-off leakage current
= 0.0V; V or V ≤ 4.5V
±100
±100
OFF
O
I
Power-up/down 3–state
= 2.0V; V = 0.5V; V
= V ; V =
O
OE
CC
I
I
I
±5.0
±50
±50
µA
PU/ PD
4
output current
GND or V
CC
I
3-State output High current
3-State output Low current
Output high leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
–80
0.5
25
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
OZL
I
= 5.5V; V = 5.5V; V = GND or V
O I CC
CEX
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–180
250
34
–50
–180
250
34
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
CCL
I
CC
= 5.5V; Outputs 3-State;
I
0.5
0.5
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
mA
CC
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip–flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. For V = 2.1V to V = 5V " 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
5
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
AC CHARACTERISTICS
LIMITS
Max
T
= -40 to
+85 C
= +5.0V ±0.5V
amb
o
T
V
= +25 C
amb
CC
o
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
V
CC
Min
Typ
Min
Max
t
t
Propagation delay
Dn to Qn
1.6
2.2
3.6
5.0
5.2
6.3
1.6
2.2
6.0
7.2
PLH
PHL
1
2
1
1
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
LE to Qn
2.0
2.8
4.1
4.8
5.6
6.3
2.0
2.8
6.5
6.9
PLH
PHL
t
t
Propagation delay
PRE to Qn
2.2
3.0
4.7
5.2
6.2
6.5
2.2
3.0
7.4
7.2
PLH
PHL
t
t
Propagation delay
MR to Qn
2.5
3.1
5.0
5.5
6.3
6.8
2.5
3.1
7.1
8.0
PLH
PHL
t
t
Output enable time
OE to Qn
4
5
1.0
2.0
2.7
4.2
4.2
5.5
1.0
2.0
5.2
6.5
PZH
PZL
t
t
Output disable time
OE to Qn
4
5
2.9
2.2
4.9
5.0
6.2
6.3
2.9
2.2
6.8
6.7
PHZ
PLZ
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
= +5.0V
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V ±0.5V
Min
Typ
Min
t (H)
t (L)
s
Setup time, High or Low
Dn to LE
2.5
3.0
1.1
1.3
2.5
3.0
s
3
3
ns
ns
t (H)
Hold time, High or Low
Dn to LE
1.0
1.0
–1.0
–1.0
1.0
1.0
h
t (L)
h
t (H)
LE pulse width, High
PRE pulse width, Low
MR pulse width, Low
PRE recovery time
MR recovery time
3
6
6
6
6
3.3
4.5
5.5
2.9
3.6
1.8
3.0
4.0
1.6
2.0
3.3
4.5
5.5
2.9
3.6
ns
ns
ns
ns
ns
w
t (L)
w
t (L)
w
t
t
rec
rec
6
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
Dn
LE
PRE
V
V
M
M
MR, Dn
V
V
M
M
t
t
PHL
PLH
t
t
PHL
Qn
PLH
V
V
M
M
Qn
V
V
M
M
SA00254
SA00255
Waveform 1. Propagation Delay, Data to Output,
Master Reset to Output, Preset to Output
Waveform 2. Propagation Delay, Latch Enable
to Output
V
V
V
V
Dn
M
M
M
M
V
V
M
OE
Qn
M
t
t (H)
s
t (H)
h
t (L)
t (L)
h
s
t
PZH
PHZ
t
w
(H)
V
–0.3V
OH
V
V
M
V
LE
M
M
V
M
0V
SA00166
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00256
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 3. Data Setup and Hold Times and Latch Enable
Pulse Width
V
V
M
PRE, MR
M
V
V
M
OE
Qn
M
t
w
(L)
t
REC
t
t
PLZ
PZL
V
M
LE
V
M
V
V
+0.3V
OL
OL
Qn
Qn
SA00109
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
SA00257
Waveform 6. Master Reset and Preset Pulse Width,
Master Reset and Preset to Latch Enable Recovery Time
TEST CIRCUIT AND WAVEFORM
7
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
7 V
500 Ω
S1
From Output
Under Test
Open
GND
500 Ω
C
= 50 pF
L
Load Circuit
TEST
S1
t
open
7 V
pd
t
/t
PLZ PZL
t
/t
open
PHZ PZH
DEFINITIONS
C
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
L
SA00012
8
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
9
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
10
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
11
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
12
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
NOTES
13
1998 Jan 16
Philips Semiconductors
Product specification
9-bit bus interface latch with set and reset
(3-State)
74ABT843
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03475
Document order number:
Philips
Semiconductors
相关型号：
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