74ABT853PWDH [NXP]
8-bit transceiver with 9-bit parity checker/ generator and flag latch 3-State; 8位收发器和9位奇偶校验器/发电机和标志锁存三态
| 型号： | 74ABT853PWDH |
| 厂家： | 
NXP |
| 描述： | 8-bit transceiver with 9-bit parity checker/ generator and flag latch 3-State |
| 文件： | 总7页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
The 74ABT853 is an octal transceiver with a parity
generator/checker and is intended for bus–oriented applications.
FEATURES
• Low static and dynamic power dissipation with high speed and
high output drive
When Output Enable A (OEA) is High, it will place the A outputs in a
high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
• Open-collector ERROR output
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
The parity generator creates an odd parity output (PARITY) when
OEB is Low. When OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a latch. The error data
can then be passed, stored, cleared, or sampled depending on the
ENABLE and CLEAR control signals.
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power-up 3-State
• Live insertion/extraction permitted
If both OEA and OEB are Low, data will flow from the A bus to the B
bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
DESCRIPTION
The 74ABT853 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
3.4
UNIT
ns
T
amb
t
t
Propagation delay
An to Bn or Bn to An
PLH
PHL
C = 50pF; V = 5V
L
CC
t
t
Propagation delay
An to PARITY
PLH
PHL
C = 50pF; V = 5V
7.4
ns
L
CC
C
Input capacitance
I/O capacitance
V = 0V or V
CC
4
7
pF
pF
µA
IN
I
C
Outputs disabled; V = 0V or V
O CC
I/O
I
Total supply current
Outputs disabled; V =5.5V
50
CCZ
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
SOT222-1
24-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT853 N
74ABT853 D
74ABT853 DB
74ABT853 PW
74ABT853 N
74ABT853 D
24-Pin plastic SO
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT853 DB
74ABT853PW DH
SOT340-1
SOT355-1
PIN CONFIGURATION
LOGIC SYMBOL
OEA
A0
1
2
3
4
5
24
23
22
21
20
V
CC
B0
B1
B2
B3
A1
2
3
4
5
6
7
8
9
A2
A3
A0 A1 A2 A3 A4 A5 A6 A7
OEB
14
1
6
7
8
9
19 B4
18 B5
A4
A5
15
10
PARITY
OEA
11
13
CLEAR
ERROR
A6
A7
17
16
15
14
B6
ENABLE
B7
B0 B1 B2 B3 B4 B5 B6 B7
ERROR 10
CLEAR 11
GND 12
PARITY
OEB
23 22 21 20 19 18 17 16
13 ENABLE
TOP VIEW
SA00263
SA00262
1
1995 Sep 06
853-1672 15702
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
PIN DESCRIPTION
SYMBOL
A0 – A7
B0 – B7
OEA
PIN NUMBER
NAME AND FUNCTION
A port 3–State inputs/outputs
2, 3, 4, 5, 6, 7, 8, 9
23, 22, 21, 20, 19, 18, 17, 16
B port 3–State inputs/outputs
Enables the A outputs when Low
Enables the B outputs when Low
Parity output/input
1
OEB
14
15
10
11
13
12
24
PARITY
ERROR
CLEAR
ENABLE
GND
Error output (open collector)
Clears the error flag register when Low
Enable input (active-Low)
Ground (0V)
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
An
Bn + PARITY
Σ OF HIGHS
MODE
OEB
OEA
An
Bn
PARITY
Σ OF HIGHS
Odd
Even
L
H
A data to B bus and generate odd parity output
L
H
(output)
(input)
An
1
B data to A bus and check for parity error
H
H
L
(output)
X
X
X
Bn
Z
(input)
Z
(input)
Z
2
A bus and B bus disabled
H
Odd
Even
H
L
A data to B bus and generate inverted parity output
L
L
(output)
(input)
An
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When ENABLE is Low, ERROR is Low if the sum of A inputs is even or ERROR is High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
CLEAR
INTERNAL NODE
POINT ”P”
OUTPUT
Bn + PARITY
Σ OF HIGHS
PRE–STATE
ERRORn–1
ERROR
OUTPUT
MODE
ENABLE
Odd
Even
H
L
H
L
Pass
L
L
X
Odd
Even
X
H
L
X
H
X
L
H
L
L
Sample
L
H
Clear
Store
H
H
L
X
X
X
X
X
H
L
H
L
H
H
H
L
X
Z
=
=
=
=
High voltage level steady state
Low voltage level steady state
Don’t care
High impedance ”off” state
2
1995 Sep 06
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
LOGIC DIAGRAM
8
8
A0 – A7
B0 – B7
8
OEB
OEA
PARITY
8
8
MUX
B
9–bit
Odd
Parity
Tree
}
}
9
”P”
A
Sel A/B
ERROR
ENABLE
CLEAR
SA00264
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3
1995 Sep 06
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
4.5
0
MAX
5.5
V
DC supply voltage
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
Input transition rise or fall rate
0
5
T
amb
Operating free-air temperature range
–40
+85
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
= 4.5V; I = –18mA
–0.9
3.5
–1.2
–1.2
V
V
IK
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
CC
OH
I
IL
IH
High–level output voltage
All outputs except ERROR
V
OH
V
CC
= 5.0V; I = –3mA; V = V or V
4.0
V
OH
I
IL
IH
V
V
= 4.5V; I = –32mA; V = V or V
IH
2.6
V
V
CC
OH
I
IL
V
OL
Low-level output voltage
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
CC
OL
I
IL
I
Input leakage Control pins
V
CC
V
CC
V
CC
= 5.5V; V = GND or 5.5V
±0.01
±5
±1.0
±100
±100
±1.0
±100
±100
µA
µA
µA
I
I
current
Data pins
= 5.5V; V = GND or 5.5V
I
I
Power-off leakage current
= 0.0V; V or V ≤ 4.5V
±5.0
OFF
O
I
Power-up/down 3-State
output current
V
CC
V
OE
= 2.1V; V = 0.5V; V = GND or V
= Don’t care
;
O
I
CC
I
±5.0
±50
±50
µA
PU/PD
3
I
+ I
+ I
3-State output High current
3-State output Low current
Output high leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
IH
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
IL
OZL
IH
I
= 5.5V; V = 5.5V; V = GND or V
O I
CEX
CC
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–100
0.5
–180
250
38
–50
–180
250
38
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
25
CCL
I
CC
= 5.5V; Outputs 3-State;
I
0.5
0.5
50
1.5
50
50
1.5
50
µA
mA
µA
CCZ
V = GND or V
I
CC
Outputs enabled, one input at 3.4V,
other inputs at V or GND; V = 5.5V
CC
CC
Additional supply current per Outputs 3-State, one data input at 3.4V,
∆I
CC
0.01
0.5
2
input pin
other inputs at V or GND; V = 5.5V
CC CC
Outputs 3-State, one enable input at 3.4V,
other inputs at V or GND; V = 5.5V
1.5
1.5
mA
CC
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This parameter is valid for any V between 0V and 2.1V, with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted. The ERROR output pin 10 is not included in this spec due to the open collector design.
4
1995 Sep 06
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
o
o
T
V
= +25 C
T
V
= –40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORMS
UNIT
= +5.0V
= +5.0V ±10%
Min
Typ
Min
Max
t
t
Propagation delay
An to Bn or Bn to An
1.2
1.0
3.4
2.6
4.8
4.0
1.2
1.0
5.3
4.5
PLH
PHL
4
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
An to PARITY
2.1
2.5
7.4
7.4
9.5
9.7
2.1
2.5
11.2
11.0
PLH
PHL
1, 4
1, 4
3
t
t
Propagation delay
OEA to PARITY
1.8
2.3
6.6
6.7
8.5
8.6
1.8
2.3
10.5
10.0
PLH
PHL
Propagation delay
CLEAR to ERROR
t
1.0
3.6
5.5
1.0
6.2
PLH
t
t
Propagation delay
ENABLE to ERROR
1.8
1.8
3.8
4.5
5.1
5.8
1.8
1.8
6.0
6.6
PLH
PHL
4
t
t
Propagation delay
Bn or PARITY to ERROR
2.0
3.0
7.9
9.0
10.1
11.5
2.0
3.0
11.7
12.8
PLH
PHL
1, 4
2, 5
2, 5
t
Output enable time
OEA to An or OEB to Bn, PARITY
1.0
2.1
3.2
4.1
5.1
5.8
1.0
2.1
6.2
6.7
PZH
t
PZL
t
Output disable time
OEA to An or OEB to Bn, PARITY
3.1
3.2
5.1
5.6
7.3
7.2
3.1
3.2
7.9
8.1
PHZ
t
PLZ
AC SETUP REQUIREMENTS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
= +5.0V
T
V
= –40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORMS
UNIT
= +5.0V ±10%
MIN
TYP
MIN
t (H)
t (L)
s
Setup time, High or Low
Bn or PARITY to ENABLE
8.5
8.5
6.5
3.6
8.5
8.5
s
6
6
6
6
3
6
ns
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
Bn or PARITY to ENABLE
0.0
0.0
–3.4
–6.3
0.0
0.0
h
t (L)
h
Setup time, High
CLEAR to ENABLE
t (H)
s
2.0
3.0
3.5
4.0
–1.6
1.8
1.0
2.5
2.0
3.0
3.5
4.0
Hold time, Low
CLEAR to ENABLE
t (L)
h
Pulse width, Low
CLEAR
t (L)
w
Pulse width, Low
ENABLE
t (L)
w
5
1995 Sep 06
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
INPUT
INPUT
V
V
M
M
V
V
M
t
M
t
t
PHL
PLH
t
PLH
PHL
V
V
OUTPUT
M
M
V
M
V
OUTPUT
SA00216
M
Waveform 1. Propagation Delay For Inverting Output
SA00023
Waveform 4. Propagation Delay For Non-Inverting Output
V
OEA, OEB
OUTPUT
V
M
M
t
t
V
PHZ
PZH
OEA, OEB
OUTPUT
M
V
M
V
–0.3V
OH
t
t
PLZ
V
PZL
M
0V
V
M
SA00238
V
+0.3V
0V
OL
Waveform 2. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
SA00239
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
CLEAR
ERROR
V
V
M
M
CLEAR,
Bn, PARITY
t
(L)
w
V
V
V
V
M
M
M
M
V
M
t (H)
t (L)
s
t
(H)
t (L)
h
s
h
t
(L)
w
t
PLH
ENABLE
SA00265
V
V
M
V
M
M
Waveform 3. CLEAR Pulse Width and CLEAR to ERROR Delay
NOTE: The shaded areas indicate when the input is permitted to
change for predictable output performance.
SA00266
Waveform 6. Data Setup and Hold Times and ENABLE Pulse
Width
6
1995 Sep 06
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS
18
16
14
12
t
PLH
10
8
6
4
t
PHL
2
0
0
100
200
300
400
500
600
Load resistor (Ω)
NOTE:
When using Open-Collector parts, the value of the pull–up resistor greatly affects the value of the t
. For example, changing the specified pull-up resistor value from
PLH
500Ω to 100Ω will improve the t
over 300% with only a slight change in the t . However, if the value of the pull-up resistor is changed, the user must make certain
PHL
PLH
that the total I current through the resistor and the total I ’s of the receivers does not exceed the I maximum specification.
OL
IL
OL
SA00241
TEST CIRCUIT AND WAVEFORM
V
t
W
CC
AMP (V)
90%
90%
V
X
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
V
V
OUT
IN
R
R
X
L
0V
(t
PULSE
D.U.T
t
t
(t
(t
)
t
TLH
)
THL
F
R
GENERATOR
)
t
(t )
R
T
C
TLH
R
THL F
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
LOAD VALUES
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
OUTPUT
ERROR 100Ω
All other 500Ω 7.0V
R
V
X
X
Input Pulse Definition
t
t
PLZ
PZL
V
CC
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
74ABT
500ns 2.5ns 2.5ns
see AC CHARACTERISTICS for value.
R = Termination resistance should be equal to Z
of
T
OUT
pulse generators.
SA00242
7
1995 Sep 06
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