74ABT899D,112 [NXP]
74ABT899 - 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) SOP 28-Pin;
| 型号： | 74ABT899D,112 |
| 厂家： | 
NXP |
| 描述： | 74ABT899 - 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) SOP 28-Pin 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT899
9-bit dual latch transceiver with 8-bit
parity generator/checker (3-State)
Product specification
Supersedes data of 1993 Oct 04
IC23 Data Handbook
1998 Jan 16
Philips
Semiconductors
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
FEATURES
DESCRIPTION
The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate
transparent latches for the A bus and B bus. Either bus can
generate or check parity. The parity bit can be fed-through with no
change or the generated parity can be substituted with the SEL
input.
• Symmetrical (A and B bus functions are identical)
• Selectable generate parity or ”feed-through” parity for A-to-B and
B-to-A directions
• Independent transparent latches for A-to-B and B-to-A directions
• Selectable ODD/EVEN parity
Parity error checking of the A and B bus latches is continuously
provided with ERRA and ERRB, even with both buses in 3-State.
• Continuously checks parity of both A bus and B bus latches as
The 74ABT899 features independent latch enables for the A and B
bus latches, a select pin for ODD/EVEN parity, and separate error
signal output pins for checking parity.
ERRA and ERRB
• Ability to simultaneously generate and check parity
• Can simultaneously read/latch A and B bus data
• Output capability: +64 mA/–32mA
FUNCTIONAL DESCRIPTION
The 74ABT899 has three principal modes of operation which are
outlined below. All modes apply to both the A-to-B and B-to-A
directions.
• Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Transparent latch, Generate parity, Check A and B bus parity:
Bus A (B) communicates to Bus B (A), parity is generated and
passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are
High and the Mode Select (SEL) is Low, the parity generated from
A0-A7 and B0-B7 can be checked and monitored by ERRA and
ERRB. (Fault detection on both input and output buses.)
• Power up 3-State
• Power-up reset
• Live insertion/extraction permitted
Transparent latch, Feed-through parity, Check A and B bus
parity:
Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL
is High. Parity is still generated and checked as ERRA and ERRB
and can be used as an interrupt to signal a data/parity bit error to the
CPU.
Latched input, Generate/Feed-through parity, Check A (and B)
bus parity:
Independent latch enables (LEA and LEB) allow other permutations of:
• Transparent latch / 1 bus latched / both buses latched
• Feed-through parity / generate parity
• Check in bus parity / check out bus parity / check in and out bus
parity
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
2.9
UNIT
ns
T
amb
t
t
Propagation delay
An to Bn or Bn to An
PLH
PHL
C = 50pF; V = 5V
L
CC
t
t
Propagation delay
An to ERRA
PLH
PHL
C = 50pF; V = 5V
6.1
ns
L
CC
C
Input capacitance
Output capacitance
Total supply current
V = 0V or V
CC
4
7
pF
pF
µA
IN
I
C
Outputs disabled; V = 0V or V
O CC
I/O
I
Outputs disabled; V =5.5V
50
CCZ
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT899 A
DWG NUMBER
SOT261-3
28-Pin Plastic PLCC
28-Pin Plastic SOP
28-Pin Plastic SSOP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT899 A
74ABT899 D
74ABT899 DB
74ABT899 D
SOT136-1
74ABT899 DB
SOT341-1
2
1998 Jan 16
853-1623 18864
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
PIN CONFIGURATION
PLCC PIN CONFIGURATION
28
ODD/EVEN
1
2
3
4
5
6
7
8
9
V
CC
27 OEB
B0
ERRA
LEA
A0
B1 B2 B3 B4 B5 B6 B7
25 24 23 22 21 20 19
26
25 B1
24 B2
23 B3
22 B4
21 B5
20 B6
19 B7
18 BPAR
B0
26
18 BPAR
A1
OEB 27
17
16
15
LEB
A2
28
1
V
SEL
CC
A3
ODD/
EVEN
TOP VIEW
ERRB
A4
14 GND
ERRA
LEA
A0
2
A5
13
12
3
OEA
A6 10
A7 11
4
APAR
APAR 12
OEA 13
GND 14
17
16
15
LEB
5
6
7
8
9
10 11
SEL
A1 A2 A3 A4 A5 A6 A7
ERRB
SA00291
SA00289
PIN DESCRIPTION
LOGIC SYMBOL
PIN
SYMBOL
NAME AND FUNCTION
NUMBER
4, 5, 6, 7,
8, 9, 10,
11
A0 - A7
B0 - B7
Latched A bus 3-State inputs/outputs
4
5
6
7
8
9
10 11 12
19, 20,
21, 22,
23, 24,
25, 26
A0 A1 A2 A3 A4 A5 A6 A7 APAR
LEA
3
Latched B bus 3-State inputs/outputs
17
LEB
16
1
SEL
ERRA
2
APAR
BPAR
12
18
A bus parity 3-State input
B bus parity 3-State input
ODD/EVEN
ERRB
15
27
13
OEB
ODD/
EVEN
Parity select input (Low for EVEN
parity)
1
OEA
B0 B1 B2 B3 B4 B5 B6 B7 BPAR
Output enable inputs (gate A to B,
B to A)
OEA, OEB
13, 27
26 25 24 23 22 21 20 19 18
SEL
16
Mode select input (Low for generate)
Latch enable inputs (transparent High)
LEA, LEB
3, 17
SA00290
ERRA,
ERRB
2, 15
Error signal outputs (active-Low)
GND
14
28
Ground (0V)
V
CC
Positive supply voltage
3
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
27
OEB
OE
9–bit
Transparent
Latch
9–bit
Output
Buffer
3
LEA
LE
4
5
1
mux
26
B0
A0
A1
Parity
Generator
25
B1
0
6
24
B2
A2
7
23
A3
B3
8
A4
22
B4
9
21
A5
B5
10
11
12
20
B6
19
A6
A7
B7
18
APAR
BPAR
9–bit
Transparent
Latch
9–bit
Output
Buffer
13
16
17
OEA
SEL
LEB
OE
LE
1
mux
Parity
Generator
2
ERRA
0
15
ERRB
1
ODD/
EVEN
SA00292
FUNCTION TABLE
INPUTS
OPERATING MODE
OEB OEA SEL LEA LEB
H
H
H
H
H
H
L
H
L
X
L
X
L
X
H
H
L
3-State A bus and B bus (input A & B simultaneously)
B → A, transparent B latch, generate parity from B0 - B7, check B bus parity
L
L
H
X
X
H
H
H
L
B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
B → A, transparent B latch, parity feed-through, check B bus parity
L
L
L
H
H
L
H
H
X
H
X
L
L
B → A, transparent A & B latch, parity feed-through, check A & B bus parity
A → B, transparent A latch, generate parity from A0 - A7, check A bus parity
A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
A → B, transparent A latch, parity feed-through, check A bus parity
H
H
H
H
H
L
L
L
L
L
L
H
H
X
H
H
X
L
H
X
A → B, transparent A & B latch, parity feed-through, check A & B bus parity
Output to A bus and B bus (NOT ALLOWED)
L
H
L
X
=
=
=
High voltage level
Low voltage level
Don’t care
4
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
PARITY AND ERROR FUNCTION TABLE
INPUTS
OUTPUTS
xPAR
(A or B)
Σ of High
Inputs
xPAR
(B or A)
SEL
ODD/EVEN
ERRt
ERRr*
PARITY MODES
Even
Odd
H
H
H
L
H
L
H
H
H
H
L
H
H
L
H
L
Odd
Even
Odd
L
L
L
H
L
H
Mode
Feed-through/check parity
Even
Odd
H
H
L
H
L
H
H
L
Even
Mode
Even
Odd
L
L
H
L
H
L
L
Even
Odd
H
L
H
L
H
H
H
H
L
H
L
Odd
Even
Odd
H
L
L
H
H
H
Mode
L
Generate parity
Even
Odd
L
H
L
H
H
H
L
H
L
Even
Mode
Even
Odd
L
H
H
L
H
H
L
L
H
L
t
=
=
=
=
High voltage level
Low voltage level
Transmit–if the data path is from A→B then ERRt is ERRA
Receive–if the data path is from A→B then ERRr is ERRB
r
*
Blocked if latch is not transparent
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
5.5
V
DC supply voltage
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
5
T
amb
Operating free-air temperature range
–40
+85
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.9
3.5
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
4.0
OH
I
IL
= 4.5V; I = –32mA; V = V or V
IH
2.6
OH
I
IL
V
OL
Low-level output voltage
Power-up output low
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
0.55
0.55
OL
I
IL
V
RST
V
CC
= 5.5V; I = 1mA; V = GND or V
CC
0.13
V
O
I
3
voltage
I
I
Input leakage Control pins
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5
±1.0
±1.0
µA
µA
CC
I
current
Data pins
= 5.5V; V = GND or 5.5V
±100
±100
CC
I
I
Power-off leakage current
Power-up/down 3-State
V
= 0.0V; V or V 4.5V
±5.0
±5.0
±100
±50
±100
±50
µA
µA
≤
I
OFF
CC
O
V
CC
V
OE
= 2.1V; V = 0.5V; V = GND or V
;
CC
O
I
I
/I
PU PD
4
output current
= Don’t care
I
+ I
+ I
3-State output High current
3-State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
–80
50
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
IH
OZH
OZL
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
IL
I
= 5.5V; V = 5.5V; V = GND or V
O I CC
CEX
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–180
250
34
–50
–180
250
34
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
28
CCL
I
CC
= 5.5V; Outputs 3-State;
I
50
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
CC
0.3
mA
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V, with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
6
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
o
o
T
V
= +25 C
T
V
= –40 to +85 C
amb
CC
L
L
amb
CC
= +5.0V
C = 50pF
R = 500Ω
= +5.0V ±10%
SYMBOL
PARAMETER
WAVEFORM
UNIT
C = 50pF
L
R = 500Ω
L
Min
Typ
Min
Max
t
t
Propagation delay
An to Bn or Bn to An
1.0
1.0
3.2
2.7
4.5
4.1
1.0
1.0
4.9
4.6
PLH
PHL
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
An to BPAR or Bn to APAR
3.0
2.5
6.0
6.4
7.5
7.9
3.0
2.5
9.0
8.8
PLH
PHL
2
t
t
Propagation delay
An to ERRA or Bn to ERRB
2.8
2.8
6.0
6.7
8.0
8.5
2.8
2.8
9.1
9.3
PLH
PHL
3
t
t
Propagation delay
APAR to BPAR or BPAR to APAR
2.0
1.3
4.0
3.2
5.2
4.4
2.0
1.3
5.7
5.0
PLH
PHL
1
t
t
Propagation delay
APAR to ERRA or BPAR to ERRB
1.5
1.5
4.2
4.0
5.4
5.4
1.5
1.5
6.0
6.1
PLH
PHL
6
t
t
Propagation delay
ODD/EVEN to APAR or BPAR
2.6
2.5
5.5
5.3
6.8
6.7
2.6
2.5
8.1
7.8
PLH
PHL
5
t
t
Propagation delay
ODD/EVEN to ERRA or ERRB
2.3
2.6
5.4
5.7
6.8
7.2
2.3
2.6
7.9
8.4
PLH
PHL
4
t
t
Propagation delay
SEL to APAR or BPAR
1.3
1.4
4.1
4.1
5.2
5.3
1.3
1.4
6.0
5.9
PLH
PHL
8
t
t
Propagation delay
SEL to ERRA or ERRB
3.7
5.1
6.8
8.3
8.3
9.7
3.7
5.1
9.8
11.0
PLH
PHL
8
t
t
Propagation delay
LEA to Bn or LEB to An
1.0
1.0
3.2
3.1
4.4
4.5
1.0
1.0
4.9
5.0
PLH
PHL
9
9
t
t
Propagation delay
LEA to BPAR or LEB to APAR
2.0
1.7
6.8
6.3
8.3
7.9
2.0
1.7
9.7
9.0
PLH
PHL
t
t
Propagation delay
LEA to ERRA or LEB to ERRB
2.0
2.0
6.3
7.1
8.3
9.2
2.0
2.0
9.6
10.3
PLH
PHL
7
t
Output enable time
OEA to An, APAR or OEB to Bn, BPAR
1.0
1.0
3.0
3.4
4.3
4.8
1.0
1.0
5.1
5.4
PZH
11, 12
11, 12
t
PZL
t
Output disable time
OEA to An, APAR or OEB to Bn, BPAR
1.0
0.5
3.4
3.0
4.7
4.2
1.0
0.5
5.5
4.7
PHZ
t
PLZ
AC SETUP REQUIREMENTS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
o
o
T
V
= +25 C
= +5.0V
T
V
= –40 to +85 C
amb
CC
L
L
amb
CC
= +5.0V ±10%
SYMBOL
PARAMETER
WAVEFORM
UNIT
C = 50pF
R = 500Ω
C = 50pF
L
R = 500Ω
L
Min
Typ
Min
Max
t (H)
t (L)
s
Setup time, High or Low
An, APAR to LEA or Bn, BPAR to LEB
2.0
1.5
0.4
0.0
2.0
1.5
s
10
10
10
ns
ns
ns
t (H)
Hold time, High or Low
An, APAR to LEA or Bn, BPAR to LEB
1.5
1.0
0.0
–0.2
1.5
1.0
h
t (L)
h
Pulse width, High
LEA or LEB
t (H)
w
3.0
1.9
3.0
7
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
1
SEL
An, APAR
(Bn, BPAR)
INPUT
V
V
M
M
t
t
PLH
PHL
Bn, BPAR
(An, APAR)
OUTPUT
SA00293
V
V
M
M
Waveform 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR
SEL
0
ODD/EVEN
0
1
LEA
(LEB)
An
(Bn)
ODD PARITY
INPUT
EVEN PARITY
ODD PARITY
V
V
M
M
t
t
PLH
PHL
BPAR
(APAR)
OUTPUT
SA00294
V
V
M
M
NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1
Waveform 2. Propagation Delay, An to BPAR or Bn to APAR
ODD/EVEN
0
APAR
(BPAR)
0
1
LEA
(LEB)
An
(Bn)
ODD PARITY
INPUT
EVEN PARITY
ODD PARITY
V
V
M
M
t
t
PHL
PLH
ERRA
(ERRB)
OUTPUT
SA00295
V
V
M
M
NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1
Waveform 3. Propagation Delay, An to ERRA or Bn to ERRB
8
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
1
APAR
(BPAR)
An
(Bn)
INPUT
EVEN PARITY
INPUT
ODD/EVEN
V
V
M
M
t
t
PLH
PHL
ERRA
(ERRB)
OUTPUT
V
V
M
M
NOTE: Only even parity mode is shown, odd parity mode would cause inverted output
SA00296
Waveform 4. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB
SEL
0
APAR
(BPAR)
0
An
(Bn)
EVEN PARITY
INPUT
INPUT
ODD/EVEN
V
V
M
M
V
t
t
PLH
PHL
BPAR
(APAR)
OUTPUT
SA00297
V
M
M
NOTE: Only even parity mode is shown, odd parity mode would cause inverted output
Waveform 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR
9
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
ODD/EVEN
0
An
(Bn)
EVEN PARITY
INPUT
APAR
(BPAR)
INPUT
V
V
M
M
V
t
t
PLH
PHL
ERRA
(ERRB)
OUTPUT
V
M
M
NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output
and odd parity mode would be with ODD/EVEN = 1
SA00298
Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB
1
ODD/EVEN
APAR
(BPAR)
0
An
(Bn)
EVEN PARITY
INPUT
INPUT
ODD PARITY
EVEN PARITY
LEA
(LEB)
V
V
M
M
t
t
PLH
PHL
ERRA
(ERRB)
OUTPUT
SA00299
V
V
M
M
NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o
Waveform 7. Propagation Delay, LEA to ERRA or LEB to ERRB
10
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
1
ODD/EVEN
APAR
(BPAR)
0
An
(Bn)
EVEN PARITY
INPUT
SEL
INPUT
V
V
M
M
V
t
t
PLH
PHL
BPAR
(APAR)
OUTPUT
V
M
M
NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output
and odd parity mode would be with ODD/EVEN = 1
SA00300
Waveform 8. Propagation Delay, SEL to BPAR or SEL to APAR
1
SEL
APAR, An]
(BPAR, Bn)
INPUT
LEA
(LEB)
INPUT
V
V
M
M
t
t
PHL
PLH
Bn, BPAR
(An, APAR)
OUTPUT
V
V
M
M
SA00301
Waveform 9. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An
APAR, BPAR,
An, Bn
V
V
V
V
M
M
M
M
t
(H)
t (L)
s
t
(H)
V
t (L)
h
s
h
LEA, LEB
V
V
M
M
M
t
(H)
w
The shaded areas indicate when the input is permitted to change for predictable output performance.
SA00302
Waveform 10. Data Setup and Hold Times, Pulse Width High
11
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
OEA,
OEB
V
V
M
M
t
t
PHZ
PZH
V
–0.3V
OH
An, APAR,
Bn, BPAR
V
M
0V
SA00303
Waveform 11. 3-State Output Enable Time to High Level and Output Disable Time from High Level
OEA,
OEB
V
V
M
M
t
t
PZL
PLZ
An, APAR,
Bn, BPAR
V
M
V
+0.3V
OL
SA00304
Waveform 12. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
7 V
500 Ω
S1
From Output
Under Test
Open
GND
500 Ω
C
= 50 pF
L
Load Circuit
TEST
S1
t
open
7 V
pd
t
/t
PLZ PZL
t
/t
open
PHZ PZH
DEFINITIONS
C
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
L
SA00012
12
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
SOT261-3
13
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
SO28: plastic small outline package; 28 leads; body width 7.5mm
SOT136-1
14
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm
SOT341-1
15
1998 Jan 16
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03478
Document order number:
Philips
Semiconductors
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