74ABTH16500CDGG [NXP]
18-bit universal bus transceiver 3-State; 18位通用总线收发器三态
| 型号： | 74ABTH16500CDGG |
| 厂家： | 
NXP |
| 描述： | 18-bit universal bus transceiver 3-State |
| 文件： | 总12页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
Product specification
1998 Feb 27
Supersedes data of 1997 Jun 12
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
FEATURES
DESCRIPTION
• 18-bit bidirectional bus interface
• 3-State buffers
• 74ABTH16500C incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
The 74ABT16500C is a high-performance BiCMOS Device which
combines low static and dynamic power dissipation with high speed
and high output drive.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CPAB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
• Negative edge-triggered clock inputs
• Latch-up protection exceeds 500mA per JEDEC Std 17
high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA. The output enables are complimentary (OEAB is
active High, and OEBA is active Low).
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
• Flexible operation permits 18 embedded D-type latches or
flip-flops to operate in clocked, transparent, or latched modes.
Two options are available, 74ABT16500C which does not have the
bus-hold feature and 74ABTH16500C which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
An to Bn or Bn to An
C = 50pF;
2.1
1.7
PLH
PHL
L
ns
V
CC
= 5V
C
Input capacitance (Control pins)
I/O pin capacitance
V = 0V or V
CC
3
7
pF
pF
IN
I
C
Outputs disabled; V = 0V or V
I/O CC
I/O
I
Outputs disabled; V = 5.5V
500
8
µA
mA
CCZ
CC
Quiescent supply current
I
Outputs low; V = 5.5V
CCL
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT16500C DL
74ABT16500C DGG
74ABTH16500C DL
74ABTH16500C DGG
BT16500C DL
BT16500C DGG
BH16500C DL
BH16500C DGG
SOT364-1
SOT371-1
SOT364-1
2
1998 Feb 27
853-1800 19027
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
LOGIC SYMBOL
3
5
6
8
9
10 12 13 14 15 16 17 19 20 21 23 24 26
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
OEAB
LEAB
CPAB
OEBA
LEBA
CPBA
1
2
55
27
28
30
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
54 52 51 49 48
47 45 44 43 42 41 40 38 37 36 34 33 31
SA00322
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
OEAB
LEAB
A0
1
2
56
GND
1
EN1
55
54
53
52
CPAB
B0
55
2C3
3
2
C3
GND
A1
4
GND
B1
G2
5
27
EN4
A2
6
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
B2
30
5C6
7
V
V
CC
CC
28
C6
A3
8
B3
G5
A4
9
B4
A5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
B5
3
54
3D
4
1
1
1
GND
A6
GND
B6
6D
5
6
52
51
49
A7
B7
A8
B8
8
9
A9
B9
48
47
A10
A11
GND
A12
A13
A14
B10
B11
GND
B12
B13
B14
10
12
13
14
45
44
43
15
42
16
17
41
40
V
V
CC
CC
19
20
38
37
A15
A16
B15
B16
21
23
24
26
36
34
33
31
GND 25
A17 26
OEBA 27
LEBA 28
GND
B17
CPBA
GND
SW00035
SH00087
3
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
PIN DESCRIPTION
PIN NUMBER
SYMBOL
OEAB
NAME AND FUNCTION
A-to-B Output enable input
1
27
OEBA
B-to-A Output enable input (active low)
A-to-B/B-to-A Latch enable input
2, 28
55,30
LEAB/LEBA
CPAB/CPBA
A-to-B/B-to-A Clock input (active falling edge)
3, 5, 6, 8, 9, 10, 12, 13, 14, 15,
16, 17, 19, 20, 21, 23, 24, 26
A0-A17
Data inputs/outputs (A side)
Data inputs/outputs (B side)
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
B0-B17
GND
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Ground (0V)
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
Internal
OPERATING MODE
Registers
OEAB
LEAB
CPAB
An
X
h
I
Bn
Z
L
L
H
↓
X
X
H
L
Disabled
X
Z
Disabled, Latch data
Disabled, Hold data
Disabled, Clock data
L
↓
X
Z
L
L
L
L
H
H
↓
H or L
X
h
I
NC
H
L
Z
L
↓
Z
L
↓
Z
H
H
H
H
H
H
H
H
X
H
L
h
I
H
L
H
L
Transparent
X
X
H
L
H
L
Latch data & display
Clock data & display
Hold data & display
↓
X
↓
L
L
L
L
h
I
H
L
H
L
↓
H or L
H or L
X
X
H
L
H
L
NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level
h
L
I
= High voltage level one set-up time prior to the Enable or Clock transition
= Low voltage level
= Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X
Z
↓
= Don’t care
= High Impedance “off” state
= High-to-Low Enable or Clock transition
4
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
LOGIC DIAGRAM
1
OEAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
27
OEBA
3
54
B1
A1
ID
C1
CLK
ID
C1
CLK
To 17 other channels
SW00234
5
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC supply voltage
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or High state
Output in Low state
–0.5 to +5.5
128
I
DC output current
mA
OUT
Output in High state
–64
T
stg
Storage temperature range
–65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
LIMITS
SYMBOL
UNIT
MIN
4.5
0
MAX
V
CC
DC supply voltage
Input voltage
5.5
V
V
V
I
V
CC
V
High-level input voltage
Input voltage
2.0
V
IH
V
0.8
–32
64
V
IL
I
High-level output current
Low-level output current
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
10
T
amb
–40
+85
6
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
= +25°C
T
= –40°C
to +85°C
amb
T
amb
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
V
Input clamp voltage
V
V
V
V
V
V
V
= 4.5V; I = –18mA
–0.8
2.9
–1.2
–1.2
V
V
V
V
V
V
IK
CC
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
4.0
OH
I
IL
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
Low-level output voltage
= 4.5V; I = 64mA; V = V or V
IH
0.35
0.13
0.55
0.55
0.55
0.55
OL
I
IL
3
V
RST
Power-up output voltage
= 5.5V; I = 1mA; V = GND or V
O I CC
= 5.5V; V = GND or
CC
I
I
Input leakage current
Control pins
"0.01 "1.0
"1.0
µA
I
5.5V
V
CC
= 4.5V; V = 0.8V
35
35
I
Bus Hold current A and B
Ports 74ABTH16500C
I
µA
V
V
V
= 4.5V; V = 2.0V
–75
–75
HOLD
6
CC
CC
CC
I
= 5.5V; V = 0 to 5.5V
±800
I
I
Power-off leakage current
Power-up/down 3-State
= 0.0V; V or V ≤ 4.5V
"2
"2
"100
"50
"100
"50
µA
µA
OFF
O
I
V
CC
V
OE
= 2.1V; V = 0.0V or V
;
CC
O
I
PU/PD
4
output current
= Don’t care
I
+ I
+ I
3-State output High current
3-State output Low current
Output High leakage current
V
CC
V
CC
V
CC
V
CC
= 5.5V; V = 5.5V; V = V or V
1.0
–1.0
2
10
–10
50
10
–10
50
µA
µA
µA
mA
IH
OZH
OZL
O
I
IL
IH
IH
I
= 5.5V; V = 0.0V; V = V or V
O I IL
IL
I
= 5.5V; V = 5.5V; V = GND or V
O I CC
CEX
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–80
–180
–50
–180
O
V
V
= 5.5V; Outputs High, V = GND or
I
CC
CC
I
I
0.5
8
2
19
2
2
19
2
mA
mA
mA
CCH
I
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V = GND or V
CCL
CCZ
I
CC
V
CC
= 5.5V; Outputs 3–State;
0.5
V = GND or V
I
CC
Additional supply current
per input pin
74ABT16500C
V
= 5.5V; one input at 3.4V,
2
CC
∆I
∆I
5.0
50
50
µA
µA
CC
other inputs at V or GND
CC
Additional supply current
per input pin
74ABTH16500C
V
= 5.5V; one input at 3.4V,
2
CC
200
500
500
CC
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V, with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10% a
CC
CC
CC
transition time of up to 100µsec is permitted.
5. Unused pins at V or GND.
CC
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
7
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
MAX
o
o
T
V
= +25 C
T
V
= –40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
MIN
TYP
MIN
MAX
f
Maximum clock frequency
1
2
150
225
150
MHz
ns
max
t
t
Propagation delay
An to Bn or Bn to An
1.0
1.0
2.1
1.7
3.0
2.5
1.0
1.0
3.4
3.0
PLH
PHL
t
t
Propagation delay
LEAB to Bn or LEBA to An
1.0
1.0
3.2
2.8
4.3
3.7
1.0
1.0
4.9
4.0
PLH
PHL
3
1
ns
ns
ns
ns
t
t
Propagation delay
CPAB to Bn or CPBA to An
1.0
1.0
3.4
2.6
4.5
3.5
1.0
1.0
5.3
4.6
PLH
PHL
t
Output enable time
to HIGH and LOW level
5
6
1.0
1.5
3.3
2.4
4.4
3.2
1.0
1.5
5.0
3.9
PZH
t
PZL
t
Output disable time
from HIGH and LOW level
5
6
1.5
1.4
3.3
2.5
4.3
3.3
1.5
1.4
5.3
3.9
PHZ
t
PLZ
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= –40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
MIN
TYP
MIN
t (H)
t (L)
s
Setup time, HIGH or LOW
An to CPAB or Bn to CPBA
2.0
2.0
0.7
0.6
2.0
2.0
s
4
4
4
4
1
3
ns
ns
ns
ns
ns
ns
t (H)
Hold time, HIGH or LOW
An to CPAB or Bn to CPBA
0.7
0.7
–0.5
–0.8
0.7
0.7
h
t (L)
h
t (H)
Setup time, HIGH or LOW
An to LEAB or Bn to LEBA
2.0
2.0
0.1
0.1
2.0
2.0
s
t (L)
s
t (H)
Hold time HIGH or LOW
An to LEAB or Bn to LEBA
0.7
0.7
–0.1
–0.1
0.7
0.7
h
t (L)
h
Pulse width, HIGH or LOW
CPAB or CPBA
t
w
3
3
1.2
1.2
3
3
Pulse width, HIGH
LEAB or LEBA
t (H)
w
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
1/f
MAX
An or Bn
V
V
M
M
V
V
M
M
CPBA or
CPAB
t
t
PLH
PHL
t
(L)
t (H)
W
W
V
V
t
OH
OL
PLH
t
PHL
V
V
M
M
An or Bn
An or Bn
V
M
V
M
SA00132
SA00324
Waveform 2. Propagation Delay, Transparent Mode
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
8
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
AC WAVEFORMS (Continued)
V
M
= 1.5V, V = GND to 3.0V
IN
OEBA
OEAB
V
V
V
V
V
M
M
M
LEAB or
LEBA
M
M
t
(H)
W
t
PLH
t
t
PHZ
PZH
t
PHL
V
OH
V
OH
An or Bn
V
–0.3V
OH
V
V
V
M
M
M
An or Bn
V
OL
SA00135
SA00133
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 3. Propagation Delay, Enable to Output, and Enable
Pulse Width
An
or
Bn
OEBA
OEAB
V
V
M
V
V
M
M
M
V
V
M
M
t (H)
S
t (H)
h
t (L)
h
t (L)
S
t
t
PLZ
PZL
An or Bn
CPAB or CPBA,
LEAB or LEBA
V
V
M
M
V
M
V
+0.3V
OL
V
OL
Note: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00136
SA00323
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
Waveform 4. Data Setup and Hold Times
TEST CIRCUIT AND WAVEFORMS
t
W
V
AMP (V)
CC
90%
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
R
L
L
0V
(t
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
TLH
)
THL
F
R
)
t
(t )
R
C
TLH
R
THL F
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
Input Pulse Definition
t
closed
PLZ
PZL
t
closed
open
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT/H16
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00018
9
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
10
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
11
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03493
Document order number:
Philips
Semiconductors
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