74AHC00D,112 [NXP]
74AHC(T)00 - Quad 2-input NAND gate SOIC 14-Pin;
| 型号： | 74AHC00D,112 |
| 厂家： | 
NXP |
| 描述： | 74AHC(T)00 - Quad 2-input NAND gate SOIC 14-Pin PC 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC00; 74AHCT00
Quad 2-input NAND gate
Rev. 04 — 28 April 2008
Product data sheet
1. General description
The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC
standard No. JESD7-A.
The 74AHC00; 74AHCT00 provides the quad 2-input NAND function.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Input levels:
N For 74AHC00: CMOS level
N For 74AHCT00: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC00
74AHC00D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
SOT402-1
SOT762-1
74AHC00PW
74AHC00BQ
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
Table 1.
Ordering information …continued
Type number
Package
Temperature range Name
Description
Version
74AHCT00
74AHCT00D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
SOT402-1
SOT762-1
74AHCT00PW
74AHCT00BQ
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
4. Functional diagram
1
3
&
&
&
1
2
1A
1B
2
1Y
2Y
3Y
3
6
8
4
5
4
5
2A
2B
6
9
9
3A
8
10 3B
10
A
B
12 4A
13 4B
12
13
4Y 11
Y
11
&
mna211
mna212
mna246
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
terminal 1
index area
2
3
4
5
6
13
12
11
10
9
1B
4B
4A
4Y
3B
3A
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
1Y
2A
2B
2Y
4B
4A
4Y
3B
3A
3Y
00
1Y
2A
00
(1)
GND
2B
2Y
8
GND
001aac939
001aac938
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
2 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
5.2 Pin description
Table 2.
Symbol
1A
Pin description
Pin
1
Description
data input
1B
2
data input
1Y
3
data output
data input
2A
4
2B
5
data input
2Y
6
data output
ground (0 V)
data output
data input
GND
3Y
7
8
3A
9
3B
10
11
12
13
14
data input
4Y
data output
data input
4A
4B
data input
VCC
supply voltage
6. Functional description
Table 3.
Function selection[1]
Input
nA
L
Output
nB
X
nY
H
X
L
H
H
H
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
3 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
−0.5
−20
−20
−25
-
Max
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
IO
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
ICC
IGND
Tstg
Ptot
supply current
ground current
−75
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
74AHC00
VCC
Operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
input voltage
2.0
5.0
5.5
V
VI
0
-
5.5
V
VO
output voltage
ambient temperature
0
-
VCC
+125
100
20
V
Tamb
−40
+25
°C
ns/V
ns/V
∆t/∆V
input transition rise and fall rate VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
74AHCT00
VCC
supply voltage
4.5
0
5.0
5.5
V
VI
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
20
V
Tamb
∆t/∆V
ambient temperature
−40
-
+25
-
°C
ns/V
input transition rise and fall rate VCC = 4.5 V to 5.5 V
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
4 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHC00
VIH
HIGH-level input VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
voltage
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level input VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
voltage
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
1.9 2.0
2.9 3.0
4.4 4.5
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
IO = −4.0 mA; VCC = 3.0 V 2.58
IO = −8.0 mA; VCC = 4.5 V 3.94
-
-
2.48
3.80
2.40
3.70
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 50 µA; VCC = 2.0 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
VI = 5.5 V or GND;
V
0.1
0.1
0.1
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage
current
-
µA
V
CC = 0 V to 5.5 V
VI = VCC or GND; IO = 0 A;
CC = 5.5 V
input capacitance VI = VCC or GND
ICC
CI
supply current
-
-
-
2.0
10
-
-
20
10
-
-
40
10
µA
V
3.0
pF
74AHCT00
VIH
HIGH-level input VCC = 4.5 V to 5.5 V
voltage
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level input VCC = 4.5 V to 5.5 V
voltage
0.8
0.8
0.8
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = −50 µA
4.4 4.5
-
-
4.4
-
-
4.4
-
-
V
V
IO = −8.0 mA
3.94
-
3.80
3.70
VOL
LOW-level output VI = VIH or VIL; VCC = 4.5 V
voltage
IO = 50 µA
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
IO = 8.0 mA
V
II
input leakage
current
VI = 5.5 V or GND;
CC = 0 V to 5.5 V
-
µA
V
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
5 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
ICC
supply current
VI = VCC or GND; IO = 0 A;
-
-
2.0
-
20
-
40
µA
VCC = 5.5 V
∆ICC
additional supply per input pin;
-
-
1.35
-
-
1.5
10
-
-
1.5
10
mA
current
VI = VCC − 2.1 V;
other pins at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
CI
input capacitance VI = VCC or GND
-
3.0
10
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max
74AHC00
[2]
tpd
propagation
delay
nA, nB to nY; see Figure 6
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
4.5
7.9
1.0
1.0
9.5
1.0
1.0
10.0
14.5
ns
ns
CL = 50 pF
6.0 11.4
13.0
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
3.2
4.5
7.0
5.5
7.5
-
1.0
1.0
-
6.5
8.5
-
1.0
1.0
-
7.0
9.5
-
ns
ns
pF
CL = 50 pF
[3]
[2]
CPD
power
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
dissipation
capacitance
74AHCT00
tpd
propagation
nA, nB to nY; see Figure 6
VCC = 4.5 V to 5.5 V
CL = 15 pF
delay
-
-
-
3.3
4.5
7.0
6.9
7.9
-
1.0
1.0
-
8.0
9.0
-
1.0
1.0
-
9.0
10.0
-
ns
ns
pF
CL = 50 pF
[3]
CPD
power
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
dissipation
capacitance
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
6 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
11. Waveforms
V
I
V
nA, nB input
GND
M
t
t
PLH
PHL
V
OH
V
nY output
M
V
OL
001aah088
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
Table 8.
Type
Measurement points
Input
VM
Output
VM
74AHC00
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
74AHCT00
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 7. Load circuitry for measuring switching times
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
7 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74AHC00
VCC
3.0 V
≤ 3.0 ns
≤ 3.0 ns
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74AHCT00
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
8 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 8. Package outline SOT108-1 (SO14)
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
9 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 9. Package outline SOT402-1 (TSSOP14)
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
10 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 10. Package outline SOT762-1 (DHVQFN14)
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
11 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charge Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20080428
Data sheet status
Change notice
Supersedes
74AHC_AHCT00_4
Modifications:
Product data sheet
-
74AHC_AHCT00_3
• Table 6: the conditions for input leakage current have been changed.
74AHC_AHCT00_3
74AHC_AHCT00_2
74AHC_AHCT00_1
20080108
19990923
19981209
Product data sheet
Product specification
Product specification
-
-
-
74AHC_AHCT00_2
74AHC_AHCT00_1
-
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
12 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT00_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2008
13 of 14
74AHC00; 74AHCT00
NXP Semiconductors
Quad 2-input NAND gate
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 April 2008
Document identifier: 74AHC_AHCT00_4
相关型号：
74AHC00D-Q100
AHC/VHC/H/U/V SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14
NXP
74AHC00D-T
IC AHC/VHC/H/U/V SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14, Gate
NXP
74AHC00PW-Q100
AHC/VHC/H/U/V SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14
NXP
74AHC00PW-T
IC AHC/VHC/H/U/V SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14, Gate
NXP
74AHC00PW/T3
IC AHC/VHC/H/U/V SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14, Gate
NXP
©2020 ICPDF网 联系我们和版权申明