74AHC14BQ,115 [NXP]
74AHC(T)14 - Hex inverting Schmitt trigger QFN 14-Pin;
| 型号： | 74AHC14BQ,115 |
| 厂家： | 
NXP |
| 描述： | 74AHC(T)14 - Hex inverting Schmitt trigger QFN 14-Pin 栅 逻辑集成电路 触发器 |
| 文件： | 总16页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC14; 74AHCT14
Hex inverting Schmitt trigger
Rev. 05 — 4 May 2009
Product data sheet
1. General description
The 74AHC14; 74AHCT14 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A.
The 74AHC14; 74AHCT14 provides six inverting buffers with Schmitt-trigger action. They
are capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Input levels:
N For 74AHC14: CMOS level
N For 74AHCT14: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC14
74AHC14D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
SOT402-1
74AHC14PW
74AHC14BQ
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals; body
2.5 × 3 × 0.85 mm
74AHCT14
74AHCT14D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
SOT402-1
74AHCT14PW
74AHCT14BQ
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals; body
2.5 × 3 × 0.85 mm
4. Functional diagram
1
3
2
4
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
2
1
3
5
6
4
6
5
9
8
8
9
11
13
10
12
10
12
11
13
A
Y
mna025
mna204
001aac497
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
(one Schmitt-trigger)
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
2 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
5. Pinning information
5.1 Pinning
terminal 1
index area
2
3
4
5
6
13
12
11
10
9
1Y
2A
2Y
3A
3Y
6A
6Y
5A
5Y
4A
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1Y
V
CC
6A
6Y
5A
5Y
4A
4Y
14
2A
(1)
GND
2Y
14
3A
3Y
001aac499
GND
8
Transparent top view
001aac498
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A
Pin description
Pin
1
Description
data input 1
data output 1
data input 2
data output 2
data input 3
data output 3
ground (0 V)
data output 4
data input 4
data output 5
data input 5
data output 6
data input 6
supply voltage
1Y
2
2A
3
2Y
4
3A
5
3Y
6
GND
4Y
7
8
4A
9
5Y
10
11
12
13
14
5A
6Y
6A
VCC
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
3 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
6. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nY
H
H
L
[1] H = HIGH voltage level;
L = LOW voltage level.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−20
−20
−25
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
IO
ICC
supply current
IGND
Tstg
Ptot
ground current
−75
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
74AHC14
VCC
Operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
input voltage
2.0
0
5.0
5.5
V
VI
-
5.5
V
VO
output voltage
ambient temperature
0
-
VCC
+125
V
Tamb
−40
+25
°C
74AHCT14
VCC
supply voltage
input voltage
4.5
0
5.0
5.5
V
VI
-
5.5
V
VO
output voltage
ambient temperature
0
-
VCC
+125
V
Tamb
−40
+25
°C
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
4 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHC14
VOH
HIGH-level
VI = VT+ or VT−
output voltage
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
IO = −4.0 mA; VCC = 3.0 V
IO = −8.0 mA; VCC = 4.5 V
VI = VT+ or VT−
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
4.4
2.58
3.94
2.48
3.80
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
0.1
0.1
0.1
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
µA
V
ICC
CI
CO
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
2.0
10
-
-
-
-
20
10
-
-
-
-
40
10
-
µA
pF
pF
V
input
capacitance
3
4
output
capacitance
74AHCT14
VOH HIGH-level
VI = VT+ or VT−
output voltage
IO = −50 µA; VCC = 4.5 V
IO = −8.0 mA; VCC = 4.5 V
VI = VT+ or VT−
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
3.94
3.80
3.70
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 4.5 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
µA
V
ICC
∆ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
2.0
-
-
20
-
-
40
µA
V
additional
per input pin;
1.35
1.5
1.5
mA
supply current VI = VCC − 2.1 V; other pins
at VCC or GND; IO = 0 A;
VCC = 4.5 V to 5.5 V
CI
input
capacitance
-
-
3
4
10
-
-
-
10
-
-
-
10
-
pF
pF
CO
output
capacitance
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
5 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions
74AHC14
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max Min
Max
Min
Max
[2]
tpd
propagation nA to nY; see Figure 6
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
4.3 12.8
5.8 16.3
1.0
1.0
15.0
18.0
1.0
1.0
16.0
20.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
3.2
8.6
1.0
1.0
-
10.0
12.0
-
1.0
1.0
-
11.0
13.5
-
ns
ns
pF
CL = 50 pF
4.2 10.6
[3]
[2]
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
10
-
74AHCT14
tpd
propagation nA to nY; see Figure 6
delay
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
-
-
-
4.0
5.4
12
7.0
8.0
-
1.0
1.0
-
8.0
9.0
-
1.0
1.0
-
9.0
10.0
-
ns
ns
pF
[3]
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
6 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
11. Waveforms
V
I
V
V
M
nA input
M
GND
t
t
PHL
PLH
V
OH
V
V
M
nY output
M
V
OL
mna344
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
Table 8.
Type
Measurement points
Input
VM
Output
VM
74AHC14
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
74AHCT14
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
Fig 7. Load circuitry for measuring switching times
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
7 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74AHC14
VCC
3.0 V
≤ 3.0 ns
≤ 3.0 ns
50 pF, 15 pF
50 pF, 15 pF
tPLH, tPHL
tPLH, tPHL
74AHCT14
12. Transfer characteristics
Table 10. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 8 and Figure 9.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHC14
VT+
VT−
VH
positive-going
threshold
voltage
V
CC = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
2.2
3.15
3.85
-
-
-
2.2
3.15
3.85
-
-
2.2
3.15
3.85
-
V
V
V
V
V
V
V
V
V
VCC = 4.5 V
VCC = 5.5 V
-
-
-
-
negative-going VCC = 3.0 V
threshold
voltage
0.9
1.35
1.65
0.3
0.4
0.5
0.9
1.35
1.65
0.3
0.4
0.5
0.9
1.35
1.65
0.25
0.35
0.45
VCC = 4.5 V
-
-
-
VCC = 5.5 V
-
-
-
hysteresis
voltage
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
1.2
1.4
1.6
1.2
1.4
1.6
1.2
1.4
1.6
74AHCT14
VT+
VT−
VH
positive-going
threshold
voltage
V
CC = 4.5 V
-
-
-
-
1.9
2.1
-
-
1.9
2.1
-
-
1.9
2.1
V
V
VCC = 5.5 V
negative-going VCC = 4.5 V
threshold
voltage
0.5
0.6
-
-
-
-
0.5
0.6
-
-
0.5
0.6
-
-
V
V
VCC = 5.5 V
hysteresis
voltage
VCC = 4.5 V
VCC = 5.5 V
0.4
0.4
-
-
1.4
1.5
0.4
0.4
1.4
1.5
0.35
0.35
1.4
1.5
V
V
13. Transfer characteristics waveforms
V
O
V
T+
V
I
V
H
V
T−
V
I
V
V
O
H
V
V
T+
T−
mna207
mna208
Fig 8. Transfer characteristics
Fig 9. Transfer characteristics definitions
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
8 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
mna411
mna412
1.5
5
I
CC
(mA)
I
CC
(mA)
4
1
3
2
1
0
0.5
0
0
1
2
3
0
1
2
3
4
5
V (V)
I
V (V)
I
a. VCC = 3.0 V
b. VCC = 4.5 V
mna413
6
I
CC
(mA)
4
2
0
0
2
4
6
V (V)
I
c. VCC = 5.5 V
Fig 10. Typical 74AHC transfer characteristics
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
9 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
mna414
mna415
8
6
I
I
CC
CC
(mA)
(mA)
6
4
4
2
0
2
0
0
1
2
3
4
5
0
2
4
6
V (V)
I
V (V)
I
a. VCC = 4.5 V
b. VCC = 5.5 V
Fig 11. Typical 74AHCT transfer characteristics
14. Application information
R
C
mna035
1
T
1
For 74AHC14: f =
For 74AHCT14: f =
≈
--- ------------------------
0.55 × RC
1
1
≈
--- ------------------------
T
0.60 × RC
Fig 12. Relaxation oscillator
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
10 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
15. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 13. Package outline SOT108-1 (SO14)
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
11 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 14. Package outline SOT402-1 (TSSOP14)
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
12 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 15. Package outline SOT762-1 (DHVQFN14)
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
13 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
16. Abbreviations
Table 11. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
17. Revision history
Table 12. Revision history
Document ID
Release date
20090504
Data sheet status
Change notice
Supersedes
74AHC_AHCT14_5
Modifications:
Product data sheet
-
74AHC_AHCT14_4
• Table 6: the conditions for HIGH-level output voltage and LOW-level output voltage have
been changed.
74AHC_AHCT14_4
74AHC_AHCT14_3
74AHC_AHCT14_2
74AHC_AHCT14_N_1
20080425
20030526
19990927
19990111
Product data sheet
-
-
-
-
74AHC_AHCT14_3
74AHC_AHCT14_2
74AHC_AHCT14_N_1
-
Product specification
Product specification
Preliminary specification
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
14 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT14_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 4 May 2009
15 of 16
74AHC14; 74AHCT14
NXP Semiconductors
Hex inverting Schmitt trigger
20. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Transfer characteristics. . . . . . . . . . . . . . . . . . . 8
Transfer characteristics waveforms. . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
16
17
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 May 2009
Document identifier: 74AHC_AHCT14_5
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AHC/VHC/H/U/V SERIES, HEX 1-INPUT INVERT GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14
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