74AHC157D [NXP]
Quad 2-input multiplexer; 四2输入多路复用器
| 型号： | 74AHC157D |
| 厂家： | 
NXP |
| 描述： | Quad 2-input multiplexer |
| 文件： | 总16页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AHC157; 74AHCT157
Quad 2-input multiplexer
Product specification
1999 Sep 24
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
FEATURES
DESCRIPTION
• ESD protection: HBM EIA/JESD22-A114-A
exceeds 2000 V MM EIA/JESD22-A115-A
exceeds 200 V CDM EIA/JESD22-C101
exceeds 1000 V
The 74AHC/AHCT157 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
• Balanced propagation delays
The 74AHC/AHCT157 are quad 2-input multiplexers which
select 4 bits of data from two sources under the control of
a common data select input (S). The enable input (E) is
active LOW. When E is HIGH, all of the outputs (1Y to 4Y)
are forced LOW regardless of all other input conditions.
• All inputs have Schmitt-trigger actions
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Inputs accept voltages higher than VCC
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 and +125 °C.
Moving the data from two groups of registers to four
common output buses is a common use of the ‘157’. The
state of the common data select input (S) determines the
particular register from which the data comes. It can also
be used as a function generator.
The device is useful for implementing highly irregular logic
by generating any four of the 16 different functions of two
variables with one variable common.
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
The ‘157’ is the logic implementation of a 4-pole, 2-position
switch, where the position of the switch is determine by the
logic levels applied to S.
E
S
nI0
nI1
nY
H
L
L
L
L
X
L
X
L
X
X
X
L
L
L
The logic equations are:
1Y = E × (1I1 × S + 1I0 × S);
2Y = E × (2I1 × S + 2I0 × S);
3Y = E × (3I1 × S + 3I0 × S);
4Y = E × (4I1 × S + 4I0 × S).
L
H
X
X
H
L
H
H
H
H
The ‘157’ is identical to the ‘158’ but has non-inverting
(true) outputs.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
ORDERING INFORMATION
OUTSIDE NORTH
PACKAGES
NORTH AMERICA
AMERICA
PINS
16
PACKAGE
SO
MATERIAL
plastic
CODE
74AHC157D
74AHC157D
SOT109-1
SOT403-1
SOT109-1
SOT403-1
74AHC157PW
74AHCT157D
74AHCT157PW
74AHC157PW DH
74AHCT157D
16
TSSOP
SO
plastic
16
plastic
74AHCT157PW DH
16
TSSOP
plastic
1999 Sep 24
2
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
AHC AHCT
SYMBOL
PARAMETER
CONDITIONS
UNIT
tPHL/tPLH propagation delay
nI0, nI1 to nY
CL = 15 pF; VCC = 5 V
3.2
4.5
3.7
3.0
4.0
3.4
5.1
4.0
3.0
4.0
ns
ns
ns
pF
pF
S to nY
CL = 15 pF; VCC = 5 V
CL = 15 pF; VCC = 5 V
VI = VCC or GND
E to nY
CI
input capacitance
output capacitance
CO
CPD
power dissipation
capacitance
CL = 50 pF; f = 1 MHz; notes 1 and 2
4 outputs switching via S
31
13
41
16
pF
pF
1 output switching via I
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC
.
PINNING
PIN
SYMBOL
DESCRIPTION
1
S
common data select input
data inputs from source 0
data inputs from source 1
multiplexer outputs
2, 5, 11 and 14
1I0 to 4I0
1I1 to 4I1
1Y to 4Y
GND
E
3, 6, 10 and 13
4, 7, 9 and 12
8
ground (0 V)
15
16
enable input (active LOW)
DC supply voltage
VCC
1999 Sep 24
3
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
handbook, halfpage
V
S
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
1I
E
0
1
2
3
5
6
11 10 14 13
handbook, halfpage
1I
4I
4I
0
1
1I
1I 2I 2I 3I 3I 4I 4I
1 0 1 0 1 0
0
1
1Y
1
S
E
157
4Y
3I
2I
0
1
15
1Y
2Y
3Y
4Y
2I
0
3I
2Y
1
4
7
9
12
MNA481
3Y
GND
MNA480
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
handbook, halfpage
1
G1
1I
0
1
2
3
15
1Y
2Y
3Y
4Y
4
7
EN
1I
2I
2I
5
6
0
1
2
1
1
MUX
4
7
9
3
5
6
MULTIPLEXER
OUTPUTS
SELECTOR
3I
3I
11
10
0
1
9
11
10
4I
4I
14
13
0
1
12
14
13
12
S
1
E
MNA483
MNA482
15
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
1999 Sep 24
4
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
handbook, halfpage
S
E
1I
1
1Y
2Y
3Y
4Y
1I
0
2I
2I
1
0
3I
3I
1
0
4I
4I
1
MNA484
0
Fig.5 Logic diagram.
1999 Sep 24
5
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
RECOMMENDED OPERATING CONDITIONS
74AHC
74AHCT
UNIT
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN. TYP. MAX. MIN. TYP. MAX.
VCC
VI
2.0
0
5.0
−
5.5
4.5
0
5.0
−
5.5
V
input voltage
5.5
5.5
V
VO
output voltage
0
−
VCC
+85
0
−
VCC
+85
V
Tamb
operating ambient temperature
range
see DC and AC
characteristics per
device
−40
−40
+25
+25
−40
+25
+25
°C
+125 −40
+125 °C
tr,tf (∆t/∆f) input rise and fall rates
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
−
−
−
−
100
20
−
−
−
−
−
ns/V
20
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
VI
−0.5 +7.0
−0.5 +7.0
V
input voltage range
V
IIK
DC input diode current
DC output diode current
VI < −0.5 V; note 1
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−
−20
±20
±25
±75
mA
mA
mA
mA
IOK
IO
−
DC output source or sink current −0.5 V < VO < VCC + 0.5 V
DC VCC or GND current
−
ICC
Tstg
PD
−
storage temperature range
−65
−
+150 °C
500 mW
power dissipation per package
for temperature range: −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 24
6
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
DC CHARACTERISTICS
74AHC family
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
OTHER VCC (V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
HIGH-level input
voltage
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
1.5
2.1
3.85
−
−
−
1.5
2.1
3.85
−
−
1.5
2.1
3.85
−
−
V
V
V
V
−
−
−
−
−
−
−
−
VIL
LOW-level input
voltage
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
−
−
−
−
−
−
−
−
VOH
HIGH-level output VI = VIH or VIL;
voltage; all
outputs
1.9
2.9
4.4
2.58
2.0
3.0
4.5
−
1.9
2.9
4.4
2.48
1.9
2.9
4.4
2.40
IO = −50 µA
−
−
−
−
−
−
HIGH-level output VI = VIH or VIL;
−
−
−
voltage
IO = −4.0 mA
VI = VIH or VIL;
4.5
3.94
−
−
3.8
−
3.70
−
IO = −8.0 mA
VOL
LOW-level output VI = VIH or VIL;
2.0
3.0
4.5
3.0
−
−
−
−
0
0
0
−
0.1
0.1
0.1
0.36
−
−
−
−
0.1
0.1
0.1
0.44
−
−
−
−
0.1
0.1
0.1
0.55
V
V
voltage; all
outputs
IO = 50 µA
LOW-level output VI = VIH or VIL;
voltage
IO = 4 mA
VI = VIH or VIL;
IO = 8 mA
4.5
−
−
−
−
−
−
−
−
−
3
0.36
0.1
−
−
0.44
1.0
±2.5
40
−
−
−
−
−
0.55
2.0
II
input leakage
current
VI = VCC or GND 5.5
µA
IOZ
ICC
CI
3-state output
OFF current
VI = VIH or VIL;
VO = VCC or GND
5.5
±0.25 −
±10.0 µA
quiescent supply VI = VCC or GND; 5.5
4.0
10
−
−
80
10
µA
current
IO = 0
input capacitance
−
10
pF
1999 Sep 24
7
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
74AHCT family
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
T
amb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
25
OTHER VCC (V)
VIH
VIL
HIGH-level input
voltage
4.5 to 5.5 2.0
−
−
2.0
−
2.0
−
V
V
V
LOW-level input
voltage
4.5 to 5.5 −
−
0.8
−
−
0.8
−
−
0.8
−
VOH
HIGH-level output VI = VIH or VIL;
4.5
4.4 4.5
4.4
4.4
voltage; all
outputs
IO = −50 µA
HIGH-level output VI = VIH or VIL;
voltage IO = −8.0 mA
LOW-level output VI = VIH or VIL;
4.5
4.5
3.94
−
−
3.8
−
3.70
−
V
V
VOL
−
0
0.1
−
0.1
−
0.1
voltage; all
outputs
IO = 50 µA
LOW-level output VI = VIH or VIL;
4.5
5.5
5.5
−
−
−
−
−
−
0.36
0.1
−
−
0.44
1.0
−
−
−
0.55
2.0
V
voltage
IO = 8 mA
II
input leakage
current
VI = VIH or VIL
µA
IOZ
3-state output
OFF current
VI = VIH or VIL;
VO = VCC or GND
per input pin;
±0.25 −
±2.5
±10.0 µA
other inputs at
VCC or GND;
IO = 0
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
−
4.0
−
−
40
−
−
80
µA
∆ICC
additional
VI = VCC − 2.1 V 4.5 to 5.5 −
1.35
1.5
1.5
mA
quiescent supply
current per input
pin
other inputs at
VCC or GND;
IO = 0
CI
input capacitance
−
−
3
10
−
10
−
10
pF
1999 Sep 24
8
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
AC CHARACTERISTICS
Type 74AHC157
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
WAVEFORMS CL
T
amb (°C)
SYMBOL
PARAMETER
25
−40 to +85
−40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH propagation delay see Figs 7 and 8 15 pF
nI0 to nY; nI1 to nY
−
−
−
−
−
−
4.4
4.8
5.9
6.3
6.8
8.4
9.7
1.0
1.0
1.0
1.0
1.0
1.0
11.5
16.0
15.5
15.0
19.5
19.0
1.0
1.0
1.0
1.0
1.0
1.0
12.5
17.0
16.5
16.5
21.5
21.0
ns
ns
ns
ns
ns
ns
propagation delay
S to nY
13.6
13.2
13.2
17.1
16.7
propagation delay see Figs 6 and 8
E to nY
propagation delay see Figs 7 and 8 50 pF
nI0 to nY; nI1 to nY
propagation delay
S to nY
propagation delay see Figs 6 and 8
E to nY
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH propagation delay see Figs 7 and 8 15 pF
nI0 to nY; nI1 to nY
−
−
−
−
−
−
3.2
3.6
4.2
4.6
5.2
6.0
6.4
1.0
1.0
1.0
1.0
1.0
1.0
7.5
1.0
1.0
1.0
1.0
1.0
1.0
8.0
ns
ns
ns
ns
ns
ns
propagation delay
S to nY
8.6
10.0
9.5
11.0
10.5
10.5
13.5
13.0
propagation delay see Figs 6 and 8
E to nY
8.1
propagation delay see Figs 7 and 8 50 pF
nI0 to nY; nI1 to nY
8.4
9.5
propagation delay
S to nY
10.6
10.1
12.0
11.5
propagation delay see Figs 6 and 8
E to nY
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
1999 Sep 24
9
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
Type 74AHCT157
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
WAVEFORMS CL
Tamb (°C)
−40 to +85
SYMBOL
PARAMETER
25
−40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH propagation delay see Figs 7 and 8 15 pF
nI0 to nY; nI1 to nY
−
−
−
−
−
−
3.2
3.7
4.7
4.6
5.2
6.7
6.4
1.0
1.0
1.0
1.0
1.0
1.0
7.5
1.0
1.0
1.0
1.0
1.0
1.0
8.0
ns
ns
ns
ns
ns
ns
propagation delay
S to nY
8.6
10.0
9.5
11.0
10.5
11.0
13.0
13.5
propagation delay see Figs 6 and 8
E to nY
8.1
propagation delay see Figs 7 and 8 50 pF
nI0 to nY; nI1 to nY
8.7
9.8
propagation delay
S to nY
10.4
10.6
12.0
12.0
propagation delay see Figs 6 and 8
E to nY
Note
1. Typical values at VCC = 5.0 V.
AC WAVEFORMS
V
handbook, halfpage
CC
V
I
handbook, halfpage
nI , nI , S
0
1
(1)
(1)
V
V
M
E INPUT
M
INPUT
GND
GND
t
t
PHL
t
t
PLH
PHL
PLH
V
V
OH
OH
(1)
(1)
V
V
M
nY OUTPUT
nY OUTPUT
M
V
V
OL
MNA485
MNA486
OL
(1)
(1)
VI INPUT
VM
VM
FAMILY
(1)
(1)
REQUIREMENTS INPUT OUTPUT
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
AHC
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHC
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHCT
GND to 3.0 V
AHCT
GND to 3.0 V
Fig.7 The data inputs (nI0, nI1) and common data
select input (S) to output (nY) propagation
delays.
Fig.6 The enable input (E) to output (nY)
propagation delays.
1999 Sep 24
10
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
S1
V
CC
open
V
CC
GND
1000 Ω
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
R
L
T
MNA219
TEST
tPLH/tPHL
PLZ/tPZL
S1
open
VCC
t
tPHZ/tPZH
GND
Fig.8 Load circuitry for switching times.
1999 Sep 24
11
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1999 Sep 24
12
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-07-12
95-04-04
SOT403-1
MO-153
1999 Sep 24
13
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Sep 24
14
Philips Semiconductors
Product specification
74AHC157;
74AHCT157
Quad 2-input multiplexer
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, LFBGA, SQFP, TFBGA
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
not suitable
suitable
suitable
suitable
suitable
suitable
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 24
15
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245002/01/pp16
Date of release: 1999 Sep 24
Document order number: 9397 750 06359
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