74AHC164D-Q100J [NXP]
74AHC(T)164-Q100 - 8-bit serial-in/parallel-out shift register SOIC 14-Pin;
| 型号： | 74AHC164D-Q100J |
| 厂家： | 
NXP |
| 描述： | 74AHC(T)164-Q100 - 8-bit serial-in/parallel-out shift register SOIC 14-Pin PC 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总19页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC164-Q100;
74AHCT164-Q100
8-bit serial-in/parallel-out shift register
Rev. 1 — 5 July 2013
Product data sheet
1. General description
The 74AHC164-Q100; 74AHCT164-Q100 shift register is a high-speed Si-gate CMOS
device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in
compliance with JEDEC standard No. 7A.
The 74AHC164-Q100; 74AHCT164-Q100 input signals are 8-bit serial through one of two
inputs (DSA or DSB). Either input can be used as an active HIGH enable for data entry
through the other input. Both inputs must be connected together or an unused input must
be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP).
It enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB).
These data inputs existed one set-up time, prior to the rising clock edge.
A LOW-level on the master reset (MR) input overrides all other inputs and clears the
register asynchronously, forcing all outputs LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than VCC
Input levels:
For 74AHC164-Q100: CMOS level
For 74AHCT164-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC164-Q100
74AHC164D-Q100
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
SOT402-1
74AHC164PW-Q100 40 C to +125 C
TSSOP14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
74AHC164BQ-Q100
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads;
14 terminals; body 2.5 3 0.85 mm
74AHCT164-Q100
74AHCT164D-Q100
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
SOT402-1
74AHCT164PW-Q100 40 C to +125 C
74AHCT164BQ-Q100 40 C to +125 C
TSSOP14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads;
14 terminals; body 2.5 3 0.85 mm
4. Functional diagram
1
2
DSA
DSB
8-BIT SERIAL−IN/PARALLEL−OUT
8
9
CP
SHIFT REGISTER
MR
3
4
5
6
10 11 12 13
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
001aac425
Fig 1. Functional diagram
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
2 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
SRG8
8
C1/
9
R
1
3
&
1D
2
4
5
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DSA
1
6
4
2
DSB
5
10
11
12
13
6
10
11
CP
8
9
12
MR
13
001aac423
001aac424
Fig 2. Logic symbol
Fig 3. IEC logic symbol
DSA
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
DSB
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aac616
Fig 4. Logic diagram
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
3 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
5. Pinning information
5.1 Pinning
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05
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(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 5. Pin configuration SO14 and TSSOP14
Fig 6. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
DSA
DSB
Q0
Pin description
Pin
1
Description
serial data input A
serial data input B
output 0
2
3
Q1
4
output 1
Q2
5
output 2
Q3
6
output 3
GND
CP
7
ground (0 V)
8
clock input (LOW-to-HIGH edge-triggered)
MR
9
master reset input (active LOW)
Q4
10
11
12
13
14
output 4
Q5
output 5
Q6
output 6
Q7
output 7
VCC
supply voltage
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
4 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
6. Functional description
Table 3.
Function table[1]
Operating mode
Control
Input
Output
MR
L
CP
X
DSA
DSB
Q0
L
Q1 to Q7
L to L
Reset (clear)
Shift
X
l
X
l
H
L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
l
h
l
L
h
h
L
h
H
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
= LOW-to-HIGH transition;
X = don’t care;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
20
20
25
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < 0.5 V
mA
mA
mA
mA
mA
C
IOK
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
IO
ICC
supply current
IGND
Tstg
Ptot
ground current
75
65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 C the value of Ptot derates linearly at 4.5 mW/K.
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
5 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
8. Recommended operating conditions
Table 5.
Symbol
Operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
74AHC164-Q100
VCC
VI
supply voltage
2.0
0
5.0
5.5
V
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
100
20
V
Tamb
t/V
ambient temperature
input transition rise and fall rate
40
-
+25
C
ns/V
ns/V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
74AHCT164-Q100
VCC
VI
supply voltage
4.5
0
5.0
5.5
V
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
20
V
Tamb
t/V
ambient temperature
input transition rise and fall rate
40
-
+25
-
C
ns/V
VCC = 4.5 V to 5.5 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74AHC164-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
VI = VIH or VIL
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
4.4
2.58
3.94
2.48
3.80
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
V
V
V
V
V
0.1
0.1
0.1
0.36
0.36
0.44
0.44
0.55
0.55
-
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
6 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
II
input leakage VI = 5.5 V or GND;
current VCC = 0 V to 5.5 V
-
-
-
-
0.1
4.0
10
-
1.0
-
2.0
A
A
pF
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
40
-
-
-
80
-
V
input
3
capacitance
74AHCT164-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
IO = 8.0 mA
3.94
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
IO = 8.0 mA
V
II
input leakage VI = 5.5 V or GND;
current VCC = 0 V to 5.5 V
-
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
4.0
-
-
40
-
-
80
A
additional
per input pin;
1.35
1.5
1.5
mA
supply current VI = VCC 2.1 V; IO = 0 A;
other pins at VCC or GND;
VCC = 4.5 V to 5.5 V
CI
input
-
3
10
-
-
-
-
pF
capacitance
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
7 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 10.
Symbol Parameter Conditions
74AHC164-Q100
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min
Max
Min
Max
[2]
tpd
propagation CP to Qn; see Figure 7
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
6.5 12.8
9.3 16.3
1.0
1.0
15.0
18.5
1.0
1.0
16.0
20.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.5
9.0
1.0
1.0
10.5
12.5
1.0
1.0
11.5
14.0
ns
ns
CL = 50 pF
6.4 11.0
[3]
MR to Qn; see Figure 8
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.3 12.8
7.6 16.3
1.0
1.0
15.0
18.5
1.0
1.0
16.0
20.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.0
8.6
1.0
1.0
10.0
12.0
1.0
1.0
11.0
13.5
ns
ns
CL = 50 pF
5.8 10.6
fmax
maximum
frequency
see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
80
50
125
75
-
-
65
45
-
-
50
35
-
-
MHz
MHz
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
125
85
175
115
-
-
105
75
-
-
85
65
-
-
MHz
MHz
CL = 50 pF
tW
pulse width CP HIGH or LOW;
see Figure 7
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
tWL
pulse width MR; see Figure 8
LOW
VCC = 3.0 V to 3.6 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
tsu
set-up time DSA, DSB to CP;
see Figure 9
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
5.0
4.5
-
-
-
-
6.0
4.5
-
-
6.0
4.5
-
-
ns
ns
th
hold time
DSA, DSB to CP;
see Figure 9
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
2.0
-
-
-
-
1.5
2.0
-
-
1.5
2.0
-
-
ns
ns
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
8 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 10.
Symbol Parameter Conditions 25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min
Max
Min
Max
trec
recovery
time
MR to CP; see Figure 8
VCC = 3.0 V to 3.6 V
2.5
2.5
-
-
-
-
-
-
2.5
2.5
-
-
-
-
2.5
2.5
-
-
-
-
ns
ns
pF
VCC = 4.5 V to 5.5 V
[4]
CPD
power
fi = 1 MHz; VI = GND to VCC
48
dissipation
capacitance
74AHCT164-Q100; VCC = 4.5 V to 5.5 V
[2]
[3]
tpd
propagation CP to Qn; see Figure 7
delay
CL = 15 pF
-
-
3.4
9.0
1.0
1.0
10.5
12.5
1.0
1.0
11.5
14.0
ns
ns
CL = 50 pF
4.9 11.0
MR to Qn; see Figure 8
CL = 15 pF
-
-
3.5
8.6
1.0
1.0
10.0
12.0
1.0
1.0
11.0
13.5
ns
ns
CL = 50 pF
5.0 10.6
fmax
maximum
frequency
see Figure 7
CL = 15 pF
CL = 50 pF
125
85
175
115
-
-
-
-
105
75
-
-
-
85
65
-
-
-
MHz
MHz
ns
tW
pulse width CP HIGH or LOW;
see Figure 7
5.0
5.0
5.0
tWL
tsu
pulse width MR; see Figure 8
LOW
5.0
4.5
2.0
2.5
-
-
-
-
-
-
-
-
5.0
4.5
2.0
2.5
-
-
-
-
-
-
5.0
4.5
2.0
2.5
-
-
-
-
-
-
ns
ns
ns
ns
pF
set-up time DSA, DSB to CP;
see Figure 9
th
hold time
DSA, DSB to CP;
see Figure 9
-
trec
CPD
recovery
time
MR to CP; see Figure 8
-
[4]
power
fi = 1 MHz; VI = GND to VCC
51
dissipation
capacitance
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] pd is the same as tPLH and tPHL
[3] tpd is the same as tPHL only.
t
.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
9 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
11. Waveforms
1/f
max
V
I
CP input
V
t
M
GND
t
W
t
PHL
PLH
V
OH
V
Qn output
M
001aac426
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock pulse width, maximum frequency and input to output propagation delays
V
I
V
MR input
M
GND
t
t
rec
WL
V
I
CP input
V
M
GND
t
PHL
V
OH
V
Qn output
M
V
OL
001aac446
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 8. Master reset pulse width, recovery time and propagation delays
74AHC_AHCT164_Q100
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Product data sheet
Rev. 1 — 5 July 2013
10 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
V
I
V
M
CP input
GND
t
t
su
su
t
t
h
h
V
I
V
DSA, DSB input
GND
M
V
OH
V
Qn output
M
V
OL
001aaf612
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Data set-up and hold times
Table 8.
Type
Measurement points
Input
VM
Output
VM
74AHC164-Q100
74AHCT164-Q100
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
74AHC_AHCT164_Q100
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Product data sheet
Rev. 1 — 5 July 2013
11 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
Fig 10. Load circuitry for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74AHC164-Q100
74AHCT164-Q100
VCC
3.0 V
3.0 ns
3.0 ns
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74AHC_AHCT164_Q100
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Product data sheet
Rev. 1 — 5 July 2013
12 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 11. Package outline SOT108-1 (SO14)
74AHC_AHCT164_Q100
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Product data sheet
Rev. 1 — 5 July 2013
13 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 12. Package outline SOT402-1 (TSSOP14)
74AHC_AHCT164_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
14 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 13. Package outline SOT762-1 (DHVQFN14)
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
15 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
ESD
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
MIL
Military
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC_AHCT164_Q100 v.1 20130705
Product data sheet
-
-
74AHC_AHCT164_Q100
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Product data sheet
Rev. 1 — 5 July 2013
16 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC_AHCT164_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
17 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT164_Q100
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Product data sheet
Rev. 1 — 5 July 2013
18 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 July 2013
Document identifier: 74AHC_AHCT164_Q100
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