74AHC240BQ-Q100 [NXP]
IC DRIVER, Bus Driver/Transceiver;
| 型号： | 74AHC240BQ-Q100 |
| 厂家： | 
NXP |
| 描述： | IC DRIVER, Bus Driver/Transceiver 驱动 逻辑集成电路 |
| 文件： | 总17页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC240-Q100;
74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
Rev. 1 — 6 November 2013
Product data sheet
1. General description
The 74AHC240-Q100 and 74AHCT240-Q100 are 8-bit inverting buffer/line drivers with
3-state outputs. These devices can be used as two 4-bit buffers or one 8-bit buffer. They
feature two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A
HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are
over voltage tolerant. This feature allows the use of these devices as translators in mixed
voltage environments.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than VCC
For 74AHC240-Q100 only: operates with CMOS input levels
For 74AHCT240-Q100 only: operates with TTL input levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
Multiple package options
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC240D-Q100
74AHCT240D-Q100
40 C to +125 C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHC240PW-Q100 40 C to +125 C
TSSOP20
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
74AHCT240PW-Q100
74AHC240BQ-Q100
74AHCT240BQ-Q100
40 C to +125 C
DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1
very thin quad flat package; no leads;
20 terminals; body 2.5 4.5 0.85 mm
4. Functional diagram
1
EN
18
2
16
14
12
4
6
8
2
1Y0 18
2Y0
1A0
3
17 2A0
4
1A1
2A1
1Y1 16
15
5
2Y1
19
11
EN
6
14
7
1Y2
2Y2
1A2
2A2
13
9
8
12
9
1Y3
2Y3
1A3
2A3
13
15
17
7
5
3
11
1OE
2OE
1
19
mgu779
mgu778
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
2 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
5. Pinning information
5.1 Pinning
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9
&&
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7UDQVSDUHQWꢌWRSꢌYLHZ
DDDꢀꢁꢁꢂꢃꢁꢂ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration SO20 and TSSOP20
Fig 4. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE
Pin description
Pin
1
Description
output enable input (active LOW)
output enable input (active LOW)
data input
2OE
19
1A0, 1A1, 1A2, 1A3 2, 4, 6, 8
2A0, 2A1, 2A2, 2A3 17, 15, 13, 11
1Y0, 1Y1, 1Y2, 1Y3 18, 16, 14, 12
2Y0, 2Y1, 2Y2, 2Y3 3, 5, 7, 9
data input
data output
data output
GND
VCC
10
20
ground (0 V)
power supply
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
3 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
6. Functional description
Table 3.
Function table[1]
Control
Input
nAn
L
Output
nOE
L
nYn
H
L
H
L
H
X
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
20
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < 0.5 V
mA
mA
mA
mA
mA
C
IOK
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
20
25
75
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
75
65
-
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = 40 C to +125 C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 package: above 70 C the value of Ptot derates linearly with 8.0 mW/K.
For TSSOP20 package: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 package: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
Recommended operating conditions
Parameter Conditions
Min
Typ
Max
Unit
74AHC240-Q100
VCC
VI
supply voltage
2.0
5.0
5.5
V
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
+125
100
20
V
Tamb
t/V
ambient temperature
input transition rise and fall rate
40
+25
C
ns/V
ns/V
VCC = 3.3 V 0.3 V
VCC = 5 V 0.5 V
-
-
-
-
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
4 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
Table 5.
Symbol
Recommended operating conditions …continued
Parameter
Conditions
Min
Typ
Max
Unit
74AHCT240-Q100
VCC
VI
supply voltage
4.5
0
5.0
5.5
V
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
20
V
Tamb
t/V
ambient temperature
input transition rise and fall rate
40
-
+25
-
C
ns/V
VCC = 5 V 0.5 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74AHC240-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
VI = VIH or VIL
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
4.4
2.58
3.94
2.48
3.80
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
0.1
0.1
0.1
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage VI = 5.5 V or GND;
-
A
current
VCC = 0 V to 5.5 V
IOZ
OFF-state
VI = VIH or VIL;
-
-
0.25
-
2.5
-
10.0
A
output current VO = VCC or GND;
VCC = 5.5 V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
4.0
10
-
-
-
-
40
10
-
-
-
-
80
10
-
A
pF
pF
input
VI = VCC or GND
3
4
capacitance
CO
output
capacitance
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
5 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74AHCT240-Q100
VIH
VIL
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
IO = 8.0 mA
3.94
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
IO = 8.0 mA
V
II
input leakage VI = 5.5 V or GND;
-
A
current
VCC = 0 V to 5.5 V
IOZ
OFF-state
VI = VIH or VIL;
-
-
0.25
-
2.5
-
10.0
A
output current VO = VCC or GND per input
pin; other inputs at
VCC or GND; IO = 0 A;
VCC = 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
4.0
-
-
40
-
-
80
A
ICC
additional
supply current VI = VCC 2.1 V;
other pins at VCC or GND;
per input pin;
1.35
1.5
1.5
mA
IO = 0 A; VCC = 4.5 V to 5.5 V
CI
input
capacitance
VI = VCC or GND
-
-
3
4
10
-
-
-
10
-
-
-
10
-
pF
pF
CO
output
capacitance
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
6 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 7.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Max Max
(85 C) (125 C)
Unit
Min Typ[1] Max Min
74AHC240-Q100
[2]
[2]
[2]
[3]
tpd
propagation delay nAn to nYn; see Figure 5
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V; CL = 50 pF
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
-
-
-
3.9
5.8
2.8
4.2
7.5
11.0
4.8
1.0
1.0
1.0
1.0
8.6
12.5
5.7
10.8
15.6
7.1
ns
ns
ns
ns
7.3
8.5
10.6
ten
enable time
nOE to nYn; see Figure 6
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V; CL = 50 pF
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
nOE to nYn; see Figure 6
-
-
-
-
4.4
5.8
3.1
4.1
10.0
13.5
6.5
1.0
1.0
1.0
1.0
12.0
15.5
7.7
19.4
19.4
12.5
12.5
ns
ns
ns
ns
8.5
10.0
tdis
disable time
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V; CL = 50 pF
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
-
-
-
-
5.3
8.9
3.9
6.2
9
9.0
13.0
5.8
8.7
-
1.0
1.0
1.0
1.0
-
10.0
14.5
6.5
9.5
-
18.1
18.1
8.1
11.8
-
ns
ns
ns
ns
pF
CPD
power dissipation VI = GND to VCC; CL = 50 pF;
capacitance fi = 1 MHz
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
7 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 7.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Max Max
(85 C) (125 C)
Unit
Min Typ[1] Max Min
74AHCT240-Q100
[2]
[2]
[2]
[3]
tpd
propagation delay nAn to nYn; see Figure 5
VCC = 4.5 V to 5.5 V; CL = 15 pF
-
-
3.0
4.4
5.8
8.4
1.0
1.0
6.8
9.5
8.5
ns
ns
VCC = 4.5 V to 5.5 V; CL = 50 pF
11.9
ten
enable time
disable time
nOE to nYn; see Figure 6
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
nOE to nYn; see Figure 6
-
-
3.4
4.5
7.5
9.5
1.0
1.0
9.0
14.4
14.4
ns
ns
11.5
tdis
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
-
-
3.9
6.2
9
6.1
8.7
-
1.0
1.0
-
6.7
9.2
-
8.3
11.5
-
ns
ns
pF
CPD
power dissipation VI = GND to VCC; CL = 50 pF;
capacitance fi = 1 MHz
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] pd is the same as tPLH and tPHL; ten is the same as tPZH and tPZL; tdis is the same as tPLZ and tPHZ
t
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
V
I
nAn input
GND
V
V
M
M
t
t
PHL
PLH
V
OH
90 %
90 %
V
V
M
nYn output
M
10 %
10 %
V
OL
t
t
THL
TLH
mgu781
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 5. Propagation delay input (nAn) to output (nYn)
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
8 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
V
I
nOE input
V
M
GND
t
t
PZL
PLZ
V
CC
nYn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
nYn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae014
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Enable and disable times
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74AHC240-Q100
74AHCT240-Q100
0.5VCC
1.5 V
0.5VCC
0.5VCC
VOL + 0.3 V
VOL + 0.3 V
VOH 0.3 V
VOH 0.3 V
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
9 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7. Load circuitry for switching times
Table 9.
Type
Test data
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74AHC240-Q100 VCC
74AHCT240-Q100 3.0 V
3.0 ns
3.0 ns
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
open
GND
VCC
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
10 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 8. Package outline SOT163-1 (SO20)
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
11 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 9. Package outline SOT360-1 (TSSOP20)
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
12 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 10. Package outline SOT764-1 (DHVQFN20)
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
13 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charge Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Military
MIL
HBM
TTL
Human Body Model
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC_AHCT240_Q100 v.1 20131106
Product data sheet
-
-
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
14 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
15 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
16 of 17
NXP Semiconductors
74AHC240-Q100; 74AHCT240-Q100
Octal buffer/line driver; inverting; 3-state
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 November 2013
Document identifier: 74AHC_AHCT240_Q100
相关型号：
74AHC240D
IC AHC/VHC/H/U/V SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20, Bus Driver/Transceiver
NXP
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