74AHC373_08 [NXP]
Octal D-type transparant latch; 3-state; 八路D型TRANSPARANT锁存器;三态
| 型号： | 74AHC373_08 |
| 厂家： | 
NXP |
| 描述： | Octal D-type transparant latch; 3-state |
| 文件： | 总17页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Rev. 03 — 20 May 2008
Product data sheet
1. General description
The 74AHC373; 74AHCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC373; 74AHCT373 consists of eight D-type transparent latches featuring
separate D-type inputs for each latch and 3-state true outputs for bus oriented
applications. A latch enable input (LE) and an output enable input (OE) are common to all
latches.
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
Dn input changes. When pin LE is LOW, the latches store the information that is present
at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.
When pin OE is LOW, the contents of the 8 latches are available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the latches.
The 74AHC373; 74AHCT373 is functionally identical to the 74AHC573; 74AHCT573, but
has a different pin arrangement.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Common 3-state output enable input
I Inputs accepts voltages higher than VCC
I Functionally identical to the 74AHC573; 74AHCT573
I Input levels:
N For 74AHC373: CMOS input level
N For 74AHCT373: TTL input level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AHC373
74AHC373D
−40 °C to +125 °C
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHC373PW
TSSOP20
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
74AHCT373
74AHCT373D
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHCT373PW −40 °C to +125 °C
TSSOP20
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
4. Functional diagram
D0
Q0
2
3
D1
D2
D3
D4
D5
D6
D7
Q1
5
4
7
Q2
6
Q3
8
9
LATCH
1 TO 8
3-STATE
OUTPUTS
Q4
Q5
Q6
Q7
13
14
17
18
12
15
16
19
LE
11
1
OE
001aae050
Fig 1. Functional diagram
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
2 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
1
OE
LE
EN
C1
11
11
3
2
1D
D0
Q0
LE
3
4
2
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
5
6
9
D1
D2
D3
Q1
Q2
Q3
5
7
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
D4
D5
D6
D7
Q4
Q5
Q6
Q7
OE
1
001aae048
001aae049
Fig 2. Logic symbol
Fig 3. IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig 4. Logic diagram
LE
LE
LE
D
Q
LE
001aae051
Fig 5. Logic diagram (one latch)
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
3 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
5. Pinning information
5.1 Pinning
74AHC373
74AHCT373
1
2
20
19
18
17
16
15
14
13
12
11
OE
Q0
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
10
GND
001aai132
Fig 6. Pin configuration SO20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
1
Description
3-state output enable input (active LOW)
3-state latch output
data input
Q0
2
D0
3
D1
4
data input
Q1
5
3-state latch output
3-state latch output
data input
Q2
6
D2
7
D3
8
data input
Q3
9
3-state latch output
ground (0 V)
GND
LE
10
11
12
13
14
15
16
17
latch enable input (active HIGH)
3-state latch output
data input
Q4
D4
D5
data input
Q5
3-state latch output
3-state latch output
data input
Q6
D6
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
4 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
Table 2.
Symbol
D7
Pin description …continued
Pin
18
19
20
Description
data input
Q7
3-state latch output
supply voltage
VCC
6. Functional description
Table 3.
Function table[1]
Operating mode
Control
Input
Internal
latch
Output
OE
LE
Dn
L
Q0 to Q7
Enable and read register (transparent mode)
Latch and read register
L
H
L
L
H
l
H
L
H
L
L
L
h
H
X
X
H
Z
Z
Latch register and disable outputs
H
X
X
X
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−20
−20
−25
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
IO
ICC
supply current
IGND
Tstg
Ptot
ground current
−75
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
5 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
8. Recommended operating conditions
Table 5.
Symbol
74AHC373
VCC
Operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
2.0
5.0
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
+125
100
20
V
Tamb
ambient temperature
input transition rise and fall rate
−40
+25
°C
ns/V
ns/V
∆t/∆V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
74AHCT373
VCC
VI
supply voltage
4.5
0
5.0
5.5
V
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
20
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
-
+25
-
°C
ns/V
VCC = 4.5 V to 5.5 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHC373
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
IO = −4.0 mA; VCC = 3.0 V
IO = −8.0 mA; VCC = 4.5 V
VI = VIH or VIL
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
4.4
2.58
3.94
2.48
3.80
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
V
V
V
V
V
0.1
0.1
0.1
0.36
0.36
0.44
0.44
0.55
0.55
-
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
6 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
IOZ
OFF-state
VI = VIH or VIL;
-
-
±0.2
-
±2.5
-
±10.0 µA
output current VO = VCC or GND;
CC = 5.5 V
5
V
II
input leakage VI = VCC or GND;
current CC = 0 V to 5.5 V
-
-
-
-
-
-
0.1
4.0
10
-
-
-
-
-
1.0
40
10
-
-
-
-
-
2.0
80
10
10
µA
µA
pF
pF
V
ICC
CI
CO
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
V
input
VI = VCC or GND
3
4
capacitance
output
capacitance
74AHCT373
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −50 µA
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
IO = −8.0 mA
3.94
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 µA
-
-
-
0
-
0.1
-
-
-
0.1
-
-
-
0.1
V
V
IO = 8.0 mA
0.36
0.44
±2.5
0.55
IOZ
OFF-state
VI = VIH or VIL;
-
±0.2
±10.0 µA
output current VO = VCC or GND per input
pin; other inputs at VCC or
5
GND; IO = 0 A; VCC = 5.5 V
II
input leakage VI = 5.5 V or GND;
-
-
-
-
-
-
0.1
4.0
-
-
-
1.0
40
-
-
-
2.0
80
µA
µA
µA
current
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
per input pin;
supply current VI = VCC − 2.1 V; other pins at
VCC = 0 V to 5.5 V
ICC
∆ICC
V
additional
1.35
1.5
1.5
V
V
CC or GND; IO = 0 A;
CC = 4.5 V to 5.5 V
CI
input
capacitance
VI = VCC or GND
-
-
3
4
10
-
-
-
10
-
-
-
10
10
pF
pF
CO
output
capacitance
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
7 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max
74AHC373
[2]
[2]
[3]
[4]
tpd
propagation Dn to Qn; see Figure 7
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
CL = 50 pF
-
-
6.0
7.8
11.4
14.9
1.0
1.0
13.5
17.0
1.0
1.0
14.5
19.0
ns
ns
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.0
5.3
7.2
9.2
1.0
1.0
8.5
1.0
1.0
9.0
ns
ns
CL = 50 pF
10.5
11.5
LE to Qn; see Figure 8
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
6.3
8.3
11.0
14.5
1.0
1.0
13.0
16.5
1.0
1.0
14.0
18.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.3
5.6
7.2
9.7
1.0
1.0
8.5
1.0
1.0
9.0
ns
ns
CL = 50 pF
11.1
12.5
ten
enable time
OE to Qn; see Figure 9
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.6
7.5
11.4
14.9
1.0
1.0
13.5
17.0
1.0
1.0
14.5
19.0
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.8
5.2
8.1
1.0
1.0
9.5
1.0
1.0
10.5
13.0
ns
ns
CL = 50 pF
10.1
11.5
tdis
disable time OE to Qn; see Figure 9
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.6
9.2
10.0
13.3
1.0
1.0
12.0
15.0
1.0
1.0
13.0
17.0
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.3
6.4
7.2
9.2
1.0
1.0
8.5
1.0
1.0
9.5
ns
ns
CL = 50 pF
10.5
11.5
tW
pulse width
set-up time
LE HIGH or LOW;
see Figure 8
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
Dn to LE; see Figure 10
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
tsu
4.0
4.0
-
-
-
-
4.0
4.0
-
-
4.0
4.0
-
-
ns
ns
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
8 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max
th
hold time
Dn to LE; see Figure 10
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.0
1.0
-
-
-
-
-
-
1.0
1.0
-
-
-
-
1.0
1.0
-
-
-
-
ns
ns
pF
[5]
[4]
CPD
power
dissipation
capacitance
fi = 1 MHz;
VI = GND to VCC
10
74AHCT373; VCC = 4.5 V to 5.5 V
tpd
propagation Dn to Qn; see Figure 7
delay
CL = 15 pF
CL = 50 pF
-
-
4.0
5.2
8.5
9.5
1.0
1.0
9.5
1.0
1.0
11.0
12.0
ns
ns
10.5
LE to Qn; see Figure 8
CL = 15 pF
[4]
[4]
-
-
4.3
5.5
12.3
13.3
1.0
1.0
13.5
14.5
1.0
1.0
15.5
17.0
ns
ns
CL = 50 pF
ten
enable time
OE to Qn; see Figure 9
CL = 15 pF
-
-
4.0
5.2
10.9
11.9
1.0
1.0
12.5
13.5
1.0
1.0
14.0
15.0
ns
ns
CL = 50 pF
tdis
disable time OE to Qn; see Figure 9
CL = 15 pF
-
4.4
6.5
-
10.2
1.0
1.0
6.5
3.5
1.5
-
11.0
1.0
1.0
6.5
3.5
1.5
-
13.0
ns
ns
ns
ns
ns
pF
CL = 50 pF
-
11.2
12.0
14.0
[4]
[5]
tW
pulse width
set-up time
hold time
LE HIGH; see Figure 8
Dn to LE; see Figure 10
Dn to LE; see Figure 10
6.5
3.5
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
tsu
th
-
-
CPD
power
fi = 1 MHz;
12
dissipation
capacitance
VI = GND to VCC
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPHL and tPLH
[3] ten is the same as tPZH and tPZL
[4] tdis is the same as tPHZ and tPLZ
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
9 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
11. Waveforms
V
I
V
M
Dn input
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
mna811
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Data input to output propagation delays
1/f
max
V
I
LE input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
M
Qn output
mna812
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Latch enable pulse width and input to output propagation delays
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
10 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
V
I
OE input
V
M
t
GND
t
PLZ
PZL
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna813
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Enable and disable times
V
I
V
M
Dn input
GND
t
t
h
h
t
t
su
su
V
I
LE input
V
M
GND
mna814
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig 10. Data set-up and hold times
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74AHC373
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
VOL + 0.3 V
VOL + 0.3 V
V
V
OH − 0.3 V
74AHCT373
OH − 0.3 V
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
11 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
S1 = test selection switch.
Fig 11. Test circuitry for switching times
Table 9.
Type
Test data
Input
Load
CL
S1 position
tPHL, tPLH
open
VI
tr, tf
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74AHC373
VCC
3.0 V
≤ 3.0 ns
≤ 3.0 ns
15 pF, 50 pF 1 kΩ
15 pF, 50 pF 1 kΩ
74AHCT373
open
GND
VCC
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
12 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 12. Package outline SOT163-1 (SO20)
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
13 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 13. Package outline SOT360-1 (TSSOP20)
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
14 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
ESD
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC_AHCT373_3 20080520
Product data sheet
-
74AHC_AHCT373_2
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 6: conditions for the input leakage current have been changed.
74AHC_AHCT373_2 19991123
Product specification
-
74AHC_AHCT373_1
74AHC_AHCT373_1 19981211
Product specification
-
-
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
15 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
16 of 17
74AHC373; 74AHCT373
NXP Semiconductors
Octal D-type transparant latch; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 May 2008
Document identifier: 74AHC_AHCT373_3
相关型号：
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