74AHCT08PW118 [NXP]

Quad 2-input AND gate Rev. 03 â 14 November 2007; 四路2输入与门启03 â ???? 2007年11月14日


型号：	74AHCT08PW118
厂家：	NXP
描述：	Quad 2-input AND gate Rev. 03 â 14 November 2007 四路2输入与门启03 â ???? 2007年11月14日
文件：	总14页 (文件大小：91K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AHC08; 74AHCT08

Quad 2-input AND gate

Rev. 03 — 14 November 2007

Product data sheet

1. General description

The 74AHC08; 74AHCT08 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard JESD7-A.

The 74AHC08; 74AHCT08 provides the quad 2-input AND function.

2. Features

■ Balanced propagation delays

■ All inputs have a Schmitt-trigger action

■ Inputs accepts voltages higher than V_CC

■ For 74AHC08 only: operates with CMOS input levels

■ For 74AHCT08 only: operates with TTL input levels

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101C exceeds 1000 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74AHC08D

−40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74AHCT08D

74AHC08PW

74AHCT08PW

74AHC08BQ

74AHCT08BQ

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

SOT762-1

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

4. Functional diagram

mna221

4Y 11

mna222

mna223

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram (one gate)

5. Pinning information

5.1 Pinning

terminal 1

index area

GND(1)

001aac946

GND

Transparent top view

001aac945

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

a supply pin or input.

Fig 4. Pin conﬁguration SO14 and TSSOP14

Fig 5. Pin conﬁguration DHVQFN14

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

2 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

5.2 Pin description

Table 2.

Symbol

Pin description

Description

data input

data output

data input

data output

ground (0 V)

data output

data input

GND

data input

data output

data input

V_CC

supply voltage

6. Functional description

Table 3.

Function selection^[1]

Input

Output

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

V_I

Parameter

Conditions

Min

−0.5

−20

Max

+7.0

Unit

supply voltage

input voltage

[1]

I_IK

input clamping current

output clamping current

output current

V_I< −0.5 V

°C

I_OK

V_O< −0.5 V or V_O> V_CC+ 0.5 V

V_O= −0.5 V to (V_CC+ 0.5 V)

±20

±25

I_O

I_CC

supply current

I_GND

T_stg

ground current

−75

−65

storage temperature

+150

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

3 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

Table 4.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

P_tot

total power dissipation

SO14 package

T_amb= −40 °C to +125 °C

[2]

[3]

[4]

500

TSSOP14 package

DHVQFN14 package

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] P_totderates linearly with 8 mW/K above 70 °C.

[3] P_totderates linearly with 5.5 mW/K above 60 °C.

[4] P_totderates linearly with 4.5 mW/K above 60 °C.

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

74AHC08

74AHCT08

Unit

Min

2.0

Typ

Max

5.5

Min

4.5

Typ

Max

5.5

V_CC

+125

V_CC

V_I

supply voltage

input voltage

5.0

5.5

V_O

output voltage

ambient temperature

V_CC

+125

100

T_amb

∆t/∆V

−40

+25

−40

+25

°C

ns/V

input transition rise

and fall rate

V_CC= 3.3 V ± 0.3 V

V_CC= 5.0 V ± 0.5 V

9. Static characteristics

Table 6.

Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

Min Typ Max

−40 °C to +85 °C −40 °C to +125 °C Unit

Min

Max

Min

Max

For type 74AHC08

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

1.5

V_CC= 3.0 V

2.1

V_CC= 5.5 V

3.85

V_IL

LOW-level

input voltage

V_CC= 2.0 V

0.5

0.9

1.65

0.5

0.9

1.65

0.5

0.9

1.65

V_CC= 3.0 V

V_CC= 5.5 V

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= −50 µA; V_CC= 2.0 V

I_O= −50 µA; V_CC= 3.0 V

I_O= −50 µA; V_CC= 4.5 V

I_O= −4.0 mA; V_CC= 3.0 V

I_O= −8.0 mA; V_CC= 4.5 V

1.9

2.9

2.0

3.0

4.5

1.9

2.9

1.9

2.9

4.4

2.4

3.7

4.4

2.58

3.94

2.48

3.8

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

4 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

Table 6.

Static characteristics …continued

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

Min Typ Max

−40 °C to +85 °C −40 °C to +125 °C Unit

Min

Max

Min

Max

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 50 µA; V_CC= 2.0 V

I_O= 50 µA; V_CC= 3.0 V

I_O= 50 µA; V_CC= 4.5 V

I_O= 4.0 mA; V_CC= 3.0 V

I_O= 8.0 mA; V_CC= 4.5 V

0.1

0.36

0.1

0.44

1.0

0.55

2.0

I_I

input leakage V_I= 5.5 V or GND; V_CC= 0 V

current to 5.5 V

µA

I_CC

C_I

supply current V_I= V_CCor GND; I_O= 0 A;

_CC= 5.5 V

2.0

µA

input

3.0

capacitance

For type 74AHCT08

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= −50 µA

4.4

4.5

4.4

3.8

4.4

3.7

I_O= −8.0 mA

3.94

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 50 µA

0.1

0.36

0.1

0.44

1.0

0.1

0.55

2.0

I_O= 8.0 mA

I_I

input leakage V_I= 5.5 V or GND; V_CC= 0 V

current to 5.5 V

µA

I_CC

∆I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

_CC= 5.5 V

2.0

µA

additional

per input pin;

1.35

1.5

supply current V_I= V_CC− 2.1 V; I_O= 0 A;

other pins at V_CCor GND;

_CC= 4.5 V to 5.5 V

C_I

input

3.0

capacitance

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

5 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

10. Dynamic characteristics

Table 7.

Dynamic characteristics

GND = 0 V; For test circuit see Figure 7.

Symbol Parameter Conditions

25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ^[1]Max Min

Max

Min

Max

For type 74AHC08

[2]

t_pd

propagation nA, nB to nY; see Figure 6

delay

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

4.0

8.8

1.0

10.5

1.0

11.0

15.5

C_L= 50 pF

5.6 12.3

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

3.0

4.2

5.9

7.9

1.0

7.0

9.0

1.0

7.5

10.0

C_L= 50 pF

[3]

[2]

C_PD

power

dissipation

capacitance

C_L= 50 pF; f_i= 1 MHz;

V_I= GND to V_CC

10.0

For type 74AHCT08

t_pd

propagation nA, nB to nY; see Figure 6

delay

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

C_L= 50 pF

3.2

4.2

6.9

7.9

1.0

8.0

9.0

1.0

9.0

10.0

[3]

C_PD

power

C_L= 50 pF; f_i= 1 MHz;

V_I= GND to V_CC

12.0

dissipation

capacitance

[1] Typical values are measured at nominal supply voltage (V_CC= 3.3 V and V_CC= 5.0 V).

[2] t_pdis the same as t_PLHand t_PHL

[3] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz, f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

Σ(C_L× V_CC²× f_o) = sum of the outputs.

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

6 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

11. Waveforms

nA, nB input

GND

PLH

PHL

nY output

mna224

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 6. The input (nA, nB) to output (nY) propagation delays

Table 8.

Type

Measurement points

Input

V_M

Output

V_M

74AHC08

0.5V_CC

1.5 V

0.5V_CC

74AHCT08

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

7 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

PULSE

GENERATOR

open

DUT

001aad983

Test data is given in Table 9.

Deﬁnitions test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

R_L= Load resistance.

S1 = Test selection switch.

Fig 7. Load circuit for switching times

Table 9.

Type

Test data

Input

Load

S1 position

t_PHL, t_PLH

open

V_I

t_r, t_f

C_L

R_L

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

V_CC

74AHC08

V_CC

3.0 V

≤ 3.0 ns

15 pF, 50 pF

1 kΩ

74AHCT08

open

GND

V_CC

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

8 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

12. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

(A )

pin 1 index

detail X

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

UNIT

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

1.75

1.27

0.05

1.05

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Fig 8. Package outline SOT108-1 (SO14)

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

9 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

1.1

0.65

0.25

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig 9. Package outline SOT402-1 (TSSOP14)

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

10 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

SOT762-1

detail X

terminal 1

index area

terminal 1

index area

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

0.05 0.30

0.00 0.18

3.1

2.9

1.65

1.35

2.6

2.4

1.15

0.85

0.5

0.3

0.05

0.1

0.2

0.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT762-1

- - -

MO-241

- - -

Fig 10. Package outline SOT762-1 (DHVQFN14)

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

11 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

13. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

LSTTL

ESD

Description

Complementary Metal Oxide Semiconductor

Low-power Schottky Transistor-Transistor Logic

ElectroStatic Discharge

HBM

Human Body Model

Machine Model

CDM

Charged Device Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date

20071114

Data sheet status

Change notice

Supersedes

74AHC_AHCT08_3

Modiﬁcations:

Product data sheet

74AHC_AHCT08_2

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 3: DHVQFN14 package added.

• Section 7: derating values added for DHVQFN14 package.

• Section 12: outline drawing added for DHVQFN14 package.

74AHC_AHCT08_2

74AHC_AHCT08_1

19990924

Product speciﬁcation

74AHC_AHCT08_1

19981218

Product speciﬁcation

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

12 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

74AHC_AHCT08_3

Product data sheet

Rev. 03 — 14 November 2007

13 of 14

74AHC08; 74AHCT08

NXP Semiconductors

Quad 2-input AND gate

17. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional description . . . . . . . . . . . . . . . . . . . 3

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.1

15.2

15.3

15.4

Contact information. . . . . . . . . . . . . . . . . . . . . 13

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 November 2007

Document identifier: 74AHC_AHCT08_3

74AHCT08PW118 [NXP]

相关型号：

74AHCT08PWDH

74AHCT08S14-13

74AHCT08T14-13

74AHCT123A

74AHCT123A-Q100

74AHCT123ABQ

74AHCT123ABQ

74AHCT123ABQ-G

74AHCT123ABQ-Q100

74AHCT123ABQ-Q100

74AHCT123ABQ-Q100X

74AHCT123AD