74AHCT1G02GV-Q100H [NXP]
74AHC(T)1G02-Q100 - 2-input NOR gate TSOP 5-Pin;型号: | 74AHCT1G02GV-Q100H |
厂家: | NXP |
描述: | 74AHC(T)1G02-Q100 - 2-input NOR gate TSOP 5-Pin 光电二极管 逻辑集成电路 |
文件: | 总12页 (文件大小:102K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74AHC1G02-Q100;
74AHCT1G02-Q100
2-input NOR gate
Rev. 1 — 6 November 2013
Product data sheet
1. General description
74AHC1G02-Q100 and 74AHCT1G02-Q100 are high-speed Si-gate CMOS devices.
They provide a 2-input NOR function.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
SOT353-1 and SOT753 package options
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
40 C to +125 C
Name
Description
Version
74AHC1G02GW-Q100
74AHCT1G02GW-Q100
74AHC1G02GV-Q100
74AHCT1G02GV-Q100
TSSOP5 plastic thin shrink small outline package;
5 leads; body width 1.25 mm
SOT353-1
40 C to +125 C
SC-74A
plastic surface-mounted package; 5 leads SOT753
NXP Semiconductors
74AHC1G02-Q100; 74AHCT1G02-Q100
2-input NOR gate
4. Marking
Table 2.
Marking codes
Type number
Marking[1]
AB
74AHC1G02GW-Q100
74AHC1G02GV-Q100
74AHCT1G02GW-Q100
74AHCT1G02GV-Q100
A02
CB
C02
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
B
1
2
1
2
B
A
Y
4
≥ 1
4
Y
A
mna103
mna104
mna105
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
ꢀꢁ$+&ꢂ*ꢃꢄꢅ4ꢂꢃꢃ
ꢀꢁ$+&7ꢂ*ꢃꢄꢅ4ꢂꢃꢃ
ꢀ
ꢁ
ꢂ
ꢃ
%
$
9
&&
ꢄ
*1'
<
DDDꢀꢁꢁꢂꢃꢄꢄ
Fig 4. Pin configuration
6.2 Pin description
Table 3.
Pin description
Pin
Symbol
Description
data input B
data input A
ground (0 V)
data output Y
B
1
2
3
4
5
A
GND
Y
VCC
supply voltage
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
2 of 12
NXP Semiconductors
74AHC1G02-Q100; 74AHCT1G02-Q100
2-input NOR gate
7. Functional description
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level
Inputs
Output
A
L
B
L
Y
H
L
L
L
L
H
L
H
H
H
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
20
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
IIK
input clamping current
output clamping current
output current
VI < 0.5 V
mA
mA
mA
mA
mA
C
[1]
IOK
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
20
25
75
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
75
65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For both TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74AHC1G02-Q100
74AHCT1G02-Q100
Unit
Min
Typ
Max
Min
4.5
0
Typ
Max
5.5
VCC
VI
supply voltage
input voltage
2.0
5.0
5.5
5.5
5.0
V
V
V
0
0
-
-
5.5
VO
output voltage
ambient temperature
-
VCC
+125
100
20
0
-
VCC
Tamb
t/V
40
-
+25
40
-
+25
+125 C
input transition rise
and fall rate
VCC = 3.3 V 0.3 V
VCC = 5.0 V 0.5 V
-
-
-
-
-
ns/V
ns/V
-
-
20
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
3 of 12
NXP Semiconductors
74AHC1G02-Q100; 74AHCT1G02-Q100
2-input NOR gate
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74AHC1G02-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
VI = VIH or VIL
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
4.4
2.58
3.94
2.48
3.8
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
0.1
0.1
0.1
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage VI = 5.5 V or GND;
current VCC = 0 V to 5.5 V
-
A
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
1.0
10
-
-
10
10
-
-
40
10
A
input
1.5
pF
capacitance
74AHCT1G02-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
4.4
4.5
-
-
-
4.4
3.8
-
-
4.4
-
-
V
V
IO = 8.0 mA
3.94
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
IO = 8.0 mA
V
II
input leakage VI = 5.5 V or GND;
current VCC = 0 V to 5.5 V
-
A
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
4 of 12
NXP Semiconductors
74AHC1G02-Q100; 74AHCT1G02-Q100
2-input NOR gate
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
1.0
-
10
-
40
A
ICC
additional
per input pin; VI = 3.4 V;
-
-
1.35
-
-
1.5
10
-
-
1.5
10
mA
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
CI
input
-
1.5
10
pF
capacitance
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; tr = tf = 3.0 ns. For test circuit, see Figure 6.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74AHC1G02-Q100
[1]
[2]
tpd
propagation
delay
A and B to Y;
see Figure 5
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
4.4
7.9
1.0
1.0
9.5
13
1.0
1.0
10.5
14.5
ns
ns
CL = 50 pF
6.3 11.4
[3]
[4]
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
3.2
4.6
18
5.5
7.5
-
1.0
1.0
-
6.5
8.5
-
1.0
1.0
-
7.0
9.5
-
ns
ns
pF
CL = 50 pF
CPD
power
per buffer;
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
74AHCT1G02-Q100
[1]
[3]
tpd
propagation
delay
A and B to Y;
see Figure 5
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
3.5
4.9
19
5.5
7.5
-
1.0
1.0
-
6.5
8.5
-
1.0
1.0
-
7.0
9.5
-
ns
ns
pF
CL = 50 pF
[4]
CPD
power
per buffer;
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
[1] tpd is the same as tPLH and tPHL
.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation PD (W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
5 of 12
NXP Semiconductors
74AHC1G02-Q100; 74AHCT1G02-Q100
2-input NOR gate
12. Waveforms
V
A, B input
Y output
M
t
t
PHL
PLH
V
M
mna106
Measurement points are given in Table 9.
Fig 5. The inputs (A and B) to output (Y) propagation delays
Table 9.
Type
Measurement point
Input
Output
VM
VI
VM
74AHC1G02-Q100
74AHCT1G02-Q100
GND to VCC
GND to 3.0 V
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
V
CC
V
V
O
I
PULSE
GENERATOR
DUT
C
L
R
T
mna101
Test data is given in Table 8. Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6. Test circuit for measuring switching times
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
6 of 12
NXP Semiconductors
74AHC1G02-Q100; 74AHCT1G02-Q100
2-input NOR gate
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 7. Package outline SOT353-1 (TSSOP5)
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
7 of 12
NXP Semiconductors
74AHC1G02-Q100; 74AHCT1G02-Q100
2-input NOR gate
Plastic surface-mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
1
2
3
p
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
02-04-16
06-03-16
SOT753
SC-74A
Fig 8. Package outline SOT753 (SC-74A)
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
8 of 12
NXP Semiconductors
74AHC1G02-Q100; 74AHCT1G02-Q100
2-input NOR gate
14. Abbreviations
Table 10. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20131106 Product data sheet
Change notice
Supersedes
74AHC_AHCT1G02_Q100 v.1
-
-
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
9 of 12
74AHC1G02-Q100; 74AHCT1G02-Q100
NXP Semiconductors
2-input NOR gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
16.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
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agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
10 of 12
74AHC1G02-Q100; 74AHCT1G02-Q100
NXP Semiconductors
2-input NOR gate
No offer to sell or license — Nothing in this document may be interpreted or
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Translations — A non-English (translated) version of a document is for
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between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 6 November 2013
11 of 12
74AHC1G02-Q100; 74AHCT1G02-Q100
NXP Semiconductors
2-input NOR gate
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 November 2013
Document identifier: 74AHC_AHCT1G02_Q100
相关型号:
74AHCT1G02GW-G
IC AHCT/VHCT SERIES, 2-INPUT NOR GATE, PDSO5, 1.25 MM, PLASTIC, MO-203, SOT353-1, SC-88A, TSSOP-5, Gate
NXP
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