74AHCT374D-Q100 [NXP]
AHCT/VHCT/VT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20;
| 型号： | 74AHCT374D-Q100 |
| 厂家： | 
NXP |
| 描述： | AHCT/VHCT/VT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总18页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC374-Q100;
74AHCT374-Q100
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 1 — 11 March 2014
Product data sheet
1. General description
The 74AHC374-Q100; 74AHCT374-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC374-Q100; 74AHCT374-Q100 comprises eight D-type flip-flops featuring
separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock input (CP) and an output enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D inputs that meet the set-up and
hold times requirements for the LOW-to-HIGH CP transition.
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than VCC
Common 3-state output enable input
Input levels:
For 74AHC374-Q100: CMOS level
For 74AHCT374-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AHC374-Q100
74AHC374D-Q100
40 C to +125 C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
SOT360-1
74AHC374PW-Q100 40 C to +125 C
TSSOP20 plastic thin shrink small outline package;
20 leads; body width 4.4 mm
74AHCT374-Q100
74AHCT374D-Q100
40 C to +125 C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
SOT360-1
74AHCT374PW-Q100 40 C to +125 C
TSSOP20 plastic thin shrink small outline package;
20 leads; body width 4.4 mm
4. Functional diagram
Q0
Q1
Q2
Q3
3
2
5
6
9
D0
D1
D2
D3
D4
4
7
8
FF1
to
FF8
3-STATE
OUTPUTS
13
Q4 12
Q5
14 D5
15
17
18
Q6 16
Q7 19
D6
D7
CP
OE
11
1
mna892
Fig 1. Functional diagram
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
2 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
1
EN
11
C1
11
CP
3
2
1D
3
4
2
5
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
5
6
9
7
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
OE
1
mna196
mna891
Fig 2. Logic symbol
Fig 3. IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
CP
FF7
Q
D
Q
CP
CP
FF2
CP
CP
CP
CP
CP
FF1
FF3
FF4
FF5
FF6
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Fig 4. Logic diagram
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
3 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
ꢀꢁ$+&ꢂꢀꢁꢃ4ꢄꢅꢅ
ꢀꢁ$+&7ꢂꢀꢁꢃ4ꢄꢅꢅ
ꢂ
ꢄ
ꢄꢀ
ꢂꢉ
ꢂꢈ
ꢂꢁ
ꢂꢃ
ꢂꢅ
ꢂꢇ
ꢂꢆ
ꢂꢄ
ꢂꢂ
2(
4ꢀ
9
&&
4ꢁ
'ꢁ
'ꢃ
4ꢃ
4ꢅ
'ꢅ
'ꢇ
4ꢇ
&3
ꢆ
'ꢀ
ꢇ
'ꢂ
ꢅ
4ꢂ
ꢃ
4ꢄ
ꢁ
'ꢄ
ꢈ
'ꢆ
ꢉ
4ꢆ
ꢂꢀ
*1'
DDDꢀꢁꢁꢂꢂꢁꢃ
Fig 5. Pin configuration SO20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
Q0
Pin description
Pin
1
Description
3-state output enable input (active LOW)
3-state flip-flop output
data input
2
D0
3
D1
4
data input
Q1
5
3-state flip-flop output
3-state flip-flop output
data input
Q2
6
D2
7
D3
8
data input
Q3
9
3-state flip-flop output
ground (0 V)
GND
CP
10
11
12
13
14
15
16
17
18
19
20
clock input (LOW-to-HIGH, edge triggered)
3-state flip-flop output
data input
Q4
D4
D5
data input
Q5
3-state flip-flop output
3-state flip-flop output
data input
Q6
D6
D7
data input
Q7
3-state flip-flop output
supply voltage
VCC
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
4 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
Table 3.
Function table[1]
Operating mode
Control
Input
Internal
flip-flop
Output
OE
L
CP
Dn
Q0 to Q7
Load and read register
Load register and disable outputs
l
L
L
L
h
l
H
L
H
Z
Z
H
H
h
H
[1] H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition;
= LOW-to-HIGH CP transition;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
0.5
0.5
20
20
25
-
Max
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < 0.5 V
mA
mA
mA
mA
mA
C
IOK
IO
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
ICC
IGND
Tstg
Ptot
supply current
ground current
75
65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
5 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
8. Recommended operating conditions
Table 5.
Operating conditions
Symbol Parameter
74AHC374-Q100
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
2.0
5.0
5.5
V
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
+125
100
20
V
Tamb
t/V
ambient temperature
input transition rise and fall rate
40
+25
C
ns/V
ns/V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
74AHCT374-Q100
VCC
VI
supply voltage
4.5
0
5.0
5.5
V
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
20
V
Tamb
t/V
ambient temperature
input transition rise and fall rate
40
-
+25
-
C
ns/V
VCC = 4.5 V to 5.5 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
74AHC374-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
1.9
2.9
4.4
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
IO = 4.0 mA; VCC = 3.0 V 2.58
IO = 8.0 mA; VCC = 4.5 V 3.94
VI = VIH or VIL
2.48
3.80
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
V
V
V
V
V
0.1
0.1
0.1
0.36
0.36
0.44
0.44
0.55
0.55
-
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
6 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
Max
Min
Max
Min
Max
II
input leakage VI = 5.5 V or GND;
-
-
0.1
-
1.0
-
2.0
A
current
VCC = 0 V to 5.5 V
IOZ
OFF-state
VI = VIH or VIL;
-
-
0.25
-
2.5
-
10.0 A
output current VO = VCC or GND;
VCC = 5.5 V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
4.0
10
-
-
-
-
40
10
-
-
-
-
80
10
-
A
pF
pF
input
VI = VCC or GND
3
4
capacitance
CO
output
capacitance
74AHCT374-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
IO = 8.0 mA
3.94
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
IO = 8.0 mA
V
II
input leakage VI = 5.5 V or GND;
-
A
current
VCC = 0 V to 5.5 V
IOZ
OFF-state
VI = VIH or VIL;
-
-
0.25
-
2.5
-
10.0 A
output current VO = VCC or GND per input
pin; other inputs at
VCC or GND; IO = 0 A;
VCC = 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
4.0
-
-
40
-
-
80
A
ICC
additional
per input pin;
1.35
1.5
1.5
mA
supply current VI = VCC 2.1 V; other pins
at VCC or GND; IO = 0 A;
VCC = 4.5 V to 5.5 V
CI
input
capacitance
VI = VCC or GND
-
-
3
4
10
-
-
-
10
-
-
-
10
-
pF
pF
CO
output
capacitance
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
7 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
74AHC374-Q100
[2]
tpd
propagation CP to Qn; see Figure 6 and
delay Figure 8
VCC = 3.0 V to 3.6 V
CL = 15 pF
CL = 50 pF
-
-
6.4 12.7
8.4 16.2
1.0
1.0
15.0
18.5
1.0
1.0
16.0
20.5
ns
ns
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.4
8.1
1.0
1.0
9.5
1.0
1.0
10.0
12.5
ns
ns
CL = 50 pF
5.7 10.1
11.5
[3]
ten
enable time OE to Qn; see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.5 11.0
7.3 14.5
1.0
1.0
13.0
16.5
1.0
1.0
14.0
18.0
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.9
5.2
7.6
9.6
1.0
1.0
9.0
1.0
1.0
9.5
ns
ns
CL = 50 pF
11.0
12.0
[4]
tdis
disable time OE to Qn; see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.6 10.5
9.4 14.0
1.0
1.0
12.5
16.0
1.0
1.0
13.0
17.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.2
6.4
6.8
8.8
1.0
1.0
8.0
1.0
1.0
8.5
ns
ns
CL = 50 pF
10.0
11.0
fmax
maximum
frequency
see Figure 6
VCC = 3.0 V to 3.6 V
CL = 15 pF
80
55
130
85
-
-
70
50
-
-
70
50
-
-
MHz
MHz
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
130
85
185
120
-
-
110
75
-
-
110
75
-
-
MHz
MHz
CL = 50 pF
tW
pulse width CP HIGH or LOW;
see Figure 6
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
5.0
5.0
-
-
-
-
5.5
5.0
-
-
5.5
5.0
-
-
ns
ns
tsu
set-up time Dn to CP; see Figure 8
VCC = 3.0 V to 3.6 V
4.5
3.0
-
-
-
-
4.0
3.0
-
-
4.0
3.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
8 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
th
hold time
Dn to CP; see Figure 8
VCC = 3.0 V to 3.6 V
2.0
2.0
-
-
-
-
-
-
2.0
2.0
-
-
-
-
2.0
2.0
-
-
-
-
ns
ns
pF
VCC = 4.5 V to 5.5 V
[5]
[2]
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
10
74AHCT374-Q100; VCC = 4.5 V to 5.5 V
tpd
propagation CP to Qn; see Figure 6 and
delay Figure 8
CL = 15 pF
CL = 50 pF
-
-
4.3
9.4
1.0
1.0
10.5
11.5
1.0
1.0
12.0
13.0
ns
ns
5.6 10.4
[3]
[4]
ten
enable time OE to Qn; see Figure 7
CL = 15 pF
-
-
3.5 10.2
4.8 11.2
1.0
1.0
11.5
12.5
1.0
1.0
13.0
14.0
ns
ns
CL = 50 pF
tdis
fmax
tW
disable time OE to Qn; see Figure 7
CL = 15 pF
-
-
3.6 10.2
5.7 11.2
1.0
1.0
11.0
12.0
1.0
1.0
13.0
14.0
ns
ns
CL = 50 pF
maximum
frequency
see Figure 6
CL = 15 pF
CL = 50 pF
90
85
140
130
-
-
-
-
80
75
-
-
-
80
75
-
-
-
MHz
MHz
ns
pulse width CP HIGH or LOW;
see Figure 6
6.5
6.5
6.5
tsu
th
set-up time Dn to CP; see Figure 8
2.5
2.5
-
-
-
-
-
-
2.5
2.5
-
-
-
-
2.5
2.5
-
-
-
-
ns
ns
pF
hold time
Dn to CP; see Figure 8
[5]
CPD
power
fi = 1 MHz; VI = GND to VCC
12
dissipation
capacitance
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
[3] en is the same as tPZH and tPZL
[4] tdis is the same as tPHZ and tPLZ
[5] PD is used to determine the dynamic power dissipation (PD in W).
.
t
.
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
9 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
10.1 Waveforms
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Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Enable and disable times
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
10 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
Dn input
M
GND
V
OH
V
Qn output
M
V
OL
mna202
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Data set-up and hold times
Table 8.
Type
Measurement points
Input
Output
VM
VM
VX
VY
74AHC374-Q100
74AHCT374-Q100
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
VOL + 0.3 V
VOL + 0.3 V
VOH 0.3 V
VOH 0.3 V
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
11 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
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Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
S1 = test selection switch.
Fig 9. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
CL
RL
74AHC374-Q100
74AHCT374-Q100
VCC
3.0 V
3.0 ns
3.0 ns
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
open
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
12 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
11. Package outline
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Fig 10. Package outline SOT163-1 (SO20)
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
13 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
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Fig 11. Package outline SOT360-1 (TSSOP20)
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
14 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
LSTTL
MIL
Low-power Schottky Transistor-Transistor Logic
Military
MM
Machine Model
13. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC_AHCT374_Q100 v.1 20140311
Product data sheet
-
-
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
15 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
14.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
16 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 11 March 2014
17 of 18
74AHC374-Q100; 74AHCT374-Q100
NXP Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
16. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
10.1
11
12
13
14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
14.1
14.2
14.3
14.4
15
16
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 March 2014
Document identifier: 74AHC_AHCT374_Q100
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