74AHCT595PW [NXP]
8-bit serial-in/serial or parallel-out shift register with output latches; 3-state; 8位串行输入/串行或并行输出移位寄存器与输出锁存器;三态
| 型号： | 74AHCT595PW |
| 厂家： | 
NXP |
| 描述： | 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state |
| 文件： | 总20页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AHC595; 74AHCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
Product specification
2000 Mar 15
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
FEATURES
DESCRIPTION
• ESD protection:
The 74AHC/AHCT595 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
The 74AHC/AHCT595 is an 8-stage serial shift register
with a storage register and 3-state outputs. The shift
register has separate clocks.
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than VCC
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and from−40 to +125 °C.
Data is shifted on the positive-going transitions of the
SHCP input. The data in each register is transferred to the
storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
APPLICATIONS
The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
• Serial-to-parallel data conversion
• Remote control holding register.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
CL = 15 pF; VCC = 5 V
UNIT
AHC AHCT
tPHL/tPLH
SHCP to Q7’
4.0
3.8
4.0
4.6
3.0
170
190
ns
STCP to Qn
4.2
4.4
3.0
170
ns
MR to Q7’
ns
CI
input capacitance
maximum clock frequency
power dissipation capacitance
pF
fmax
CPD
MHz
pF
CL = 50 pF; f = 1 MHz; notes 1, 2 and 3 180
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC
3. All 9 outputs switching.
.
2000 Mar 15
2
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
FUNCTION TABLE
See note 1.
INPUT
OE
OUTPUT
FUNCTION
SHCP STCP
MR
DS
Q7’
Qn
X
X
X
X
↑
L
L
L
L
L
X
X
X
L
L
L
NC
L
a LOW level on MR only affects the shift registers
empty shift register loaded into storage register
X
H
Z
shift register clear. Parallel outputs in high impedance
OFF-state.
↑
X
L
H
H
Q6’
NC
logic HIGH level shifted into shift register stage 0.
Contents of all shift register stages shifted through, e.g.
previous state of stage 6 (internal Q6’) appears on the
serial output (Q7’).
X
↑
↑
L
L
H
H
X
X
NC
Q6’
Qn’
Qn’
contents of shift register stages (internal Qn’) are
transferred to the storage register and parallel output
stages
↑
contents of shift register shifted through. Previous
contents of the shift register is transferred to the storage
register and the parallel output stages.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH transition;
↓ = HIGH-to-LOW transition;
X = don’t care;
NC = no change;
Z = high impedance OFF-state.
ORDERING INFORMATION
TYPE NUMBER
PACKAGES
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74AHC595D
−40 to +125 °C
16
16
16
16
SO
plastic
plastic
plastic
plastic
SOT109-1
SOT403-1
SOT109-1
SOT403-1
74AHC595PW
74AHCT595D
74AHCT595PW
TSSOP
SO
TSSOP
2000 Mar 15
3
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
PINNING
PIN
SYMBOL
DESCRIPTION
1, 2, 3, 4, 5, 6, 7 and 15
Q1, Q2, Q3, Q4, Q5, Q6, Q7 and Q0
parallel data output
8
GND
Q7’
ground (0 V)
9
serial data output
10
11
12
13
14
16
MR
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
SHCP
STCP
OE
DS
VCC
DC supply voltage
handbook, halfpage
11
12
handbook, halfpage
SH
ST
V
Q
CP
1
2
3
4
5
6
7
8
16
15
14
CP
CC
1
9
15
1
Q '
7
Q
Q
Q
D
2
3
0
Q
0
S
Q
1
2
Q
2
Q
13 OE
4
14
3
595
Q
3
D
S
12
11
10
9
ST
Q
Q
Q
CP
5
6
7
4
Q
4
5
SH
CP
Q
5
6
Q
6
MR
7
Q
7
Q '
7
GND
MR
10
OE
13
MNA551
MNA552
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2000 Mar 15
4
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
13
handbook, halfpage
EN3
C2
12
handbook, halfpage
D
14
S
10
11
SRG8
R
SH
CP
11
8-STAGE SHIFT REGISTER
C1/
MR
10
12
Q '
9
7
14
15
1
1D
2D
3
ST
CP
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
2
3
4
13
OE
5
6
Q
4
Q
6
Q
2
Q
3
Q
5
Q
Q
1
Q
7
7
4
6
2
3
5
0
1
7
9
15
MNA554
MNA553
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
STAGE 0
STAGES 1 TO 6
STAGE 7
D
S
Q '
7
D
Q
D
Q
D
Q
FF7
CP
FF0
CP
R
R
SH
CP
MR
D
Q
D
Q
LATCH
CP
LATCH
CP
ST
CP
OE
MNA555
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
Fig.5 Logic diagram.
5
2000 Mar 15
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
SH
CP
D
S
ST
CP
MR
OE
Z-state
Q
0
Z-state
Q
1
Z-state
Z-state
Q
6
Q
7
Q ’
7
MNA556
Fig.6 Timing diagram.
2000 Mar 15
6
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
RECOMMENDED OPERATING CONDITIONS
74AHC
74AHCT
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
VCC
VI
2.0
0
5.0
−
5.5
4.5
0
5.0
−
5.5
V
input voltage
5.5
5.5
V
VO
output voltage
0
−
VCC
+85
0
−
VCC
+85
V
Tamb
operating ambient temperature see DC and AC
−40
−40
+25
+25
−40
+25
+25
°C
characteristics per
device
+125 −40
+125 °C
tr, tf
input rise and fall ratios (∆t/∆V) VCC = 3.3 ±0.3 V
VCC = 5 ±0.5 V
−
−
−
−
100
20
−
−
−
−
−
ns/V
ns/V
20
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
VI
−0.5 +7.0
−0.5 +7.0
V
input voltage
V
IIK
DC input diode current
VI < −0.5 V; note 1
−
−
−20
±20
mA
mA
IOK
DC output clamping diode
current
−0.5 > VO > VCC + 0.5 V; note 1
IO
DC output sink current
DC VCC or GND current
storage temperature
−0.5 < VO < VCC + 0.5 V
−
±25
±75
mA
mA
ICC
Tstg
PD
−
−65
−
+150 °C
500 mW
power dissipation per package for temperature range: −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
2000 Mar 15
7
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
DC CHARACTERISTICS
74AHC family
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS Tamb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
25
OTHER
VCC (V)
VIH
HIGH-level input
voltage
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
1.5
2.1
3.85
−
−
−
1.5
2.1
3.85
−
−
1.5
2.1
3.85
−
−
V
V
V
V
V
V
V
V
V
V
−
−
−
−
−
−
−
−
VIL
LOW-level input
voltage
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
−
−
−
−
−
−
−
−
VOH
HIGH-level output VI = VIH or VIL;
voltage
1.9
2.9
4.4
2.58
2.0
3.0
4.5
−
1.9
2.9
4.4
2.48
1.9
2.9
4.4
2.40
IO = −50 µA
−
−
−
−
−
−
VI = VIH or VIL;
−
−
−
IO = −4.0 mA
VI = VIH or VIL;
4.5
3.94
−
−
3.8
−
3.70
−
V
IO = −8.0 mA
VOL
LOW-level output VI = VIH or VIL;
2.0
3.0
4.5
3.0
−
−
−
−
0
0
0
−
0.1
0.1
0.1
0.36
−
−
−
−
0.1
0.1
0.1
0.44
−
−
−
−
0.1
0.1
0.1
0.55
V
V
V
V
voltage
IO = 50 µA
VI = VIH or VIL;
IO = 4.0 mA
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
−
−
−
−
−
−
−
3
0.36
0.1
−
−
0.44
1.0
±2.5
40
−
−
−
−
−
0.55
2.0
V
II
input leakage
current
VI = VCC or GND 5.5
µA
IOZ
ICC
CI
3-state output
VI = VIH or VIL; 5.5
OFF-state current VO = VCC or GND
±0.25 −
±10.0 µA
quiescent supply VI = VCC or GND; 5.5
4.0
10
−
−
80
10
µA
current
IO = 0
input capacitance
−
10
pF
2000 Mar 15
8
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
74AHCT family
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
OTHER VCC (V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
VIL
HIGH-level input
voltage
4.5 to 5.5 2.0
−
−
2.0
−
2.0
−
V
LOW-level input
voltage
4.5 to 5.5 −
−
0.8
−
−
0.8
−
−
0.8
−
V
VOH
HIGH-level output VI = VIH or VIL;
voltage
4.5
4.5
4.5
4.5
5.5
5.5
4.4 4.5
4.4
3.8
−
4.4
3.70
−
V
IO = −50 µA
VI = VIH or VIL;
IO = −8.0 mA
3.94
−
0
−
−
−
−
−
−
V
VOL
LOW-level output VI = VIH or VIL;
voltage
−
−
−
−
0.1
0.36
0.1
0.1
0.44
1.0
±2.5
0.1
0.55
2.0
V
IO = 50 µA
VI = VIH or VIL;
IO = 8.0 mA
−
−
V
II
input leakage
current
VI = VIH or VIL
−
−
µA
IOZ
3-state output
VI = VIH or VIL;
±0.25 −
−
±10.0 µA
OFF-state current VO = VCC or GND
per input pin;
other inputs at
VCC or GND;
IO = 0
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
−
4.0
−
−
40
−
−
80
µA
∆ICC
additional
VI = VCC − 2.1 V 4.5 to 5.5 −
1.35
1.5
1.5
mA
quiescent supply
current per input
pin
other inputs at
VCC or GND;
IO = 0
CI
input capacitance
−
−
3
10
−
10
−
10
pF
2000 Mar 15
9
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
AC CHARACTERISTICS
Type 74AHC595
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85
−40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH propagation delay
SHCP to Q7’
see Figs 7
and 12
15 pF −
5.7
5.9
5.9
5.6
5.4
7.7
7.7
7.4
7.4
8.7
−
13.0
11.9
12.8
11.5
11.0
16.5
15.4
16.3
15.0
15.7
−
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.0
5.0
5.0
3.5
8.5
1.5
3.0
60
15.0
13.5
13.7
13.5
13.0
18.5
17.0
17.2
17.0
16.2
−
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.0
5.0
5.0
3.5
8.5
1.5
3.0
40
16.5
15.0
15.0
15.0
14.5
20.1
18.5
18.7
18.5
17.5
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
propagation delay
STCP to Qn
see Figs 8
and 12
−
tPHL
propagation delay
MR to Q7’
see Figs 10
and 12
−
t
t
t
PZH/tPZL 3-state output enable see Figs 11
−
time OE to Qn
and 12
PHZ/tPLZ 3-state output disable
time OE to Qn
−
PHL/tPLH propagation delay
SHCP to Q7’
see Figs 7
and 12
50 pF −
propagation delay
STCP to Qn
see Figs 8
and 12
−
−
−
−
tPHL
propagation delay
MR to Q7’
see Figs 10
and 12
tPZH/tPZL 3-state output enable see Figs 11
time OE to Qn
and 12
t
PHZ/tPLZ 3-state output disable
time OE to Qn
tW
shift clock pulse width see Figs 7
5.0
HIGH or LOW
and 12
storage clock pulse
width HIGH or LOW
see Figs 8
and 12
5.0
5.0
3.5
8.5
1.5
3.0
80
−
−
−
−
master reset pulse
width LOW
see Figs 10
and 12
−
−
−
−
tsu
set-up time
DS to SHCP
see Figs 8
and 12
−
−
−
−
set-up time
SHCP to STCP
see Figs 9
and 12
−
−
−
−
th
hold time
−
−
−
−
DS to SHCP
trem
fmax
removal time
MR to SHCP
see Figs 10
and 12
−
−
−
−
maximum clock pulse see Figs 7, 8
125
−
−
−
frequency
and 12
SHCP or STCP
2000 Mar 15
10
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85
−40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH propagation delay
SHCP to Q7’
see Figs 7
and 12
15 pF −
4.0
4.2
4.4
4.0
3.8
5.4
5.5
5.6
5.3
5.8
−
8.2
7.4
8.0
8.6
8.0
10.0
9.0
10.0
10.6
10.3
−
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.0
5.0
5.0
3.0
5.0
2.0
2.5
110
9.4
8.5
9.1
10.0
9.5
11.4
10.5
11.1
12.0
11.0
−
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.0
5.0
5.0
3.0
5.0
2.0
2.5
90
10.5
9.5
10.0
11.0
10.5
12.5
11.5
12.0
13.0
12.0
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
propagation delay
STCP to Qn
see Figs 8
and 12
−
tPHL
propagation delay
MR to Q7’
see Figs 10
and 12
−
t
t
t
PZH/tPZL 3-state output enable see Figs 11
−
time OE to Qn
and 12
PHZ/tPLZ 3-state output disable
time OE to Qn
−
PHL/tPLH propagation delay
SHCP to Q7’
see Figs 7
and 12
50 pF −
propagation delay
STCP to Qn
see Figs 8
and 12
−
−
−
−
tPHL
propagation delay
MR to Q7’
see Figs 10
and 12
tPZH/tPZL 3-state output enable see Figs 11
time OE to Qn and 12
tPHZ/tPLZ 3-state output disable
time OE to Qn
tW
shift clock pulse width see Figs 7
5.0
HIGH or LOW
and 12
storage clock pulse
width HIGH or LOW
see Figs 8
and 12
5.0
5.0
3.0
5.0
2.0
2.5
−
−
−
−
master reset pulse
width LOW
see Figs 10
and 12
−
−
−
−
tsu
set-up time
DS to SHCP
see Figs 8
and 12
−
−
−
−
set-up time
SHCP to STCP
see Figs 9
and 12
−
−
−
−
th
hold time
−
−
−
−
DS to SHCP
trem
fmax
removal time
MR to SHCP
see Figs 10
and 12
−
−
−
−
maximum clock pulse see Figs 7, 8
130 170
−
−
−
frequency
and 12
SHCP or STCP
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
2000 Mar 15
11
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
Type 74AHCT595
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85
−40 to +125 UNIT
WAVEFORMS CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH propagation delay
SHCP to Q7’
see Figs 7
and 12
15 pF −
3.8
4.0
4.6
4.8
3.6
5.2
5.3
5.8
6.2
5.8
−
8.2
7.4
8.2
9.0
6.9
10.0
9.0
10.5
11.6
10.3
−
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.0
5.0
5.0
5.0
3.0
2.0
3.0
110
9.0
8.5
9.5
11.0
8.0
11.0
10.5
11.5
13.0
11.0
−
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.0
5.0
5.0
5.0
3.0
2.0
3.0
90
10.0
9.5
10.5
12.0
9.0
12.0
11.5
12.5
14.5
12.0
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
propagation delay
STCP to Qn
see Figs 8
and 12
−
tPHL
propagation delay
MR to Q7’
see Figs 10
and 12
−
tPZH/tPZL 3-state output enable see Figs 11
−
time OE to Qn
and 12
tPHZ/tPLZ 3-state output disable
time OE to Qn
−
tPHL/tPLH propagation delay
see Figs 7
and 12
50 pF −
SHCP to Q7’
propagation delay
STCP to Qn
see Figs 8
and 12
−
−
−
−
tPHL
propagation delay
MR to Q7’
see Figs 10
and 12
tPZH/tPZL 3-state output enable see Figs 11
time OE to Qn
and 12
tPHZ/tPLZ 3-state output disable
time OE to Qn
tW
shift clock pulse width see Figs 7
5.0
HIGH or LOW
and 12
storage clock pulse
width HIGH or LOW
see Figs 8
and 12
5.0
5.0
5.0
3.0
2.0
3.0
−
−
−
−
master reset pulse
width LOW
see Figs 10
and 12
−
−
−
−
tsu
set-up time
see Figs 8
and 12
−
−
−
−
SHCP to STCP
set-up time
DS to SHCP
see Figs 9
and 12
−
−
−
−
th
hold time
−
−
−
−
DS to SHCP
trem
fmax
removal time
MR to SHCP
see Figs 10
and 12
−
−
−
−
maximum clock pulse see Figs 7, 8
130 170
−
−
−
frequency
and 12
SHCP or STCP
Note
1. Typical values at VCC = 5.0 V.
2000 Mar 15
12
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
AC WAVEFORMS
1/f
max
V
I
(1)
t
SH
CP
input
V
M
t
GND
W
t
PHL
PLH
V
OH
(2)
V
Q ' output
7
M
V
OL
MNA557
(1)
(2)
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
GND to VCC 50% VCC 50% VCC
GND to 3.0 V 1.5 V 50% VCC
AHC
AHCT
Fig.7 The clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width (tW) and maximum shift
clock frequency (fmax).
V
I
(1)
SH
input
V
CP
CP
M
t
GND
1/f
max
su
V
I
(1)
t
ST
input
V
M
GND
W
t
t
PHL
PLH
V
OH
(2)
V
Q
output
M
n
V
OL
MNA558
(1)
(2)
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
AHC
GND to VCC 50% VCC 50% VCC
GND to 3.0 V 1.5 V 50% VCC
AHCT
Fig.8 The storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width (tW) and the
shift clock to storage clock set-up time (tsu).
2000 Mar 15
13
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
V
I
(1)
V
SH
CP
input
M
GND
t
t
su
su
t
t
h
h
V
I
(1)
V
D
input
M
S
GND
V
OH
(2)
V
Q ' output
M
7
V
OL
MNA560
(1)
(2)
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
GND to VCC 50% VCC 50% VCC
GND to 3.0 V 1.5 V 50% VCC
AHC
The shaded areas indicate when the input is permitted to change for
predictable output performance.
AHCT
Fig.9 The data set-up (tsu) and hold (th) times for the DS input.
V
I
(1)
V
MR input
M
GND
t
t
W
rem
V
I
(1)
SH
input
V
CP
M
GND
t
PHL
V
OH
(2)
M
V
Q ' output
7
V
OL
MNA561
(1)
(2)
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
GND to VCC 50% VCC 50% VCC
GND to 3.0 V 1.5 V 50% VCC
AHC
AHCT
Fig.10 The master reset (MR) pulse width, the master reset to output (Q7’) propagation delays and the master
reset to shift clock (SHCP) removal time (trem).
2000 Mar 15
14
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
V
I
(1)
t
V
OE input
M
GND
t
PLZ
PZL
V
CC
output
LOW-to-OFF
OFF-to-LOW
(2)
V
M
V
+ 0.3 V
V
OL
V
OL
t
t
PHZ
PZH
V
OH
− 0.3 V
OH
output
(2)
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA450
(1)
(2)
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
GND to VCC 50% VCC 50% VCC
GND to 3.0 V 1.5 V 50% VCC
AHC
AHCT
Fig.11 3-state enable and disable times.
S1
V
CC
open
V
CC
GND
1000 Ω
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
R
L
T
MNA219
TEST
S1
t
PLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
open
VCC
Definitions for test circuit.
CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”).
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
GND
Fig.12 Load circuitry for switching times.
15
2000 Mar 15
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-05-22
99-12-27
SOT109-1
076E07
MS-012
2000 Mar 15
16
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-04-04
99-12-27
SOT403-1
MO-153
2000 Mar 15
17
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Mar 15
18
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
REFLOW(1)
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
not suitable
suitable
suitable
suitable
suitable
suitable
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Mar 15
19
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
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Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
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Norway: Box 1, Manglerud 0612, OSLO,
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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
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Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
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Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
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Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
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South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
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France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
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Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
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Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
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209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
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Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613507/01/pp20
Date of release: 2000 Mar 15
Document order number: 9397 750 06822
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