74AHCU04BQ [NXP]
Hex inverter; 六反相器
| 型号： | 74AHCU04BQ |
| 厂家： | 
NXP |
| 描述： | Hex inverter |
| 文件： | 总14页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHCU04
Hex inverter
Rev. 03 — 14 November 2007
Product data sheet
1. General description
The 74AHCU04 is high-speed Si-gate CMOS devices and is pin compatible with low
power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.
The 74AHCU04 is a general purpose hex inverter. Each of the six inverters is a single
stage.
2. Features
■ Low power dissipation
■ Balanced propagation delays
■ Inputs accepts voltages higher than VCC
■ ESD protection:
◆ HBM JESD22-A114E: exceeds 2000 V
◆ MM JESD22-A115-A: exceeds 200 V
◆ CDM JESD22-C101C: exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74AHCU04D
−40 °C to +125 °C SO14
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74AHCU04PW −40 °C to +125 °C TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74AHCU04BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1
quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
74AHCU04
NXP Semiconductors
Hex inverter
4. Functional diagram
1
1
1
1
1
1
1
3
2
1Y
2Y
3Y
4Y
5Y
6Y
1A
2A
3A
4A
5A
6A
2
4
1
3
4
5
6
6
5
9
8
8
9
10
12
11
13
11
13
10
12
A
Y
mna343
mna045
mna342
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one inverter)
5. Pinning information
terminal 1
index area
2
3
4
5
6
13
12
11
10
9
1Y
6A
6Y
5A
5Y
4A
1
2
3
4
5
6
7
14
2A
2Y
3A
3Y
1A
1Y
V
CC
13
12
11
10
9
6A
6Y
5A
5Y
4A
4Y
04
2A
(1)
GND
2Y
04
3A
3Y
001aac442
GND
8
Transparent top view
001aac441
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It can not be
used as a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
5.1 Pin description
Table 2.
Symbol
1A
Pin description
Pin
1
Description
data input
1Y
2
data output
data input
2A
3
2Y
4
data output
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
2 of 14
74AHCU04
NXP Semiconductors
Hex inverter
Table 2.
Symbol
3A
Pin description …continued
Pin
5
Description
data input
3Y
6
data output
ground (0 V)
data output
data input
GND
4Y
7
8
4A
9
5Y
10
11
12
13
14
data output
data input
5A
6Y
data output
data input
6A
VCC
supply voltage
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level
Input
nA
L
Output
nY
H
H
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−20
−0.5
-
Max
+7.0
-
Unit
V
supply voltage
input clamping current
input voltage
VI < −0.5 V
mA
V
[1]
VI
+7.0
±20
±25
75
IOK
output clamping current
output current
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
mA
mA
mA
mA
°C
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−75
−65
-
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
3 of 14
74AHCU04
NXP Semiconductors
Hex inverter
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
Min
2.0
0
Typ
Max
5.5
Unit
V
VCC
VI
supply voltage
5.0
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
100
20
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
−40
-
+25
°C
-
-
ns/V
ns/V
-
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
1.7
2.4
4.4
-
Max
-
Min
1.7
2.4
4.4
-
Max
-
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.7
2.4
4.4
-
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 3.0 V
-
-
-
VCC = 5.5 V
-
-
-
VIL
LOW-level
input voltage
VCC = 2.0 V
0.3
0.6
1.1
0.3
0.6
1.1
0.3
0.6
1.1
VCC = 3.0 V
-
-
-
VCC = 5.5 V
-
-
-
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
1.8
2.7
4.0
2.0
3.0
4.5
-
-
-
-
-
-
1.8
2.7
-
-
-
-
-
1.8
2.7
4.0
2.4
3.7
-
-
-
-
-
V
V
V
V
V
4.0
IO = −4.0 mA; VCC = 3.0 V 2.58
IO = −8.0 mA; VCC = 4.5 V 3.94
VI = VIH or VIL
2.48
3.8
-
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.2
0.3
-
-
-
-
-
-
0.2
0.3
-
-
-
-
-
-
0.2
0.3
V
V
0.5
0.5
0.5
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
µA
V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
2.0
10
-
-
20
10
-
-
40
10
µA
V
input
3
pF
capacitance
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
4 of 14
74AHCU04
NXP Semiconductors
Hex inverter
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
[1]
[2]
tpd
propagation
delay
nA to nY; see Figure 6
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
3.0
7.1
1.0
1.0
8.5
1.0
1.0
9.0
ns
ns
CL = 50 pF
3.4 10.6
12.0
13.5
[3]
[4]
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
2.4
3.5
9.1
5.5
7.0
-
1.0
1.0
-
6.5
8.0
-
1.0
1.0
-
7.0
9.0
-
ns
ns
pF
CL = 50 pF
CPD
power
dissipation
capacitance
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[1] tpd is the same as tPLH and tPHL
.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
11. Waveforms
V
I
V
V
M
nA input
M
V
CC
GND
V
V
O
I
t
t
PHL
PLH
PULSE
GENERATOR
DUT
V
OH
C
50 pF
L
R
T
V
V
M
nY output
M
V
OL
mna344
mna034
VM = 0.5 × VCC; VI = GND to VCC
.
Test data is given in Table 7.
Definitions for test circuit:
CL = Load capacitance including jig and probe
capacitance.
RT = Termination resistance should be equal to
output impedance Zo of the pulse generator.
Fig 6. The input (nA) to output (nY) propagation delay
times
Fig 7. Load circuit for switching times
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
5 of 14
74AHCU04
NXP Semiconductors
Hex inverter
12. Typical transfer characteristics
mna352
6
mna353
2
700
I
4
3
2
1
0
V
O
V
(V)
V
O
(V)
I
O
CC
CC
(µA)
(mA)
V
O
1.5
1
500
4
I
I
CC
CC
300
2
0.5
0
100
0
0
−100
−2
0
1
2
3
0
0.5
1
1.5
2
V (V)
V (V)
i
i
Tamb = 25 °C.
Tamb = 25 °C.
Fig 8. VCC = 2.0 V; IO = 0 A
Fig 9. VCC = 3.0 V; IO = 0 A
mna351
8
30
V
I
CC
O
(V)
(mA)
6
4
2
0
20
R
= 560 kΩ
bias
10
0
V
CC
I
CC
0.47 µF
100 µF
input
output
V
O
V
I
A
I
O
(f = 1 kHz)
−10
GND
mna050
0
2
4
6
V (V)
i
Tamb = 25 °C.
∆Io
g fs
=
---------
∆Vi
fi = 1 kHz at VO is constant
Fig 10. VCC = 5.5 V; IO = 0 A
Fig 11. Test set-up for measuring forward
transconductance
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
6 of 14
74AHCU04
NXP Semiconductors
Hex inverter
mna355
40
g
fs
(mA/V)
30
20
10
0
0
2
4
6
V
(V)
CC
Tamb = 25 °C.
Fig 12. Typical forward transconductance as a function of the supply voltage
13. Application information
Some applications are:
• Linear amplifier (see Figure 13)
• In crystal oscillator design (see Figure 14)
Remark: All values given are typical unless otherwise specified.
R2
R1
V
CC
R2
1 µF
R1
U04
U04
C1
C2
Z
L
out
mna052
mna053
Maximum Vo(p-p) = VCC − 1.5 V centered at
0.5 × VCC
C1 = 47 pF (typical)
C2 = 33 pF (typical)
.
Gol
---------------------------------------
R1
R1 = 1 MΩ to 10 MΩ (typical
Gv = –
R2 optimum value depends on the frequency and
required stability against changes in VCC or average
minimum ICC (ICC is typically 5 mA at VCC = 5 V and
fi = 10 MHz).
1 +
(1 + G )
ol
------
R2
Gol = open loop gain
Gv = voltage gain
R1 ≥ 3 kΩ, R2 ≤ 1 MΩ
ZL > 10 kΩ; Gol = 12 (typical)
Typical unity gain bandwidth product is 5 MHz.
Fig 13. Used as a linear amplifier
Fig 14. Crystal oscillator configuration
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
7 of 14
74AHCU04
NXP Semiconductors
Hex inverter
Table 8.
External components for resonator (f < 1 MHz)
All values given are typical and must be used as an initial set-up.
Frequency
R1
R2
C1
C2
10 kHz to 15.9 kHz
16 kHz to 24.9 kHz
25 kHz to 54.9 kHz
55 kHz to 129.9 kHz
130 kHz to 199.9 kHz
200 kHz to 349.9 kHz
350 kHz to 600 kHz
22 MΩ
22 MΩ
22 MΩ
22 MΩ
22 MΩ
10 MΩ
10 MΩ
220 kΩ
220 kΩ
100 kΩ
100 kΩ
47 kΩ
47 kΩ
47 kΩ
56 pF
56 pF
56 pF
47 pF
47 pF
47 pF
47 pF
20 pF
10 pF
10 pF
5 pF
5 pF
5 pF
5 pF
Table 9.
Frequency
3 kHz
Optimum value for R2
R2
Optimum for
minimum required ICC
2.0 kΩ
8.0 kΩ
1.0 kΩ
4.7 kΩ
0.5 kΩ
2.0 kΩ
0.5 kΩ
1.0 kΩ
-
minimum influence due to change in VCC
minimum required ICC
6 kHz
minimum influence by VCC
minimum required ICC
10 kHz
14 kHz
>14 kHz
minimum influence by VCC
minimum required ICC
minimum influence by VCC
replace R2 by C3 with a typical value of 35 pF
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
8 of 14
74AHCU04
NXP Semiconductors
Hex inverter
14. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 15. Package outline SOT108-1 (SO14)
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
9 of 14
74AHCU04
NXP Semiconductors
Hex inverter
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 16. Package outline SOT402-1 (TSSOP14)
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
10 of 14
74AHCU04
NXP Semiconductors
Hex inverter
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 17. Package outline SOT762-1 (DHVQFN14)
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
11 of 14
74AHCU04
NXP Semiconductors
Hex inverter
15. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
LSTTL
ESD
Description
Complementary Metal Oxide Semiconductor
Low-power Schottky Transistor-Transistor Logic
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
CDM
Charge Device Model
TTL
Transistor-Transistor Logic
16. Revision history
Table 11. Revision history
Document ID
74AHCU04_3
Modifications:
Release date
20071114
Data sheet status
Change notice
Supersedes
Product data sheet
-
74AHCU04_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 3: DHVQFN14 package added.
• Section 8: derating values added for DHVQFN14 package.
• Section 14: outline drawing added for DHVQFN14 package.
74AHCU04_2
74AHCU04_1
19990927
Product specification
-
74AHCU04_1
-
19990226
Product specification
-
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
12 of 14
74AHCU04
NXP Semiconductors
Hex inverter
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
17.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
13 of 14
74AHCU04
NXP Semiconductors
Hex inverter
19. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical transfer characteristics . . . . . . . . . . . . 6
Application information. . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
3
4
5
5.1
6
7
8
9
10
11
12
13
14
15
16
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 November 2007
Document identifier: 74AHCU04_3
相关型号：
74AHCU04D-T
IC AHC/VHC/H/U/V SERIES, HEX 1-INPUT INVERT GATE, PDSO14, 3.90 MM, PLASTIC, MS-12, SOT108-1, SOP-14, Gate
NXP
74AHCU04PW-T
IC AHC/VHC/H/U/V SERIES, HEX 1-INPUT INVERT GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14, Gate
NXP
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