74ALS112 [NXP]
Dual J-K negative edge-triggered flip-flop; 双J-K·负边沿触发的触发器
| 型号： | 74ALS112 |
| 厂家： | 
NXP |
| 描述： | Dual J-K negative edge-triggered flip-flop |
| 文件： | 总10页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ALS112A
Dual J-K negative edge-triggered flip-flop
Product specification
IC05 Data Handbook
1996 June 27
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
DESCRIPTION
PIN CONFIGURATION
The 74ALS112A, dual negative edge-triggered JK-type flip-flop
features individual J, K, clock (CPn), set (SD), and reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
CP0
K0
1
2
3
4
5
16
V
CC
15 RD0
14 RD1
13 CP1
12 K1
The SD and RD inputs, when Low, set or reset the outputs as shown
in the function table regardless of the level at the other inputs.
J0
SD0
Q0
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and the flip-flop will perform
according to the function table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
Q0
Q1
6
7
8
11 J1
10 SD1
GND
9
Q1
SF00103
TYPICAL
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
f
MAX
ORDERING INFORMATION
74ALS112A
50MHz
3.0mA
ORDER CODE
DRAWING
NUMBER
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
16-pin plastic DIP
16-pin plastic SO
74ALS112AN
74ALS112AD
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74ALS (U.L.)
LOAD VALUE
PINS
DESCRIPTION
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/2.0
1.0/2.0
1.0/2.0
20/80
HIGH/LOW
20µA/0.1mA
20µA/0.2mA
20µA/0.2mA
20µA/0.2mA
20µA/0.2mA
0.4mA/8mA
CP0, CP1
J0, J1
Clock Pulse input (active falling edge)
J inputs
K0, K1
K inputs
SD0, SD1
RD0, RD1
Q0, Q1, Q0, Q1
Set inputs (active-Low)
Reset inputs (active-Low)
Data outputs
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
3
11
2 12
5
6
3
1J
C1
1
2
J0 J1 K0 K1
CP0
1K
R
1
4
15
4
SD0
RD0
CP1
SD1
RD1
15
13
10
14
S
11
2J
9
7
13
12
C2
Q0 Q0 Q1 Q1
2K
R
14
10
S
5
6
9
7
V
= Pin 16
CC
GND = Pin 8
SF00105
SF00104
2
1996 Jun 27
853-1846 16995
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
LOGIC DIAGRAM
5, 9
Qn
6, 7
Qn
4, 10
SDn
15, 14
3, 11
RDn
Jn
2, 12
Kn
1, 13
CPn
V
= Pin 16
CC
GND = Pin 8
SF00106
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD
L
RD
H
L
CP
X
X
X
↓
J
X
X
X
h
h
l
K
X
X
X
h
l
Q
Q
L
H
L
Asynchronous Set
Asynchronous Reset
Undetermined *
Toggle
H
L
H
H*
q
L
H*
q
H
H
H
H
H
H
H
H
H
H
↓
H
L
L
Load “1” (Set)
↓
h
l
H
q
Load “0” (Reset)
Hold “no change”
Hold “no change”
↓
l
q
H
X
X
q
q
H
h
L
l
q
X
↓
*
=
=
=
=
=
=
=
=
High voltage level
High state must be present one setup time prior to High-to-Low clock transition
Low voltage level
Low state must be present one setup time prior to High-to-Low clock transition
Lower case indicate the state of the referenced output prior to the High-to-Low clock transition
Don’t care
High-to-Low clock transition
Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously
Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level. Set and reset are independent of clock.
Simultaneous Low on both SD and RD makes both Q and Q High.
3
1996 Jun 27
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
Supply voltage
V
I
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
CC
V
IN
Input voltage
Input current
V
mA
V
IN
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
16
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
CC
Supply voltage
5.0
5.5
V
V
V
IH
High-level input voltage
Low-level input voltage
Input clamp current
2.0
V
IL
0.8
–18
–0.4
8
V
I
Ik
mA
mA
mA
°C
I
High-level output current
Low-level output current
OH
I
OL
T
amb
Operating free-air temperature range
0
+70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
TYP
MAX
V
V
= ±10%,
= MAX, V = MIN
CC
IL
V
OH
High-level output voltage
I
= –0.4mA
V
CC
– 2
V
OH
IH
V
V
V
V
V
= MIN, V = MAX,
I
I
= 4mA
= 8mA
0.25
0.35
0.40
0.50
V
V
CC
IL
OL
V
Low-level output voltage
OL
= MIN
IH
OL
V
Input clamp voltage
= MIN, I = I
IK
–0.73 –1.5
V
IK
CC
CC
CC
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
0.1
20
mA
µA
mA
I
I
I
IH
= MAX, V = 2.7V
I
CPn
–0.1
I
IL
Low-level input current
V = MAX, V = 0.4V
CC I
SDn, RDn,
Jn, Kn
–0.2
mA
3
I
Output current
V
V
= MAX, V = 2.25V
–30
–112
mA
mA
O
CC
O
I
Supply current (total)
= MAX
2.5
4.5
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, I
.
OS
4
1996 Jun 27
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
SYMBOL
PARAMETER
TEST CONDITION
UNIT
C = 50pF, R = 500Ω
L
L
MIN
35
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
MHz
ns
MAX
t
t
Propagation delay
CPn to Qn or Qn
2.0
4.0
10.0
10.5
PLH
PHL
t
t
Propagation delay
SDn or RD to Qn or Qn
1.5
3.5
8.0
9.5
PLH
PHL
Waveform 2, 3
ns
AC SETUP REQUIREMENTS
LIMITS
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
SYMBOL
PARAMETER
TEST CONDITION
UNIT
C = 50pF, R = 500Ω
L
L
MIN
MAX
t
t
(H)
(L)
Setup time, High or Low
Jn, Kn to CPn
8.0
8.0
su
su
Waveform 1
Waveform 1
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
Jn, Kn to CPn
0.0
0.0
h
h
t (L)
t
t
(H)
(L)
CPn Pulse width
high or Low
11.0
8.0
w
w
Waveform 1
SDn or RDn Pulse width
Low
t
(L)
Waveform 2, 3
Waveform 2, 3
6.0
8.0
w
Recovery time,
SDn or RDn to CPn
t
REC
5
1996 Jun 27
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
AC WAVEFORMS
For all waveforms, V = 1.3V.
M
The sahded areas indicate when the input is permitted to change for predictable output performance.
Jn, Kn
V
V
V
V
M
M
M
M
t
(H)
t (H)
h
t
(L)
t (L)
h
su
su
1/f
M
max
t
(L)
w
CPn
Qn
V
V
M
V
M
t
(H)
w
t
PHL
t
PLH
V
V
M
M
M
t
t
PHL
PLH
V
M
V
Qn
SC00136
Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, Clock Pulse Width, and Maximum Clock
Frequency
Jn, Kn
Jn, Kn
t
(L)
t (L)
w
w
SDn
CPn
RDn
CPn
V
V
M
V
V
M
M
t
M
t
REC
REC
V
V
M
M
t
PHL
t
PLH
Qn
Qn
Qn
Qn
V
V
V
V
M
M
M
M
t
t
PLH
PHL
SC00049
SC00050
Waveform 2. Propagation Delay for Set to Output,
Set Pulse Width, and Recovery Time for Set to Clock
Waveform 3. Propagation Delay for Reset to Output,
Reset Pulse Width, and Recovery Time for Reset to Clock
6
1996 Jun 27
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0.3V
PULSE
GENERATOR
D.U.T.
t
t )
f
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Totem-pole Outputs
10%
10%
0.3V
t
w
Input Pulse Definition
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
INPUT PULSE REQUIREMENTS
V
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
Family
Rep.Rate
t
w
t
t
THL
Amplitude
M
TLH
2.0ns
2.0ns
of
74ALS
3.5V
1.3V
1MHz
500ns
OUT
SC00005
7
1996 Jun 27
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
8
1996 Jun 27
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
9
1996 Jun 27
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips
Semiconductors
相关型号：
©2020 ICPDF网 联系我们和版权申明