74ALVC00D-Q100_技术文档

74ALVC00-Q100

Quad 2-input NAND gate

Rev. 1 — 16 May 2014

Product data sheet

1. General description

The 74ALVC00-Q100 is a quad 2-input NAND gate.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 3) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 3)

 Specified from 40 C to +85 C

 Wide supply voltage range from 1.65 V to 3.6 V

 3.6 V tolerant inputs/outputs

 CMOS low power consumption

 Direct interface with TTL levels (2.7 V to 3.6 V)

 Power-down mode

 Latch-up performance exceeds 250 mA

 Complies with JEDEC standards:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74ALVC00D-Q100

40 C to +85 C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74ALVC00PW-Q100 40 C to +85 C

74ALVC00BQ-Q100 40 C to +85 C

TSSOP14

plastic thin shrink small outline package; 14 leads; SOT402-1

body width 4.4 mm

DHVQFN14 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 14 terminals;

body 2.5  3  0.85 mm

SOT762-1

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

4. Functional diagram

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Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram for one gate

5. Pinning information

5.1 Pinning

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(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 4. Pin configuration SO14 and TSSOP14

Fig 5. Pin configuration DHVQFN14

5.2 Pin description

Table 2.

Symbol

1A to 4A

1B to 4B

1Y to 4Y

GND

Pin description

Description

1, 4, 9, 12

2, 5, 10, 13

3, 6, 8, 11

7

data input

data output

ground (0 V)

supply voltage

V_CC

14

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

2 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

6. Functional description

Table 3.

Function selection^[1]

Input

nA

L

Output

nB

X

nY

H

X

L

H

L

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+4.6

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

V_I

+4.6

50

V_CC+ 0.5

+4.6

50

100

-

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

output HIGH or LOW state

output 3-state

mA

V

[1] [2]

[2]

V_O

0.5

-

V

power-down mode, V_CC= 0 V

V_O= 0 V to V_CC

V

I_O

output current

mA

C

mW

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

100

65

-

storage temperature

total power dissipation

+150

500

[3]

T_amb= 40 C to +85 C

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When V_CC= 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.

[3] For SO14 packages: above 70 C derate linearly with 8 mW/K.

For TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K.

For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

3 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

1.65

0

Max

3.6

V_CC

3.6

+85

20

Unit

V

supply voltage

input voltage

output voltage

V_I

V

V_O

output HIGH or LOW state

output 3-state

0

V

0

V

power-down mode; V_CC= 0 V

in free air

0

V

T_amb

ambient temperature

40

0

C

ns/V

t/V

input transition rise and fall rate

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

0

10

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

T_amb= 40 C to +85 C

Unit

Min

Typ^[1]

Max

V_IH

HIGH-level input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

0.65  V_CC

-

V

1.7

V_CC= 2.7 V to 3.6 V

2.0

V_IL

LOW-level input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

-

0.35  V_CC

0.7

0.8

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= 100 A; V_CC= 1.65 V to 3.6 V

V_CC 0.2

1.25

1.8

-

V

I_O= 6 mA; V_CC= 1.65 V

I_O= 12 mA; V_CC= 2.3 V

I_O= 18 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 18 mA; V_CC= 3.0 V

I_O= 24 mA; V_CC= 3.0 V

1.51

2.10

2.01

2.53

2.76

2.68

1.7

2.2

2.4

2.2

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 100 A; V_CC= 1.65 V to 3.6 V

I_O= 6 mA; V_CC= 1.65 V

-

0.2

0.3

0.4

0.6

0.4

0.55

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V

0.11

0.17

0.25

0.16

0.23

0.30

0.1

V

I_O= 12 mA; V_CC= 2.3 V

V

I_O= 18 mA; V_CC= 2.3 V

V

I_O= 12 mA; V_CC= 2.7 V

V

I_O= 18 mA; V_CC= 3.0 V

V

I_O= 24 mA; V_CC= 3.0 V

V

I_I

input leakage current

V_CC= 3.6 V; V_I= 3.6 V or GND

A

I_OFF

power-off leakage current V_CC= 0 V; V_Ior V_O= 0 V to 3.6 V

10

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

4 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

Table 6.

Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

T_amb= 40 C to +85 C

Unit

Min

Typ^[1]

Max

I_CC

I_CC

C_I

supply current

V_CC= 3.6 V; V_I= V_CCor GND;

I_O= 0 A

-

0.2

20

750

-

A

pF

additional supply current

input capacitance

per input pin; V_CC= 3.0 V to 3.6 V;

V_I= V_CC 0.6 V; I_O= 0 A

5

3.5

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 C.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 7.

Symbol Parameter

Conditions

T_amb= 40 C to +85 C Unit

Min

Typ^[1]

Max

[2]

t_pd

propagation delay

nA, nB to nY; see Figure 6

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

1.0

-

2.8

2.1

2.6

2.1

28

4.4

2.8

3.2

3.0

-

ns

pF

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

[3]

C_PD

power dissipation

capacitance

per gate; V_I= GND to V_CC; V_CC= 3.3 V

[1] Typical values are measured at T_amb= 25 C

[2] _pdis the same as t_PHLand t_PLH

t

.

[3] C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

5 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

11. Waveforms

V

I

V

t

nA, nB input

GND

M

t

PHL

PLH

V

OH

nY output

V

M

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V

OL

Measurement points are given in Table 8.

Fig 6. Inputs nA, nB to output nY propagation delay times

Table 8. Measurement points

Supply voltage V_CC

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

Input V_I

V_CC

V_M

0.5V_CC

1.5 V

V_CC

2.7 V

3.0 V to 3.6 V

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

6 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

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Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 7. Test circuit for measuring switching times

Table 9.

Test data

Supply voltage V_CC

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

6 V

t_PHZ, t_PZH

GND

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

V_CC

2.7 V

 2.0 ns

 2.5 ns

30 pF

50 pF

1 k

500 

open

GND

open

GND

3.0 V to 3.6 V

open

6 V

GND

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

7 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

12. Package outline

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Fig 8. Package outline SOT108-1 (SO14)

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

8 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

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Fig 9. Package outline SOT402-1 (TSSOP14)

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

9 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

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Fig 10. Package outline SOT762-1 (DHVQFN14)

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

10 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

13. Abbreviations

Table 10. Abbreviations

Acronym

DUT

ESD

HBM

MIL

Description

Device Under Test

ElectroStatic Discharge

Human Body Model

Military

MM

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date

20140516

Data sheet status

Change notice

Supersedes

74ALVC00_Q100 v.1

Product data sheet

-

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

11 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

15.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

12 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74ALVC00-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 16 May 2014

13 of 14

74ALVC00-Q100

NXP Semiconductors

Quad 2-input NAND gate

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

6

Functional description . . . . . . . . . . . . . . . . . . . 3

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 13

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 May 2014

Document identifier: 74ALVC00-Q100


型号：	74ALVC00D-Q100
厂家：	NXP
描述：	IC NAND GATE, Gate 栅光电二极管逻辑集成电路
文件：	总14页 (文件大小：187K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74ALVC00D-Q100 [NXP]

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