74ALVC02BQ [NXP]
Quad 2-input NOR gate; 四路2输入NOR门
| 型号： | 74ALVC02BQ |
| 厂家： | 
NXP |
| 描述： | Quad 2-input NOR gate |
| 文件： | 总13页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74ALVC02
Quad 2-input NOR gate
Product specification
2003 Jul 14
Supersedes data of 2003 Feb 05
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 to 3.6 V
• 3.6 V tolerant inputs/outputs
The 74ALVC02 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
• CMOS low power consumption
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
• Direct interface with TTL levels (2.7 to 3.6 V)
• Power-down mode
The 74ALVC02 provides the 2-input NOR function.
• Latch-up performance exceeds 250 mA
• Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
ns
t
PHL/tPLH
propagation delay nA, nB to nY
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
2.8
V
V
V
CC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.0
ns
ns
ns
pF
pF
CC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.5
CC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.2
3.5
CI
input capacitance
CPD
power dissipation capacitance per buffer
VCC = 3.3 V; notes 1 and 2
32
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2003 Jul 14
2
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PACKAGE
TEMPERATURE
PINS
MATERIAL
CODE
RANGE
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
74ALVC02D
74ALVC02PW
74ALVC02BQ
14
14
14
SO14
plastic
plastic
plastic
SOT108-1
SOT402-1
SOT762-1
TSSOP14
DHVQFN14
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nA
nB
nY
L
L
L
H
L
H
L
L
L
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level
PINNING
Pin
SYMBOL
1Y
DESCRIPTION
1
2
data output
1A
1B
2Y
2A
2B
GND
3A
3B
3Y
4A
4B
4Y
VCC
data input
data input
data output
data input
data input
ground (0 V)
data input
data input
data output
data input
data input
data output
supply voltage
handbook, halfpage
1Y
1A
1
2
3
4
5
6
7
V
CC
14
3
4
13
12
11
10
9
4Y
4B
4A
3Y
3B
3A
5
1B
6
2Y
02
7
2A
8
2B
9
8
GND
10
11
12
13
14
MNA214
Fig.1 Pin configuration SO14 and TSSOP14.
2003 Jul 14
3
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
V
1Y
1
handbook, halfpage
CC
14
1A
2
3
13 4Y
12 4B
1B
handbook, halfpage
A
B
(1)
2Y
2A
2B
4
5
6
11 4A
10 3Y
GND
Y
MNA215
9
3B
7
8
GND 3A
Top view
MNA951
(1) (1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN14.
Fig.3 Logic diagram (one gate).
2
handbook, halfpage
≥ 1
≥ 1
≥ 1
≥ 1
1
4
3
handbook, halfpage
2
3
1A
1B
1Y
2Y
1
4
5
6
5
6
2A
2B
8
9
3A
3B
3Y 10
4Y 13
8
9
10
13
11
12
4A
4B
11
12
MNA216
MNA217
Fig.4 Function diagram.
Fig.5 IEC logic symbol.
2003 Jul 14
4
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
UNIT
3.6
3.6
V
V
V
V
VI
input voltage
0
VO
output voltage
VCC = 1.65 to 3.6 V
CC = 0 V; Power-down mode
0
VCC
4.6
+85
20
V
0
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.65 to 2.7 V
CC = 2.7 to 3.6 V
ns/V
ns/V
V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +4.6
V
IIK
input diode current
input voltage
VI < 0
−
−50
mA
V
VI
−0.5
−
+4.6
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
notes 1 and 2
mA
V
−0.5
−0.5
−
VCC + 0.5
+4.6
±50
Power-down mode; note 2
VO = 0 to VCC
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
mA
mA
°C
mW
ICC, IGND
−
±100
+150
500
Tstg
Ptot
−65
−
Tamb = −40 to +85 °C; note 3
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
3. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
2003 Jul 14
5
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
voltage
2.3 to 2.7
2.7 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.7
2
VIL
LOW-level input
voltage
−
0.35 × VCC
0.7
−
−
0.8
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 6 mA
1.65 to 3.6
1.65
2.3
−
−
−
−
−
−
−
−
0.2
0.3
0.4
0.6
0.4
0.4
0.55
V
V
V
V
V
V
V
0.11
0.17
0.25
0.16
0.23
0.30
IO = 12 mA
IO = 18 mA
2.3
IO = 12 mA
2.7
IO = 18 mA
3.0
IO = 24 mA
3.0
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −6 mA
1.65 to 3.6
1.65
2.3
V
CC − 0.2
−
−
V
1.25
1.8
1.7
2.2
2.4
2.2
−
1.51
2.10
2.01
2.53
2.76
2.68
±0.1
−
V
IO = −12 mA
IO = −18 mA
IO = −12 mA
IO = −18 mA
IO = −24 mA
VI = 3.6 V or GND
−
V
2.3
−
V
2.7
−
V
3.0
−
V
3.0
−
V
ILI
input leakage
current
3.6
±5
µA
Ioff
power OFF leakage VI or VO = 3.6 V
current
0.0
−
−
−
±0.1
0.2
5
±10
20
µA
µA
µA
ICC
∆ICC
quiescent supply
current
VI = VCC or GND; IO = 0
3.6
additional quiescent VI = VCC − 0.6 V; IO = 0
supply current per
3.0 to 3.6
750
input pin
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Jul 14
6
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
AC CHARACTERISTICS
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
Tamb = −40 to +85 °C
tPHL/tPLH propagation delay
nA, nB to nY
see Figs 6 and 7
1.65 to 1.95 1.0
2.8
2.0
2.5
2.2
4.7
ns
2.3 to 2.7
2.7
1.0
1.0
1.0
3.1
2.9
2.8
ns
ns
ns
3.0 to 3.6
Note
1. All typical values are measured at Tamb = 25 °C.
AC WAVEFORMS
V
handbook, halfpage
nA, nB input
I
V
M
GND
t
t
PHL
PLH
V
OH
V
nY output
M
V
OL
t
t
THL
TLH
MNA218
INPUT
tr = tf
VCC
VM
VI
VCC
1.65 to 1.95 V 0.5 × VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
2.3 to 2.7 V
2.7 V
0.5 × VCC
1.5 V
VCC
2.7 V
2.7 V
3.0 to 3.6 V
1.5 V
Fig.6 Inputs nA, nB to output nY propagation delay times.
2003 Jul 14
7
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
VCC
VI
VCC
CL
RL
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
open
open
open
open
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
VCC
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
3.0 to 3.6 V
6 V
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
2003 Jul 14
8
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
2003 Jul 14
9
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
2003 Jul 14
10
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
C
1
y
e
b
v
M
C
C
A
B
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
2003 Jul 14
11
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jul 14
12
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/02/pp13
Date of release: 2003 Jul 14
Document order number: 9397 750 11272
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