74ALVC164245BQ,515 [NXP]
74ALVC164245BQ;
NXP 
74ALVC164245
16-bit dual supply translating transceiver; 3-state
Rev. 8 — 15 March 2012
Product data sheet
1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. It is
designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply
environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.
nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables
data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH,
disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins
nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B)
.
In suspend mode, when one of the supply voltages is zero, there will be no current flow
from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state
and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) VCC(A)
(except in suspend mode).
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range:
3 V port (VCC(A)): 1.5 V to 3.6 V
5 V port (VCC(B)): 1.5 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Control inputs voltage range from 2.7 V to 5.5 V
Inputs accept voltages up to 5.5 V
High-impedance outputs when VCC(A) or VCC(B) = 0 V
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and 40 C to +125 C
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Temperature
range
Package
Name
Description
Version
74ALVC164245DL
40 C to +125 C SSOP48
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74ALVC164245DGG 40 C to +125 C TSSOP48
74ALVC164245BX 40 C to +125 C HXQFN60
plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4 6 0.5 mm
SOT1134-2
4. Functional diagram
2DIR
1DIR
2OE
2B0
2B1
2B2
2B3
2B4
2B5
2B6
1OE
1B0
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B7
001aaa789
Fig 1. Logic symbol
74ALVC164245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
2 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
1OE
G3
1DIR
3EN1[BA]
3EN2[AB]
G6
2OE
6EN1[BA]
6EN2[AB]
2DIR
1A0
1B0
1
2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2A0
4
5
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2B1
2B2
2B3
2B4
2B5
2B6
2B7
001aaa790
Fig 2. IEC logic symbol
74ALVC164245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
3 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1OE
1A0
1A1
GND
1A2
1A3
1B0
1B1
GND
1B2
1B3
3
4
5
6
7
V
V
CC(A)
CC(B)
8
1B4
1A4
1A5
GND
1A6
1A7
2A0
2A1
GND
2A2
2A3
9
1B5
GND
1B6
1B7
2B0
2B1
GND
2B2
2B3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
74ALVC164245
V
V
CC(A)
CC(B)
2B4
2A4
2A5
GND
2A6
2A7
2OE
2B5
GND
2B6
2B7
2DIR
001aab037
Fig 3. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
74ALVC164245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
4 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
terminal 1
index area
D1
A32
D5
A31
A30
A29
A28
A27
D8
D4
B20
B19
B18
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
B1
B2
B3
B4
B5
B6
B7
B17
B16
B15
B14
B13
B12
B11
74ALVC164245
(1)
GND
D6
B8
B9
B10
D7
D2
A11
A12
A13
A14
A15
A16
D3
001aai851
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 4. Pin configuration SOT1134-2 (HXQFN60)
74ALVC164245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
5 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
SOT370-1 and SOT362-1
SOT1134-2
1DIR, 2DIR 1, 24
A30, A13
direction control input
1B0 to 1B7 2, 3, 5, 6, 8, 9, 11, 12
B20, A31, D5, D1, A2, B2, B3, A5
data input/output
2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 A6, B5, B6, A9, D2, D6, A12, B8
data input/output
GND
4, 10, 15, 21, 28, 34, 39, 45
7, 18
A32, A3, A8, A11, A16, A19, A24, A27
ground (0 V)
VCC(B)
A1, A10,
A29, A14
supply voltage B (5 V bus)
output enable input (active LOW)
1OE, 2OE 48, 25
1A0 to 1A7 47, 46, 44, 43, 41, 40, 38, 37 B18, A28, D8, D4, A25, B16, B15, A22 data input/output
2A0 to 2A7 36, 35, 33, 32, 30, 29, 27, 26 A21, B13, B12, A18, D3, D7, A15, B10 data input/output
VCC(A)
n.c.
31, 42
-
A17, A26
supply voltage A (3 V bus)
A4, A7, A20, A23, B1, B4, B7, B9, B11, not connected
B14, B17, B19
6. Functional description
Table 3.
Function table[1]
Inputs
Outputs
nOE
L
nDIR
nAn
nBn
L
nAn = nBn
inputs
Z
inputs
nBn = nAn
Z
L
H
X
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See
[1]
.
Symbol
VCC(B)
VCC(A)
IIK
Parameter
Conditions
VCC(B) VCC(A)
VCC(B) VCC(A)
VI < 0 V
Min
0.5
0.5
50
0.5
0.5
-
Max
Unit
V
supply voltage B
supply voltage A
input clamping current
input voltage
+6.0
+4.6
V
-
mA
V
[2]
VI
+6.0
VI/O
input/output voltage
VCC + 0.5
50
V
IOK
output clamping current VO > VCC or VO < 0 V
mA
V
[2]
[2]
VO
output voltage
output HIGH or LOW
output 3-state
0.5
0.5
-
VCC + 0.5
+6.0
V
IO(sink/source)
ICC
output sink or source
current
VO = 0 V to VCC
50
mA
supply current
-
100
mA
74ALVC164245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
6 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See
[1]
.
Symbol
IGND
Parameter
Conditions
Min
100
65
Max
-
Unit
mA
C
ground current
Tstg
storage temperature
total power dissipation
+150
Ptot
Tamb = 40 C to +125 C
(T)SSOP48 package
HXQFN60 package
[3]
[4]
-
-
500
mW
mW
1000
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
[2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VCC(B)
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage B
VCC(B) VCC(A)
maximum speed performance
low-voltage applications
VCC(B) VCC(A)
2.7
1.5
-
-
5.5
5.5
V
V
VCC(A)
supply voltage A
input voltage
maximum speed performance
low-voltage applications
control inputs: nOE and nDIR
2.7
1.5
0
-
-
-
-
-
-
-
-
-
-
-
-
3.6
V
3.6
V
VI
5.5
V
VI/O
input/output voltage nAn port
nBn port
0
VCC(A)
VCC(B)
VCC(A)
VCC(B)
+125
20
V
0
V
VO
output voltage
nAn port
nBn port
0
V
0
V
Tamb
ambient temperature
40
0
C
ns/V
ns/V
ns/V
ns/V
t/V
input transition rise
and fall rate
VCC(A) = 2.7 V to 3.0 V
VCC(A) = 3.0 V to 3.6 V
VCC(B) = 3.0 V to 4.5 V
VCC(B) = 4.5 V to 5.5 V
0
10
0
20
0
10
74ALVC164245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
7 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1] Max
Min
Typ[1] Max
VIH
HIGH-level
nBn port
input voltage
[2]
[2]
VCC(B) = 3.0 V to 5.5 V
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V
VCC(A) = 2.3 V to 2.7 V
nBn port
2.0
-
-
2.0
-
-
V
2.0
1.7
-
-
-
-
2.0
1.7
-
-
-
-
V
V
VIL
LOW-level
input voltage
[2]
[2]
VCC(B) = 4.5 V to 5.5 V
VCC(B) = 3.0 V to 3.6 V
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V
VCC(A) = 2.3 V to 2.7 V
nBn port; VI = VIH or VIL
IO = 24 mA; VCC(B) = 4.5 V
IO = 12 mA; VCC(B) = 4.5 V
IO = 18 mA; VCC(B) = 3.0 V
IO = 100 A; VCC(B) = 3.0 V
nAn port; VI = VIH or VIL
IO = 24 mA; VCC(A) = 3.0 V
IO = 100 A; VCC(A) = 3.0 V
IO = 12 mA; VCC(A) = 2.7 V
IO = 8 mA; VCC(A) = 2.3 V
IO = 100 A; VCC(A) = 2.3 V
nBn port; VI = VIH or VIL
IO = 24 mA; VCC(B) = 4.5 V
IO = 12 mA; VCC(B) = 4.5 V
IO = 100 A; VCC(B) = 4.5 V
IO = 18 mA; VCC(B) = 3.0 V
IO = 100 A; VCC(B) = 3.0 V
nAn port; VI = VIH or VIL
IO = 24 mA; VCC(A) = 3.0 V
IO = 100 A; VCC(A) = 3.0 V
IO = 12 mA; VCC(A) = 2.7 V
IO = 12 mA; VCC(A) = 2.3 V
IO = 100 A; VCC(A) = 2.3 V
-
-
-
-
0.8
0.7
-
-
-
-
0.8
0.7
V
V
-
-
-
-
0.8
0.7
-
-
-
-
0.8
0.7
V
V
[2]
VOH
HIGH-level
output voltage
VCC(B) 0.8
VCC(B) 0.5
VCC(B) 0.8
-
-
-
-
-
-
-
VCC(B) 1.2
VCC(B) 0.8
VCC(B) 1.0
-
-
-
-
-
-
-
V
V
V
V
VCC(B) 0.2 VCC(B)
VCC(B) 0.3 VCC(B)
VCC(A) 0.7
VCC(A) 0.2
VCC(A) 0.5
VCC(A) 0.6
-
-
-
-
-
-
-
-
-
VCC(A) 1.0
VCC(A) 0.3
VCC(A) 0.8
VCC(A) 0.6
-
-
-
-
-
-
-
-
-
V
V
V
V
V
VCC(A) 0.2 VCC(A)
VCC(A) 0.3 VCC(A)
VOL
LOW-level
output voltage
-
-
-
-
-
-
-
-
-
-
0.55
0.40
0.20
0.55
0.20
-
-
-
-
-
-
-
-
-
-
0.60
0.80
0.30
0.80
0.30
V
V
V
V
V
-
-
-
-
-
-
-
0.55
0.20
0.40
0.60
0.20
5
-
-
-
-
-
-
-
0.80
0.30
0.60
0.60
0.20
V
V
V
V
V
-
-
-
-
-
-
-
-
II
input leakage VI = 5.5 V or GND
current
0.1
0.1
10 A
[3]
IOZ
OFF-state
VI = VIH or VIL;
-
0.1 10
-
0.1
20 A
output current VO = VCC or GND
74ALVC164245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
8 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1] Max
Min
Typ[1] Max
ICC
supply current VI = VCC or GND; IO = 0 A
additional per control pin;
-
-
0.1
5
40
-
-
0.1
5
80 A
5000 A
[4]
ICC
500
supply current VI = VCC 0.6 V; IO = 0 A
CI
input
capacitance
-
-
4.0
5.0
-
-
-
-
-
-
-
-
pF
pF
CI/O
input/output
capacitance
nAn and nBn port
[1] All typical values are measured at VCC(B) = 5.0 V, VCC(A) = 3.3 V and Tamb = 25 C.
[2] If VCC(A) < 2.7 V, the switching levels at all inputs are not TTL compatible.
[3] For transceivers, the parameter IOZ includes the input leakage current.
[4]
VCC(A) = 2.7 V to 3.6 V: other inputs at VCC(A) or GND; VCC(B) = 4.5 V to 5.5 V: other inputs at VCC(B) or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
Conditions
T
amb
= 40 C to +85 C
T
= 40 C to +125 C Unit
amb
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation
delay
nAn to nBn; see Figure 5
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.5
1.0
1.0
3.3
3.0
2.9
7.6
5.9
5.8
1.5
9.5
7.5
7.5
ns
ns
ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V
1.0
1.0
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
[2]
nBn to nAn; see Figure 5
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.0
1.0
1.2
3.0
4.3
2.5
7.6
6.7
5.8
1.0
1.0
1.2
9.5
8.5
7.5
ns
ns
ns
VCC(A) = 2.7 V;
V
CC(B) = 4.5 V to 5.5 V
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
74ALVC164245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
9 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
Conditions
T
amb
= 40 C to +85 C
T
= 40 C to +125 C Unit
amb
Min
Typ[1]
Max
Min
Max
[2]
[2]
[2]
[2]
ten
enable time
nOE to nBn; see Figure 6
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.5
1.5
1.0
4.1
3.6
3.2
11.5
9.2
1.5
14.5
11.5
12.0
ns
ns
ns
VCC(A) = 2.7 V;
1.5
1.0
V
CC(B) = 4.5 V to 5.5 V
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
8.9
nOE to nAn; see Figure 6
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.5
1.5
1.0
4.6
4.3
3.2
12.3
9.3
1.5
1.5
1.0
15.5
12.0
11.5
ns
ns
ns
VCC(A) = 2.7 V;
V
CC(B) = 4.5 V to 5.5 V
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
8.9
tdis
disable time
nOE to nBn; see Figure 6
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
2.0
2.5
2.1
2.7
4.6
4.9
10.5
9.0
2.0
2.5
2.1
13.5
11.5
11.0
ns
ns
ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V
VCC(A) = 3.0 V to 3.6 V;
8.6
VCC(B) = 4.5 V to 5.5 V
nOE to nAn; see Figure 6
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.0
1.5
2.0
2.7
3.5
3.2
9.3
9.0
8.6
1.0
1.5
2.0
12.0
11.5
11.0
ns
ns
ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
74ALVC164245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
10 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
Conditions
T
amb
= 40 C to +85 C
T
= 40 C to +125 C Unit
amb
Min
Typ[1]
Max
Min
Max
[3][4]
[3][4]
CPD
power
dissipation
capacitance
5 V port: nAn to nBn;
V
CC(B) = 5 V; VCC(A) = 3.3 V
outputs enabled
-
-
30
15
-
-
-
-
-
-
pF
pF
outputs disabled
3 V port: nBn to nAn;
VCC(B) = 5 V; VCC(A) = 3.3 V
outputs enabled
outputs disabled
-
-
40
5
-
-
-
-
-
-
pF
pF
[1] All typical values are measured at nominal voltage for VCC(B) and VCC(A) and at Tamb = 25 C.
[2]
t
pd is the same as tPLH and tPHL
.
ten is the same as tPZL and tPZH
.
tdis is the same as tPLZ and tPHZ
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
[4] The condition is VI = GND to VCC
.
11. AC waveforms
V
I
nAn, nBn
input
V
M
GND
t
t
PHL
PLH
V
OH
nBn, nAn
output
V
M
001aaa792
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. Input (nAn, nBn) to output (nBn, nAn) propagation delays
74ALVC164245
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Product data sheet
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74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
V
I
nOE input
GND
V
M
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna362
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with output load.
Fig 6. 3-state enable and disable times
Table 8.
Measurement points
Supply voltage
Direction
Input
VI
Output
VM
VCC(A)
VCC(B)
VM
VX
VY
nAn port to nBn 2.3 V to 2.7 V 2.7 V to 3.6 V VCC(A)
port
0.5 VCC(A) 1.5 V
VOL(B) + 0.3 V VOH(B) 0.3 V
0.5 VCC(A) VOL(A) + 0.15 V VOH(A) 0.15 V
0.5 VCC(B) 0.2 VCC(B) 0.8 VCC(B)
nBn port to nAn 2.3 V to 2.7 V 2.7 V to 3.6 V 2.7 V
port
1.5 V
1.5 V
1.5 V
nAn port to nBn 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V
port
nBn port to nAn 2.7 V to 3.6 V 4.5 V to 5.5 V 3.0 V
port
1.5 V
VOL(A) + 0.3 V VOH(A) 0.3 V
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Product data sheet
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74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 7. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
VCC(A)
Direction
Load
CL
VEXT
VCC(B)
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
nAn port to nBn 2.3 V to 2.7 V
port
2.7 V to 3.6 V 50 pF
2.7 V to 3.6 V 50 pF
4.5 V to 5.5 V 50 pF
4.5 V to 5.5 V 50 pF
500
GND
2 VCC
nBn port to nAn 2.3 V to 2.7 V
port
500
500
500
open
open
open
GND
GND
GND
6.0 V
nAn port to nBn 2.7 V to 3.6 V
port
2 VCC
6.0 V
nBn port to nAn 2.7 V to 3.6 V
port
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Product data sheet
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13 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
Fig 8. Package outline SOT370-1 (SSOP48)
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Product data sheet
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14 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
Fig 9. Package outline SOT362-1 (TSSOP48)
74ALVC164245
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Product data sheet
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15 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads;
60 terminals; body 4 x 6 x 0.5 mm
SOT1134-2
D
B
A
terminal 1
index area
A
A
2
E
A
1
detail X
e
2
b
v
C
C
A
B
w
e
1
eR
C
C
A
B
e
v
C
eT
1/2 e
B8 B10
w
y
y
C
1
L
1
D2
A11
A16
D3
D7
D6
L
A17
B11
A10
B7
e
eR
eT
E
h
e
3
e
4
1/2 e
B1
A1
B17
A26
terminal 1
index area
D5
D1
B20 B18
D8
D4
eT
eR
A32
A27
X
D
h
K
eT
eR
0
5 mm
Dimensions
Unit
A
A
1
A
2
b
D
D
h
E
E
e
e
e
2
e
3
e
eR eT
K
L
L
v
w
y
y
1
h
1
4
1
max 0.50 0.08 0.42 0.28 4.1 1.95 6.1 3.95
0.25 0.28 0.195
mm nom
min
0.05 0.40 0.23 4.0 1.85 6.0 3.85 0.5 1.0 2.5 3.0 4.5 0.5 0.49 0.20 0.23 0.145 0.1 0.05 0.08 0.1
0.02 0.38 0.18 3.9 1.75 5.9 3.75
0.15 0.18 0.095
sot1134-2_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
SOT1134-2
11-08-15
Fig 10. Package outline SOT1134-2 (HXQFN60)
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Product data sheet
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NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20120315
Data sheet status
Change notice
Supersedes
74ALVC164245 v.8
Modifications:
Product data sheet
-
74ALVC164245 v.7
• For type number 74ALVC164245BX the sot code has changed to SOT1134-2.
74ALVC164245 v.7
Modifications:
20111117
Product data sheet
-
74ALVC164245 v.6
• Legal pages updated.
74ALVC164245 v.6
74ALVC164245 v.5
74ALVC164245 v.4
74ALVC164245 v.3
74ALVC164245 v.2
74ALVC164245 v.1
20110616
20100413
20081111
20040914
20040601
19980826
Product data sheet
-
-
-
-
-
-
74ALVC164245 v.5
74ALVC164245 v.4
74ALVC164245 v.3
74ALVC164245 v.2
74ALVC164245 v.1
-
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product specification
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NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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18 of 20
74ALVC164245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
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19 of 20
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NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 March 2012
Document identifier: 74ALVC164245
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