74ALVC573PW [NXP]
Octal D-type transparent latch 3-state; 八D型透明锁存器3 -STATE
| 型号： | 74ALVC573PW |
| 厂家： | 
NXP |
| 描述： | Octal D-type transparent latch 3-state |
| 文件： | 总20页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74ALVC573
Octal D-type transparent latch;
3-state
Product specification
2003 Jun 25
Supersedes data of 2002 Mar 01
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
FEATURES
The 74ALVC573 is an octal D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
internal latches.
• Wide supply voltage range from 1.65 to 3.6 V
• Complies with JEDEC standards:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
The 74ALVC573 consists of eight D-type transparent
latches with 3-state true outputs. When LE is HIGH, data
at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state
each time its corresponding D-input changes.
JESD8B/JESD36 (2.7 to 3.6 V).
• 3.6 V tolerant inputs and outputs
• CMOS low power consumption
• Direct interface with TTL levels (2.7 to 3.6 V)
• Power-down mode
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
• Latch-up performance exceeds 250 mA
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC573 is functionally identical to the
74ALVC373, but the has a different pin arrangement.
The 74ALVC573 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL/tPLH
propagation delay input Dn to output Qn VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ 2.5
ns
ns
ns
ns
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.0
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.3
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.2
3.5
CI
input capacitance
pF
CPD
power dissipation capacitance per buffer VCC = 3.3 V; notes and 1
outputs enabled
outputs disabled
37
7
pF
pF
Notes
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
1. The condition is VI = GND to VCC
.
2003 Jun 25
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
FUNCTION TABLE
See note 1
INPUT
OUTPUT
INTERNAL
LATCH
OPERATING MODES
OE
LE
Dn
Qn
Enable and read register
(transparent mode)
L
L
H
H
L
L
L
L
L
H
l
L
H
L
L
H
L
Latch and read register
L
L
h
l
H
L
H
Z
Z
Latch register and disable
outputs
H
H
h
H
Note
1. H = HIGH voltage level;
a) h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
b) L = LOW voltage level;
c) l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
d) Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
PINS
PACKAGE
MATERIAL
CODE
RANGE
74ALVC573D
74ALVC573PW
74ALVC573BQ
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
20
20
20
SO20
plastic
plastic
plastic
SOT163-1
SOT360-1
SOT764-1
TSSOP20
DHVQFN20
PINNING
PIN
SYMBOL
DESCRIPTION
PIN
SYMBOL
DESCRIPTION
11
LE
latch enable input (active
HIGH)
1
OE
output enable input (active
LOW)
12
13
14
15
16
17
18
19
20
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
3-state latch output
3-state latch output
3-state latch output
3-state latch output
3-state latch output
3-state latch output
3-state latch output
3-state latch output
supply voltage
2
3
D0
D1
D2
D3
D4
D5
D6
D7
GND
data input
data input
data input
data input
data input
data input
data input
data input
ground (0 V)
4
5
6
7
8
9
10
2003 Jun 25
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
V
handbook, halfpage
OE
1
CC
20
2
3
4
5
6
7
8
9
19
Q0
D0
handbook, halfpage
V
OE
1
2
20
19
CC
D1
D2
D3
D4
D5
D6
D7
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
Q0
D0
D1
3
18 Q1
17 Q2
D2
4
(1)
GND
16
15
D3
5
Q3
Q4
573
6
D4
7
14 Q5
D5
8
13
12
11
Q6
D6
9
D7
Q7
LE
GND
10
10
11
MNA806
GND LE
Top view
MNA979
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO20 and TSSOP20.
Fig.2 Pin configuration DHVQFN20.
handbook, halfpage
11
C1
handbook, halfpage
1
1
EN1
OE
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
19
1D
3
4
5
18
17
16
6
7
8
9
15
14
13
12
LE
11
MNA807
MNA808
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
2003 Jun 25
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
handbook, halfpage
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
19
Q0
LE
LE
Q1 18
handbook, halfpage
17
16
15
14
13
12
Q2
Q3
LATCH
1 to 8
3-STATE
OUTPUTS Q4
LE
LE
Q5
Q6
Q7
D
Q
MNA692
LE
11
1
OE
MNA809
Fig.5 Function diagram.
Fig.6 Logic diagram (one latch).
D0
D1
D2
D3
D4
D5
D6
D7
a n d b o o k , f u l l p a g e w
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MNA810
Fig.7 Logic diagram.
5
2003 Jun 25
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
3.6
UNIT
V
VI
input voltage
0
3.6
VCC
3.6
3.6
+85
20
V
VO
output voltage
VCC = 1.65 to 3.6 V; enable mode 0
V
V
CC = 1.65 to 3.6 V; disable mode 0
V
VCC = 0 V; Power-down mode
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.65 to 2.7 V
VCC = 2.7 to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +4.6
V
IIK
input diode current
input voltage
VI < 0
−
−50
mA
V
VI
−0.5
−
+4.6
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
enable mode; notes 1 and 2
disable mode
mA
V
−0.5
−0.5
−0.5
−
VCC + 0.5
+4.6
+4.6
±50
V
Power-down mode; note 2
VO = 0 to VCC
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
mA
mA
°C
mW
ICC, IGND
−
±100
+150
500
Tstg
Ptot
−65
−
Tamb = −40 to +85 °C; note 3
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
3. For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
a) For TSSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
b) For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
2003 Jun 25
6
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85°C
VIH HIGH-level input
1.65 to 1.95 0.65 × VCC
−
−
−
−
V
V
V
V
V
V
voltage
2.3 to 2.7
2.7 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.7
2
−
−
−
−
−
VIL
LOW-level input
voltage
−
0.35 × VCC
0.7
−
−
0.8
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 6 mA
1.65 to 3.6
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.2
0.3
0.4
0.6
0.4
0.4
0.55
V
V
V
V
V
V
V
IO = 12 mA
IO = 18 mA
IO = 12 mA
IO = 18 mA
IO = 24 mA
VI = VIH or VIL
IO = −100 µA
IO = −6 mA
IO = −12 mA
IO = −18 mA
IO = −12 mA
IO = −18 mA
IO = −24 mA
2.3
2.7
3.0
3.0
VOH
HIGH-level output
voltage
1.65 to 3.6
1.65
V
CC − 0.2
−
−
V
1.25
1.8
1.7
2.2
2.4
2.2
−
−
−
V
2.3
−
−
V
2.3
−
−
V
2.7
−
−
V
3.0
−
−
V
3.0
−
−
V
ILI
input leakage current VI = 3.6 V or GND
3.6
±0.1
0.1
±5
±10
µA
µA
IOZ
3-state output
OFF-state current
VI = VIH or VIL;
VO = 3.6 V or GND;
note 2
1.65 to 3.6
−
Ioff
power OFF leakage
current
VI or VO = 0 to 3.6 V
0.0
−
−
−
±0.1
0.2
5
±10
10
µA
µA
µA
ICC
∆ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
3.6
additional quiescent
supply current per
input pin
VI = VCC − 0.6 V;
IO = 0
3.0 to 3.6
750
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2. For transceivers, the parameter IOZ includes the input leakage current.
2003 Jun 25
7
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
AC CHARACTERISTICS
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 to +85 °C; see note 1
tPHL/tPLH propagation delay Dn to Qn see Figs 8 and 12
1.65 to 1.95 1.0
2.5
5.4
ns
2.3 to 2.7
2.7
1.0
1.0
1.0
2.0
2.3
2.2
2.8
2.1
2.4
2.3
3.0
2.4
3.0
2.3
3.4
2.2
2.8
2.7
−
3.5
3.6
3.3
6.0
3.8
3.7
3.3
6.4
4.5
4.6
4.0
7.0
4.4
4.4
4.4
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0 to 3.6
tPHL/tPLH propagation delay LE to Qn see Figs 9 and 12
1.65 to 1.95 1.0
2.3 to 2.7
2.7
1.0
1.0
1.0
3.0 to 3.6
tPZH/tPZL
3-state output enable time
OE to Qn
see Figs 10 and 12 1.65 to 1.95 1.5
2.3 to 2.7
2.7
1.0
1.5
1.0
3.0 to 3.6
tPHZ/tPLZ
3-state output disable time
OE to Qn
see Figs 10 and 12 1.65 to 1.95 1.5
2.3 to 2.7
2.7
1.0
1.5
1.0
3.0 to 3.6
tW
tsu
th
LE pulse with HIGH
set-up time Dn to LE
hold time Dn to LE
see Figs 9 and 12
1.65 to 1.95 3.8
2.3 to 2.7
2.7
3.3
3.3
3.3
−
−
−
−
3.0 to 3.6
−
−
see Figs 11 and 12 1.65 to 1.95 0.8
−
−
2.3 to 2.7
2.7
0.8
0.8
0.8
−
−
−
−
3.0 to 3.6
−
−
see Figs 11 and 12 1.65 to 1.95 0.8
−
−
2.3 to 2.7
2.7
0.8
0.8
0.7
−
−
−
−
3.0 to 3.6
−
−
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Jun 25
8
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
AC WAVEFORMS
V
handbook, halfpage
Dn input
I
V
M
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
MNA811
INPUT
tr = tf
VCC
VM
VI
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
VCC
VCC
≤ 2.0 ns 0.5 × VCC
≤ 2.0 ns 0.5 × VCC
2.7 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
3.0 to 3.6 V
Fig.8 Input Dn to output Qn propagation delay times.
1/f
max
V
I
LE input
V
M
t
GND
t
W
t
PHL
PLH
V
OH
V
Qn output
M
V
OL
MNA812
INPUT
VCC
VM
VI
tr = tf
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
VCC
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
2.7 V
2.7 V
3.0 to 3.6 V
1.5 V
Fig.9 Latch Enable (LE) input pulse width and latch enable input to output (Qn) propagation delays.
2003 Jun 25
9
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
V
I
OE input
V
M
t
GND
t
PLZ
PZL
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA813
INPUT
VCC
VM
VX
VY
VI
tr = tf
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
VCC
VCC
≤ 2.0 ns 0.5 × VCC VOL + 0.15 V
≤ 2.0 ns 0.5 × VCC VOL + 0.15 V
V
V
OH − 0.15 V
OH − 0.15 V
2.7 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
VOL + 0.3 V
OL + 0.3 V
V
OH − 0.3 V
3.0 to 3.6 V
V
VOH − 0.3 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.10 3-state enable and disable times.
2003 Jun 25
10
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
V
I
V
Dn input
M
GND
t
t
h
h
t
t
su
su
V
I
LE input
V
M
GND
MNA814
INPUT
tr = tf
VCC
VM
VI
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
0.5 × VCC VCC
0.5 × VCC VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.11 Data set-up and hold times for Dn input to LE input.
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
VCC
VI
CL
RL
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
VCC
VCC
30 pF
30 pF
1 kΩ
open
open
open
open
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
500 Ω
500 Ω
500 Ω
2.7 V 50 pF
2.7 V 50 pF
3.0 to 3.6 V
6 V
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.12 Load circuitry for switching times.
11
2003 Jun 25
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
PACKAGE OUTLINES
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
0.25
0.01
0.1
0.25
0.01
1.27
0.05
1.4
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
2003 Jun 25
12
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
2003 Jun 25
13
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
2003 Jun 25
14
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
Introduction to soldering surface mount packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
• below 220 °C (SnPb process) or below 245 °C (Pb-free
process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
– for all BGA and SSOP-T packages
Manual soldering
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
volume ≥ 350 mm3 so called thick/large packages.
• below 235 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2003 Jun 25
15
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(4)
suitable
PLCC(5), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(5)(6) suitable
not recommended(7)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Jun 25
16
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jun 25
17
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
NOTES
2003 Jun 25
18
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
NOTES
2003 Jun 25
19
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/02/pp20
Date of release: 2003 Jun 25
Document order number: 9397 750 11268
相关型号：
74ALVC574PW,112
74ALVC574 - Octal D-type flip-flop; positive edge trigger; 3-state TSSOP2 20-Pin
NXP
©2020 ICPDF网 联系我们和版权申明