74ALVCH16244DGG,11 [NXP]
74ALVC(H)16244 - 2.5 V / 3.3 V 16-bit buffer/line driver (3-State) TSSOP 48-Pin;
| 型号： | 74ALVCH16244DGG,11 |
| 厂家： | 
NXP |
| 描述： | 74ALVC(H)16244 - 2.5 V / 3.3 V 16-bit buffer/line driver (3-State) TSSOP 48-Pin PC 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总20页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74ALVC16244; 74ALVCH16244
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
Product specification
2003 May 14
Supersedes data of 1998 Jun 29
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
The 74ALVC16244; 74ALVCH16244 is a 16-bit
non-inverting buffer/line driver with 3-state outputs. The
device can be used as four 4-bit buffers, two 8-bit buffers
or one 16-bit buffer. The 3-state outputs are controlled by
the output enable inputs 1OE, 2OE, 3OE and 4OE. A
HIGH on nOE causes the outputs to assume a
high-impedance OFF-state.
• MultiByte flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum
noise and ground bounce
• Direct interface with TTL levels
• Bus hold on data inputs (74ALVCH16244 only)
• Output drive capability 50 Ω transmission lines at 85 °C
• Current drive ±24 mA at 3.0 V
The 74ALVCH16244 has active bus hold circuitry which is
provided to hold unused or floating data inputs at a valid
logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
• Complies with JEDEC standard no. 8-1 A
The 74ALVC16244 has 5 V tolerant inputs.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETERS
CONDITIONS
TYPICAL
1.9
UNIT
t
PHL/tPLH
propagation delay nAn to nYn
VCC = 2.5 V; CL = 30 pF
ns
ns
pF
V
CC = 3.3 V; CL = 50 pF
1.9
5.0
CI
input capacitance
CPD
power dissipation capacitance per buffer
notes 1 and 2
outputs enabled
outputs disabled
25
4
pF
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2003 May 14
2
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
FUNCTION TABLE
See note 1
INPUT
OUTPUT
nYn
nOE
nAn
L
L
L
H
X
L
H
Z
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74ALVC16244DL
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
48
48
48
48
SSOP48
SSOP48
TSSOP48
TSSOP48
plastic
plastic
plastic
plastic
SOT370-1
SOT370-1
SOT362-1
SOT362-1
74ALVCH16244DL
74ALVC16244DGG
74ALVCH16244DGG
2003 May 14
3
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
PINNING
PIN
SYMBOL
DESCRIPTION
PIN
SYMBOL
DESCRIPTION
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
3OE
4A3
4A2
GND
4A1
4A0
VCC
3A3
3A2
GND
3A1
3A0
2A3
2A2
GND
2A1
2A0
VCC
1A3
1A2
GND
1A1
1A0
2OE
output enable input (active LOW)
data input
1
2
1OE
1Y0
1Y1
GND
1Y2
1Y3
VCC
2Y0
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
3Y2
3Y3
VCC
4Y0
4Y1
GND
4Y2
4Y3
4OE
output enable input (active LOW)
data output
data input
3
data output
ground (0 V)
data input
4
ground (0 V)
data output
5
data input
6
data output
supply voltage
data input
7
supply voltage
data output
8
data input
9
data output
ground (0 V)
data input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ground (0 V)
data output
data input
data output
data input
data output
data input
data output
ground (0 V)
data input
ground (0 V)
data output
data input
data output
supply voltage
data input
supply voltage
data output
data input
data output
ground (0 V)
data input
ground (0 V)
data output
data input
data output
output enable input (active LOW)
output enable input (active LOW)
2003 May 14
4
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
handbook, halfpage
1OE
1Y0
1Y1
GND
1Y2
1Y3
1
2
3
4
5
6
7
8
9
48 2OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
2
3
5
6
13
14
16
17
47
36
35
33
handbook, halfpage
1A0
1Y0
1Y1
1Y2
1Y3
3A0
3A1
3A2
3Y0
3Y1
3Y2
3Y3
46
1A1
44
V
42
V
CC
1A2
CC
2Y0
2Y1
41 2A0
40 2A1
39 GND
38 2A2
37 2A3
36 3A0
35 3A1
34 GND
33 3A2
32 3A3
43
32
25
1A3
3A3
1
GND 10
2Y2 11
2Y3 12
3Y0 13
3Y1 14
GND 15
3Y2 16
3Y3 17
1OE
3OE
8
19
20
22
23
41
30
29
27
16244
2A0
2Y0
2Y1
2Y2
2Y3
4A0
4A1
4A2
4Y0
4Y1
4Y2
4Y3
40
9
2A1
11
12
38
2A2
37
26
24
2A3
4A3
V
18
31
V
CC
CC
48
4Y0 19
4Y1 20
GND 21
4Y2 22
4Y3 23
4OE 24
30 4A0
29 4A1
28 GND
27 4A2
26 4A3
25 3OE
2OE
4OE
MNA996
MNA995
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2003 May 14
5
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
1
handbook, halfpage
1EN
2EN
3EN
4EN
48
25
24
2
47
1
1
1
1
1
2
3
3
5
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
V
handbook, halfpage
CC
6
8
9
To internal
circuit
Data input
11
12
13
14
16
17
19
20
22
23
MNA998
4
MNA997
Fig.3 Logic symbol (IEEC/IEC).
Fig.4 Bus hold circuit.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
UNIT
maximum speed performance
V
CC = 2.5 V; CL = 30 pF
2.3
2.7
3.6
3.6
VCC
5.5
5.5
VCC
+85
20
V
V
V
V
V
V
V
VCC = 3.3 V; CL = 50 pF
low-voltage applications
for pins nAn with bus hold
for pins nAn without bus hold
for pins nOE
3.0
1.2
0
VI
input voltage
0
0
VO
output voltage
0
Tamb
tr, tf
operating temperature
input rise and fall times
in free air
−40
0
°C
VCC = 2.3 to 3.0 V
ns/V
ns/V
V
CC = 3.0 to 3.6 V
0
10
2003 May 14
6
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+4.6
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0
for data inputs with bus hold; note 1
−
−50
mA
V
VI
−0.5
VCC + 0.5
+5.5
for data inputs without bus hold; note 1 −0.5
V
for control pins; note 1
VO > VCC or VO < 0
note 1
−0.5
−
+5.5
V
IOK
VO
IO
output diode current
output voltage
±50
mA
V
−0.5
−
VCC + 0.5
±50
output source or sink current VO = 0 to VCC
mA
mA
°C
ICC, IGND VCC or GND current
−
±100
Tstg
Ptot
storage temperature
power dissipation
−65
+150
Tamb = −40 to +85 °C; note 2
SSOP48 package
−
−
850
600
mW
mW
TSSOP48 package
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SSOP48 packages: above 55 °C the value of Ptot derates linearly with 11.3 mW/K.
For TSSOP48 packages: above 55 °C the value of Ptot derates linearly with 8 mW/K.
2003 May 14
7
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input
1.2
1.8
VCC
0.7 × VCC
−
−
−
−
−
V
V
V
V
V
V
V
V
voltage
0.9
1.2
1.5
−
2.3 to 2.7 1.7
2.7 to 3.6 2.0
VIL
LOW-level input
voltage
1.2
−
−
−
−
GND
0.2 × VCC
0.7
1.8
0.9
1.2
1.5
2.3 to 2.7
2.7 to 3.6
0.8
VOH
HIGH-leveloutput VI = VIH or VIL
voltage
IO = −100 µA
1.8 to 3.6
1.8
VCC − 0.2
VCC − 0.4
VCC − 0.3
VCC − 0.5
VCC − 0.6
VCC − 0.5
VCC − 1.0
VCC
−
−
−
−
−
−
−
V
V
V
V
V
V
V
IO = −6 mA
IO = −6 mA
V
V
V
V
V
V
CC − 0.10
2.3
CC − 0.08
CC − 0.17
CC − 0.26
CC − 0.14
CC − 0.28
IO = −12 mA
2.3
IO = −18 mA
2.3
IO = −12 mA
2.7
IO = −24 mA
3.0
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 100 µA
1.8 to 3.6
1.8
−
−
−
−
−
−
−
−
GND
0.09
0.07
0.15
0.23
0.14
0.27
0.1
0.20
0.30
0.20
0.40
0.60
0.40
0.55
5
V
IO = 6 mA
IO = 6 mA
IO = 12 mA
IO = 18 mA
IO = 12 mA
IO = 24 mA
V
2.3
V
2.3
V
2.3
V
2.7
V
3.0
V
ILI
input leakage
current
data pin with bus hold;
VI = VCC or GND
1.8 to 3.6
µA
data pin without bus hold; 1.8 to 3.6
VI = 5.5 V or GND
−
−
0.1
0.1
5
5
µA
µA
control pin;
1.8 to 3.6
VI = 5.5 V or GND
I
IHZ, IILZ
3-state input
current for
common I/O pins
VI = VCC or GND
1.8 to 2.7
3.6
−
−
0.1
0.1
10
15
µA
µA
IOZ
3-state output
OFF-state current VI = VIH or VIL
VI = VCC or GND;
1.8 to 2.7
3.6
−
−
−
−
0.1
0.1
0.1
0.2
5
µA
µA
µA
µA
10
20
40
ICC
quiescent supply VI = VCC or GND; IO = 0
current
1.8 to 2.7
2.3 to 3.6
2003 May 14
8
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
TEST CONDITIONS
OTHER
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
VCC (V)
∆ICC
additional
VI =VCC − 0.6 V; IO = 0
quiescent supply
current per pin
data pin with bus hold
2.7 to 3.6
−
150
750
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
data pin without bus hold 2.7 to 3.6
−
5
500
500
−
control pin
2.7 to 3.6
2.3
−
5
IBHL
bus hold LOW
sustaining current
VI = 0.7 V; note 2
VI = 0.8 V; note 2
VI = 1.7 V; note 2
VI = 2.0 V; note 2
note 2
45
75
−
3.0
150
−
IBHH
bus hold HIGH
sustaining current
2.3
−45
−
−
3.0
−75
−175
−
IBHLO
bus hold LOW
overdrive current
2.7
300
−
−
−
−
−
3.6
450
−
IBHHO
bus hold HIGH
overdrive current
note 2
2.7
−300
−450
−
3.6
−
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Valid for data inputs of bus hold parts.
2003 May 14
9
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.0 ns and CL = 30 pF for VCC < 2.7 V; tr = tf ≤ 2.5 ns and CL = 50 pF for VCC ≥ 2.7 V.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
T
amb = −40 to +85 °C; note 1
tPHL/tPLH propagation
delay nAn to nYn
see Figs 5 and 7
1.2
1.8
−
5.8
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
2.8
1.9
2.1
1.9
8.4
3.8
2.5
2.9
2.3
5.9
3.1
2.1
3.0
2.7
5.1
3.7
3.6
3.0
−
2.3 to 2.7 1.0
2.7 1.0
3.0 to 3.6 1.0
t
PZH/tPZL
3-state output
see Figs 6 and 7
see Figs 6 and 7
1.2
1.8
−
enable time
nOE to nYn
1.5
7.1
4.9
4.9
4.0
−
2.3 to 2.7 1.0
2.7 1.0
3.0 to 3.6 1.0
tPHZ/tPLZ
3-state output
disable time
nOE to nYn
1.2
1.8
−
1.5
5.4
4.1
4.5
4.1
2.3 to 2.7 1.0
2.7 1.0
3.0 to 3.6 1.0
Note
1. All typical values are measured at Tamb = 25 °C.
Typical values for VCC = 2.3 to 2.7 V are measured at VCC = 2.5 V.
Typical values for VCC = 3.3 to 3.6 V are measured at VCC = 3.3 V.
AC WAVEFORMS
V
handbook, halfpage
nAn input
I
V
M
GND
t
t
PLH
PHL
V
OH
V
nYn output
M
V
OL
MNB013
VM = 0.5VCC at VCC < 2.7 V and VM = 1.5 V at VCC ≥ 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.5 Input (nAn) to output (nYn) propagation delays.
10
2003 May 14
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
V
handbook, full pagewidth
I
nOE input
V
M
t
GND
t
PLZ
PZL
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA999
VM = 0.5VCC at VCC < 2.7 V and VM = 1.5 V at VCC ≥ 2.7 V.
VX = VOL + 0.15 V at VCC < 2.7 V and VX = VOL + 0.3 V at VCC ≥ 2.7 V.
VY = VOH − 0.15 V at VCC < 2.7 V and VY = VOH − 0.3 V at VCC ≥ 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.6 3-state enable and disable times.
S1
2 × V
CC
open
GND
V
CC
R
L
500 Ω
V
V
O
I
PULSE
D.U.T.
GENERATOR
R
500 Ω
L
C
R
L
T
MNA755
TEST
S1
VCC
VI
t
PLH/tPHL open
<2.7 V
VCC
tPLZ/tPZL 2 × VCC
2.7 to 3.6 V 2.7 V
tPHZ/tPZH GND
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
11
2003 May 14
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
PACKAGE OUTLINES
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
2003 May 14
12
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.25
0.5
1
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
2003 May 14
13
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
Introduction to soldering surface mount packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
• below 220 °C (SnPb process) or below 245 °C (Pb-free
process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
– for all the BGA packages
Manual soldering
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
volume ≥ 350 mm3 so called thick/large packages.
• below 235 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2003 May 14
14
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
PLCC(4), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(4)(5) suitable
not recommended(6)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 May 14
15
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 May 14
16
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
NOTES
2003 May 14
17
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
NOTES
2003 May 14
18
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
NOTES
2003 May 14
19
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/03/pp20
Date of release: 2003 May 14
Document order number: 9397 750 10793
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