74ALVCH16373DGG,118_技术文档

74ALVCH16373

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

Rev. 04 — 31 May 2010

Product data sheet

1. General description

The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for

each latch and 3-state outputs for bus oriented applications.

Incorporates bus hold data inputs which eliminate the need for external pull-up or

pull-down resistors to hold unused inputs.

One latch enable (LE) input and one output enable (OE) are provided per 8-bit section.

The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state

true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition

the latches are transparent, therefore a latch output will change each time its

corresponding D-input changes.

When LE is LOW, the latches store the information that was present at the nDn inputs at a

set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents

of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the

high-impedance OFF-state. Operation of the OE input does not affect the state of the

latches.

2. Features and benefits

Wide supply voltage range from 1.2 V to 3.6 V

Complies with JEDEC standard JESD8-B

CMOS low power consumption

MULTIBYTE flow-through standard pin-out architecture

Low inductance multiple V_CCand GND pins for minimum noise and ground bounce

Direct interface with TTL levels

All data inputs have bus hold

Output drive capability 50 Ω transmission lines at 85 °C

Current drive ±24 mA at V_CC= 3.0 V

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Temperature range Package

Name

Description

Version

74ALVCH16373DL

−40 °C to +85 °C

SSOP48

plastic shrink small outline package; 48 leads;

body width 7.5 mm

SOT370-1

74ALVCH16373DGG −40 °C to +85 °C

TSSOP48

plastic thin shrink small outline package;

48 leads; body width 6.1 mm

SOT362-1

4. Functional diagram

1

24

1OE

2OE

47

46

44

43

41

40

38

37

36

35

33

32

30

29

27

26

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2

3

5

6

8

9

11

12

13

14

16

17

19

20

22

23

1LE

48

2LE

25

001aam007

Fig 1. Logic symbol

74ALVCH16373_4

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Product data sheet

Rev. 04 — 31 May 2010

2 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

1

1OE

1LE

2OE

2LE

1EN

C1

48

24

25

2EN

C4

47

46

44

43

41

40

38

37

36

35

33

32

30

29

27

26

2

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

3D

1

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

3

5

6

8

9

11

12

13

14

16

17

19

20

22

23

4D

2

001aam009

Fig 2. IEC logic symbol

V

CC

data input

to internal circuit

mna705

Fig 3. Bus hold circuit

1D0

D

Q

1Q0

2D0

D

Q

2Q0

LATCH

1

9

LE LE

1LE

2LE

1OE

2OE

to 7 other channels

001aam010

Fig 4. Logic diagram

74ALVCH16373_4

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Product data sheet

Rev. 04 — 31 May 2010

3 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

5. Pinning information

5.1 Pinning

74ALVCH16373

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1OE

1LE

1D0

1D1

GND

1D2

1D3

1Q0

1Q1

GND

1Q2

1Q3

3

4

5

6

7

V

CC

V

CC

8

1Q4

1Q5

GND

1Q6

1Q7

2Q0

2Q1

GND

2Q2

2Q3

1D4

1D5

GND

1D6

1D7

2D0

2D1

GND

2D2

2D3

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

V

CC

2Q4

2Q5

GND

2Q6

2Q7

2OE

2D4

2D5

GND

2D6

2D7

2LE

001aam008

Fig 5. Pin configuration

74ALVCH16373_4

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Product data sheet

Rev. 04 — 31 May 2010

4 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

5.2 Pin description

Table 2.

Pin description

Symbol

Description

1OE, 2OE

1Q0 to 1Q7

2Q0 to 2Q7

GND

1, 24

output enable input (active LOW)

data outputs

2, 3, 5, 6, 8, 9, 11, 12

13, 14, 16, 17, 19, 20, 22, 23

4, 10, 15, 21, 28, 34, 39, 45

7, 18, 31, 42

data outputs

ground (0 V)

V_CC

positive supply voltage

data inputs

1D0 to 1D7

2D0 to 2D7

1LE, 2LE

47, 46, 44, 43, 41, 40, 38, 37

36, 35, 33, 32, 30, 29, 27, 26

48, 25

data inputs

latch enable input (active HIGH)

6. Functional description

6.1 Function table

Table 3.

Function table^[1]

Inputs

Internal latches Outputs nQn

Operating mode

nOE

L

nLE

H

L

nDn

L

H

l

L

enable and read register

(transparent mode)

L

H

L

H

L

latch and read register

(hold mode)

L

h

l

H

L

H

Z

H

L

latch register and disable outputs

H

L

h

H

[1] H = HIGH voltage level;

L = LOW voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;

I = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;

Z = high-impedance OFF-state.

74ALVCH16373_4

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Product data sheet

Rev. 04 — 31 May 2010

5 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

−0.5

−50

−0.5

-

Max

+4.6

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

control inputs

data inputs

+4.6

V_CC+ 0.5

±50

V

I_OK

V_O

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

mA

V

[1]

−0.5

-

V_CC+ 0.5

±50

I_O

output current

V_O= 0 V to V_CC

mA

°C

I_CC

I_GND

T_stg

P_tot

supply current

-

100

ground current

−100

−65

-

storage temperature

total power dissipation

+150

T_amb= −40 °C to +125 °C

SSOP48 package

[2]

[3]

-

850

600

mW

TSSOP48 package

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Above 55 °C the value of P_totderates linearly with 11.3 mW/K.

[3] Above 55 °C the value of P_totderates linearly with 8 mW/K.

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

maximum speed performance

C_L= 30 pF

2.3

3.0

1.2

0

-

2.7

3.6

V_CC

5.5

V_CC

+85

20

V

C_L= 50 pF

V

low voltage applications

data inputs

V

V_I

input voltage

V

control inputs

0

V

V_O

output voltage

0

V

T_amb

Δt/ΔV

ambient temperature

in free air

−40

0

°C

ns/V

input transition rise and fall rate V_CC= 2.3 V to 3.0 V

V_CC= 3.0 V to 3.6 V

0

10

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Product data sheet

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74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

T_amb= −40 °C to +85 °C

V_IH

HIGH-level input

voltage

V_CC= 1.2 V

V_CC

-

V

V_CC= 1.8 V

0.7V_CC

0.9

1.2

1.5

-

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

1.7

-

2.0

V_IL

LOW-level input

voltage

-

0

V_CC= 1.8 V

0.9

1.2

1.5

0.2V_CC

0.7

0.8

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

V_OH

HIGH-level output

voltage

I_O= −100 μA; V_CC= 1.8 V to 3.6 V

I_O= −6 mA; V_CC= 1.8 V

I_O= −6 mA; V_CC= 2.3 V

I_O= −12 mA; V_CC= 2.3 V

I_O= −12 mA; V_CC= 2.7 V

I_O= −18 mA; V_CC= 2.3 V

I_O= −24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

V_CC− 0.2

V_CC− 0.4

V_CC

-

V

V_CC− 0.1

V_CC− 0.3 V_CC− 0.08

V_CC− 0.5 V_CC− 0.17

V_CC− 0.5 V_CC− 0.14

V_CC− 0.6 V_CC− 0.26

V_CC− 1.0 V_CC− 0.28

V_OL

LOW-level output

voltage

I_O= 100 μA; V_CC= 1.8 V to 3.6 V

I_O= 6 mA; V_CC= 1.8 V

I_O= 6 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 18 mA; V_CC= 2.3 V

I_O= 24 mA; V_CC= 3.0 V

V_CC= 1.8 V to 3.6 V

control input; V_I= 5.5 V or GND

data input; V_I= V_CCor GND

V_I= V_IHor V_IL; V_O= V_CCor GND

V_CC= 1.8 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_CCor GND

-

0

0.20

0.30

0.20

0.40

0.60

0.55

V

0.09

0.07

0.15

0.14

0.23

0.27

I_I

input leakage current

-

0.1

5

μA

I_OZ

I_LIZ

I_CC

OFF-state output

current

-

0.1

5

μA

10

OFF-state input

leakage current

V_CC= 1.8 V to 2.7 V

V_CC= 3.6 V

-

0.1

10

15

μA

supply current

V_I= V_CCor GND; I_O= 0 A;

V_CC= 1.8 V to 2.7 V

V_CC= 2.7 V to 3.6 V

-

0.2

40

μA

74ALVCH16373_4

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Product data sheet

Rev. 04 — 31 May 2010

7 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

Table 6.

Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

ΔI_CC

additional supply

current

V_I= V_CC− 0.6 V; I_O= 0 A;

V_CC= 2.7 V to 3.6 V

per control input

per data I/O input

-

5

500

μA

pF

150

750

[2]

I_BHL

I_BHH

I_BHLO

I_BHHO

C_I

bus hold LOW current V_CC= 2.3 V; V_I= 0.7 V

V_CC= 3.0 V; V_I= 0.8 V

45

-

75

150

bus hold HIGH current V_CC= 2.3 V; V_I= 1.7 V

V_CC= 3.0 V; V_I= 2.0 V

−45

−75

300

450

−300

−450

-

−175

bus hold LOW

overdrive current

V_CC= 2.7 V

V_CC= 3.6 V

V_CC= 2.7 V

V_CC= 3.6 V

-

bus hold HIGH

overdrive current

-

input capacitance

5.0

[1] All typical values are measured at T_amb= 25 °C.

[2] Valid for data inputs of bus hold parts only.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max Unit

T_amb= −40 °C to +85 °C

[2]

[3]

t_pd

propagation delay

nDn to nQn; see Figure 6

V_CC= 1.2 V

-

8.8

3.2

2.1

2.3

2.1

-

ns

V_CC= 1.8 V

1.5

1.0

5.7

3.9

3.7

3.3

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

[4]

[2]

V_CC= 3.0 V to 3.6 V

nLE to nQn; see Figure 7

V_CC= 1.2 V

-

7.4

3.4

2.2

-

ns

V_CC= 1.8 V

1.5

1.0

5.9

3.9

3.5

3.2

[3]

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

[4]

[2]

V_CC= 3.0 V to 3.6 V

nOE to nQn; see Figure 8

V_CC= 1.2 V

t_en

enable time

-

8.9

4.0

2.6

2.9

2.3

-

ns

V_CC= 1.8 V

1.5

1.0

7.3

5.2

4.9

4.2

[3]

[4]

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

74ALVCH16373_4

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Product data sheet

Rev. 04 — 31 May 2010

8 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

Table 7.

Dynamic characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max Unit

[2]

t_dis

disable time

nOE to nQn; see Figure 8

V_CC= 1.2 V

-

8.9

3.2

2.2

3.1

2.8

-

ns

V_CC= 1.8 V

1.5

1.0

5.6

4.1

4.7

4.1

[3]

[4]

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nLE HIGH; see Figure 7

V_CC= 1.8 V

t_W

pulse width

set-up time

hold time

3.5

3.0

2.5

1.0

-

ns

[3]

[4]

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nDn to nLE; see Figure 9

V_CC= 1.8 V

t_su

1.0

−0.1

0.0

-

ns

[3]

[4]

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nDn to nLE; see Figure 9

V_CC= 1.8 V

t_h

1.2

1.5

1.2

0.1

0.2

0.4

0.2

-

ns

[3]

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

[4]

[5]

V_CC= 3.0 V to 3.6 V

per flip-flop; V_I= GND to V_CC

outputs enabled

outputs disabled

C_PD

power dissipation

capacitance

-

16

10

-

pF

[1] All typical values are measured at T_amb= 25 °C.

[2] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

.

[3] Typical values are measured at V_CC= 2.5 V.

[4] Typical values are measured at V_CC= 3.3 V.

[5] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in Volts;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

74ALVCH16373_4

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Product data sheet

Rev. 04 — 31 May 2010

9 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

11. Waveforms

V

I

V

t

V

M

nDn input

M

GND

t

PHL

PLH

V

OH

nQn output

V

M

V

OL

001aam011

Measurement points are given in Table 8.

V_OLand V_OHare typical output levels that occur with the output load.

Fig 6. Propagation delay, input (nDn) to data output (nQn)

V

I

nLE input

V

M

V

t

M

GND

t

W

t

PHL

PLH

V

OH

nQn output

V

M

V

M

V

OL

001aam012

Measurement points are given in Table 8.

V_OLand V_OHare typical output levels that occur with the output load.

Fig 7. Propagation delay, latch enable input (nLE) to data output (nQn), and pulse width

V

I

nOE input

V

M

GND

t

PZL

PLZ

V

CC

nQn output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

nQn output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aal795

Measurement points are given in Table 8.

V_OLand V_OHare typical output levels that occur with the output load.

Fig 8. 3-state enable and disable times

74ALVCH16373_4

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Product data sheet

Rev. 04 — 31 May 2010

10 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

V

I

nDn input

V

M

GND

t

h

t

su

V

I

nLE input

V

M

GND

001aam013

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 9. Data setup and hold times for input (nDn) to input (nLE)

Table 8.

Measurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

V_X

V_Y

2.3 V to 2.7 V and V_CC

< 2.3 V

0.5

V_OL+ 0.15 V

V_OH− 0.15 V

2.7 V

1.5 V

V_OL+ 0.3 V

V_OH− 0.3 V

3.0 V to 3.6 V

74ALVCH16373_4

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Product data sheet

Rev. 04 — 31 May 2010

11 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

12. Test information

V

EXT

V

CC

R

L

V

O

I

G

DUT

R

C

R

T

L

mna616

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 10. Load circuit for measuring switching times

Table 9.

Test data

Supply voltage

V_CC

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

t_PHZ, t_PZH

2.3 V to 2.7 V and

< 2.3 V

V_CC

≤ 2.0 ns

30 pF

500 Ω

2 × V_CC

GND

2.7 V

2.5 ns

50 pF

500 Ω

open

2 × V_CC

GND

3.0 V to 3.6 V

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Product data sheet

Rev. 04 — 31 May 2010

12 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

13. Package outline

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm

SOT370-1

D

E

A

X

c

y

H

v

M

A

E

Z

25

48

Q

p

A

2

A

(A )

3

1

θ

pin 1 index

L

24

1

detail X

w

M

b

p

e

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

Q

v

w

y

Z

θ

p

1

2

3

max.

8^o

0^o

0.4

0.2

2.35

2.20

0.3

0.2

0.22 16.00

0.13 15.75

7.6

7.4

10.4

10.1

1.0

0.6

1.2

1.0

0.85

0.40

mm

2.8

0.25

0.635

1.4

0.25

0.18

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT370-1

MO-118

Fig 11. Package outline SOT370-1 (SSOP48)

74ALVCH16373_4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 04 — 31 May 2010

13 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

E

D

A

X

c

H

v

M

A

y

E

Z

48

25

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

24

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

12.6

12.4

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.8

0.4

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT362-1

MO-153

Fig 12. Package outline SOT362-1 (TSSOP48)

74ALVCH16373_4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 04 — 31 May 2010

14 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

14. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

TTL

Transistor-Transistor Logic

15. Revision history

Table 11. Revision history

Document ID

Release date

20100531

Data sheet status

Change notice

Supersedes

74ALVCH16373_4

Modifications:

Product data sheet

-

74ALVCH16373_3

–

The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

–

Legal texts have been adapted to the new company name where appropriate.

Table 7 “Dynamic characteristics”: voltage ranges corrected.

Table 2 “Pin description”: nQn pin descriptions corrected.

74ALVCH16373_3

74ALVCH16373_2

74ALVCH16373_1

19990920

19980629

19970321

Product specification

-

74ALVCH16373_2

74ALVCH16373_1

-

74ALVCH16373_4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 04 — 31 May 2010

15 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

suitable for use in medical, military, aircraft, space or life support equipment,

16.2 Definitions

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

74ALVCH16373_4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 04 — 31 May 2010

16 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74ALVCH16373_4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 04 — 31 May 2010

17 of 18

74ALVCH16373

NXP Semiconductors

2.5 V/3.3 V 16-bit D-type transparent latch; 3-state

18. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6

6.1

7

Functional description . . . . . . . . . . . . . . . . . . . 5

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Test information. . . . . . . . . . . . . . . . . . . . . . . . 12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

8

9

10

11

12

13

14

15

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 17

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 31 May 2010

Document identifier: 74ALVCH16373_4


型号：	74ALVCH16373DGG,118
厂家：	NXP
描述：	IC ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48, Bus Driver/Transceiver 驱动光电二极管输出元件逻辑集成电路
文件：	总18页 (文件大小：473K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74ALVCH16373DGG,118 [NXP]

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