74ALVCH16623DG-T [NXP]
IC ALVC/VCX/A SERIES, 16-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-362, TSSOP-48, Bus Driver/Transceiver;
| 型号： | 74ALVCH16623DG-T |
| 厂家： | 
NXP |
| 描述： | IC ALVC/VCX/A SERIES, 16-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-362, TSSOP-48, Bus Driver/Transceiver |
| 文件： | 总16页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74ALVCH16623
16-bit transceiver with dual enable;
3-state
Product specification
1999 Sep 20
Supersedes data of 1998 Aug 31
File under Integrated Circuits, IC24
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
FEATURES
DESCRIPTION
• Complies with JEDEC standard
no. 8-1A
The 74ALVCH16623 is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
• CMOS low power consumption
• Direct interface with TTL levels
The 74ALVCH16623 is a 16-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions.
• MULTIBYTE flow-through
This 16-bit bus transceiver is designed for asynchronous two-way
standard pin-out architecture
communication between data buses. The control function implementation
allows maximum flexibility in timing. This device allows data transmission from
the A bus to the B bus or from the B bus to the A bus, depending upon the logic
levels at the enable inputs (nOEAB, nOEBA). The enable inputs can be used to
disable the device so that the buses are effectively isolated. The dual enable
function configuration gives this transceiver the capability to store data by
simultaneous enabling of nOEAB and nOEBA. Each output reinforces its input in
this transceiver configuration. Thus, when all control inputs are enabled and all
other data sources to the four sets of the bus lines are at high-impedance
OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes
appearing on the two double sets of buses will be complementary. This device
can be used as two 8-bit transceivers or one 16-bit transceiver.
• All data inputs have bus hold
circuitry
• Output drive capability 50 Ω
transmission lines at 85 °C
• Current drive ±24 mA at 3.0 V.
To ensure the high-impedance state during power-on or power-down, OEBA
should be tied to VCC through a pull-up resistor and OEAB should be tied to GND
through a pull-down resistor; the minimum value of the resistor is determined
by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a
valid logic level.
QUICK REFERENCE DATA
Ground = 0; Tamb = 25 °C; tr = tf = 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
2.0
UNIT
t
PHL/tPLH
propagation delay nAn, nBn to nBn, nAn CL = 30 pF; VCC = 2.5 V
CL = 50 pF; VCC = 3.3 V
ns
ns
pF
pF
1.9
CI/O
CI
input/output capacitance
10.0
3.0
input capacitance
CPD
power dissipation capacitance per buffer notes 1 and 2
outputs enabled
35
5
pF
pF
outputs disabled
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
CL = output load capacitance in pF;
fo = output frequency in MHz;
VCC = supply voltage in Volts;
Σ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC
1999 Sep 20
.
2
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PACKAGE
TEMPERATURE RANGE
PINS
MATERIAL
CODE
74ALVCH16623DGG
−40 to +85 °C
48
TSSOP
plastic
SOT362-1
FUNCTION TABLE
See note 1.
INPUTS
INPUTS/OUTPUTS
nOEAB
nOEBA
nAn
nBn
L
H
L
L
H
H
L
A = B
inputs
Z
inputs
B = A
Z
H
A = B
B = A
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
PINNING
PIN
SYMBOL
DESCRIPTION
1, 24
1OEAB, 2OEAB
1B0 to 1B7
GND
output enable input (active HIGH)
data inputs/outputs
2, 3, 5, 6, 8, 9, 11, 12
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
ground (0 V)
VCC
DC supply voltage
13, 14, 16, 17, 19, 20, 22, 23
25, 48
2B0 to 2B7
2OEBA, 1OEBA
2A7 to 2A0
1A7 to 1A0
data inputs/outputs
output enable input (active LOW)
data inputs/outputs
26, 27, 29, 30, 32, 33, 35, 36
37, 38, 40, 41, 43, 44, 46, 47
data inputs/outputs
1999 Sep 20
3
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
page
1OE
1
2
3
4
5
6
7
8
9
48 1OE
AB
BA
1B
47 1A
0
0
1
1OE
1OE
2OE
2OE
BA
BA
1B
46 1A
1
48
1
25
24
36
GND
45 GND
AB
AB
1B
2
44 1A
2
1B
3
43 1A
3
2A
0
1A
0
V
42
V
CC
CC
47
46
1B
1B
1B
1B
1B
1B
1B
1B
2B
0
0
1
2
3
4
5
6
7
1B
4
41 1A
40 1A
2
3
13
4
5
2A
1
1A
1
1B
5
35
33
2B
1
GND 10
39 GND
14
1A
2
2A
2
1B 11
6
38 1A
6
44
2B
2
1B 12
7
37 1A
7
5
6
16
16623
1A
3
2A
3
2B 13
0
36 2A
0
43
41
40
32
30
29
2B
3
17
2B 14
1
35 2A
1
2A
4
1A
4
GND 15
34 GND
2B
4
8
19
2B 16
2
33 2A
2
2A
5
1A
5
2B 17
3
32 2A
3
2B
5
9
20
V
18
31
V
CC
CC
2A
6
1A
6
38
37
27
26
2B 19
4
30 2A
29 2A
4
5
2B
6
11
12
22
2B 20
5
1A
7
2A
7
GND 21
28 GND
2B
7
23
2B 22
6
27 2A
6
MNA308
2B
23
24
26 2A
7
7
25
2OE
2OE
BA
AB
MNA307
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1999 Sep 20
4
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
48
25
24
handbook, halfpage
1EN1
2EN1
2EN2
1
1EN2
1
1
2
13
47
36
V
CC
handbook, halfpage
2
2
46
44
43
41
40
38
37
3
5
35
33
32
30
29
27
26
14
16
17
19
20
22
23
data
input
to internal circuit
6
8
MNA310
9
11
12
MNA309
Fig.3 IEC logic symbol.
Fig.4 Bus hold circuit.
1999 Sep 20
5
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
for max. speed performance
for max. speed performance
for low-voltage applications
DC input voltage
CL = 30 pF
2.3
2.5
2.7
3.6
3.6
V
CL = 50 pF
3.0
1.2
0
3.3
2.4
−
V
V
VI
VCC
VCC
+85
20
V
VO
DC output voltage
0
−
V
Tamb
tr, ft
operating ambient temperature
input rise and fall times
in free air
−40
0
−
°C
ns/V
ns/V
VCC = 2.3 to 3.0 V
−
VCC = 3.0 to 3.6 V
0
−
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
−
MAX.
+4.6
UNIT
VCC
IIK
V
DC input diode current
DC input voltage
VI < 0
note 1
−50
mA
V
VI
−0.5
−
+4.6
IOK
VO
IO
DC output diode current
DC output voltage
VO > VCC or VO < 0
note 1
±50
mA
V
−0.5
−
VCC + 0.5
±50
DC output source or sink current VO = 0 to VCC
mA
mA
°C
ICC, IGND DC VCC or GND current
−
±100
+150
600
Tstg
Ptot
storage temperature
power dissipation
−65
−
for temperature range: −40 to +125 °C;
mW
note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of Ptot derates linearly with 8 mW/K.
1999 Sep 20
6
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
DC CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
OTHER VCC (V)
2.3 to 2.7 1.7
2.7 to 3.6 2.0
Tamb = −40 TO +85 °C
SYMBOL
PARAMETER
UNIT
VI (V)
MIN.
TYP.(1)
1.2
MAX.
VIH
HIGH-level input voltage
−
V
V
V
1.5
1.2
1.5
−
VIL
LOW-level input voltage
2.3 to 2.7
2.7 to 3.6
−
−
0.7
0.8
−
VOH
HIGH-level output voltage VIH or VIL IO = −100 µA 2.3 to 3.6 VCC − 0.2 VCC
IO = −6 mA
2.3
V
V
V
V
V
−
−
−
−
−
−
CC − 0.3 VCC − 0.08
−
IO = −12 mA 2.3
IO = −12 mA 2.7
IO = −12 mA 3.0
IO = −24 mA 3.0
CC − 0.6 VCC − 0.26
−
CC − 0.5 VCC − 0.14
−
CC − 0.6 VCC − 0.09
−
CC − 1.0 VCC − 0.28
−
VOL
LOW-level output voltage
input leakage current
VIH or VIL IO = 100 µA
IO = 6 mA
2.3 to 3.6
2.3
GND
0.07
0.15
0.14
0.27
0.1
0.20
0.40
0.70
0.40
0.55
5
V
IO = 12 mA
IO = 12 mA
IO = 24 mA
2.3
2.7
3.0
Il
VCC or
GND
2.3 to 3.6
µA
µA
µA
µA
IOZ
ICC
∆ICC
3-state output OFF-state
current
VIH or VIL VO = VCC or 2.3 to 3.6
GND
−
−
−
0.1
0.2
150
10
quiescent supply voltage
VCC or
GND
IO = 0
2.3 to 3.6
40
additional quiescent supply
current given per data I/O
pin with bus hold
VCC − 0.6 IO = 0
2.3 to 3.6
750
IBHL
bus hold LOW sustaining
current
0.7(2)
0.8(2)
2.3(2)
3.0(2)
2.3(2)
3.0(2)
3.6(2)
45
−
−
−
−
−
−
µA
µA
75
150
IBHH
bus hold HIGH sustaining 1.7(2)
current
−45
−75
500
2.0(2)
−175
IBHLO
IBHHO
bus hold LOW overdrive
current
−
µA
µA
bus hold LOW overdrive
current
3.6(2)
−500
−
−
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Valid for data inputs of bus hold parts.
1999 Sep 20
7
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
AC CHARACTERISTICS FOR VCC = 2.3 TO 2.7 V
Ground = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF.
TEST CONDITIONS
T
amb = −40 TO +85 °C
SYMBOL
tPHL/tPLH
PARAMETER
propagation delay
UNIT
ns
WAVEFORMS
VCC (V)
MIN. TYP.(1) MAX.
see Figs 5 and 8
2.3 to 2.7 1.0
2.3 to 2.7 1.0
2.3 to 2.7 1.0
2.3 to 2.7 1.0
2.3 to 2.7 1.0
2.4
3.0
3.0
2.8
2.4
3.5
5.0
5.1
4.5
4.0
nAn, nBn to nBn, nAn
tPZH/tPZL
tPHZ/tPLZ
tPZH/tPZL
3-state output enable time
nOEAB to nBn
see Figs 7 and 8
see Figs 6 and 8
see Figs 7 and 8
see Figs 6 and 8
ns
ns
ns
ns
3-state output disable time
nOEBA to nAn
3-state output enable time
nOEAB to nBn
tPHZ/tPLZ
3-state output disable time
nOEBA to nAn
Note
1. All typical values are measured at Tamb = 25 °C and VCC = 2.5 V.
AC CHARACTERISTICS FOR VCC = 2.7 V AND VCC = 3.0 TO 3.6 V
Ground = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF.
TEST CONDITIONS
Tamb = −40 TO +85 °C
SYMBOL
PHL/tPLH
PARAMETER
UNIT
WAVEFORMS
VCC (V)
MIN.
TYP.(1)
MAX.
3.4
t
propagation delay
nAn, nBn to nBn, nAn
see Figs 5 and 8
2.7
−
2.5
ns
ns
ns
ns
ns
3.0 to 3.6 1.0
2.7
3.0 to 3.6 1.0
2.7
3.0 to 3.6 1.0
2.7
3.0 to 3.6 1.0
2.7
3.0 to 3.6 1.0
2.6(2)
3.1
4.5
4.0
5.0
4.2
5.4
4.6
4.5
4.3
tPZH/tPZL
3-state output enable time
nOEAB to nBn
see Figs 7 and 8
−
2.8
2.6(2)
3.3
2.8(2)
tPHZ/tPLZ
3-state output disable time see Figs 6 and 8
nOEBA to nAn
−
tPZH/tPZL
3-state output enable time
nOEAB to nBn
see Figs 7 and 8
−
3.8
3.3(2)
3.2
3.0(2)
tPHZ/tPLZ
3-state output disable time see Figs 6 and 8
nOEBA to nAn
−
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Typical values at VCC = 3.3 V.
1999 Sep 20
8
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
AC WAVEFORMS
Notes: VCC = 2.3 to 2.7 V
VM = 0.5VCC
;
VX = VOL + 150 mV;
VY = VOH − 150 mV;
VI = VCC
;
VOL and VOH are typical output voltage drop that occur
with the output load.
V
handbook, halfpage
nA , nB
I
n
n
V
Notes: VCC = 3.0 to 3.6 V and VCC = 2.7 V
M
input
GND
VM = 1.5 V;
t
t
PHL
PLH
VX = VOL + 300 mV;
VY = VOH − 300 mV;
VI = 2.7 V;
V
OH
nB , nA
n
output
n
V
M
MNA311
V
OL
VOL and VOH are typical output voltage drop that occur
with the output load.
Fig.5 The input nAn, nBn to output nBn, nAn
propagation delay times.
V
I
nOE
input
V
BA
M
GND
t
t
PLZ
PZL
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA312
Fig.6 3-state enable and disable times for nOEBA input.
9
1999 Sep 20
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
V
I
nOE
input
V
AB
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA313
Fig.7 3-state enable and disable times for nOEAB times.
S1
2 × V
CC
open
GND
V
CC
R
500 Ω
L
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
50 pF
R
L
500 Ω
L
R
T
MNA296
Definitions for test circuit.
TEST
S1
open
CL = load capacitance including jig and probe capacitance
(See Chapter “AC characteristics”).
VCC
VI
t
PLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL = load resistance.
<2.7 V
VCC
2 × VCC
RT = termination resistance should be equal to the output impedance
Zo of the pulse generator.
2.7 to 3.6 V 2.7 V
GND
Fig.8 Load circuitry for switching times.
10
1999 Sep 20
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
PACKAGE OUTLINE
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.25
0.5
1
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-02-03
95-02-10
SOT362-1
MO-153ED
1999 Sep 20
11
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Sep 20
12
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 20
13
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
NOTES
1999 Sep 20
14
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
NOTES
1999 Sep 20
15
Philips Semiconductors – a worldwide company
Argentina: see South America
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Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245004/02/pp16
Date of release: 1999 Sep 20
Document order number: 9397 750 05254
相关型号：
74ALVCH16623DGG-T
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74ALVCH16623DL,112
IC ALVC/VCX/A SERIES, 16-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
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