74ALVT16374DGG,112 [NXP]
74ALVT16374 - 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48-Pin;
| 型号： | 74ALVT16374DGG,112 |
| 厂家： | 
NXP |
| 描述： | 74ALVT16374 - 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48-Pin |
| 文件： | 总18页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ALVT16374
16-bit edge-triggered D-type flip-flop; 3-state
Rev. 04 — 4 July 2005
Product data sheet
1. General description
The 74ALVT16374 is a high performance BiCMOS product designed for VCC operation at
2.5 V or 3.3 V with I/O compatibility up to 5 V.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state
outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels
set up at the D inputs.
2. Features
■ 16-bit edge-triggered flip-flop
■ 5 V I/O compatible
■ 3-state buffers
■ Output capability: +64 mA and −32 mA
■ TTL input and output switching levels
■ Input and output interface capability to systems at 5 V supply
■ Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
■ Live insertion and extraction permitted
■ Power-up reset
■ Power-up 3-state
■ No bus current loading when output is tied to 5 V bus
■ Latch-up protection exceeds 500 mA per JESD78
■ Electrostatic discharge protection:
◆ MIL STD 883 method 3015: exceeds 2000 V
◆ Machine model: exceeds 200 V
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
3. Quick reference data
Table 1:
Quick reference data
Tamb = 25 °C.
Symbol Parameter
VCC = 2.5 V
Conditions
Min
Typ
Max Unit
tPLH
tPHL
Ci
propagation delay nCP to nQx
propagation delay nCP to nQx
CL = 50 pF
CL = 50 pF
-
-
-
-
2.6
2.8
3
-
-
-
-
ns
ns
pF
pF
input capacitance nCP and nOE VI = 0 V or VCC
Co
output capacitance
outputs disabled;
VO = 0 V or VCC
9
ICC
supply current
outputs disabled
-
40
-
µA
VCC = 3.3 V
tPLH
tPHL
Ci
propagation delay nCP to nQx
propagation delay nCP to nQx
CL = 50 pF
CL = 50 pF
-
-
-
-
2.1
2.3
3
-
-
-
-
ns
ns
pF
pF
input capacitance nCP and nOE VI = 0 V or VCC
Co
output capacitance
outputs disabled;
VO = 0 V or VCC
9
ICC
supply current
outputs disabled
-
40
-
µA
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
74ALVT16374DGG −40 °C to +85 °C
TSSOP48
plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
74ALVT16374DL
−40 °C to +85 °C
SSOP48
plastic shrink small outline package; 48 leads; body SOT370-1
width 7.5 mm
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
2 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
5. Functional diagram
1
EN1
C3
1OE
1CP
2OE
2CP
48
24
25
EN2
C4
47
46
44
43
41
40
38
37
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
3D
1
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
1CP
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
48
1
5
6
8
2
3
5
6
8
9
11
27
12
26
9
11
12
13
14
16
17
19
20
22
23
36
35
33
32
30
29
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
2CP
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
4D
2
25
24
13
14
16
17
19
20
22
23
001aad246
001aaa254
Fig 1. Logic symbol
Fig 2. IEC logic symbol
nD0
D
nD1
nD2
nD3
nD4
nD5
nD6
D
nD7
D
D
D
D
D
D
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
001aac371
Fig 3. Logic diagram
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
3 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
6. Pinning information
6.1 Pinning
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q0
1Q1
GND
1Q2
1Q3
1CP
1D0
1D1
GND
1D2
1D3
3
4
5
6
7
V
CC
V
CC
8
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
16374
V
CC
V
CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
2D4
2D5
GND
2D6
2D7
2CP
001aad248
Fig 4. Pin configuration
6.2 Pin description
Table 3:
Symbol
1OE
Pin description
Pin
1
Description
output enable input (active LOW)
data output
1Q0
2
1Q1
3
data output
GND
1Q2
4
ground (0 V)
data output
5
1Q3
6
data output
VCC
7
supply voltage
data output
1Q4
8
1Q5
9
data output
GND
1Q6
10
11
ground (0 V)
data output
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
4 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
Table 3:
Symbol
1Q7
2Q0
2Q1
GND
2Q2
2Q3
VCC
Pin description
Pin
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Description
data output
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
ground (0 V)
data output
data output
2Q4
2Q5
GND
2Q6
2Q7
2OE
2CP
2D7
2D6
GND
2D5
2D4
VCC
output enable input (active LOW)
clock pulse input (active rising edge)
data input
data input
ground (0 V)
data input
data input
supply voltage
data input
2D3
2D2
GND
2D1
2D0
1D7
1D6
GND
1D5
1D4
VCC
data input
ground (0 V)
data input
data input
data input
data input
ground (0 V)
data input
data input
supply voltage
data input
1D3
1D2
GND
1D1
1D0
1CP
data input
ground (0 V)
data input
data input
clock pulse input (active rising edge)
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
5 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
7. Functional description
7.1 Function table
Table 4:
Function table[1]
Input
Internal register Output
Operating mode
nOE
L
nCP
↑
nDx
nQx
L
l
L
load and read register
L
↑
h
H
H
L
NC
NC
↑
X
NC
NC
nDx
NC
Z
hold
H
X
disable outputs
H
nDx
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V)
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
Max
+4.6
+7.0
+7.0
Unit
V
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
output in OFF-state or
HIGH-state
V
IIK
IOK
IO
input diode current
VI < 0 V
-
−50
−50
128
−64
+150
150
mA
mA
mA
mA
°C
output diode current VO < 0 V
-
output current
output in LOW-state
output in HIGH-state
-
-
Tstg
Tj
storage temperature
junction temperature
−65
[2]
-
°C
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability.
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
6 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
9. Recommended operating conditions
Table 6:
Symbol
Recommended operating conditions
Parameter Conditions
Min
Typ
Max
Unit
VCC = 2.5 V ± 0.2 V
VCC
VI
supply voltage
2.3
-
-
-
-
-
-
-
2.7
5.5
-
V
input voltage
0
V
VIH
VIL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
1.7
V
-
-
-
0.7
−8
8
V
mA
mA
mA
LOW-level output current none
duty cycle < 50 %;
24
f ≥ 1 kHz
∆t/∆V
input transition rise or fall outputs enabled
rate
-
-
-
10
ns/V
Tamb
ambient temperature
−40
+85
°C
VCC = 3.3 V ± 0.3 V
VCC
VI
supply voltage
3.0
-
-
-
-
-
-
-
3.6
5.5
-
V
input voltage
0
V
VIH
VIL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current none
2.0
V
-
-
-
-
0.8
−32
32
64
V
mA
mA
mA
duty cycle < 50 %;
f ≥ 1 kHz
∆t/∆V
input transition rise or fall outputs enabled
rate
-
-
-
10
ns/V
Tamb
ambient temperature
−40
+85
°C
10. Static characteristics
Table 7:
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
amb = −40 °C to +85 °C.
Static characteristics
T
Symbol Parameter
VCC = 2.5 V ± 0.2 V[1]
Conditions
Min
Typ
Max
Unit
VIK
input diode voltage
VCC = 2.3 V; IIK = −18 mA
VCC = 2.3 V to 3.6 V; IOH = −100 µA
VCC = 2.3 V; IOH = −8 mA
VCC = 2.3 V; IOL = 100 µA
VCC = 2.3 V; IOL = 24 mA
-
−0.85 −1.2
V
V
V
V
V
V
VOH
HIGH-level output voltage
LOW-level output voltage
V
CC − 0.2 VCC
-
1.8
2.1
0.07
0.3
-
-
VOL
-
-
-
0.2
0.5
0.55
[2]
VRST
power-up LOW-state output VCC = 2.7 V; IO = 1 mA;
voltage VI = VCC or GND
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
7 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
Table 7:
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
amb = −40 °C to +85 °C.
Static characteristics …continued
T
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ILI
input leakage current
control pins
VCC = 2.7 V; VI = VCC or GND
VCC = 0 V or 2.7 V; VI = 5.5 V
VCC = 2.7 V; VI = VCC
-
-
-
-
-
-
-
-
0.1
0.1
0.1
+0.1
0.1
90
±1
10
1
µA
µA
µA
µA
µA
µA
µA
µA
[3]
[3]
I/O data pins
VCC = 2.7 V; VI = 0 V
−5
±100
-
IOFF
output power-down current VCC = 0 V; VI or VO = 0 V to 4.5 V
[4] [5]
[4] [5]
IHOLD
bus hold current D inputs
VCC = 2.3 V; VI = 0.7 V
VCC = 2.3 V; VI = 1.7 V
−10
10
-
IEX
IPU
IPD
IOZ
external current into output output in HIGH-state when
VO > VCC; VO = 5.5 V; VCC = 2.3 V
125
[6]
[6]
power-up 3-state output
current
V
CC ≤ 1.2 V; VO = 0.5 V to VCC
;
-
-
1
1
100
100
µA
µA
VI = GND or VCC; nOE = don’t care
power-down 3-state output
current
VCC ≤ 1.2 V; VO = 0.5 V to VCC;
VI = GND or VCC; nOE = don’t care
VCC = 2.7 V; VI = VIH or VIL
output HIGH; VO = 2.3 V
3-state OFF-state output
current
-
-
0.5
5
µA
µA
output LOW; VO = 0.5 V
+0.5
−5
ICC
supply current
VCC = 2.7 V; VI = VCC or GND;
IO = 0 A
outputs HIGH-state
outputs LOW-state
outputs disabled
-
-
-
-
0.04
2.7
0.1
4.5
0.1
0.4
mA
mA
mA
mA
[7]
[8]
0.04
0.04
∆ICC
additional supply current per VCC = 2.3 V to 2.7 V; one input at
input pin
VCC − 0.6 V; other inputs at
VCC or GND
Ci
input capacitance nCP and VI = 0 V or VCC
nOE
-
-
3
9
-
-
pF
pF
Co
output capacitance
outputs disabled; VO = 0 V or VCC
VCC = 3.3 V ± 0.3 V[9]
VIK
input clamp voltage
VCC = 3.0 V; IIK = −18 mA
VCC = 3.0 V to 3.6 V; IOH = −100 µA
VCC = 3.0 V; IOH = −32 mA
VCC = 3.0 V; IOL = 100 µA
VCC = 3.0 V; IOL = 16 mA
VCC = 3.0 V; IOL = 32 mA
VCC = 3.0 V; IOL = 64 mA
-
−0.85 −1.2
V
V
V
V
V
V
V
V
VOH
HIGH-level output voltage
LOW-level output voltage
V
CC − 0.2 VCC
-
2.0
2.3
0.07
0.25
0.3
0.4
-
-
VOL
-
-
-
-
-
0.2
0.4
0.5
0.55
0.55
[2]
VRST
power-up LOW-state output VCC = 3.6 V; IO = 1 mA;
voltage VI = VCC or GND
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
8 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
Table 7:
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
amb = −40 °C to +85 °C.
Static characteristics …continued
T
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ILI
input leakage current
control pins
VCC = 3.6 V; VI = VCC or GND
VCC = 0 V or 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = VCC
-
0.1
0.1
0.1
0.1
0.1
130
−140
-
±1
10
1
µA
µA
µA
µA
µA
µA
µA
µA
µA
-
[3]
[3]
I/O data pins
-
VCC = 3.6 V; VI = 0 V
-
−5
±100
-
IOFF
output power-down current VCC = 0 V; VI or VO = 0 V to 4.5 V
-
[5]
[5]
[5]
IHOLD
bus hold current D inputs
VCC = 3.0 V; VI = 0.8 V
VCC = 3.0 V; VI = 2.0V
75
−75
±500
-
-
VCC = 0 V to 3.6 V; VI = 3.6 V
-
IEX
IPU
IPD
IOZ
external current into output output in HIGH-state when
VO > VCC; VO = 5.5 V; VCC = 3.0 V
10
125
[10]
[10]
power-up 3-state output
current
V
CC ≤ 1.2 V; VO = 0.5 V to VCC
;
-
-
1
1
±100
±100
µA
µA
VI =VCC or GND; nOE = don’t care
power-down 3-state output
current
VCC ≤ 1.2 V; VO = 0.5 V to VCC;
VI =VCC or GND; nOE = don’t care
VCC = 3.6 V; VI = VIH or VIL
output HIGH; VO = 3.0 V
3-state OFF-state output
current
-
-
0.5
5
µA
µA
output LOW; VO = 0.5 V
+0.5
−5
ICC
supply current
VCC = 3.6 V; VI = GND or VCC
IO = 0 A
;
outputs HIGH-state
outputs LOW-state
outputs disabled
-
-
-
-
0.04
3.7
0.1
6
mA
mA
mA
mA
[7]
[8]
0.04
0.04
0.1
0.4
∆ICC
additional supply current per VCC = 3.0 V to 3.6 V; one input at
input pin
VCC − 0.6 V; other inputs at
VCC or GND
Ci
input capacitance nCP and VI = 0 V or VCC
nOE
-
-
3
9
-
-
pF
pF
Co
output capacitance
outputs disabled; VO = 0 V or VCC
[1] Typical values are at VCC = 2.5 V and Tamb = 25 °C.
[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3] Unused pins at VCC or GND.
[4] Not guaranteed
[5] This is the bus-hold overdrive current required to force the input to the opposite logic state.
[6] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[7] ICC is measured with outputs pulled to VCC or GND.
[8] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
[9] Typical values are at VCC = 3.3 V and Tamb = 25 °C.
[10] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
9 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
11. Dynamic characteristics
Table 8:
Dynamic characteristics
Tamb = −40 °C to +85 °C; GND = 0 V; for test circuit see Figure 9.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.5 V ± 0.2 V[1]
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
tsu(L)
th(H)
th(L)
tWH
maximum clock frequency
see Figure 5
see Figure 5
see Figure 5
see Figure 6
see Figure 7
see Figure 6
see Figure 7
see Figure 8
see Figure 8
see Figure 8
see Figure 8
see Figure 5
see Figure 5
150
1.5
1.5
1.0
1.0
2.0
1.0
1.0
1.5
0.5
0.5
1.5
1.5
-
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
propagation delay nCP to nQx
propagation delay nCP to nQx
output enable time to HIGH-level
output enable time to LOW-level
output disable time from HIGH-level
output disable time from LOW-level
setup time HIGH nDx to nCP
setup time LOW nDx to nCP
hold time HIGH nDx to nCP
hold time LOW nDx to nCP
nCP pulse width HIGH
2.6
2.8
3.4
2.6
2.7
2.0
0
4.2
4.5
5.6
4.7
4.4
3.3
-
0.4
0
-
-
0
-
-
-
tWL
nCP pulse width LOW
-
-
VCC = 3.3 V ± 0.3 V[2]
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
tsu(L)
th(H)
th(L)
tWH
maximum clock frequency
see Figure 5
see Figure 5
see Figure 5
see Figure 6
see Figure 7
see Figure 6
see Figure 7
see Figure 8
see Figure 8
see Figure 8
see Figure 8
see Figure 5
see Figure 5
250
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
0.5
0.5
1.5
1.5
-
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
propagation delay nCP to nQx
propagation delay nCP to nQx
output enable time to HIGH-level
output enable time to LOW-level
output disable time from HIGH-level
output disable time from LOW-level
setup time HIGH nDx to nCP
setup time LOW nDx to nCP
hold time HIGH nDx to nCP
hold time LOW nDx to nCP
nCP pulse width HIGH
2.1
2.3
2.3
2.0
2.7
2.6
0
3.2
3.2
3.8
3.2
4.2
3.6
-
0
-
0
-
0
-
-
-
tWL
nCP pulse width LOW
-
-
[1] Typical values are at VCC = 2.5 V and Tamb = 25 °C.
[2] Typical values are at VCC = 3.3 V and Tamb = 25 °C.
9397 750 15193
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Product data sheet
Rev. 04 — 4 July 2005
10 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
12. Waveforms
1/f
max
V
V
I
input nCP
V
V
M
M
M
0 V
t
t
WL
WH
t
t
PLH
PHL
V
OH
V
M
V
M
output nQx
V
OL
001aad250
Measurement points are given in Table 9.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5. Propagation delay clock input to output, clock pulse width and maximum clock
frequency
V
I
V
V
M
input nOE
M
t
0 V
t
PZH
PHZ
V
OH
V
Y
V
M
output nQx
0 V
001aad251
Measurement points are given in Table 9.
VOH is typical voltage output drop that occur with the output load.
Fig 6. 3-state output enable time to HIGH-level and output disable time from HIGH-level
V
I
V
V
M
input nOE
M
0 V
t
t
PLZ
PZL
V
OH
V
M
output nQx
V
X
V
OL
001aad253
Measurement points are given in Table 9.
VOL is typical voltage output drop that occur with the output load.
Fig 7. 3-state output enable time to LOW-level and output disable time from LOW-level
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
11 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
V
I
input nDx
V
M
V
V
M
V
M
M
0 V
t
t
t
t
h(L)
s(H)
h(H)
s(L)
V
I
output nCP
V
V
M
M
0 V
001aad252
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 8. Data setup and hold times
Table 9: Measurement points
Supply voltage
Input
VM
Output
VM
VX
VY
≥ 3 V
1.5 V
1.5 V
VOL + 0.3 V
VOL + 0.15 V
V
OH − 0.3 V
OH − 0.15 V
≤ 2.7 V
0.5 × VCC
0.5 × VCC
V
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
12 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
t
W
V
I
90 %
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
(t )
f
t
(t )
TLH r
THL
t
(t )
t
(t )
THL f
TLH
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
10 %
0 V
t
W
001aac221
Measurement points are given in Table 9.
a. Input pulse definition
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
C
L
R
L
R
T
mna616
Test data is given in Table 10.
Definitions:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
b. Test circuit
Fig 9. Load circuitry for switching times
Table 10: Test data
Input
Load
CL
VEXT
VI
fi
tW
tr, tf
RL
tPLH, tPHL tPHZ, tPZH tPLZ, tPZL
3.0 V or VCC
whichever is
less
≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open
GND
6 V or 2 ×
VCC
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
13 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
13. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
Fig 10. Package outline SOT362-1 (TSSOP48)
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
14 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
Fig 11. Package outline SOT370-1 (SSOP48)
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
15 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
14. Revision history
Table 11: Revision history
Document ID
74ALVT16374_4
Modifications:
Release date Data sheet status
20050704 Product data sheet
Change notice Doc. number
Supersedes
-
9397 750 15193 74ALVT16374_3
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Section 2 “Features”: Changed JEDEC Std 17 to JESD78
• Section 11 “Dynamic characteristics”: Changed tPLZ typical value to 2.6 ns and maximum value
to 3.6 ns
74ALVT16374_3
74ALVT16374_2
74ALVT16374_1
19991018
19980213
19960610
Product specification
Product specification
Product specification
-
-
-
9397 750 06513 74ALVT16374_2
9397 750 03565 74ALVT16374_1
-
-
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
16 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
16. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Trademarks
Notice — All referenced brands, product names, service names and
17. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 15193
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2005
17 of 18
74ALVT16374
Philips Semiconductors
16-bit edge-triggered D-type flip-flop; 3-state
20. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 6
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information . . . . . . . . . . . . . . . . . . . . 17
9
10
11
12
13
14
15
16
17
18
19
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 4 July 2005
Document number: 9397 750 15193
Published in The Netherlands
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