74AUC1G02GW [NXP]
Single 2-input NOR gate; 单路2输入或非门
| 型号： | 74AUC1G02GW |
| 厂家： | 
NXP |
| 描述： | Single 2-input NOR gate |
| 文件： | 总12页 (文件大小：54K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AUC1G02
Single 2-input NOR gate
Preliminary specification
2002 Nov 12
File under Integrated Circuits, IC24
Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
FEATURES
DESCRIPTION
• Wide supply voltage range from 0.8 to 2.7 V
• Performance optimised for VCC = 1.8 V
• High noise immunity
The 74AUC1G02is a high-performance, low-power,
low-voltage, Si-gate CMOS device.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall time.
• Complies with JEDEC standard:
– JESD76 (1.65 to 1.95 V)
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging current backflow through the
device when it is powered down.
• 8 mA output drive (VCC = 1.65 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
The 74AUC1G02 provides the single 2-input NOR
function.
• ESD protection:
2000 V Human Body Model (A 114-A)
200 V Machine Model (A 115-A)
• 3.3 V tolerant inputs/outputs
• SC-88A and SC-74A package.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; input slewrate ≥ 1 V/ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH propagation delay inputs A and B to
output Y
VCC = 0.8 V; CL = 15 pF; RL = 2 kΩ
VCC = 1.2 V; CL = 15 pF; RL = 2 kΩ
VCC = 1.5 V; CL = 15 pF; RL = 2 kΩ
4.6
1.9
1.4
1.5
ns
ns
ns
ns
ns
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 1.2
CI
input capacitance
4
pF
pF
CPD
power dissipation capacitance per buffer
VCC = 1.8 V; notes 1 and 2
14
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC
.
2002 Nov 12
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Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
Y
A
B
L
L
L
H
L
H
L
L
L
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TEMPERATURE
PINS
PACKAGE MATERIAL
CODE
MARKING
RANGE
74AUC1G02GW
74AUC1G02GV
−40 to +85 °C
−40 to +85 °C
5
5
SC-88A
SC-74A
plastic
plastic
SOT353
SOT753
FB
F02
PINNING
PIN
1
SYMBOL
DESCRIPTION
B
A
data input B
data input A
ground (0 V)
data output Y
supply voltage
2
3
GND
Y
4
5
VCC
handbook, halfpage
B
A
1
2
3
5
4
V
Y
CC
handbook, halfpage
1
2
B
A
Y
4
02
GND
MNA103
MNA102
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2002 Nov 12
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Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
handbook, halfpage
B
1
2
handbook, halfpage
≥1
4
Y
MNA104
A
MNA105
Fig.3 IEE/IEC logic symbol.
Fig.4 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
0.8
MAX.
UNIT
2.7
2.7
VCC
2.7
+85
20
V
V
V
V
VI
input voltage
0
VO
output voltage
active mode
VCC = 0 V; Power-down mode
0
0
Tamb
operating ambient temperature
input rise and fall times
−40
0
°C
tr,tf (∆t/∆f)
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +3.6
V
IIK
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+3.6
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
mA
V
active mode; notes 1 and 2
−0.5
VCC + 0.5
+3.6
±60
Power-down mode; notes 1 and 2 −0.5
V
IO
output source or sink current
VCC or GND current
VO = 0 to VCC
−
mA
mA
°C
mW
ICC, IGND
Tstg
−
±100
+150
250
storage temperature
−65
−
PD
power dissipation per package
for temperature range from
−40 to +85 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC =0 (Powered-down mode), the output voltage can be 2.7 V in normal operation.
2002 Nov 12
4
Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
−40 to +85
UNIT
OTHER
VCC (V)
0.8
MIN.
VCC
TYP.(1)
MAX.
VIH
HIGH-level input
voltage
−
−
−
−
V
1.1 to 2.3
2.3 to 2.7
0.8
0.65 × VCC
−
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
1.7
−
−
VIL
LOW-level input
voltage
−
GND
1.1 to 2.3
2.3 to 2.7
−
−
0.35 × VCC
−
−
0.7
−
VOH
HIGH-level output VI = VIH or VIL; IO = −100 µA 0.8 to 2.7
voltage
VCC − 0.1
−
VI = VIH or VIL; IO =− 700 µA 0.8
−
0.55
−
−
VI = VIH or VIL; IO =− 3 mA
VI = VIH or VIL; IO = −5 mA
VI = VIH or VIL; IO = −8 mA
VI = VIH or VIL; IO = −9 mA
1.1
1.5
1.65
2.3
VCC − 0.3
VCC − 0.4
VCC − 0.45
−
−
−
−
−
1.8
−
−
−
VOL
LOW-level output VI = VIH or VIL; IO = 100 µA 0.8 to 2.7
voltage
−
0.2
−
VI = VIH or VIL; IO = 700 µA 0.8
−
0.25
−
VI = VIH or VIL; IO = 3 mA
VI = VIH or VIL; IO = 5 mA
VI = VIH or VIL; IO = 8 mA
VI = VIH or VIL; IO = 9 mA
VI = VCC or GND
1.1
−
0.3
0.4
0.45
0.6
±5
1.5
−
−
1.65
2.3
−
−
−
−
II
input leakage
current
0 to 2.7
−
±0.1
Ioff
ICC
power OFF
leakage current
VI or VO = 2.7 V
0
−
−
±0.1
±10
µA
µA
quiescent supply VI = VCC or GND; IO = 0
current
0.8 to 2.7
0.1
10
Note
1. All typical values are at VCC = 1.8 V and Tamb = 25 °C.
2002 Nov 12
5
Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
AC CHARACTERISTICS
GND = 0 V; input slewrate ≥ 1 V/ns.
TEST CONDITIONS
VCC (V) CL(pF) RL(kΩ)
0.8
Tamb (°C)
SYMBOL
PARAMETER
−40 to +85
UNIT
WAVEFORMS
MIN. TYP. MAX.
tPHL/tPLH propagation delay
see
15
15
15
30
30
2
2
−
4.6
1.9
1.4
1.5
1.2
ns
ns
ns
ns
ns
inputs A and B to output Y Figs 5 and 6
1.1 to 1.3
1.4 to 1.6
1.65 to 1.95
2.3 to 2.7
0.9
0.5
0.7
0.5
3.2
2.2
2.4
2.1
2
1
0.5
AC WAVEFORMS
V
handbook, halfpage
A, B input
I
V
M
GND
t
t
PHL
PLH
V
OH
V
Y output
M
MNA611
V
OL
INPUT
VCC
VM
0.5 × VCC VCC
VI
Slewrate
0.8 to 2.7 V
≥ 1 V/ns
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 Inputs A, B to output Y propagation delay times.
2002 Nov 12
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Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
TPLH/TPHL TPZH/TPHZ TPZL/TPLZ
VCC
<1.65 V
VI
VCC
VCC
VCC
CL
RL
15 pF
30 pF
30 pF
2 kΩ
open
GND
GND
GND
2 × VCC
2 × VCC
2 × VCC
1.65 to 1.95 V
2.3 to 2.7 V
1 kΩ
open
open
0.5 kΩ
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”).
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2002 Nov 12
7
Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
PACKAGE OUTLINE
Plastic surface mounted package; 5 leads
SOT353
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
(2)
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-88A
97-02-28
SOT353
2002 Nov 12
8
Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
Plastic surface mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
SOT753
SC-74A
02-04-16
2002 Nov 12
9
Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by
a smooth laminar wave.
This text gives a very brief insight to a complex
technology. A more in-depth account of soldering ICs can
be found in our “Data Handbook IC26; Integrated Circuit
Packages” (document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package
placement.
• For packages with leads on four sides, the footprint
must be placed at a 45° angle to the transport direction
of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side
corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package
must be fixed with a droplet of adhesive. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit
boards with a high component density, as solder bridging
and non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Nov 12
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Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
not suitable
REFLOW(1)
BGA, HBGA, LFBGA, SQFP, TFBGA
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
PLCC(3), SO, SOJ
suitable
suitable
suitable
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Nov 12
11
Philips Semiconductors
Preliminary specification
Single 2-input NOR gate
74AUC1G02
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
STATUS
DEFINITIONS (1)
Objective specification
Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury.
Philips Semiconductors customers using or selling these
products for use in such applications do so at their own
risk and agree to fully indemnify Philips Semiconductors
for any damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in
the Characteristics sections of the specification is not
implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or
title under any patent, copyright, or mask work right to
these products, and makes no representations or
warranties that these products are free from patent,
copyright, or mask work right infringement, unless
otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will
be suitable for the specified use without further testing or
modification.
2002 Nov 12
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